NAME: Vikash Gurjar

ROLL NO: 21104111

EXPERIMENT: 3(a)
AIM: Implement full adder using data flow and structural modeling
SOFTWARE: Xilinx
Full adder using data flow modelling
Code:
`timescale 1ns / 1ps

module fulladder(

input a,

input b,

input cin,

output sum,

output carry );

assign sum = (a^b)^cin ;

assign carry = (a&b)|(b&cin)|(cin&a);

endmodule

RTL:

SIMULATION:
`timescale 1ns / 1ps

module full_adders();

reg a,b,cin;
 wire s,carry;

fulladder uut(a,b,cin,s,carry);

initial

begin

a = 0; b = 0;cin=0;

#20 a = 0; b = 0;cin=1;

#20 a = 0; b = 1;cin=0;

#20 a = 0; b = 1;cin=1;

#20 a = 1; b = 0;cin=0;

#20 a = 1; b = 0;cin=1;

#20 a = 1; b = 1;cin=0;

#20 a = 1; b = 1;cin=1;

#20 $finish;

end

endmodule

WAVEFORM:

Full Adder using Structural Modelling

Code:
`timescale 1ns / 1ps

module fulladder(

input a,b,cin,

output sum,carry);

wire w,x,y,z;

xor(sum ,a,b,cin);
and( w,a,b);

and(x,b,cin);

and(y,cin,a);

or(z,w,x);

or(carry,z,y);

endmodule

Full Adder Simulation using Structural Modelling

`timescale 1ns / 1ps

module full_adders();

reg a,b,cin;

wire s,carry;

fulladder uut(a,b,cin,s,carry);

initial

begin

a = 0; b = 0;cin=0;

#20 a = 0; b = 0;cin=1;

#20 a = 0; b = 1;cin=0;

#20 a = 0; b = 1;cin=1;

#20 a = 1; b = 0;cin=0;

#20 a = 1; b = 0;cin=1;

#20 a = 1; b = 1;cin=0;

#20 a = 1; b = 1;cin=1;

#20 $finish;

end

endmodule

RTL:
WAVEFORM:

EXPERIMENT: 3(b)
AIM: Implement full adder using two half adder
Full adder using two half adder
Code:
`timescale 1ns / 1ps

module half_adder_(

input a,b,

output sum,carry

);

xor(sum,a,b);

and(carry,a,b);

endmodule

module full_adder(

input a,b,cin,

output sum,carry);
 wire c,c1,s;

half_adder_ ha0(a,b,s,c);

half_adder_ ha1(cin,s,sum,c1);

or(carry,c,c1);

endmodule

simulation
code:
`timescale 1ns / 1ps

module full_adders();

reg a,b,cin;

wire s,carry;

full_adder uut(a,b,cin,s,carry);

initial

begin

a = 0; b = 0;cin=0;

#20 a = 0; b = 0;cin=1;

#20 a = 0; b = 1;cin=0;

#20 a = 0; b = 1;cin=1;

#20 a = 1; b = 0;cin=0;

#20 a = 1; b = 0;cin=1;

#20 a = 1; b = 1;cin=0;

#20 a = 1; b = 1;cin=1;

#20 $finish;

end

endmodule

RTL
Waveform: