136
1, JANUARY 2023
Non-Volatile Nano-Electro-Mechanical Switches
and Hybrid Circuits in a 16 nm CMOS
Back-End-of-Line Process
Urmita Sikder , Member, IEEE, Rawan Naous, Vladimir Stojanović , Senior Member, IEEE,
and Tsu-Jae King Liu, Fellow, IEEE
Abstract — Reprogrammable non-volatile (NV) vertically-
oriented nano-electro-mechanical (NEM) switches with a
compact footprint are successfully implemented using mul-
tiple back-end-of-line (BEOL) interconnect layers of a stan-
dard 16-nm CMOS process technology, with no additional
lithography steps. A compact decoder circuit comprising
an array of these reconfigurable interconnects is success-
fully demonstrated. As the minimum metal pitch decreases
with each new manufacturing process generation, hybrid
CMOS+NEM technology becomes increasingly attractive for
ultra-low-power reconfigurable computing applications.
Index Terms — Non-volatile, reconfigurable, monolithic
integration, data search, BEOL, interconnects.
I. I NTRODUCTION
O NGOING miniaturization (scaling) of complemen-
tary metal-oxide-semiconductor (CMOS) transistors and
interconnects has created new opportunities for monolithic
integration of nano-electro-mechanical (NEM) switches with
CMOS transistors to implement hybrid circuits at low incre-
mental cost [1], [2], [3], [4], [5]. This is because the metallic
interconnect layers formed using the back-end-of-line (BEOL)
steps of a CMOS manufacturing process can be used to
implement NEM switches [6], [7], [8], [9], [10]. In this
manner, discrete laterally oriented NEM switches have been
fabricated using standard CMOS manufacturing processes as
advanced as 16 nm-generation [11]. The energy-efficiency and
switching speed of a NEM switch are projected to improve
with miniaturization [5], [12].
Hybrid CMOS + NEM circuits can be more functional
and/or energy efficient than CMOS implementations due to
the unique properties of NEM switches, i.e., abrupt switching
characteristics, non-volatile (NV) switching capability and
high resistance ratio between programmed states [13], [14],
[15], [16], [17], [18], [19], [20]. Therefore, CMOS-integrated
Manuscript received 25 October 2022; accepted 8 November 2022.
Date of publication 10 November 2022; date of current version
28 December 2022. This work was supported in part by the National Sci-
ence Foundation (NSF) Center for Energy Efficient Electronics Science
under Award 0939514 and in part by the Berkeley Wireless Research
Center. The review of this letter was arranged by Editor N. Barniol.
(Corresponding author: Urmita Sikder.)
Urmita Sikder, Vladimir Stojanović, and Tsu-Jae King Liu are with the
Department of EECS, University of California, Berkeley, CA 94720 USA
(e-mail: urmita@berkeley.edu).
Rawan Naous is with Meta Platforms, Menlo Park, CA 94025 USA.
Color versions of one or more figures in this letter are available at
https://doi.org/10.1109/LED.2022.3221701.
Digital Object Identifier 10.1109/LED.2022.3221701
0741-3106 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
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IEEE ELECTRON DEVICE LETTERS, VOL. 44, NO.
NEM switches have been proposed for energy-efficient routing
in Field-Programmable Gate Arrays (FPGAs) [2], [21], [22]
and for implementation of fast and energy-efficient look-up
tables (LUT) [23], [24] and decoder circuits [11], [25]. The
footprint of a NEM switch can be minimized by vertically
orienting the movable electrode [24]. It is worthwhile to note
here that implementation of compact hybrid CMOS + NEM
circuits in advanced technology nodes requires additional
design rules to ensure high manufacturing yield while min-
imizing layout area.
In this work, vertically oriented NV-NEM switches are
successfully implemented using multiple metal interconnect
layers and corresponding via layers in a standard 16 nm-
generation CMOS BEOL process. The results reported herein
represent a significant advancement over prior work: the
single-pole/double-throw switches have a footprint of only
0.055 μm2 , which is much smaller than the footprint of
previously reported BEOL switches [11], [24], [26]. Also,
a compact decoder circuit comprising an array of BEOL
NV-NEM switches and CMOS inverters is demonstrated using
16 nm-node FinFETs. The array of BEOL NEM switches
(with four switches spanning 1.6 µm) is much more com-
pact than in our previous work (∼75μm [11]). Performance
improvement with technology scaling is discussed to show that
CMOS + NEM technology is promising for future data-centric
computing applications.
II. N ANO -E LECTRO -M ECHANICAL S WITCH D ESIGN
The NV-NEM switch design used in this work is a single-
pole-double-throw (SPDT) switch consisting of five terminals:
a movable beam, two actuation electrodes (Prog 0/1) on either
side of the movable beam, and two corresponding conduct-
ing/dataline electrodes (D0/1). Fig. 1(a) shows the movable
beam in its as-fabricated (neutral, non-contacting) position.
A programming voltage pulse can be applied to either actua-
tion electrode (Prog 0 or Prog 1) to generate an electrostatic
force (Felec ) and thereby actuate the beam into physical contact
with a conducting electrode (D0 as in Fig. 1(b) or D1 as in
Fig. 1(c)). The programmed states are non-volatile because the
spring restoring force of the movable beam is designed to be
smaller than the contact adhesive force. The state of the switch
can be changed by applying a programming voltage pulse
to the opposite actuation electrode. Fig. 1(d) is a schematic
cross-section of vertically oriented NV-NEM switches imple-
mented using multiple interconnect and via layers in a 16 nm
SIKDER et al.: NV NEM SWITCHES AND HYBRID CIRCUITS IN A 16 nm CMOS BEOL PROCESS
Fig. 1. Schematic diagrams illustrating a vertically oriented NV-NEM
switch (a) in as-fabricated (neutral) state, and in programmed (b) state
“0” and (c) state “1”. Schematic cross-sections illustrating BEOL NV-NEM
switches (d) after the release-etch process and (e) after program-
ming. BEOL material layers, including metal and via layers, inter-metal
dielectric (IMD) and intra-layer dielectric (ILD) layers are shown. Cross-
sectional Scanning Electron Microscope (SEM) images of as-fabricated
BEOL NV-NEM switches implemented using (f) three, and (g) six metal
layers and corresponding via layers.
CMOS BEOL process. Note that the lowermost metal layers
are used because they have the tightest pitch and therefore can
be used to form the smallest air gaps, to achieve the smallest
possible programming voltage and/or actuation electrode area.
After the CMOS and interconnect fabrication process steps
are completed, the low-κ dielectric material surrounding the
movable beam electrodes is selectively etched away to allow
for physical movement of the beams. Fig. 1(e) illustrates the
NV-NEM switches after programming operation.
In this work, SF6 − O2 plasma was used for the “release
etch” process, to selectively remove > 3μm-thick low-κ
dielectric. Dummy metal structures in the upper metal layers
were placed strategically to form a hard-mask without an
additional lithography step and protect the rest of the chip
from the etchant [11]. Fig. 1(f) is a cross-sectional Scanning
Electron Microscope (SEM) image of a NV-NEM switch
implemented using the three lowermost metal layers, achiev-
ing the minimum contact gap of 32 nm. Fig. 1(g) shows a
NV-NEM switch implemented using the six lowermost metal
layers, with a contact gap of i.e. 80 nm.
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137
Fig. 2. (a) Measured quasi-static current-vs.-voltage characteristics
of NV-NEM switches fabricated using 16nm technology for the first
three program cycles. The ON-state current is artificially limited to
100nA during measurement to avoid Joule-heating-induced contact
welding. (b) Experimentally extracted programming voltages are com-
pared against simulated values for 65nm [24] and 16nm technology
nodes.
III. NV-NEM S WITCH C HARACTERISTICS
Fig. 2(a) shows experimentally measured quasi-static
current-vs.-voltage characteristics of a fabricated NV-NEM
switch (Fig. 1(g)) for its initial three (re)programming
cycles. The voltage applied to the program electrode was
bi-directionally swept with 1.5 V and 0 V applied to the
corresponding conducting electrode and to the beam and
opposite conducting electrode, respectively. The initial change
of state from neutral to “0”, i.e. the write operation occurs
when VProg,0 exceeds the switching voltage at 5.5 V. Subse-
quent reprogramming operations require higher programming
voltage due to the larger effective actuation gap and contact
gap, and possibly larger contact adhesive force due to higher
contact velocity. It should be noted that this hot-switching
procedure was used in this work only to determine the required
programming voltage. In practice, no voltage should be applied
to the conducting electrode during a programming operation,
to avoid unnecessary power consumption and to achieve high
cycling endurance [27]. Device lifetime can also be improved
by optimizing the contacting electrode material [28], [29]
and/or hermetic packaging to prevent contact oxidation.
Fig. 2(b) compares the experimentally measured program-
ming voltages of NV-NEM switches fabricated using 65 nm
and 16 nm process technologies against values obtained
through simulations using the Coventor MEMS+ compact
model. Cross-sectional SEM images of the switches are shown
in the insets. As expected, the switch fabricated using a
more advanced (16 nm) CMOS BEOL process operates with
considerably lower (re)programming voltage.
IV. 16 NM CMOS + NEM C IRCUIT D EMONSTRATION
In this work, a hybrid CMOS + NEM decoder circuit
design [11] is implemented using a 16 nm FinFET-based
CMOS process technology for the first time. A compact
4×2 array of NV-NEM switches is used to store four 2-bit data
strings, one in each row. Fig. 3(a) shows the circuit diagram
and Fig. 3(b) is a cross-sectional SEM image showing four
movable beams along a single column of the 4 × 2 array,
demonstrating the most compact BEOL switch array reported
so far. When a 2-bit input string is applied, the output bit
138
Fig. 3. (a) Circuit diagram for a CMOS+NEM 2-to-4 line decoder. Lines
colored in red indicate wires that are driven to high voltage. (b) Cross-
sectional SEM image showing the four movable beams along a single
column of the array. Measured voltage waveforms for the (c)-(d) input
bits and (e) output bits demonstrate proper circuit operation.
line for the row in which that string is stored is the only
one that is not pulled high. (Note that this circuit essentially
performs a memory-based parallel data search operation.) To
demonstrate the operation of this hybrid circuit, the NV-NEM
switches are programmed to store a 2-bit data string in each
of the four rows of the array On , (n = 0, 1, 2, 3): 00, 10,
01 and 11, respectively. Subsequently, a decoding operation
can be performed to find the address (bit line) of the data string
that matches the input data string. In the example shown in
Fig. 3(a), the address of the data string 00 is found by setting
both the inputs A and B low; after applying the input address
00, all the bit lines except O0 are driven high because it stores
the matching data string. CMOS buffer gates serve to restore
the output bit-line high voltage level to VDD . Input bit-line
voltage swing needs to be >1.4 V for proper CMOS buffer
operation.
The measured waveform in Fig. 3(e) shows the output bit
line O0 voltage as the 2-bit input address is cycled through
all four possible values (Fig. 3(c) and Fig. 3(d)), showing
that the voltage goes low only when the input address is 00.
The dashed and solid lines in Fig. 3(e) are measured output
bit-line voltages before and after the CMOS buffer gates,
respectively. The RC charging/discharging delay is found to be
a few microseconds due to large ON-resistance and parasitic
capacitance associated with the probe pads and coaxial cable.
The ON-resistance of a standalone NEM switch was measured
to be 167−250 k (measured RC-time constant ≈ 225 ns,
estimated intrinsic delay < 1 ns), which is substantially higher
than the value predicted by the empirical contact resistance
model (74 k) [10]. This discrepancy may be explained by the
disproportionate increase of interconnect resistance at scaled
dimensions due to the reduced volume fraction of copper
compared to the high-resistivity liner and diffusion-barrier
layers.
V. S CALING T RENDS
As the minimum pitch decreases with each new generation
of CMOS process technology, the programming voltage and
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IEEE ELECTRON DEVICE LETTERS, VOL. 44, NO. 1, JANUARY 2023
Fig. 4. Simulated values of (a) minimum programming voltage of opti-
mized vertical NEM switches with different actuation electrode lengths,
and corresponding (b) minimum programming energy, (c) programming
time (vacuum conditions) and (d) NV-NEM switch footprint. Here F refers
to the minimum metal half-pitch.
speed of BEOL NV-NEM switches is expected to improve
[14], [30]. Performance parameters for the BEOL NEM
switch design shown in Fig. 1(g) are simulated using Coven-
tor MEMS+ and plotted in Fig. 4 for various beam- and
actuation-electrode lengths: L b = 3F, 5F, 7F, where F is
the minimum metal half-pitch. With increased actuation area,
lower programming voltage can be used. This comes at a
trade-off of larger device footprint and slower programming
speed due to larger mass. All the performance parameters,
especially the programming energy and cell area, are projected
to improve rapidly with technology scaling. At the 16 nm
node, the NV-NEM switch has a footprint (0.055μ2) that is
considerably smaller than that of a six-transistor SRAM bit cell
(0.074 µm2 [31]) and is projected to have comparable readout
energy and speed.
VI. C ONCLUSION
Vertically oriented NV-NEM switches, with a footprint of
0.055μm2 , are implemented using multiple BEOL intercon-
nect layers in a conventional 16 nm FinFET-based CMOS
process technology to enable compact implementation of
CMOS + NEM circuits. NV-NEM switch performance
improves with technology scaling, so that this hybrid technol-
ogy shows promise for future data-centric computing applica-
tions. Further work is needed to achieve lower ON-resistance
of the NV-NEM switches.
ACKNOWLEDGMENT
The authors would like to thank Dr. Qichen Zhang for
his support with the CMOS chip design. The chips were
designed in collaboration with Berkeley Wireless Research
Center (BWRC) and fabricated by the MOSIS Service using
TSMC 16FFC technology. They were post-processed in the
UC Berkeley Marvell Nanofabrication Laboratory.
SIKDER et al.: NV NEM SWITCHES AND HYBRID CIRCUITS IN A 16 nm CMOS BEOL PROCESS
R EFERENCES
[1] H. F. Dadgour and K. Banerjee, “Hybrid NEMS–CMOS integrated
circuits: A novel strategy for energy-efficient designs,” IET Comput.
Digit. Techn., vol. 3, no. 6, pp. 593–608, 2009.
[2] V. K. Sirigir, K. Alzoubi, D. G. Saab, F. Kocan, and M. Tabib-Azar,
“Ultra-low-power ultra-fast hybrid CNEMS-CMOS FPGA,” in Proc. Int.
Conf. Field Program. Log. Appl., Aug. 2010, pp. 368–373.
[3] S. Chong, B. Lee, K. B. Parizi, J. Provine, S. Mitra, R. T. Howe,
and H.-S.-P. Wong, “Integration of nanoelectromechanical (NEM) relays
with silicon CMOS with functional CMOS-NEM circuit,” in IEDM Tech.
Dig., Dec. 2011, pp. 5–30.
[4] T.-J.-K. Liu, U. Sikder, K. Kato, and V. Stojanovic, “There’s plenty of
room at the top,” in Proc. IEEE 30th Int. Conf. Micro Electro Mech.
Syst. (MEMS), Jan. 2017, pp. 1–4.
[5] U. Sikder and T.-J. King Liu, “3D integrated CMOS-NEM systems:
Enabling next-generation computing technology,” in Proc. IEEE Int.
Meeting Future Electron Devices, Kansai (IMFEDK), Nov. 2021,
pp. 1–4.
[6] G. K. Fedder, S. Santhanam, M. L. Reed, S. C. Eagle, D. F. Guillou,
M. S.-C. Lu, and L. R. Carley, “Laminated high-aspect-ratio microstruc-
tures in a conventional CMOS process,” Sens. Actuators A, Phys.,
vol. 57, no. 2, pp. 103–110, Nov. 1996.
[7] J. L. Muñoz-Gamarra, G. Vidal-Álvarez, F. Torres, A. Uranga, and
N. Barniol, “CMOS-MEMS switches based on back-end metal layers,”
Microelectron. Eng., vol. 119, pp. 127–130, May 2014.
[8] M. Riverola, G. Sobreviela, F. Torres, A. Uranga, and N. Barniol,
“A monolithically integrated torsional CMOS-MEMS relay,”
J. Micromech. Microeng., vol. 26, no. 11, Nov. 2016, Art. no. 115012.
[9] W. Y. Choi and Y. J. Kim, “Three-dimensional integration of com-
plementary metal-oxide-semiconductor-nanoelectromechanical hybrid
reconfigurable circuits,” IEEE Electron Device Lett., vol. 36, no. 9,
pp. 887–889, Sep. 2015.
[10] U. Sikder, G. Usai, T.-T. Yen, K. Horace-Herron, L. Hutin, and
T.-J.-K. Liu, “Back-end-of-line nano-electro-mechanical switches for
reconfigurable interconnects,” IEEE Electron Device Lett., vol. 41, no. 4,
pp. 625–628, Apr. 2020.
[11] U. Sikder, K. Horace-Herron, T.-T. Yen, G. Usai, L. Hutin, V. Stojanovic,
and T.-J.-K. Liu, “Toward monolithically integrated hybrid CMOS-NEM
circuits,” IEEE Trans. Electron Devices, vol. 68, no. 12, pp. 6430–6436,
Dec. 2021.
[12] J. W. Ko, G. Baek, and W. Y. Choi, “Scaling trends of monolithic
3-D complementary metal–oxide–semiconductor nanoelectromechanical
reconfigurable logic circuits,” IEEE Trans. Electron Devices, vol. 67,
no. 9, pp. 3861–3867, Sep. 2020.
[13] K. Akarvardar and H.-S.-P. Wong, “Nanoelectromechanical logic and
memory devices,” ECS Trans., vol. 19, no. 1, pp. 49–59, May 2009.
[14] T.-J. King Liu, J. Jeon, R. Nathanael, H. Kam, V. Pott, and E. Alon,
“Prospects for MEM logic switch technology,” in IEDM Tech. Dig.,
Dec. 2010, p. 18.
[15] O. Y. Loh and H. D. Espinosa, “Nanoelectromechanical contact
switches,” Nature Nanotechnol., vol. 7, no. 5, p. 283, 2012.
[16] M. A. Beunder, R. van Kampen, D. Lacey, M. Renault, and C. G. Smith,
“A new embedded NVM technology for lowpower, high temperature,
rad-hard applications,” in Proc. Symp. Non-Volatile Memory Technol.,
Nov. 2005, p. 4.
Authorized licensed use limited to: KTH Royal Institute of Technology. Downloaded on October 26,2023 at 13:52:14 UTC from IEEE Xplore. Restrictions apply.
139
[17] W. Y. Choi, T. Osabe, and T. J. K. Liu, “Nano-electro-
mechanical nonvolatile memory (NEMory) cell design and scaling,”
IEEE Trans. Electron Devices, vol. 55, no. 12, pp. 3482–3488,
Dec. 2008.
[18] S. W. Lee, S. J. Park, E. E. B. Campbell, and Y. W. Park,
“A fast and low-power microelectromechanical system-based non-
volatile memory device,” Nature Commun., vol. 2, no. 1, p. 220,
Sep. 2011.
[19] V. Pott, G. Chua, R. Vaddi, J. Lin, and T. Kim, “The shuttle nanoelectro-
mechanical nonvolatile memory,” IEEE Trans. Electron Devices, vol. 59,
no. 4, pp. 1137–1143, Apr. 2012.
[20] B. Soon, E. J. Ng, N. Singh, J. M. Tsai, Y. Qian, and C. Le,
“A bistable electrostatic silicon nanofin relay for nonvolatile memory
application,” J. Microelectromech. Syst., vol. 22, no. 5, pp. 1004–1006,
Oct. 2013.
[21] C. Chen, H.-S.-P. Wong, S. Mitra, R. Parsa, N. Patil, S. Chong,
K. Akarvardar, J. Provine, D. Lewis, J. Watt, and R. T. Howe, “Effi-
cient FPGAs using nanoelectromechanical relays,” in Proc. 18th Annu.
ACM/SIGDA Int. Symp. Field Program. Gate Arrays (FPGA), 2010,
pp. 273–282.
[22] Y. J. Kim and W. Y. Choi, “Nonvolatile nanoelectromechanical memory
switches for low-power and high-speed field-programmable gate arrays,”
IEEE Trans. Electron Devices, vol. 62, no. 2, pp. 673–679, Feb. 2015.
[23] K. Kato, V. Stojanovic, and T.-J. K. Liu, “Embedded nano-electro-
mechanical memory for energy-efficient reconfigurable logic,” IEEE
Electron Device Lett., vol. 37, no. 12, pp. 1563–1565, Dec. 2016.
[24] U. Sikder, L. P. Tatum, T.-T. Yen, and T.-J.-K. Liu, “Vertical NV-NEM
switches in CMOS back-end-of-line: First experimental demonstration
and array programming scheme,” in IEDM Tech. Dig., Dec. 2020,
pp. 2–21.
[25] K. Kato, V. Stojanovic, and T.-J. K. Liu, “Non-volatile nano-electro-
mechanical memory for energy-efficient data searching,” IEEE Electron
Device Lett., vol. 37, no. 1, pp. 31–34, Jan. 2016.
[26] J. Yoon, H. S. Kwon, and W. Y. Choi, “Multi-layer nanoelectromechan-
ical (NEM) memory switches for multi-path routing,” IEEE Electron
Device Lett., vol. 43, no. 1, pp. 162–165, Jan. 2022.
[27] R. Chan, R. Lesnick, D. Becher, and M. Feng, “Low-actuation volt-
age RF MEMS shunt switch with cold switching lifetime of seven
billion cycles,” J. Microelectromech. Syst., vol. 12, no. 5, pp. 713–719,
Oct. 2003.
[28] H. Kam, E. Alon, and T.-J. K. Liu, “A predictive contact reliability model
for MEM logic switches,” in IEDM Tech. Dig., Dec. 2010, pp. 4–16.
[29] B. Osoba, B. Saha, L. Dougherty, J. Edgington, C. Qian, F. Niroui,
J. H. Lang, V. Bulovic, J. Wu, and T.-J.-K. Liu, “Sub-50 mV NEM
relay operation enabled by self-assembled molecular coating,” in IEDM
Tech. Dig., Dec. 2016, pp. 8–26.
[30] C. Pawashe, K. Lin, and K. J. Kuhn, “Scaling limits of electro-
static nanorelays,” IEEE Trans. Electron Devices, vol. 60, no. 9,
pp. 2936–2942, Sep. 2013.
[31] Y.-H. Chen, W.-M. Chan, W.-C. Wu, H.-J. Liao, K.-H. Pan, J.-J. Liaw,
T.-H. Chung, Q. Li, G. H. Chang, C.-Y. Lin, M.-C. Chiang, S.-Y. Wu,
S. Natarajan, and J. Chang, “13.5 A 16nm 128Mb SRAM in high-κ
metal-gate FinFET technology with write-assist circuitry for low-VMIN
applications,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech.
Papers, Feb. 2014, pp. 238–239.