Solutions of MST

Q1a) The architecture of the processor can be differentiated on the basis of code and data memory
organization as:

Von-Neumann Harvard Architecture

➢ The data and program are stored in the ➢ The data and program memories are
same separate
Memory. ➢ Has separate buses for data and
➢ Share single common bus for data as well Instructions
as instruction fetching. fetching.

➢ Pipelining complex. Low performance as ➢ Easier to pipeline, so high performance

compared to Harvard ➢ Faster
➢ More costly
➢ Slow ➢ Wastage of memory
➢ Cheaper ➢ The data and instructions can be fetched
➢ Efficient utilization of memory space at the same time.
➢ The data and instructions can not be
fetched ➢ Harvard Mark I Computer
at the same time.
➢ John Von-Neumann

Von Neumann Architecture:

Harvard Architecture:
 The different instruction set architectures: CISC and RISC

1) CISC instructions operate on memory 1) RISC instructions operate mainly on

and registers registers
2) Generally multiple cycle instructions, 2) Generally single cycle instructions, fixed
variable length instructions length instructions
3) More addressing modes 3) Few addressing modes
4) Few Registers 4) Lots of registers
5) Instruction set large and complex 5) Instruction set reduced and simple
6) Decoding Complex 6) Decoding simple
7) Pipeline harder and poor 7) Pipeline easier and excellent
8) Small program for a specific task 8) Large program for a specific task
9) More emphasis on hardware 9) More emphasis on software
10) Use of Microprogrammed Control Unit 10) Use of Hardwired Control Unit
11) E.g. Intel, AMD X86 11) E.g. ARM, DLX, PIC

Q1b)

➢ R0=0x00001001
R1=00000073

➢ R0=0x00001000
R1=858B5A73

➢ R0=0x00001000
R1=0x00005A73

➢ R0=0x00001004
R1=3B19779F