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AEC Course Material
AEC Course Material
K. V. Jyothi Prakash
Assistant Professor
Course Outcomes: At the end of the course the student should be able to
CO1 Design clipper, Clamper components to provide solutions for communication
problems, to design rectifier to meet the power supply requirement. (L3)
CO2 Analyze characteristics of MOSFET to design biasing circuit for Amplifiers. (L3)
CO3 Analyze characteristics of MOSFET amplifiers using small signal model at low and
high frequencies. (L2)
CO4 Analyze and evaluate MOS differential Amplifiers. (L2)
CO5 Compare different negative feedback topologies. (L1)
CO6 Analyze and evaluate the performance of power amplifiers. (L2)
Unit-1
Applications of Diode: Analysis of full wave rectifier with capacitor filter - approximate
method to calculate ripple factor, Two level clipping circuits, Clamping circuits, Voltage
doublers. Special Diode Types: The Schottky-Barrier Diode (SBD), Varactors, LED and
Photo diode. 7 Hrs
Unit-2
Device Structure & Physical Operation : Device structure, Operation, iD - vDS Relationship
(qualitative analysis), Symbol, iD –vDS characteristics, Output Resistance in saturation, The
body effect, Temperature effect, Breakdown & Input protection, MOSFET Circuit at DC.
MOSFET as an Amplifier and as a Switch: Large signal operation-transfer characteristics,
Operation as a switch, Operation as a Linear Amplifier (qualitative analysis).
Biasing in MOS Amplifier Circuits: Biasing by fixing VGS, Biasing by fixing VG and
connecting a resistance in the source, Biasing Using a Drain to Gate feedback Resistor,
Constant-Current-Source Biasing (using current mirror). 8 Hrs
Unit-3
Small-Signal Operation and Models: DC Bias Point, Signal Current in the Drain Terminal,
Voltage Gain, Small-Signal equivalent-Circuit Models, Trans conductance gm, The T
equivalent Circuit model.
Single-Stage MOS Amplifiers: The Basic structure, Characterizing MOS Amplifiers,
Common Source Amplifier, Common Source Amplifier with Source Resistance, Common
Gate Amplifier (qualitative analysis), Common Drain Amplifier (qualitative analysis),
Comparison.
The MOSFET Internal Capacitance & High-Frequency Model: Gate Capacitance Effect,
Junction Capacitance, High-Frequency Model, Unity Gain frequency-fT. Frequency
Response of CS Amplifier (qualitative analysis) 8 Hrs
Unit-4
The MOS Differential Pair: Operation with a Common-Mode Input Voltage and
Differential Input voltage. Small-Signal Operation of the MOS Differential Pair: Differential
Gain and Common Mode Rejection Ratio Other Non-ideal Characteristics of the Differential
Amplifier: Input Offset Voltage of the Differential Pair, Input Common-Mode Range.
The Differential Amplifier with Active Load: Differential-to-Single-Ended Conversion,
Active-Loaded MOS Differential Pair, Differential Gain of the Active-Loaded MOS Pair,
Common Mode Gain and CMRR. 8 Hrs
Unit-5
Feedback Amplifiers: General Feedback Structure, Properties of Negative Feedback, Four
Basic Feedback Topologies-Series-Shunt, Series-Series, Shunt-Shunt & Shunt-Series
Amplifier (Qualitative Analysis).
Power Amplifiers: Introduction, Classification, Class A - Operation, Transfer
Characteristics, Signal Waveforms, Power Dissipation, Power Conversion efficiency
(qualitative analysis), Transformer Coupled Power Amplifiers (qualitative analysis), Class B
– operation, Transfer Characteristics, Power Dissipation, Power Conversion efficiency,
Reducing Cross-Over Distortion, Class AB – Operation, Output Resistance 8 Hrs
TEXT BOOK
1 Adel S. Sedra Kenneth Microelectronic Circuits : Theory and Applications, 5th
C. Smith Edition, Oxford International Student Edition, 10th
impression 2012.
REFERENCE BOOKS
1 Behzad Razavi Fundamentals of Microelectronics, Wiley Student Edition,
Reprint 2012.
2 Robert L. Boylestad and Electronic Devices and Circuit Theory. 11th Edition, PHI,
Louis Nashelsky. 2013.
CONTENTS
Syllabus
Unit-1 Applications of Diode 1
1.1 Full wave rectifier with Capacitor filter 1
1.1.1 Expression for ripple factor 2
1.2 Clipping circuits 5
1.2.1 Two level series clippers 5
1.2.2 Two level shunt clippers 6
1.2.3 Design 8
1.3 Clamping circuits 13
1.3.1 Negative clampers 13
1.3.2 Positive clampers 17
1.3.3 Design 22
1.4 Voltage multiplier 24
1.4.1 Half wave voltage doubler 24
1.4.2 Full wave voltage doubler 25
1.5 Special diode types 27
1.5.1 Schottky barrier diode 27
1.5.2 Varactors 28
1.5.3 Photo diode 29
1.5.4 Light emitting diode 30
Questions 31
A X +
+
Vi = Vm Sin t C
-
230 V
50 Hz
AC Supply Y -
Vi = Vm Sin t
Fig. 1.1 Centre tap full wave rectifier with ‘C’ filter
Working
During positive half cycle the diode D1 is forward biased in centre tap full wave
rectifier and diode D1 and D2 are forward biased in bridge rectifier. Hence the capacitor C
will charge from 0 V towards the peak value of input Vm. At , input Vi will be at Vm
and the charge on capacitor will also be equal to Vm, hence the diodes will turn off (since
both anode and cathode of diodes will be at same potential). Now the capacitor starts
discharging through the load RL, if the load is very light (load resistance is very high and load
current is low) the capacitor will discharge by a small amount, by that time next half cycle
charges the capacitor back to Vm. Thus the output voltage remains almost constant. The full
wave rectifier with ‘C’ filter waveform is shown in Fig. 1.3.
D4 D1
230V
50 Hz X
Vi = Vm Sin t
AC Supply
D3 D2 C +
-
B
Y
Fig. 1.2 Bridge rectifier with ‘C’ filter
Vi
Vm
0 2 t
Vo with ‘C’
Vo filter
Vm
Vrp-p
0 2 3 t
Problems :
P1. Design a bridge rectifier with C filter to have an output dc voltage 12V at load current
100 mA and ripple less than 5%.
Solution :
A
D4 D1
230V
50 Hz X
Vi = Vm Sin t
AC Supply
D3 D2 C +
-
B
Y
P3. Calculate the ripple voltage of a full wave rectifier with a 120 F capacitor connected
to a load of 60 mA, frequency of ac source is 50 Hz.
i) If the peak voltage of the rectified wave is 60 V. Calculate the DC voltage at
the output.
ii) If the capacitor value is doubled what will be the modified ripple voltage.
Solution :
i)
ii)
P3. A full wave bridge rectifier with a 120 V rms sinusoidal input has a load resistor of 1
K . Determine the required PIV rating of each diode.
Solution :
P4. A full wave rectifier with C filter is fed by a 50 Hz sinusoidal waveform and delivers
a load current of 100 mA with a peak to peak ripple voltage of 1 V. What is the value
of capacitor used?
Solution :
1. To pass positive peak above (VR1+V) level and negative peak above -(VR2+V) level
The clipping circuit to pass positive peak above (VR1+V) level and negative peak above
-(VR2+V) level is shown in Fig. 1.4, the waveform and transfer characteristics are shown
in Fig. 1.5.
, ,
Fig. 1.4 Clipping circuit to pass positive peak above (VR1+V) level and negative peak above
-(VR2+V) level
Vi
VO Slope = 1
(VR1+V) -(VR2+V)
-(VR2+V) t (VR1+V) Vi
Slope = 1
Vo
Fig. 1.5 Waveform and transfer characteristic of clipping circuit to pass positive peak above
(VR1+V) level and negative peak above -(VR2+V) level
i)
ii)
iii)
iv)
v)
Fig. 1.6 Clipping circuit to pass between (VR1+V) and –(VR2+V) level
Vi
VO
VR1+V
VR1+V
t
-(VR2+V) -(VR2+V)
VR1+V Vi
Vo
VR1+V -(VR2+V)
Slope = 1
t
-(VR2+V)
Fig. 1.7 Waveform and transfer characteristic of clipping circuit to pass between (VR1+V)
and –(VR2+V) level
i)
ii)
iii)
iv)
v)
Fig. 1.8 Clipping circuit to pass waveform between (VR1-V) and (VR2+V)
Vi
VR2+V VO
VR1-V
VR2+V
t
Slope = 1
VR1-V
Vo
VR1-V VR2+V Vi
VR2+V
VR1-V
t
Fig. 1.9 Waveform and transfer characteristic of clipping circuit to pass between (VR1-V)
and (VR2+V) level
i)
ii)
iii)
iv)
v)
When diode is ON the diode can be replaced by the forward resistance R f as shown in
Fig. 1.11.
When diode is ON, for ideal response entire input voltage Vi should fall across R
without any drop across Rf. This is possible only when
When diode is OFF the diode can be replaced by the reverse resistance R r as shown in
Fig. 1.12.
When diode is OFF, for ideal response entire input voltage Vi should fall across Rr
without any drop across R. This is possible only when
Problems :
P1. Design a clipping circuit to obtain the transfer characteristics shown in Fig. P1. Ad
sketch the input output waveform VO
Slope = 1
-2V
3V Vi
Slope = 1
Fig. P1
Solution :
3V
-2 V t
Vo
P2. The input to a clipping circuit is a sine wave of peak value 25 V. Design the
components values such that the output should have its positive peak clipped at 15 V
and negative peak clipped at -18 V. Sketch the circuit, input/output waveform and
transfer characteristics.
Solution :
Vi
VO
15 V
15 V
t
-18 V
-18 V
15 V Vi
Vo
15 V -18 V
Slope = 1
t
-18 V
P3. Design a clipper to obtain the transfer characteristics shown in Fig. P3. Sketch the
input / output waveform. (Assume V = 0.7 V)
VO
4V
Slope = 1
3V
3V 4V Vi
Fig. P3
Solution :
Vi
4V
3V
Vo
4V
3V
Fig. 1.13 Circuit to clamp positive peak to V level and the input / output waveform
Circuit operation
i) When Vi = + Vm (during positive half cycle), diode D is forward biased and
the capacitor charges as shown in Fig. 1.14.
ii) When Vi = -Vm (during negative half cycle), diode D is reverse biased and
the equivalent circuit is shown in Fig. 1.15.
Fig. 1.16 Circuit to clamp positive peak to VR + V level and the input / output waveform
Circuit operation
i) When Vi = + Vm (during positive half cycle), diode D is forward biased and the
capacitor charges as shown in Fig. 1.17.
ii) When Vi = -Vm (during negative half cycle), diode D is reverse biased and the
equivalent circuit is shown in Fig. 1.18.
Fig. 1.19 Circuit to clamp positive peak to –VR + V level and the input / output waveform
Circuit operation
i) When Vi = + Vm (during positive half cycle), diode D is forward biased and the
capacitor charges as shown in Fig. 1.20.
ii) When Vi = -Vm (during negative half cycle), diode D is reverse biased and the
equivalent circuit is shown in Fig. 1.21.
Fig. 1.22 Circuit to clamp negative peak to -V level and the input / output waveform
Circuit operation
i) When Vi = - Vm (during negative half cycle), diode D is forward biased and the
capacitor charges as shown in Fig. 1.23.
ii) When Vi = +Vm (during positive half cycle), diode D is reverse biased and the
equivalent circuit is shown in Fig. 1.24.
Fig. 1.25 Circuit to clamp negative peak to -VR-V level and the input / output waveform
Circuit operation
i) When Vi = - Vm (during negative half cycle), diode D is forward biased and the
capacitor charges as shown in Fig. 1.26.
ii) When Vi = +Vm (during positive half cycle), diode D is reverse biased and the
equivalent circuit is shown in Fig. 1.27.
Fig. 1.28 Circuit to clamp negative peak to VR-V level and the input / output waveform
Circuit operation
i) When Vi = - Vm (during negative half cycle), diode D is forward biased and the
capacitor charges as shown in Fig. 1.29.
ii) When Vi = +Vm (during positive half cycle), diode D is reverse biased and the
equivalent circuit is shown in Fig. 1.30.
Problems
P1. Design clamping circuit to clamp negative peak to zero level. Assume V = 0.6 V.
Solution :
P2. Design a suitable circuit represented by the box shown in Fig. P2, which has the input
and output waveforms as indicated. (Assume V = 0.6 V)
Vi VO
10 V 2.7 V
Circuit using
silicon t
t diodes
-10 V
-17.3 V
Solution :
,
P3. Design a clamping circuit to obtain an output with positive peak at 20 V and negative
peak at –10 V. The input is a square wave of 15 V at 1 KHz. Assume silicon diode.
Solution :
,
Circuit operation
During the first negative half cycle diode D1 is forward biased and D2 is reverse
biased. Hence the capacitor C1 charges to Vm (Assuming ideal diode with V = 0) as shown in
Fig. 1.33.
During the next positive half cycle diode D1 is reverse biased and D2 is forward
biased. Hence the input voltage Vi and the charge present on capacitor C1 together will
charge capacitor C2 to 2Vm, hence VO = 2 Vm as shown in Fig. 1.34. Hence the output voltage
is double of the input voltage.
During the positive half cycle diode D1 is forward biased and D2 is reverse biased.
Hence the capacitor C1 charges to Vm (Assuming ideal diode with V = 0) as shown in Fig.
1.36.
During the negative half cycle diode D1 is reverse biased and D2 is forward biased.
Hence the capacitor C2 charges to Vm (Assuming ideal diode with V = 0) as shown in Fig.
1.37.
A normal p-n junction diode allows a small amount of electric current under reverse
bias condition. To increase the electric current under reverse bias condition, we need to
generate more minority carriers. The external reverse voltage applied to the p-n junction
diode will supply energy to the minority carriers but not increase the population of minority
carriers. When external energy (light) is directly applied to the depletion region more charge
carriers are generated in depletion region.
The different materials used to construct photodiodes are Silicon (Si), Germanium,
(Ge), Gallium Phosphide (GaP), Indium Gallium Arsenide (InGaAs), Indium Arsenide
Antimonide (InAsSb), Extended Range Indium Gallium Arsenide (InGaAs), Mercury
Cadmium Telluride (MCT, HgCdTe).
Photodiode applications
Compact disc players
Smoke detectors
Space applications
Medical applications such as computed tomography, instruments to analyze
samples, and pulse oximeters
Optical communications
LEDs are available in different colors and they are widely used in display devices
Questions (1 or 2 Marks)
1. In a full wave rectifier if C = 1000 F and RL = 1 K , calculate ripple factor.
2. Draw clamping circuit to clamp positive peak to +3 V (assume ideal diode).
3. Draw full wave voltage doubler circuit.
4. A full wave bridge rectifier with a 120V rms sinusoidal input has a load resistance of
1K . Determine the required PIV rating of each diode.
5. Mention about schottky barrier diode.
6. Discuss the working of voltage doubler.
7. A full wave rectifier with C filter is fed by a 50 Hz sinusoidal waveform and delivers
a load current of 100 mA with a peak to peak ripple voltage of 1 V. What is the value
of capacitor used?
8. Design a clamping circuit to clamp negative peak of a sine wave at +4V. Assume Si
diode.
9. The photo diode is operated under ____________ biased and LED is operated under
________ biased condition.
Questions (Descriptive) / Problems
1. Calculate the ripple voltage of a full wave rectifier with a 120 F capacitor connected
to a load of 60 mA, frequency of ac source is 50 Hz.
i) If the peak voltage of the rectified wave is 60 V. Calculate the DC voltage at
the output.
ii) If the capacitor value is doubled what will be the modified ripple voltage.
2. Design clamping circuit to clamp negative peak to zero level. (Assume V = 0.6 V).
3. With the help of circuit diagram and waveform, explain the working of full wave
rectifier with ‘C’ filter. Derive the expression for ripple factor.
4. Design a suitable circuit represented by the box shown in Fig. P2, which has the input
and output waveforms as indicated. (Assume V = 0.6 V)
Vi VO
10 V 2.7 V
Circuit using
silicon t
t diodes
-10 V
-17.3 V
5. Design a clamping circuit to obtain an output with positive peak at 20 V and negative
peak at –10 V. The input is a square wave of 15 V at 1 KHz. Assume silicon diode.
6. The input to a clipping circuit is a sine wave of peak value 25 V. Design the
components values such that the output should have its positive peak clipped at 15 V
and negative peak clipped at -18 V. Sketch the circuit, input/output waveform and
transfer characteristics.
7. Write short notes on SBD and varactor diodes.
8. Design a clipper circuit which limits the input ssignal Vi = 10 Sin t between +5V
and -3V. (Assume V = 0.7 V).
9. Design a clamper circuit which clamps positive peak of a input signal at -2 V. Input
signal is square wave with amplitude 5 V and frequency 1 KHz.
10. With the help of a neat circuit diagram, explain the working of a voltage doubler.
11. What is a light emitting diode? Explain its working and mention any one application
of it.
12. Design a clipping circuit to obtain the transfer characteristics shown in Fig. P1. Ad
sketch the input output waveform VO
Slope = 1
-2V
3V Vi
Slope = 1
Fig. P1
13. The input to a clipping circuit is a sine wave of peak value 25 V. Design the
components values such that the output should have its positive peak clipped at 15 V
and negative peak clipped at -18 V. Sketch the circuit, input/output waveform and
transfer characteristics.
14. Design a clipper to obtain the transfer characteristics shown in Fig. P3. Sketch the
input / output waveform. (Assume V = 0.7 V)
VO
4V
Slope = 1
3V
3V 4V Vi
In this chapter one of the very important three terminal semiconductor device Metal
Oxide Semiconductor Field Effect Transistor (MOSFET) will be discussed. MOSFET is most
commonly used in the design of integrated circuits (ICs) both in analog and digital circuits.
MOSFET is a voltage controlled, unipolar device which can be used as switch and
amplifier. The classification of MOSFETs can be done as
MOSFET
n+ n+
p – Substrate
B
(a)
(Substrate / Bulk)
S G D
Enlarged
n+ n+ depletion layer
p – Substrate
S G D
Depletion layer
n+ n+
L
Induced n-type
p – Substrate channel
Fig. 2.3 Channel formation when VDS = 0 and VGS > Vt is applied
After the channel is induced with the application of VGS > Vt, if a voltage is applied
between drain and source (VDS) current flows through the channel induced, correspondingly
this MOSFET is called an n-channel MOSFET (NMOS). NMOS is created on p-substrate and
the channel is created by inverting the substrate surface from p to n-type hence the channel is
called inversion layer.
The gate and the channel region form a parallel plate capacitor with the oxide layer
acting as insulator (dielectric). The positive gate voltage causes positive charge to accumulate
on top plate (gate) and the negative charge on the bottom plate. An electric field is developed
in the vertical direction which controls the amount of charge in the channel which determines
the channel conductivity in turn the current that flow through the channel when VDS is
applied.
VDS
VGS > Vt
S G D
n+ n+
ID
p – Substrate
Fig. 2.4 Flow of ID when small VDS and VGS > Vt are applied
ID
VGS3
VGS2
VGS1 > Vt
VDS
Fig. 2.5 Linear drain current, ID at small value of VDS
VDS
VGS > Vt
S G D
n+ n+
Tapered channel
p – Substrate
Fig. 2.6 Tapered channel when VDS and VGS > Vt are applied
As VDS is increased channel becomes more tapered and its resistance increases
correspondingly, thus the ID - VDS curve does not continue as a straight line but bends as
shown in Fig. 2.7.
Saturation
ID VDS = VDS sat
region
Curve bends because of
increase in channel VDS > VGS - Vt
VGS > Vt
resistance
(Linear) Curve saturates because
the channel is pinched
off
When VDS is increased such that VDS = VGS - Vt, the channel is said to be pinched off.
Increasing VDS beyond this value has little effect on channel shape and current saturates,
hence MOSFET will enter saturation region as shown in Fig. 2.8. The voltage at which
saturation occurs is denoted as
n+ n+
Channel
Source Drain
G B G B G G
S S S S
G Gate
Simplified symbol when source is
D Drain connected to the body (bulk)
S Source
B Body or Bulk
The spacing between the two vertical lines represent the gate electrode insulated from
the body of the device
The drain is always positive with respect to source in an n-channel MOSFET
Even though the drain and source are clearly distinguished, in practice the polarity of
the voltage impressed across it determines source and drain
ID
+ RD
IG = 0
VDS VDD
+
VGG VGS
- -
(a)
VGS1 > Vt
Fig. 2.10 (a) Circuit to plot ID - VDS characteristics (b) ID - VDS characteristics of NMOSFET
The characteristic curve indicates that there are three distinct regions of operation
namely the cut off region, the triode / ohmic / linear region and the saturation region.
The saturation region is used to operate MOSFET as an amplifier. The cut off and
triode / ohmic / linear region are used to operate MOSFET as switch (Open switch in cutoff
region and closed switch in triode / ohmic / linear region).
To operate MOSFET in cut off region VGS < Vt and to operate in triode / ohmic /
linear region, first the channel must be induced by applying VGS > Vt and then VDS should be
maintained small, that is VDS < VGS - Vt.
In triode region the ID - VDS characteristics can be described as
Thus in saturation drain current is independent of VDS and is determined by the gate
voltage VGS, hence the saturated MOSFET behaves as an ideal current source whose value is
controlled by VGS. The transfer characteristic of MOSFET (ID versus VGS) is shown in Fig.
2.11.
ID
Vt VGS
Fig. 2.11 Transfer characteristics of NMOSFET
The circuit representation of MOSFET in saturation region is shown in Fig. 2.12 and
is called as large signal equivalent circuit model
In boundary between triode and saturation region, where VDS = VGS – Vt, the drain
current,
n+ n+
Channel
Source Drain
- VD Sat = VGS - Vt +- + VDS – VD Sat
L
L - L L
The voltage across the channel remains constant at (VGS - Vt) = VD Sat and the
additional voltage applied to the drain appears as a voltage drop across the narrow depletion
region between the drain and the end of the channel. This voltage accelerates the electrons
that reach the drain end of the channel and sweeps them across the depletion region into the
drain.
This concept of channel length reduced from L to L - L is known as channel length
modulation. Since ID is inversely proportional to L, ID increases with VDS.
Considering the channel length modulation
The ID - VDS characteristics showing the channel length modulation effect is shown in
Fig. 2.14.
VGS2
VGS1 > Vt
-VA = - VDS
Fig. 2.14 ID - VDS characteristics showing the channel length modulation effect
This term is
independent of VDS
By incorporating rO the large signal model can be written as shown in Fig. 2.15.
extends through the channel to the source. The drain current then increases rapidly (It is not
permanent damage).
Another kind of breakdown occurs when the gate to source voltage exceeds (30 V).
This is the breakdown of the gate oxide and results in permanent damage to the device. To
prevent this usually gate protection devices (clamping diodes) are used at the input terminals
of MOSFET.
2.5 V
ID RD
VD
RS
-2.5 V
Fig. P1
Solution :
P2. Design the circuit shown in Fig. P2 to obtain ID = 80A. Find the value of R and VD.
Let NMOS have Vt = 0.6, n Cox = 200A / V2, L = 0.8 m and W = 4 m. Assume
= 0. 3V
VD
Fig. P2
Solution :
P3. Design the circuit shown in Fig. P3 to establish a drain voltage of 0.1 V. What is the
effective resistance between D and S at this operating voltage? Let V t = 1V and
5V
RD
0.1 V
Fig. P3
Solution :
iD Saturation region
Triode / Ohmic /
Linear region
VGS4
C VGS3
B
Q VGS2
VGS1 > Vt
A
VDS = VO
From the transfer characteristics when Vi < Vt, MOSFET will be cutoff and iD = 0
hence VO = VDD point ‘A’ in transfer curve.
As Vi increases beyond Vt, the transistor turns on, iD increases and VO decreases.
Since VO will be initially high transistor will be operating in the saturation region. This
corresponds to segment of the load line from A to B and the point identified in this region of
operation is labeled as Q – operating point.
Saturation region operation continues until VO decreases to the point that it is below
Vi by Vt. At this point VDS = VGS – Vt and the device enters triode region, indicated as point
‘B’. For Vi > ViB, the transistor is driven more deeper into the triode region.
At Point ‘C’ when Vi = VDD, output voltage VOC will be very small.
If the operating point Q selected is close to VDD, the positive signal of output will be
clipped off, since device enters triode region. If Q point is selected close to 0the negative
signal of output will be clipped since device enters in to cutoff region. Hence the Q point
should be selected in middle of the graph.
The values of Vt, Cox and vary among devices manufactured by same manufacturers.
Further Vt and n depend on temperature, hence if we fix VGS, ID will not be constant. ID
becomes very much temperature dependent.
If VG is much greater than VGS, ID will be mostly determined by the values of VG and
RS.
Even if VG is not larger than VGS, RS provides negative feedback which stabilize the
bias current ID which is shown in Fig. 2.20.
ID ID VGS
VS
Two possible practical implementations of this biasing circuit are shown in Fig. 2.22.
From equation if ID tries to increase, VGS has to decrease since VDD is constant,
hence ID remains constant
(a)
(b)
Fig. 2.24 (a) MOSFET biased with constant current source (b) Current Mirror
In the current mirror circuit, the drain of transistor Q1 is shorted to the gate and thus
operating in the saturation region, hence
Now consider transistor Q2, it has the same VGS as Q1 hence it is assumed that Q2 is
also operating in saturation region. The drain current, ID2 of Q2 which is the desired current
‘I’ of the current source will be
Problems :
P1. Design a MOSFET biasing circuit by fixing VG and connecting a resistance in the
source to establish a DC drain current ID = 0.5 mA. The MOSFET has Vt = 1V,
. Assume = 0 and VDD = 15 V.
Solution :
P2. Design the circuit shown in Fig. P2 to operate at a DC drain current of 0.5 mA and VD
= 2V. Let Vt = 1V, , = 0 and VDD = VSS = 5V.
Fig. P2
Solution :
P3. Design the circuit shown in Fig. P3 to operate at a DC drain current of 0.5 mA and
VDD = 5V. Let Vt = 1V, , = 0.
Fig. P3
Solution :
P4. Design a current mirror circuit to bias a MOSFET amplifier at a constant current of
1mA. Let VDD = VSS = 5V, Vt = 1V, , = 0.
Solution :
Questions (1 or 2 Marks)
1. What should be the condition of VGS and VDS in triode region?
2. In which region the MOSFET is operated as open and closed switch.
3. Draw the small signal equivalent circuit model of the N channel MOSFET and write
the expression for rO.
4. A large feedback resistance is connected from drain to gate in a MOSFET. What is
the DC voltage at the gate.
5. What is the effect of temperature on MOSFET performance?
6. Discuss the effect of temperature on drain current in NMOSFET.
7. A n-channel MOSFET has , and overdrive voltage of 0.5V. Find
8. Design the circuit shown in Fig. 8.a so that the transistor operates at ID = 0.4mA and
VD = 0.5V. The NMOS transistor has Vt = 0.7 V, n Cox = 100A / V2, L = 1m, W =
32 m. Assume = 0 (neglect channel length modulation).
2.5 V
ID RD
VD
RS
-2.5 V
Fig. 8.a
9. Design a MOSFET biasing circuit by fixing VG and connecting a resistance in the
source to establish a DC drain current ID = 0.5 mA. The MOSFET has Vt = 1V,
, = 0 and VDD = 15 V. (Assume equal voltages across RD and RS)
10. Design the circuit shown in Fig. 10.a to obtain ID = 80A. Find the value of R and VD.
Let NMOS have Vt = 0.6, n Cox = 200A / V2, L = 0.8 m and W = 4 m. Assume
= 0. 3V
R
VD
Fig. 10.a
11. Design the circuit shown in Fig. P3 to establish a drain voltage of 0.1 V. What is the
effective resistance between D and S at this operating voltage? Let V t = 1V and
5V
RD
0.1 V
Fig. P3
VDD
RD
The first term in the equation is DC bias current, the second term is directly
proportional to the applied input signal and the third term in the equation is
undesirable since it is non linear distortion. To reduce this non linear distortion the input
signal should be kept small so that
If this small signal condition is satisfied then the non linear distortion can be
neglected and can be expressed as
Negative sign indicates 180 out of phase of output signal with input signal
The total instantaneous voltages and are shown in Fig. 3.2.
drain. The input resistance is very high, ideally infinity and output resistance seen from drain
terminal is , putting all together we arrive at the small signal model or small signal
equivalent circuit of the MOSFET as shown in Fig. 3.3.
The equivalent circuit drawn by replacing the MOSFET by its small signal model is
shown in Fig.3.4.
VDD
RD
Fig. 3.4 Equivalent circuit drawn by replacing MOSFET by its small signal model
Fig. 3.7 Common source amplifier biased with constant current source
The equivalent circuit of the amplifier by replacing the MOSFET by its equivalent
small signal model and transferring all components from circuit on to the equivalent circuit is
shown in Fig. 3.8. All capacitors have to be replaced by short circuit, voltage sources to be
replaced by short circuit and current sources should be replaced by open circuit.
Fig. 3.8 Equivalent circuit of common source amplifier replacing the MOSFET by its
equivalent small signal model
The equivalent circuit of the amplifier by replacing the MOSFET by its equivalent
small signal T - model (Since the source is not directly connected to ground) and transferring
all components from circuit on to the equivalent circuit is shown in Fig. 3.10.
Fig. 3.10 Equivalent circuit of common source amplifier with source resistance
replacing the MOSFET by its equivalent small signal T – model
Note :
Common gate amplifier is a non inverting amplifier, that is output signal will be in
phase with the input signal
Common gate amplifier has low input resistance hence the circuit is
more suitable to feed signal current source
The common gate amplifier with signal current source as input is shown in Fig. 3.13
Fig. 3.13 Common gate amplifier with signal current source as input
1. Gate capacitance : Since the gate material is separated by the channel by an insulator
(SiO2) it forms a parallel plate capacitor called oxide capacitor (Cox)
2. The source – body and drain – body depletion layer capacitances : These are the
capacitances formed by reverse biased pn - junctions of N+ source and P substrate and
N+ drain and P substrate.
These two capacitive effects can be modeled by including capacitances in the
MOSFET model between its four terminals G, D, S and B (bulk). There will be five
capacitances in total Cgs, Cgd, Cgb, Csb and Cdb.
S D
Cgs Cgd
2. When MOSFET operates in saturation region the channel tapered and pinched off
near drain end hence G
S Cgs D
Cgd = 0
4. Additional small capacitance component that should be added to Cgs and Cgd in all the
preceding formulas is the capacitance that that result due to source and drain
diffusions extended slightly under the gate oxide. If the overlap length is LOV then the
overlap capacitance is given by G
S LOV D
When the source is connected to the bulk (body) the model simplifies as shown in Fig. 3.17.
Fig. 3.17 High frequency equivalent circuit of MOSFET when body connected to source
Fig. 3.18 High frequency equivalent circuit of MOSFET when body connected to source and
Cdb is neglected
Note :
Midband
All capacitances can be neglected
Low High
frequency frequency
band band
The gain falls off in the low frequency band due to higher impedance of coupling
capacitors CC1 and CC2 and by pass capacitor Cs
The gain falls off in the high frequency band due to lower impedance of junction
capacitors (internal capacitors) Cgs and Cgd
The 3 dB bandwidth of amplifier,
Problems :
P1. For the common source amplifier shown in Fig. P1, if Rsig = 1K , RG = 4.7M ,
RD = 10K , I = 0.5 mA, CS = 50F, CC1 = CC2 = 0.1 F, RL = 15K , VDD = 15V and
VSS = -10V, find Rin, Rout, AV, AVO and GV. Given VA = 50V, and
= 0.
Fig. P1
Solution :
Replacing MOSFET by its appropriate model and drawing the equivalent circuit
P2. In a common gate amplifier if Rsig = 1K , RD = 10K , I = 0.5 mA, CC1 = CC2 = 0.1
F, RL = 100 K , VDD = 15V and VSS = -10V, find Rin, Rout, AV, AVO and GV. Given
Replacing MOSFET by its appropriate model and drawing the equivalent circuit
P3. In a common source MOSFET amplifier if Rsig = 1K , RG = 4.7 M , Cgs = 1pF, Cgd
Solution :
P4. Calculate unity gain frequency (fT) for an n - channel MOSFET, given Cgs = 30 fF,
Cgd = 2 fF, and ID = 0.5 mA.
Solution :
P5. Find midband gain AM and the upper 3 dB frequency fH of a common source amplifier
fed with a signal source having an internal resistance Rsig = 100 K . The amplifier
has RG = 4.7 M , RD = RL = 15 K . gm = 1mA / V, ro = 150 K , Cgs = 1 pF and Cgd
= 0.4 pF.
Solution :
Questions (1 or 2 Marks)
1. In a MOSFET circuit if and ID = 0.5 mA, calculate gm.
2. Calculate fT for n-channel MOSFET for the specifications given Cgs = 44.7 fF and Cgd
= 3.72 fF, and ID = 0.2 mA.
3. Sketch the frequency response of common source amplifier and mark different
regions.
4. Draw relevant diagram to determine short circuit current gain Io / Ii on NMOSFET.
Write the expression for fT.
5. Give reasons for fall of gain at low and high frequencies in a CS amplifier.
6. An n-channel MOSFET has Cgs = 30 fF and Cgd = 2 fF, gm = 0.4 mA / V and
calculate the unity gain frequency fT.
biasing voltages are VGS = 4V, VDS = 5V, Vt = 0.8V, and for
9. With the help of frequency response curve of common source amplifier, explain the
reason for reduction in gain in low and high frequency region.
10. Discuss the MOSFET internal capacitances with relevant diagram and draw the high
frequency model of MOSFET.
11. In a common drain amplifier if Rsig = 100 , RG = 5.3 M , ID = 0.5 mA, CC1 = CC2 =
0.1 F, RL = 100 K , VDD = 15V and VSS = -10V, find Rin, Rout, AV, AVO and GV.
Amplifier (A)
Fig. 4.3 MOS differential pair with common mode input voltage VCM
Now if the common mode voltage VCM is varied, the current I will divide equally
between Q1 and Q2 as long as the transistors remain in saturation region, hence the output
voltage will be zero. Thus the differential pair rejects the common mode input signal VCM.
The lowest value of VCM is determined by the need to allow for a sufficient voltage
across current source I for it to operate properly. If a voltage VCS is needed across the current
source then
Fig. 4.4 MOS differential pair with differential input voltage Vid
Assume that vGS1 is fixed such that the entire current I flows through Q1 and vGS2 = Vt then
Thus the current I can be steered from one transistor to other by varying Vid in the
range
Problems :
P1. In a MOS differential amplifier with a common mode voltage, VCM applied. Let VDD
= VSS = 1.5 V, , Vt = 0.5V, I = 0.4mA, RD = 2.5 K , = 0. Find
(i)
(ii)
(iii)
(iv)
(v)
(vi)
(i)
(ii)
(iii)
Fig. 4.5 MOS differential amplifier with a common mode voltage applied to set the DC bias
voltage at the gates and with vid applied in a complementary manner
and
VCM denotes a common mode DC voltage within the input common mode range of
the differential amplifier. Typically VCM is at the middle value of power supplies, when two
complementary supplies are utilised VCM = 0.
Equivalent circuit for small signal analysis is shown in Fig. 4.6.
Fig. 4.7 MOS differential amplifier with rO and RSS and equivalent circuit
4.2.2 Common mode gain and common mode rejection ratio (CMRR)
The common mode
The MOS differential amplifier with common mode signal vicm applied and equivalent
circuit is shown in Fig. 4.8.
Fig. 4.8 MOS differential amplifier with common mode signal vicm applied and equivalent
circuit
The symmetry of the circuit enables us to break it into two identical halves known as
CM half circuit.
Neglecting the effect of rO we can write the expression for gain as
Common Source amplifier with RS,
discussed in unit - III
Problems :
P1. A MOS differential pair is operated at a total bias current of 0.8mA, using transistors
with a ratio of 100, , VA = 20V and RD = 5K . Find VOV, gm,
rO and Ad.
Solution :
P2. A MOS differential pair operated at a bias current of 0.8mA employs transistor with a
= 100 and , using RD = 5K and RSS = 25K .
i) Find the differential gain, common mode gain and CMRR (in dB) if the output
is taken single endedly and the circuit is perfectly matched.
ii) Repeat (i) when the output is taken differentially
iii) Repeat (i) when the output is taken differentially when drain resistance have
1% mismatch
iv) Repeat (i) when the output is taken differentially when gm have 2% mismatch
Solution :
i)
ii)
iii)
iv)
Now let us consider the case where Q1 and Q2 are perfectly matched but RD1 and RD2
show a mismatch ΔRD that is
Such a mismatch causes the current I to no longer divide equally between Q1 and Q2 hence
Now we consider the effect of a mismatch between the two threshold voltages
Problems :
P1. A MOS differential pair operated at a bias current of 0.8mA employs transistor with a
= 100 and , using RD = 5K and RSS = 25K . Find the three
Solution :
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 100
3REC01 Analog Electronic Circuits III Semester E&C Engg.
If output is taken between two drains the differential gain will be double and much
reduced common mode gain of output taken at one of the drain with respect to ground.
Assume the two input terminals are connected to a DC voltage equal to the common
mode equilibrium value, in this case 0V as shown in Fig. 4.12.
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 101
3REC01 Analog Electronic Circuits III Semester E&C Engg.
Assuming perfect matching the bias current I divide equally between Q1 and Q2. The
drain current of Q1 is fed to the input transistor of the mirror, Q3. Thus a replica of this
current is provided by the output transistor of the mirror Q4. Observe at the output node the
two currents balance each other out, leaving a zero current to flow out to the next stage or
load. If Q4 is perfectly matched with Q3, the drain voltages of both the MOS will be same.
Hence the output voltage at equilibrium is . But in practical case there will always
be mismatches which cause a large deviation in output voltage from the ideal value.
Consider the circuit with a differential input voltage applied as shown in Fig. 4.13
Since we are doing small signal analysis DC sources are removed and the output
resistance rO of all transistors is ignored. Transistor Q1 will conduct a drain signal current
and transistor Q2 will conduct equal and opposite current i. The drain signal
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 102
3REC01 Analog Electronic Circuits III Semester E&C Engg.
Even though the circuit is not symmetrical, when the output is shorted to ground, the
circuit becomes almost symmetrical. This is because the voltage between the drain of Q1 and
ground is very small because the low resistance between the node and ground which is equal
to 1 / gm3. Hence we can assume a virtual ground at source of Q1 and Q2, in this way the
equivalent circuit is written.
The voltage vg3 that develops at the common gate line of the mirror can be found as
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 103
3REC01 Analog Electronic Circuits III Semester E&C Engg.
The current i that enters Q2 must exist at its source. It then enters Q1 existing at the
drain to feed the feed the Q3 - Q4 mirror. Since of transistor Q3 is much smaller than
rO3, most of the current i will flow in to the drain of Q4 which determines the relation
between i and vx
Now Q2 is a common gate (CG) transistor has in its source the input resistance of Q1
which is connected in the CG configuration (Q1) with a small resistance in the drain
(approximately ) thus its input resistance is approximately
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 104
3REC01 Analog Electronic Circuits III Semester E&C Engg.
From the circuit shown in Fig. 4.15, we can write at the output node
Even though the output is single ended, the active loaded MOS differential has low
common mode gain and correspondingly high CMRR. Even though the circuit is not
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 105
3REC01 Analog Electronic Circuits III Semester E&C Engg.
symmetrical and hence we cannot use the common mode half circuit, we can split RSS equally
between Q1 and Q2 as shown in Fig. 4.16. It can now be seen that each of Q1 and Q2 is a
common source transistor with a large source degeneration resistance 2RSS. Since 2RSS is
much larger than of each of Q1 and Q2, the signal at the source terminals will be
approximately equal to vicm.
Note that RO1 will be much greater than the parallel resistance introduced by
Q3
Similarly RO2 will be much greater than rO4. Hence RO1and RO2 can be easily neglected
while finding the total resistance between each of the drain nodes and ground.
Transistor rO4 senses this voltage and hence provides a drain current i4
At the output node the current difference between i4 and i2 passes through rO4 (Since
RO2 >> rO4) to provide vO
Substituting for i1 and i2 and setting gm3 = gm4 it can be simplified with manipulation
as
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 106
3REC01 Analog Electronic Circuits III Semester E&C Engg.
Problem :
Solution :
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 107
3REC01 Analog Electronic Circuits III Semester E&C Engg.
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 108
3REC01 Analog Electronic Circuits III Semester E&C Engg.
Questions (1 or 2 Marks)
1. Write the circuit diagram of MOS differential pair.
2. Define the terms differential gain and input offset voltage of differential MOS pair.
3. Define the term CMRR of differential MOS pair and write the expression for CMRR.
4. A MOS differential pair is operated at a total bias current of 0.8mA. Using MOSFET
with a W/L ratio of 100. nCox = 0.2mA/V2 rO = 50K and RD = 5K . Find gm.
5. Draw the diagram of MOS differential pair to represent the output DC offset voltage.
a. Find the differential gain, common mode gain and CMRR (in dB) if the output
is taken single endedly and the circuit is perfectly matched.
b. Repeat (a) when the output is taken differentially
c. Repeat (a) when the output is taken differentially when drain resistance have
1% mismatch
d. Repeat (a) when the output is taken differentially when gm have 2% mismatch
7. Draw the basic MOS differential pair circuit and show how it can be modified to
operate with a common mode input voltage Vcm. Derive an expression for the voltage
at each drain terminal VD.
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 109
3REC01 Analog Electronic Circuits III Semester E&C Engg.
8. With relevant diagram derive an expression for CMRR of MOS differential pair.
9. Draw the circuit diagram of of a resistively loaded MOS differential pair and explain
its working.
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 110
3REC01 Analog Electronic Circuits III Semester E&C Engg.
Feedback is a process of combining a part of output signal with input signal. There are
two types of feedback namely positive feedback (regenerative feedback) and negative
feedback (degenerative feedback).
Mixer
Basic
+ Amplifier (A)
-
Feedback
network ()
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 111
3REC01 Analog Electronic Circuits III Semester E&C Engg.
From the expression the gain of the feedback amplifier is determined by the feedback
network, which consists of only passive components hence the gain is more stable with
feedback.
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 112
3REC01 Analog Electronic Circuits III Semester E&C Engg.
Hence the percentage change in Af is smaller than the percentage change in A.
2. Bandwidth extension
Consider an amplifier whose high frequency response is characterized by a single
pole. Its gain at mid and high frequencies can be expressed as
Application of negative feedback with a frequency independent factor () around this
amplifier results in a closed loop gain Af(s) given by
Hence the bandwidth of the amplifier is increased by the same factor by which its
midband gain is decreased.
3. Noise reduction
Negative feedback can be employed to reduce the noise in an amplifier or to increase
the noise to signal ratio
Vn
Vs A1 Vo
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 113
3REC01 Analog Electronic Circuits III Semester E&C Engg.
Vn
+ +
Vs A2 A1 Vo
Vo
- -
- +
In the amplifier without feedback shown in Fig. 5.2 the signal to noise ratio is given
by
Vi (V)
In the graph shown in figure curve (a) represents amplifier transfer characteristics
without feedback and curve (b) represents amplifier transfer characteristics with
feedback. The amplifier characteristic is more linear with feedback compared to
without feedback.
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 114
3REC01 Analog Electronic Circuits III Semester E&C Engg.
Feedback
network
Basic Current IO
IS RS amplifier RL
If If
IO
Feedback
network
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 115
3REC01 Analog Electronic Circuits III Semester E&C Engg.
RS
+
Basic IO
VS Transconductance RL
- + amplifier
- Vf
IO
Feedback
network
Basic
RS Transresistance RL VO
IS
amplifier
If If
Feedback
network
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 116
3REC01 Analog Electronic Circuits III Semester E&C Engg.
Ii RO
+ + + +
Ri AVi
VS Vi VO
- - + - -
-
VO Basic Amplifier
Rif ROf
+ +
VO VO
- -
Feedback Network
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 117
3REC01 Analog Electronic Circuits III Semester E&C Engg.
To find output resistance, ROf Set VS = 0, apply a test voltage Vt at the output
terminals which drives a current I, then
RO
I
AVi Vt
+
VS = 0 Ri
Vi
-
- Vf +
Vf = VO
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 118
3REC01 Analog Electronic Circuits III Semester E&C Engg.
Ii IO
+ +
VS Vi Ri RO
AVi
- - + -
IO
Rif ROf
+
IO IO
-
IS Ri AIi RO
If
Rif ROf
IO IO
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 119
3REC01 Analog Electronic Circuits III Semester E&C Engg.
Ii
RO
IS Ri AIi VO
If
Rif ROf
VO
Problems :
P1. An amplifier has bandwidth of 200 KHz and voltage gain of 1000. What should be the
amount of feedback if the bandwidth received is 1 MHz.
Solution :
P2. An amplifier with a voltage gain of 100 and bandwidth of 100 KHz is provided with
3% negative feedback. What are the values of gain and bandwidth after feedback.
Solution :
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 120
3REC01 Analog Electronic Circuits III Semester E&C Engg.
P3. Calculate the loop gain (A) of a negative feedback amplifier if Af = 20 and = 1%.
Solution :
P4. In a series shunt feedback amplifier, the basic voltage amplifier has gain 120, input
resistance 1M and output resistance 75 , if 0.2% of output signal is fed back to the
input, what will be the modified gain, input resistance and output resistance.
Solution :
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 121
3REC01 Analog Electronic Circuits III Semester E&C Engg.
Class - A Stage
Class - B Stage
The Class - B stage is biased at zero
current, hence transistor conducts for
only 180 that is half the cycle of input
sine wave as shown in Fig. 5.13. Since
transistor conducts half the cycle of input
Fig. 5.13 Collector current in Class - B power efficiency is good and the output
Stage will be distorted.
To overcome this problem one more transistor will be used in Class - B mode to obtain the
negative half cycle.
Class - AB Stage
An intermediate class between A and
B appropriately named Class - AB
involves biasing the transistor at a non
zero dc current much smaller than the
peak current of the sine wave signal.
Fig. 5.14 Collector current in Class - AB As a result transistor conducts for an
Stage
interval slightly greater than half a
cycle as shown in Fig. 5.14.
The resulting conduction angle is greater than 180 but much less than 360.
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 122
3REC01 Analog Electronic Circuits III Semester E&C Engg.
Class - C Stage
In Class - C stage the transistor
conducts for an interval shorter than
that of a half cycle, that is the
conduction angle is less than 180 as
shown in Fig. 5.15 hence the collector
Fig. 5.15 Collector current in Class - C current is periodically pulsating
Stage
waveform.
In class - C stage the power efficiency is very good but output is distorted. To overcome this
problem parallel LC circuit is used at output tuned to the frequency of the input signal.
The transistor Q1 is biased with a constant current I supplied by transistor Q2. Since
the emitter current the bias current I must be greater than the largest negative
load current. Otherwise Q1 cuts off and Class - A operation will no longer be maintained. The
transfer characteristic of the emitter follower is shown in Fig. 5.17.
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 123
3REC01 Analog Electronic Circuits III Semester E&C Engg.
In the negative direction depending on the value of I and R L, the limit of the linear
region is determined either by Q1 turning off
or by Q2 saturating
this is achieved provided the bias current I is greater than the magnitude of the
corresponding load current
Signal waveform
Consider the operation of emitter follower circuit shown in Fig. 5.16 for sine wave
input. Neglecting VCESat, if the bias current I is properly selected, the output voltage can
swing from –VCC to +VCC with the quiescent value being zero and the corresponding
waveforms VCE1 = VCC –vO are shown in Fig. 5.18. Assuming that the bias current I is
selected to allow a maximum negative load current of the collector current of Q1
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 124
3REC01 Analog Electronic Circuits III Semester E&C Engg.
Power dissipation
When input is zero, the maximum power dissipation in Q1 is VCC I hence the
transistor Q1 must be capable of withstanding this power. When R L = , is constant
and the instantaneous power dissipation in Q1 will depend on the instantaneous value of vO.
The maximum power dissipation will occur when vO = -VCC, for this case VCE1 = 2 VCC and
pD1 = 2 VCC I.
When RL = 0, the load current will be infinity, hence current through Q1 is very large
resulting in large power dissipation, if this condition persist for long duration Q1 may burn
up. The maximum power dissipation of Q2 is also 2 VCC I.
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 125
3REC01 Analog Electronic Circuits III Semester E&C Engg.
In a voltage follower assuming the output voltage will take up the maximum value
and minimum value
Hence Class - A output stage is rarely used in high power applications
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 126
3REC01 Analog Electronic Circuits III Semester E&C Engg.
zero, hence slope is infinity. AC load line is drawn with slope where is ac
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 127
3REC01 Analog Electronic Circuits III Semester E&C Engg.
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 128
3REC01 Analog Electronic Circuits III Semester E&C Engg.
Circuit operation
When Vi = 0, both transistors are in cut off and the output voltage, VO = 0. As input
increases in positive direction and exceeds 0.5 V (V) QN conducts and operates as emitter
follower, that is VO = Vi – VbeN and QN supplies load current. When input increases in
negative direction by more than 0.5 V, QP turns on and acts as emitter follower and supplies
load current, the output voltage, VO = Vi + VEBP or VO = Vi - VBEP
Transfer characteristics
The transfer characteristics of Class - B output stage is shown in Fig. 5.24. From the
figure it is clear that near origin both transistors will be cutoff and VO = 0. This dead band
results with cross over distortion is shown in Fig. 5.25.
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 129
3REC01 Analog Electronic Circuits III Semester E&C Engg.
Fig. 5.25 Cross over distortion (dead zone) in class - B output stage
Power dissipation
The maximum power dissipation in NPN transistor and PNP transistor is,
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 130
3REC01 Analog Electronic Circuits III Semester E&C Engg.
A bias voltage VBB is applied between the base of QN and QP. When input, Vi = 0 the
output VO = 0 and voltage appears across base to emitter junction of each of QN and QP.
Circuit operation
When Vi goes positive, the voltage at the base of QN increases by the same amount
and the output becomes positive
The positive VO causes a current IL to flow through RL and thus IN must increase that
is
The increase in iN will increase VBEN, since the voltage between the two bases remain
constant at VBB, the increase in VBEN results in decrease in VEBP and hence iP hence
Thus as iN increases, iP decreases by the same ratio while the product remains constant
combining equation and yields
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 131
3REC01 Analog Electronic Circuits III Semester E&C Engg.
From the equation discussed above, it can be seen that for positive output voltages the
load current is supplied by QN and mean while QP conducts a current that decreases as VO
increases which can be neglected for large VO. For negative input voltage the opposite
occurs.
The transfer characteristics of Class - AB output stage is shown in Fig. 5.27.
The class - AB output stage operates almost in the same manner as class - B with an
exception that for small Vi both transistors conduct and as Vi increases or decreases one of
the two transistors take over the operation. Since the transition is smooth cross over distortion
will be eliminated.
The power relationship in the class - AB output stage is almost identical to those
discussed for class - B output stage. The only difference is under quiescent conditions class -
AB circuit dissipates a power of VCC IQ per transistor and since IQ is usually much smaller
than the peak current the quiescent power is negligible.
Output resistance
The equivalent circuit of class - AB output stage to determine output resistance is
shown in Fig. 5.28.
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 132
3REC01 Analog Electronic Circuits III Semester E&C Engg.
Problems :
P1. A transformer coupled class - A power amplifier supplies power to an 80 load
connected across the secondary of a step down transformer having a turn ration 5:1.
Determine the maximum power output for a zero signal collector of 120 mA.
Solution :
P2. A Class - B push pull amplifier is supplied with VCC = 50 V, the signal brings the
collector voltage down to Vmin = 5 V. The total dissipation from both transistors is 40
W. Find the total power and conversion efficiency.
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 133
3REC01 Analog Electronic Circuits III Semester E&C Engg.
Solution :
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 134
3REC01 Analog Electronic Circuits III Semester E&C Engg.
Questions (1 or 2 Marks)
6. A Class - B push pull amplifier is supplied with VCC = 50 V, the signal brings the
collector voltage down to Vmin = 5 V. The total dissipation from both transistors is 40
W. Find the total power and conversion efficiency.
7. Mention any two advantages of negative feedback amplifier.
8. What is the maximum conversion efficiency of class - A power amplifier (transformer
coupled) and class - B push pull amplifier?
9. Define the terms i) Gain de-sensitivity and ii) Bandwidth extension as applicable to
negative feedback.
10. An amplifier has a bandwidth of 200 KHz and voltage gain of 1000. What should be
the amount of feedback with the bandwidth received is 1 MHz.
11. An amplifier with a voltage gain of 100 and bandwidth of 100 KHz is provided with 3
% negative feedback. What are the values of gain and bandwidth after feedback?
12. Draw the general structure of a negative feedback amplifier.
13. The theoretical value of of transformer coupled class A power amplifier is ______
and that of class B power amplifier is ________.
14. Calculate the open loop gain (A) of a negative feedback amplifier if Af = 20 and =
1%.
15. How cross over distortion is reduced in Class AB amplifiers?
16. In feedback amplifiers, feedback factor of the feedback network is represented by
_________ and is less than or equal to ________.
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 135
3REC01 Analog Electronic Circuits III Semester E&C Engg.
6. With neat sketch, explain transformer coupled class - B push pull amplifier.
7. Compare class - A and transformer coupled class - A output stages.
8. Discuss different types of feedback topologies.
9. With neat circuit diagram and transfer characteristics, explain class - B output stage
and show how cross over distortion can be reduced.
10. Discuss transformer coupled class - A output stage and explain the advantages of it
over class - A output stage.
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 136