Department of Electrical Engineering

SEECS, NUST

EE 421: Digital System Design

Spring 2024

Lab - 06

Finite State Machines

Department of Electrical Engineering, SEECS, NUST

Version 1.1 – Feb 29, 2024
© Copyright Rapid Silicon

Page 1 of 6
1. Objective

The purpose of these laboratory exercises is to design finite state machines in Verilog.

2. Finite State Machinesliegisters

Finite State Machines (FSM) are sequential circuits used in many digital systems to control
the behaviour of systems and data flow paths. Examples of FSM include control units and
sequencers. This lab introduces the concept of two types of FSMs, Mealy and Moore, and
the modelling styles to develop such machines.

The state machines are modelled using two basic types of sequential networks- Mealy and
Moore.

In a Mealy machine, the output depends on both the present (current) state and the present
(current) inputs. In the Moore machine, the output depends only on the present state. A
general model of a Mealy sequential machine consists of a combinatorial network, which
generates the outputs and the next state, and a state register which holds the present state
as shown below. The state register is normally modelled as D flip-flops. The state register
must be sensitive to a clock edge. The other block(s) can be modelled either using the
always procedural block or a mixture of the always procedural block and dataflow modelling
statements; the always procedural block will have to be sensitive to all inputs being read into
the block and must have all output defined for every branch in order to model it as a
combinatorial block. The two blocks Mealy machine can be viewed as

Figure 1. A generic representation of Finite State Machine (FSM)

A Moore State Machine is a type of finite state machine (FSM) where the outputs are
determined solely by the current state of the machine, independent of the inputs. This means
that the output associated with a state is fixed and does not change until the machine
transitions to a different state. The fundamental characteristic of a Moore machine is that the
output is a function of the state only.

Figure 2. Mealy State Machine Model

Department of Electrical Engineering, SEECS, NUST

Version 1.1 – Feb 29, 2024
© Copyright Rapid Silicon

Page 2 of 6
Consider an example of a 4-bit sequence detector

module SequenceDetector(
input clk, // Clock input
input reset, // Asynchronous reset input
input in_bit, // Serial input bit
output reg detected // Output signal indicating sequence detection
);

// Define states
reg [2:0] state, next_state;
parameter IDLE = 3'b000,
S1 = 3'b001, // State after receiving '1'
S2 = 3'b010, // State after receiving '11'
S3 = 3'b011, // State after receiving '110'
S4 = 3'b100; // State after receiving '1101' (sequence detected)

// State transition logic

always @(posedge clk or posedge reset) begin
if (reset)
state <= IDLE;
else
state <= next_state;
end

// Next state logic based on the current state and input bit
always @(*) begin
case (state)
IDLE: next_state = in_bit ? S1 : IDLE;
S1: next_state = in_bit ? S2 : IDLE;
S2: next_state = in_bit ? S2 : S3;
S3: next_state = in_bit ? S4 : IDLE;
S4: next_state = IDLE;
default: next_state = IDLE;
endcase
end

// Output logic: Detected signal goes high when in S4

always @(posedge clk) begin
if (reset)
detected <= 1'b0;
else if (state == S4)
detected <= 1'b1;
else
detected <= 1'b0;
end

endmodule

Department of Electrical Engineering, SEECS, NUST

Version 1.1 – Feb 29, 2024
© Copyright Rapid Silicon

Page 3 of 6
The above Verilog code implements a sequence detector module that detects a specific
sequence of bits in a serial input stream. Here's a breakdown of how it works:

The system has the following Inputs and outputs:

clk, Clock input used for synchronous operation.

reset, Asynchronous reset input used to reset the state machine.
in_bit, Serial input bit that is being analysed for the desired sequence.
Outputs:

detected is an output signal indicating whether the desired sequence has been detected.
States:

The module has five states defined by the parameter key word IDLE, S1, S2, S3, and S4.
Each state represents a different stage in the sequence detection process.

State Transition Logic:

The state register is updated based on the current state and the input bit.So it is a mealy
machine.

The state transition logic is defined in the always @(posedge clk or posedge reset) block. It
uses a case statement to determine the next state based on the current state and the input
bit.

Output Logic:

The detected output signal is set high (1'b1) when the sequence detection is successful (i.e.,
when the state machine reaches state S4). The output logic is defined in the always
@(posedge clk) block. It sets detected to high when the state machine is in state S4.

Task 1(a) : Simulation and Implementation of Sequence Detector

● Simulate and Implement the Sequence Detector code given in the example.

● Use slide switches to set the sequence to be detected.

● Use a Push Button as the Clock Source, and Receive the Serial Input via a Slide
Switch.

● Visualize the Previous 4 Inputs and the Single Bit Output on LEDs.

Task 1(b) : Sequence Detector with count

Department of Electrical Engineering, SEECS, NUST

Version 1.1 – Feb 29, 2024
© Copyright Rapid Silicon

Page 4 of 6
 ● Add a counter module in your design to count the number of times that specific
sequence occurs.

● Use push buttons to reset the counter.Display the counter value on a seven segment
display.

Task 2 : Digital Lock Using FSM

Design a Digital Lock using FSM having following specifications:

● First Set a specific fixed password in registers.

● Use 2 state FSM to implement the Digital Lock.

● Use 4 switches for the user to enter the password.

● Use an "Open" push button for the user to submit the entered password. And use a
"Close" push button to close the LOCK.

● For password entry, User presses the "Open" push button after entering the
password, the FSM will verify the entered password against the fixed password.

● If the entered password is correct, move to UNLOCKED state and display "OPEN"
on the Seven-Segment displays.

● If the entered password is incorrect, stay in the lock state and display "CLOS" on the
Seven-Segment displays

Task 3 : Extended Digital Lock Using FSM

● Modify the above task and add one more state to handle consecutive fails.

● If the user enters the wrong password consecutively for the third time the system
should move to the failed state and display "FAIL" on the Seven-Segment Displays.

● Stay in Failed state for 5 seconds, use counter to add 5 second delay. After a 5
second delay, move to the LOCK stage again.

3. Learning Outcomes Checklist

After this lab, you will be able to:

Department of Electrical Engineering, SEECS, NUST

Version 1.1 – Feb 29, 2024
© Copyright Rapid Silicon

Page 5 of 6
🗹 State encoding in finite state machine

🗹 FSM next state transition logic and output logic to generate outputs

Department of Electrical Engineering, SEECS, NUST

Version 1.1 – Feb 29, 2024
© Copyright Rapid Silicon

Page 6 of 6