Combinational Logic Circuit:

Block Diagram of Combinational Logic Circuit:

Points to Remember on Combinational Logic Circuit:

1. Output depends upon the combination of inputs.
2. Output is a pure function of present inputs only i.e., Previous State
inputs won’t have any effect on the output. Also, It doesn’t use
memory.
3. In other words,
OUTPUT=f(INPUT)
1. Inputs are called Excitation from circuits and outputs are called
Responses of combinational logic circuits.
Classification of Combinational Logic Circuits:

Arithmetic:
● Adders
● Subtractors
● Multipliers
● Comparators
2. Data Handling:
● Multiplexers
● DeMultiplexers
● Encoders and Decoders
3. Code Converters:
● BCD to Excess-3 code and vice versa
● BCD to Gray code and vice versa
 ●Seven Segment
Design of Half Adders and Full Adders:
● A combinational logic circuit that performs the addition of two
single bits is called Half Adder.
● A combinational logic circuit that performs the addition of three
single bits is called Full Adder.
1. Half Adder:

●It is a arithmetic combinational logic circuit designed to perform

addition of two single bits.
● It contain two inputs and produces two outputs.
● Inputs are called Augend and Added bits and Outputs are called
Sum and Carry.
Let us observe the addition of single bits,

0+0=0
0+1=1
1+0=1
1+1=10
Since 1+1=10, the result must be two bit output. So, Above can be rewritten
as,
0+0=00
0+1=01
1+0=01
1+1=10
The result of 1+1 is 10, where ‘1’ is carry-output (Cout) and ‘0’ is Sum-output
(Normal Output).
Truth Table of Half Adder:

Next Step is to draw the Logic Diagram. To draw Logic Diagram, We need
Boolean Expression, which can be obtained using K-map (karnaugh map).
Since there are two output variables ‘S’ and ‘C’, we need to define K-map for
each output variable.
K-map for output variable Sum ‘S’:

K-map is of Sum of products form. The equation obtained is

S = AB' + A'B
which can be logically written as,
S = A xor B
K-map for output variable Carry ‘C’:

The equation obtained from K-map is,

C = AB
Using the Boolean Expression, we can draw logic diagram as follows..

Limitations: Adding of Carry is not possible in Half adder.

2. Full Adder:

● To overcome the above limitation faced with Half adders, Full

Adders are implemented.
● It is a arithmetic combinational logic circuit that performs addition of
three single bits.
● It contains three inputs (A, B, Cin) and produces two outputs (Sum
and Cout).
● Where, Cin -> Carry In and Cout -> Carry Out
Truth table of Full Adder:
K-map Simplification for output variable Sum ‘S’ :

The equation obtained is,

S = A'B'Cin + AB'Cin' + ABC + A'BCin'
The equation can be simplified as,
S = B'(A'Cin+ACin') + B(AC + A'Cin')
S = B'(A xor Cin) + B (A xor Cin)'
S = A xor B xor Cin
K-map Simplification for output variable ‘Cout‘

The equation obtained is,

Cout = BCin + AB + ACin
Logic Diagram of Full Adder:
Full Adder is the adder that adds three inputs and produces two outputs. The
first two inputs are A and B and the third input is an input carry as C-IN. The
output carry is designated as C-OUT and the normal output is designated as
S which is SUM. The C-OUT is also known as the majority 1’s detector,
whose output goes high when more than one input is high. A full adder logic
is designed in such a manner that can take eight inputs together to create a
byte-wide adder and cascade the carry bit from one adder to another. we use
a full adder because when a carry-in bit is available, another 1-bit adder
must be used since a 1-bit half-adder does not take a carry-in bit. A 1-bit full
adder adds three operands and generates 2-bit results.
 Full Adder logic circuit.

Implementation of Full Adder using Half Adders:

2 Half Adders and an OR gate is required to implement a Full Adder.

With this logic circuit, two bits can be added together, taking a carry from the
next lower order of magnitude, and sending a carry to the next higher order
of magnitude.
Implementation of Full Adder using NAND gates:

Implementation of Full Adder using NOR gates:

Total 9 NOR gates are required to implement a Full Adder.

In the logic expression above, one would recognize the logic expressions of a
1-bit half-adder. A 1-bit full adder can be accomplished by cascading two
1-bit half adders.

Advantages and Disadvantages of Full Adder in Digital Logic

Advantages of Full Adder in Digital Logic:
1.Flexibility: A full snake can add three information bits, making it more
flexible than a half viper. It can likewise be utilized to add multi-bit numbers
by binding different full adders together.
2.Carry Info: The full viper has a convey input, which permits it to perform
expansion of multi-bit numbers and to chain different adders together.
3.Speed: The full snake works at an extremely fast, making it reasonable for
use in rapid computerized circuits.
Disadvantages of Full Adder in Digital Logic:
1.Complexity: The full snake is more mind boggling than a half viper and
requires more parts like XOR, AND, or potentially entryways. It is likewise
more challenging to execute and plan.
2.Propagation Deferral: The full viper circuit has a proliferation delay, which
is the time it takes for the result to change in light of an adjustment of the
info. This can cause timing issues in computerized circuits, particularly in fast
frameworks.
Application of Full Adder in Digital Logic:
1.Arithmetic circuits: Full adders are utilized in math circuits to add twofold
numbers. At the point when different full adders are associated in a chain,
they can add multi-bit paired numbers.
2.Data handling: Full adders are utilized in information handling applications
like advanced signal handling, information encryption, and mistake
rectification.
3.Counters: Full adders are utilized in counters to addition or decrement the
count by one.
4.Multiplexers and demultiplexers: Full adders are utilized in multiplexers
and demultiplexers to choose and course information.
5.Memory tending to: Full adders are utilized in memory addressing circuits
to produce the location of a particular memory area.
6.ALUs: Full adders are a fundamental part of Number juggling Rationale
Units (ALUs) utilized in chip and computerized signal processors.

Half Subtractor in Digital Logic

A half subtractor is a digital logic circuit that performs binary subtraction of

two single-bit binary numbers. It has two inputs, A and B, and two outputs,
DIFFERENCE and BORROW. The DIFFERENCE output is the difference
between the two input bits, while the BORROW output indicates whether
borrowing was necessary during the subtraction.
The half subtractor can be implemented using basic gates such as XOR and
NOT gates. The DIFFERENCE output is the XOR of the two inputs A and B,
while the BORROW output is the NOT of input A and the AND of inputs A
and B.
Half Subtractor
Half subtractor is a combination circuit with two inputs and two outputs that
are different and borrow. It produces the difference between the two binary
bits at the input and also produces an output (Borrow) to indicate if a 1 has
been borrowed. In the subtraction (A-B), A is called a Minuend bit and B is
called a Subtrahend bit.

Advantages of Half Adder and Half Subtractor

1. Simplicity: The half adder and half subtractor circuits are simple
and easy to design, implement, and debug compared to other binary
arithmetic circuits.
2. Building blocks: The half adder and half subtractor are basic
building blocks that can be used to construct more complex
arithmetic circuits, such as full adders and subtractors, multiple-bit
adders and subtractors, and carry look-ahead adders.
3. Low cost: The half adder and half subtractor circuits use only a few
gates, which reduces the cost and power consumption compared to
more complex circuits.
4. Easy integration: The half adder and half subtractor can be easily
integrated with other digital circuits and systems.

Disadvantages of Half Adder and Half Subtractor

1. Limited functionality: The half adder and half subtractor can only
perform binary addition and subtraction of two single-bit numbers,
respectively, and are not suitable for more complex arithmetic
operations.
2. Inefficient for multi-bit numbers: For multi-bit numbers, multiple
half adders or half subtractors need to be cascaded, which increases
the complexity and decreases the efficiency of the circuit.
3. High propagation delay: The propagation delay of the half adder
and half subtractor is higher compared to other arithmetic circuits,
which can affect the overall performance of the system.
Application of Half Subtractor in Digital Logic:
1.Calculators: Most mini-computers utilize advanced rationale circuits to
perform numerical tasks. A Half Subtractor can be utilized in a number
cruncher to deduct two parallel digits from one another.
2.Alarm Frameworks: Many caution frameworks utilize computerized
rationale circuits to identify and answer interlopers. A Half Subtractor can be
utilized in these frameworks to look at the upsides of two parallel pieces and
trigger a caution in the event that they are unique.
3.Automotive Frameworks: Numerous advanced vehicles utilize
computerized rationale circuits to control different capabilities, like the motor
administration framework, stopping mechanism, and theater setup. A Half
Subtractor can be utilized in these frameworks to perform computations and
examinations.
4.Security Frameworks: Advanced rationale circuits are usually utilized in
security frameworks to identify and answer dangers. A Half Subtractor can
be utilized in these frameworks to look at two double qualities and trigger a
caution in the event that they are unique.
5.Computer Frameworks: Advanced rationale circuits are utilized broadly in
PC frameworks to perform estimations and examinations. A Half Subtractor
can be utilized in a PC framework to deduct two paired values from one
another.

● It is a combinational logic circuit designed to perform the

subtraction of two single bits.
● It contains two inputs (A and B) and produces two outputs
(Difference and Borrow-output).
Truth Table of Half Subtractor:
K-map Simplification for output variable ‘D’:

The equation obtained is,

D = A'B + AB'
which can be logically written as,
D = A xor B
K-map Simplification for output variable ‘Bout‘ :
The equation obtained from above K-map is,
Bout = A'B
Logic Diagram of Half Subtractor:

Full Subtractor in Digital Logic

A full subtractor is a combinational circuit that performs subtraction of two
bits, one is minuend and other is subtrahend, taking into account borrow of
the previous adjacent lower minuend bit. This circuit has three inputs and
two outputs. The three inputs A, B and Bin, denote the minuend, subtrahend,
and previous borrow, respectively. The two outputs, D and Bout represent
the difference and output borrow, respectively. Although subtraction is
usually achieved by adding the complement of subtrahend to the minuend, it
is of academic interest to work out the Truth Table and logic realisation of a
full subtractor; x is the minuend; y is the subtrahend; z is the input borrow; D
is the difference; and B denotes the output borrow. The corresponding maps
for logic functions for outputs of the full subtractor namely difference and
borrow.

Here’s how a full subtractor works:

1. First, we need to convert the binary numbers to their two’s complement
form if we are subtracting a negative number.
2. Next, we compare the bits in the minuend and subtrahend at the
corresponding positions. If the subtrahend bit is greater than or equal to the
minuend bit, we need to borrow from the previous stage (if there is one) to
subtract the subtrahend bit from the minuend bit.
3. We subtract the two bits along with the borrow-in to get the difference bit.
If the minuend bit is greater than or equal to the subtrahend bit along with
the borrow-in, then the difference bit is 1, otherwise it is 0.
4. We then calculate the borrow-out bit by comparing the minuend and
subtrahend bits. If the minuend bit is less than the subtrahend bit along with
the borrow-in, then we need to borrow for the next stage, so the borrow-out
bit is 1, otherwise it is 0.

The circuit diagram for a full subtractor usually consists of two

half-subtractors and an additional OR gate to calculate the borrow-out bit.
The inputs and outputs of the full subtractor are as follows:
Inputs:
A: minuend bit
B: subtrahend bit
Bin: borrow-in bit from the previous stage
Outputs:
Diff: difference bit
Bout: borrow-out bit for the next stage
Truth Table –
From above table we can draw the K-Map as shown for “difference” and

“borrow”.

Logical expression for difference –

D = A’B’Bin + A’BBin’ + AB’Bin’ + ABBin
= Bin(A’B’ + AB) + Bin’(AB’ + A’B)
= Bin( A XNOR B) + Bin’(A XOR B)
= Bin (A XOR B)’ + Bin’(A XOR B)
= Bin XOR (A XOR B)
= (A XOR B) XOR Bin
Logical expression for borrow –
Bout = A’B’Bin + A’BBin’ + A’BBin + ABBin
= A’B’Bin +A’BBin’ + A’BBin + A’BBin + A’BBin + ABBin
= A’Bin(B + B’) + A’B(Bin + Bin’) + BBin(A + A’)
= A’Bin + A’B + BBin

OR
Bout = A’B’Bin + A’BBin’ + A’BBin + ABBin
= Bin(AB + A’B’) + A’B(Bin + Bin’)
= Bin( A XNOR B) + A’B
= Bin (A XOR B)’ + A’B
Logic Circuit for Full Subtractor –

Implementation of Full Subtractor using Half Subtractors – 2 Half

Subtractors and an OR gate is required to implement a Full Subtractor.

● t is a Combinational logic circuit designed to perform subtraction of

three single bits.
● It contains three inputs(A, B, Bin) and produces two outputs (D, Bout).
● Where, A and B are called Minuend and Subtrahend bits.
● And, Bin -> Borrow-In and Bout -> Borrow-Out
Truth Table of Full Subtractor:

K-map Simplification for output variable ‘D’ :

he equation obtained from above K-map is,

D = A'B'Bin + AB'Bin' + ABBin + A'BBin'
which can be simplified as,
D = B'(A'Bin + ABin') + B(ABin + A'Bin')
D = B'(A xor Bin) + B(A xor Bin)'
D = A xor B xor Bin
K-map Simplification for output variable ‘Bout‘ :

The equation obtained is,

Bout = BBin + A'B + A'Bin

Logic Diagram of Full Subtractor:

Applications:
 1. For performing arithmetic calculations in electronic calculators and
other digital devices.
2. In Timers and Program Counters.
3. Useful in Digital Signal Processing.

Parallel Adder and Parallel Subtractor

Parallel Adder –
A single full adder performs the addition of two one bit numbers and an
input carry. But a Parallel Adder is a digital circuit capable of finding the
arithmetic sum of two binary numbers that is greater than one bit in length
by operating on corresponding pairs of bits in parallel. It consists of full
adders connected in a chain where the output carry from each full adder is
connected to the carry input of the next higher order full adder in the chain. A
n bit parallel adder requires n full adders to perform the operation. So for
the two-bit number, two adders are needed while for four bit number, four
adders are needed and so on. Parallel adders normally incorporate carry
lookahead logic to ensure that carry propagation between subsequent stages
of addition does not limit addition speed.

Working of parallel Adder –

1. As shown in the figure, firstly the full adder FA1 adds A1 and B1
along with the carry C1 to generate the sum S1 (the first bit of the
output sum) and the carry C2 which is connected to the next adder
in chain.
2. Next, the full adder FA2 uses this carry bit C2 to add with the input
bits A2 and B2 to generate the sum S2(the second bit of the output
 sum) and the carry C3 which is again further connected to the next
adder in chain and so on.
3. The process continues till the last full adder FAn uses the carry bit
Cn to add with its input An and Bn to generate the last bit of the
output along last carry bit Cout.
Parallel Subtractor –
A Parallel Subtractor is a digital circuit capable of finding the arithmetic
difference of two binary numbers that is greater than one bit in length by
operating on corresponding pairs of bits in parallel. The parallel subtractor
can be designed in several ways including combination of half and full
subtractors, all full subtractors or all full adders with subtrahend
complement input.

Working of Parallel Subtractor –

1. As shown in the figure, the parallel binary subtractor is formed by
combination of all full adders with subtrahend complement input.
2. This operation considers that the addition of minuend along with
the 2’s complement of the subtrahend is equal to their subtraction.
3. Firstly the 1’s complement of B is obtained by the NOT gate and 1
can be added through the carry to find out the 2’s complement of B.
This is further added to A to carry out the arithmetic subtraction.
4. The process continues till the last full adder FAn uses the carry bit
Cn to add with its input An and 2’s complement of Bn to generate
the last bit of the output along last carry bit Cout.
Advantages of parallel Adder/Subtractor –
1. The parallel adder/subtractor performs the addition operation faster
as compared to serial adder/subtractor.
 2. Time required for addition does not depend on the number of bits.
3. The output is in parallel form i.e all the bits are added/subtracted at
the same time.
4. It is less costly.
Disadvantages of parallel Adder/Subtractor –
1. Each adder has to wait for the carry which is to be generated from
the previous adder in chain.
2. The propagation delay( delay associated with the travelling of carry
bit) is found to increase with the increase in the number of bits to be
added.
Note:
Subtraction of two binary numbers can be accomplished by adding 2’s
complement of the subtrahend to the minuend and disregarding the final
carry if any. If the MSB bit in the result of addition is a ‘0’. then the result of
addition is the correct answer. If the MSB bit is a ‘1’. , this implies that the
answer has a negative sign. The true magnitude, in this case, is given by 2’s
complement of the result of the addition.