DTM w22 22323

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION
(Autonomous)
(ISO/IEC - 27001 - 2005 Certified)
WINTER – 2022 EXAMINATION

MODEL ANSWER
Subject: Digital Techniques & Microprocessor Subject Code: 22323
Important Instructions to examiners:

1) The answers should be examined by key words and not as word-to-word as given
in the model answer scheme.
2) The model answer and the answer written by candidate may vary but the examiner
may try to assess the understanding level of the candidate.
3) The language errors such as grammatical, spelling errors should not be given more
Importance (Not applicable for subject English and Communication Skills.
4) While assessing figures, examiner may give credit for principal components
indicated in the figure. The figures drawn by candidate and model answer may
vary. The examiner may give credit for anyequivalent figure drawn.
5) Credits may be given step wise for numerical problems. In some cases, the
assumed constant values may vary and there may be some difference in the
candidate’s answers and model answer.
6) In case of some questions credit may be given by judgement on part of examiner
of relevant answer based on candidate’s understanding.
7) For programming language papers, credit may be given to any other program
based on equivalent concept.
8) As per the policy decision of Maharashtra State Government, teaching in
English/Marathi and Bilingual (English + Marathi) medium is introduced at first year
of AICTE diploma Programme from academic year 2021-2022. Hence if the
students in first year (first and second semesters) write answers in Marathi or
bilingual language (English +Marathi), the Examiner shall consider the same and
assess the answer based on matching of concepts with model answer.
Q. Sub Answer Marking

No Q.N. Scheme
1. Attempt any FIVE of the following: 10
a) Compare TTL and CMOS Logic families 2M
Ans. TTL CMOS Any two
points 1M
TTL stands for Transistor- CMOS stands for
each
Transistor Logic. The name is Complementary Metal Oxide
derived from the use of two Semiconductor.
Bipolar Junction Transistors or
BJTs in the design of each logic
gate.
TTL is a classification of CMOS is another
integrated circuits. classification of ICs that uses
field effect transistors in the
design.
The density of logic gates is less The primary advantage of
in TTL as compared to CMOS. CMOS chips to TTL chips is
in the greater density of logic
Page 1 / 18
(Autonomous)

MODEL ANSWER
gates within the same

material.
A single gate on a TTL chip can An equivalent single gate in a
consume around 10mW of power. CMOS chip can consume
around 10nW.
TTL chips are lesser delicate and CMOS chips are a bit more
is not very susceptible to delicate compared to TTL
electrostatic discharge. chips when it comes to
handling as it is quite
susceptible to electrostatic
discharge.
TTL chips do not have CMOS There are CMOS chips that
logic. have TTL logic and are meant
as replacements for TTL
chips.
TTL circuits consume more CMOS circuits consume less
power compared to CMOS power at rest.
circuits at rest.
b) Draw symbol of EX.OR gate and also write its truth table. 2M
Ans. Symbol 1M
Truth table
1M
c) State the role of preset and clear terminal in flip-flop. 2M

Ans. In the Flip-Flop with clocked circuit, when power is first applied to a 1M for each
flip-flop circuit, the initial logical state of the outputs can be Preset and
clear
completely random (Uncertain).This uncertainty in its switching is
undesired. It can be overcome by using two additional asynchronous
inputs referred to as Preset (PR) and Clear (CLR).
These additional inputs allow the flip-flop to be cleared, (Q = 0)
whenever the CLEAR input is “0”, and the PRESET input is “1”.
The flip-flop can be preset to the logic “1” state whenever the
PRESET input is “0” and the CLEAR input is “1”.
If the PRESET and CLEAR inputs are active HIGH (P = CLR = 1)
then the circuit operates as a normal gated SR flip-flop circuit.
Page 2 / 18
(Autonomous)

MODEL ANSWER
d) State the different triggering methods in digital circuits. 2M

Ans. Triggering methods are classified as- Any two
 Level Triggering type
1M for each
 Positive level triggering type
 Negative level triggering
 Edge Triggering
i. Positive edge triggering
ii. Negative edge triggering
e) Enlist the names of segment registers in 8086 Microprocessor. 2M
Ans. There are four segment registers in 8086 microprocessor- Four types
i. Data Segment register DS ½M each
ii. Code segment register CS
iii. Stack segment register SS
iv. Extra segment register ES
f) List any two addressing modes of 8086 with example. 2M
Ans. Addressing modes of 8086: Any 2
1. Immediate addressing mode: addressing
modes with
An instruction in which 8-bit or 16-bit operand (data) is specified in example
the instruction, then theaddressing mode of such instruction is known 1M each
as Immediate addressing mode.
Example:
MOV AX, 67D3H
2. Register addressing mode

An instruction in which an operand (data) is specified in general
purpose registers, then the addressingmode is known as register
addressing mode.
Example:
MOV AX, CX
3. Direct addressing mode

An instruction in which 16 bit effective address of an operand is
specified in the instruction, then theaddressing mode of such
instruction is known as direct addressing mode.
Example:
MOV CL, [2000H]
4. Register Indirect addressing mode
An instruction in which address of an operand is specified in pointer
register or in index register or inBX, then the addressing mode is
known as register indirect addressing mode.
Page 3 / 18
(Autonomous)

MODEL ANSWER
Example:
MOV AX, [BX]
5. Indexed addressing mode

An instruction in which the offset address of an operand is stored in
index registers (SI or DI) then theaddressing mode of such instruction
is known as indexed addressing mode.
DS is the default segment for SI and DI.
For string instructions DS and ES are the default segments for SI and
DI respectively this is a special case of register indirect addressing
mode.
Example:
MOV AX,[SI]
6. Based Indexed addressing mode

an instruction in which the address of an operand is obtained by
adding the contents of base register(BX or BP) to the content of an
index register (SI or DI)The default segment register may be DS or
ES
Example:
MOV AX, [BX][SI]
7. Register relative addressing mode

An instruction in which the address of the operand is obtained by
adding the displacement (8-bit or 16bit) with the contents of base
registers or index registers (BX, BP, SI, DI). the default segment
registeris DS or ES
Example:
MOV AX, 50H[BX]
8. Relative Based Indexed addressing mode

An instruction in which the address of the operand is obtained by
adding the displacement (8 bit or16 bit) with the base registers (BX or
BP) and index registers (SI or DI) to the default segment.
Example:
MOV AX, 50H [BX][SI]
2. Attempt any THREE of the following: 12

a) Perform binary subtraction using 2's complement method for 4M
(12)10- (08)10
Page 4 / 18
(Autonomous)

MODEL ANSWER
Ans. (12)10= (1100)2

(08)10= (1000)2 Binary
conversion
2‟s complement of (08)10 = (1000)2– 1M
1000 2’s
0111 complement
+ 1 subtraction
1000 with steps
3M
1100
+1000
10100As carry is generated in 2‟s complement method discard it.
Actual answer is (0100)2= (4)10
b) Minimize the following expression using k-map and realize it 4M
using basic
logic gates Y= ∑ m (1,3,4,5,6,7) K map 2M
Ans.
equation
1M
realization
1M
Simplified Equation Y = A + C
c) Convert following expression into canonical SOP form 4M

:Y=A+BC+ABC Each step
Ans. Y= A(B+B‟)(C+C‟)+BC(A+A‟)+ABC 1M
= (AB+AB‟)(C+C‟)+ABC+A‟BC+ABCby OR law A+A=A

= ABC+ABC‟+AB‟C+AB‟C‟+A‟BC+ABCby OR law A+A=A
Y = ABC+A‟BC+AB‟C+ABC‟+AB‟C‟
d) Describe working of SR flip-flop using NAND gates with proper 4M
truth table.
Page 5 / 18
(Autonomous)

MODEL ANSWER
Ans. Diagram
2M
Description
1M
Truth Table
Working of SR 1M
S R Q n+1 Q n+1’ Remark

0 0 Qn Qn‟ Last state
0 1 0 1 Reset
1 0 1 0 Set
1 1 ? ? Forbidden/ unstable
flip flop
Case 1 S=0, R=0
S‟=R‟=1, since 1 at one of the input of a NAND gate has no effect on
its output. Hence flip flop remain in its last state.
Case 2 S=0, R=1
The flip flop will be in RESET state, as R=1, R‟=0 as one of the input
of NAND gate is 0 output is set, hence Q‟=1andQ=0
Case 3 R=0, S=1
The flip flop will be in SET state, as S=1, S‟=0 as one of the input of
NAND gate is 0 its output is 1, henceQ=1 & Q‟=0
Case 4 R=1, S=1
The flip flop will be in undefined state. Because the high inputs of S
and R, violates the rule of flip flop that the outputs should
complement to each other.
a) Convert the following into Binary and add them: 4M
(A96)16 + (28B)16
Ans. Binary
conversion
2M
Addition 2M
Page 6 / 18
(Autonomous)

MODEL ANSWER
b) Describe function of Full adder circuit with its truth table and 4M
Logical diagram
Ans. Diagram
1M
Truth table
1M
Sum and
carry 1M
Logical
diagram 1M
Based on the truth table, the Boolean functions for Sum (S) and Carry
(Cout) can be derived using K – Map.
For Sum S:
For Carry(COUT)
COUT=AB+ACin+BCin
Page 7 / 18
(Autonomous)

MODEL ANSWER
Logical Diagram
(Note: Logic Diagram using basic or universal gate also can be
consider)
c) Study the following circuit (Fig. 1) and draw waveforms for Q 4M

and x. Consider last value of Q=1. Correct
waveforms
4M
Ans. Truth table can be considered
d) Write an assembly language program to find, whether the 4M

number is even or odd.
Ans. (Note: Any other logic shall be considered).
DATA SEGMENT
EV DB “EVEN NUMBER$”
Page 8 / 18
(Autonomous)

MODEL ANSWER
OD DB “ODD NUMBER$”
DATA ENDS
CODE SEGMENT Correct
ASSUME CS:CODE, DS:DATA logic 2M
START:
MOV AX,DATA Correct
MOV DS,AX syntax 2M
MOV AH,1
INT 21H
MOV BL,2
DIV BL
CMP AH,0
JE EVEN NUMBER
MOV AH,10
MOV AH,2
INT 21H
MOV AH,13
MOV AH,2
INT 21H
MOV DX,OFFSET ODD
MOV AH,9
INT 21H
MOV AH,4CH
INT 21H
EVEN NUMBER:
MOV AH,10
MOV AH,2
INT 21H
MOV AH,13
MOV AH,2
INT 21H
MOV DX,OFFSETEVEN
MOV AH,9
INT 21H
MOV AH,4CH
INT 21H
CODE ENDS
ENDS START
Page 9 / 18
(Autonomous)

MODEL ANSWER

a) Prove 4M
Ans.i) Given Each solved

A + AB = A equation
LHS A + AB 2M
=A(1+B) [Distributed Law]
=A
Hence proved
ii) Given
b) Design Half adder using K-map and implement using gates 4M

Ans. Half Adder: Half adder is a combinational logic circuit with two
inputs and two output , circuit has two outputs namely “carry” and Truth table
“sum”, and two inputs A and B. 1M
Truth Table: K-map for
sum and
carry 2M
Logical
diagram 1M
K-map for Sum:
Page 10 / 18
(Autonomous)

MODEL ANSWER
K-map for Carry
Logical Diagram:
c) Draw the symbol and truth table of D- flip-flop and T – flip-flop 4M

D Flip-flop: Symbol
Ans. (Any one can be considered)
Symbol and
truth table
of D- flip
flop 2M
Truth table:
D Qn+1
0 0
1 1
T Flip-flop: Symbol
Symbol and
truth table
of T- flip
flop 2M
Truth table:
T Qn+1
0 Qn
1 Qn
Page 11 / 18
(Autonomous)

MODEL ANSWER
d) State the use of OF,TF,AF and PF flag in 8086 4M

Ans. Overflow Flag (OF):
This flag is set if an overflow occurs, i.e. if the result of a signed 1M for each
use
operation is large enough to be accommodated in destination register.
Trap Flag (TF):
It is a control flag. Set 1 if program can be run in single step
Auxiliary Flag (AF):
Set 1 if carry from lower nibble to upper nibble.
Parity Flag (PF):
This flag is set to 1 if the lower byte of the result contains even
number of 1‟s otherwise it is reset.
e) Describe concept of memory segmentation of 8086 4M
Ans.  Each segment is a 64kilobytes in size
 16 bit segment register actually points to the starting location of a Explanation
2M
particular segment.
 To specify a memory location within a segment we need an offset Diagram
or displacement. 2M
 The offset address is 16 bit long so that maximum value can be
FFFF H and maximum size of any segment is 64K.
 The CPU 8086 is able to address 1MB of physical memory.
 Can be divided into 16 segment, each of 64kbytes in size as
shown in the figure.
5. Attempt any TWO of the following: 12

a) (i) State and prove De' Morgans's theorems. 6M
(ii) Reduce the following Boolean expression using Boolean Laws
Page 12 / 18
(Autonomous)

MODEL ANSWER
De' Morgans's theorem 1:

Ans. Statement: : It states that the compliment of sum is equal to the De'
product of the compliment of individual variables. Morgans's
theorem-1
2M
Truth Table:
De' Morgans's theorem 2:

Statement: : It states that the compliment of product is equal to the De'
Morgans's
sum of the compliment of individual variables. theorem-2
2M
Truth Table:
ii) Reduce the following Boolean expression using Boolean Laws :
Page 13 / 18
(Autonomous)

MODEL ANSWER
Boolean
Ans expression
solution 2M
b) Explain maximum mode 8086 configuration with diagram. 6M

Ans. Maximum Mode Diagram:
Explanation:
Maximum
 When MN/ MX‟ = 0 , 8086 works in max mode.
Mode
 Clock is provided by 8284 clock generator. Diagram
 8288 bus controller- Address form the address bus is latched 3M
into 8282 8-bit latch. Three such latches are required
because address bus is 20 bit. The ALE(Address latch enable) is Explanation
3M
connected to STB(Strobe) of the latch. The ALE for latch is
given by 8288 bus controller. Or Relevant
 The data bus is operated through 8286 8-bit transceiver. Two contents
such transceivers are required, because data bus is 16-bit. The
transceivers are enabled the DEN signal, while the direction of
data is controlled by the DT/R signal. DEN is connected
to OE‟ and DT/ R‟ is connected to T. Both DEN and DT/ R‟ are
given by 8288 bus controller.
 Control signals for all operations are generated by decoding S‟2,

S‟1 and S‟0 using 8288 bus controller.
Page 14 / 18
(Autonomous)

MODEL ANSWER
 Bus request is done using RQ‟ / GT‟ lines interfaced with 8086.
RQ0/GT0 has more priority than RQ1/GT1.
 INTA‟ is given by 8288, in response to an interrupt on INTR
line of 8086.
 In max mode, the advanced write signals get enabled one T-state
in advance as compared to normal write signals. This gives
slower devices more time to get ready to accept the data,
therefore it reduces the number of cycles.
c) Write assembly language instructions of 8086 to 6M
(i) Multiply 4H by 5H
(ii) Rotate content of AX by 4-bit towards left.
(iii) To perform logical OR operation of AX & BX.
Each
Ans. i) Multiply 4H by 5H assembly
MOV AL,04H language
MOV BL,05H instruction
MUL BL 2M
ii) Rotate content of AX by 4-bit towards left.
MOV CL,04H
ROL AX, CL
iii) To perform logical OR operation of AX & BX.
OR AX,BX
6. Attempt any TWO of the following: 12
a) i) Design 16:1 multiplexer using 8:1 multiplexer. 6M
ii) Draw circuit diagram of l:4 DEMUX using logic gates. Write
its truth table.
Page 15 / 18
(Autonomous)

MODEL ANSWER
Ans. 16:1 multiplexer using 8:1 multiplexer:

Design
Multiplexer
Tree
2M
1:4
Demultiplex
er circuit
diagram 2M
Truth Table
Explanation
2M
l:4 DEMUX:
Truth Table
Page 16 / 18
(Autonomous)

MODEL ANSWER
Circuit diagram
b) Compare microprocessor 8086 with Pentium III on the basis of 6M

i) Address and data bus
ii) Clock speed
iii) Memory
iv) Operations Modes
Ans. Parameters 8086 Pentium III
For Address
Address and Address Bus-20bits Address Bus-32bits and data
data bus Data Bus-16bits Data Bus-32bits bus 2M
Clock Speed 5 to 10MHz 16 to 33MHz For other

1MB 4GB comparison
Memory
Points
Operation Two Operating Modes Three Operating Modes 4M
Modes  Maximum Modes  Real-address mode
 Minimum Modes  Protected mode
 System management
mode
c) (i)Explain XLAT and XCHG instructions of 8086 6M
microprocessor.
ii) Write an assembly language program to reverse the string.
Page 17 / 18
(Autonomous)

MODEL ANSWER
Ans.
Instruction
explanation
3M
ii) Write an assembly language program to reverse the string.

Ans DATA SEGMENT
STRB DB „COMPUTER PROGRAM $‟
REV DB 0FH DUP (?) Program
DATA ENDS 3M
CODE SEGMENT
START:ASSUME CS:CODE,DS:DATA
MOV DX,DATA
MOV DS,DX
LEA SI,STRB
MOV CL,0FH
LEA DI,REV
ADD DI,0FH
UP:MOV AL,[SI]
MOV [DI],AL
INC SI
DEC DI
LOOP UP
MOV AH,4CH
INT 21H
CODE ENDS
END START
Page 18 / 18

DTM w22 22323

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

DTM w22 22323

Uploaded by

Copyright:

Available Formats

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION

WINTER – 2022 EXAMINATION

Important Instructions to examiners:

Q. Sub Answer Marking

WINTER – 2022 EXAMINATION

gates within the same

c) State the role of preset and clear terminal in flip-flop. 2M

WINTER – 2022 EXAMINATION

d) State the different triggering methods in digital circuits. 2M

2. Register addressing mode

3. Direct addressing mode

WINTER – 2022 EXAMINATION

5. Indexed addressing mode

6. Based Indexed addressing mode

7. Register relative addressing mode

8. Relative Based Indexed addressing mode

2. Attempt any THREE of the following: 12

WINTER – 2022 EXAMINATION

Ans. (12)10= (1100)2

c) Convert following expression into canonical SOP form 4M

= (AB+AB‟)(C+C‟)+ABC+A‟BC+ABCby OR law A+A=A

WINTER – 2022 EXAMINATION

S R Q n+1 Q n+1’ Remark

WINTER – 2022 EXAMINATION

WINTER – 2022 EXAMINATION

c) Study the following circuit (Fig. 1) and draw waveforms for Q 4M

Ans. Truth table can be considered

d) Write an assembly language program to find, whether the 4M

WINTER – 2022 EXAMINATION

WINTER – 2022 EXAMINATION

4. Attempt any THREE of the following: 12

Ans.i) Given Each solved

b) Design Half adder using K-map and implement using gates 4M

K-map for Sum:

WINTER – 2022 EXAMINATION

K-map for Carry

c) Draw the symbol and truth table of D- flip-flop and T – flip-flop 4M

WINTER – 2022 EXAMINATION

d) State the use of OF,TF,AF and PF flag in 8086 4M

5. Attempt any TWO of the following: 12

WINTER – 2022 EXAMINATION

De' Morgans's theorem 1:

De' Morgans's theorem 2:

ii) Reduce the following Boolean expression using Boolean Laws :

WINTER – 2022 EXAMINATION

b) Explain maximum mode 8086 configuration with diagram. 6M

 Control signals for all operations are generated by decoding S‟2,

WINTER – 2022 EXAMINATION

WINTER – 2022 EXAMINATION

Ans. 16:1 multiplexer using 8:1 multiplexer:

WINTER – 2022 EXAMINATION

b) Compare microprocessor 8086 with Pentium III on the basis of 6M

Clock Speed 5 to 10MHz 16 to 33MHz For other

WINTER – 2022 EXAMINATION

ii) Write an assembly language program to reverse the string.

You might also like