Sequential Circuits

Digital Electronics (Sequential Circuits)
1. Which of the following is not a synchronous input with reference to Flip-Flops

(a)J input of J-K Flip-Flop (b) S input of R-S Flip-Flop
(c) Preset Input of ]-K Flip-Flop (d) D input of D Flip-Flop
2. The decoding glitches are more likely to occur in case of

(a) Ripple counters (b) Parallel counters
(c) Johnson counter (d) Ring counter
3. Which of the following is true of the following circuit
(a) Positive edge detector

(b) Negative edge detector
(c) Both
(d) None of the above
4. Find the output frequency ‘f0’ of the following sequential circuit
(a) 5 kHz
(b) 2.5 kHz
(c) 2 kHz
(d) 1.25 kHz
5. The characteristic equation of the following flip-flop is
(a) Q(t+1)=JQ+KQ
(b) Q(t+1)=JQ+KQ
(c) Q(t+1)=JQ+KQ
(d) Q(t+1)=JQ+KQ
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6. The maximum frequency of operation of the following circuit, if propagation delay of Flip-
Flop and inverter are 20ns, 5ns respectively is _________ MHz
7. The contents of a register initially is 0110. The register is shifted six times to the right with
serial input being 1011100. The contents of the register after 3rd, 4th & 6th shifts respectively
are.
(a) 1010, 1101, 1110 (b) 0001, 0011, 0111
(c) 1000, 1100, 1011 (d) 1000, 1100, 0111
8. The count of a mod 10 (4 bit) counter is represented as b3b2b1b0, where b3 is the MSB & b0
is the LSB. If the counter counts from ‘0’ onwards, then the duty cycle of the bit ‘b2’ is
(a) 20 % (b) 40%
(c) 60% (d) 50%
9. In a four stage ripple counter, the propagation delay of a flip-flop is 40ns and strobe pulse
width is 40ns. The maximum frequency at which the counter operates reliably is ________ (in
MHZ)
10. A counter is needed that will count the number of items passing on a conveyer belt. A
photocell and light source combination is used to generate a single pulse each time an item
crosses its path. The counter must be able to count as many as one thousand times. The
number of flip-flops required are ________
11. For a JK FF ϴn is output at time step tn which of the following Boolean Expression θ n+1 ?
(a) Jn n  Knn (b) Jnn  Kn n
(c) Jnn  Kn (d) Jnn  nKn

12. Match (list - I) circuit with list - II (application) and select the correct answer using the
Code given below lists :
List - I List - II
1. Division P. Ripple up counter
2. Multiplication Q. Synchronous down counter
3. To create delay R. Shift left Register
4. Transient states S. Shift right Register
Codes :
P Q R S P Q R S
(a) 2 3 4 1 (b) 2 1 4 3
(c) 4 1 2 3 (d) 4 3 2 1
13. The digital circuit shown in the ﬁgure works as a
(a) JK flip-flop
(b) Clocked RS flip-flop
(c) T flip-flop
(d) Ring counter
14. Identify the following circuit, constructed using multiplexers
(a) 2-Bit counter
(b) Master-Slave D-FF
(c) D-Latch
(d) 2-Bit Johnson counter
15. The initial state of the ring counter is 0100010. Determine number of clock pulses
required to return to the initial state
(a) 5 (b) 14
(c) 6 (d) 7

16. The function performed by the circuit shown in figure is
(a) A counter with repeated sequence of 00, 10, 11

(b) A counter with repeated sequence of 11, 10, 01
(c) A counter with repeated sequence of 00, 01, 10
(d) A counter with repeated sequence of 00, 10, 01, 11
17. A sequential circuit has two JK flip-flop A and B and one input x the circuit is described
by the following flip-ﬂop input equations:
JA  x , K A  B
JB  x , KB  A
The state equations A(t  1) and B(t  1) for the given sequential circuit are
(a) A(t  1)  xA(t)  A(t)B , B(t  1)  A(t)B(t)  xB(t)
(b) A(t  1)  xA(t)  A(t)B(t) , B(t  1)  A(t)B(t)  xB(t)
(c) A(t  1)  A(t)B(t)  xB(t) , B(t  1)  xA(t)  A(t)B
(d) A(t  1)  xA(t)  A(t)B , B(t  1)  A(t)B(t)  xB(t)
18. In the figure below. Assume initially Q0  Q1  0, what would be the logic state of
Q0andQ1 immediately after 727th clock pulse?
(a) Q0Q1  10
(b) Q0Q1  01
(c) Q 0 Q1  11
(d) Q 0 Q1  00

19. The frequency of the pulses at the point d in the following circuit is _____Hz.
20. In the circuit shown below, find the frequencies of C1 and C2 .
(a) 5 KHz & 2.5 KHz
(b) 5 KHz & 5 KHz
(c) 2.5 KHz & 5 KHz
(d) 2.5 KHz & 2.5 KHz
21. A 4-bit MOD-16 ripple counter use JK flip flop. If the propagation delay of each flip flop
is 50ns, then the maximum clock frequency is __________MHz
22. A Johnson counter is a normal ring counter except
(a) The output of last counter connected to its own input

(b) The complimented output is connected to the clock pulse
(c) All inverted outputs are connected to the preceding input except the last
(d) That Q n is connected to D 0
23. Consider a Johnson counter with n number of flip-flops. The number of states of the
counter is
(a) 2n  1 (b) n
(c) 2n (d) 2n  n

24. Symmetrical square wave of time period 100 μs can be obtained from square wave of
time period 10 μs by using a
(a) Divide by - 5 circuit

(b) Divide by -2 circuit
(c) Divide by -5 circuit followed by a divide by -2 circuit
(d) None of these
25. A certain JK flip flop has tpd = 12 ns, What is the largest MOD counter, which can be
constructed from these flip-flops and still operates up to 10MHz?
(a) 16 (b) 64
(c) 128 (d) 256
26. The number of states to be eliminated when mod 2014 counter is designed with 11 flip-
flops are
(a) 10 (b) 34
(c) 44 (d) 24
27. A digital circuit is designed with three D-flip flops and an Ex-OR gate as shown in below
figure. If the initial value of Q A Q B Q C was 110 then the minimum number of clock pulses
required to get Q A Q B Q C as 011 is_____.

28. Which of the following statements is/are true.
(i) Race around condition occurs in dynamic triggering.

(ii) Static shift registers are made up of flip-flops.
(iii) An 8 bit Johnson counter is mod-16 counter.
(iv) A master-slave flip-flop can store 2 bits of information.
(a) (i), (ii) and (iv) (b) (i), (ii) and (iii)
(c) (ii) and (iii) (d) (i) and (ii)
29. Consider the sequential circuit given below. The number of unused states are _____.
30. Consider a mod-1000 ripple up counter. The duty cycle for its MSB is________%.
31. Which of the following statements best describes the action of pulse-triggered flip-flop?
(a) The clock and inputs must be pulse shaped.

(b) The data is entered on the leading edge of the clock and transferred out
on the trailing edge of the clock
(c) A pulse on the clock transfers data from input to output.
(d) The synchronous inputs must be pulsed.

32. The input A and clock applied to the D flip-flop (Positive Edge Trigger). The output Q

33. Consider the circuit given below
If Enable = 0 ; 7 segment display 11 (b = c = e = f = 1)

Enable = 1 ; 7 segment display data according to Inputs
Initially both the counter were cleared. After 78 clock pulses the data displayed on the 7
segment display is _____.
34. A new two input flip flop is designed as shown in figure. The table shows the
characteristic table of the A - B flip flop.
A B Q n 1
0 0 Qn
0 1 1
1 0 Qn
1 1 0
The combination logic is

(a) (b)
(c) (d)
35. Three 4 bit shift registers are connected in cascade as shown in figure below. Each
register is applied with same clock
A 4 bit data 1011 is applied to the shift register 1. The minimum number of Clock pulses
required to get same input data at output are with same clock
(a) 11 (b) 12
(c) 9 (d) 7

36. Consider the circuit given below
MSB and LSB of MOD 10 ripple up counter acts as clock to 4 bit ripple down and up counter
respectively. Initially all the counter were cleared and output of comparator was A = B. The
clock pulse is applied. The minimum number of clock pulses required to make A = B again
are
37. The digital circuit shown in the figure works as
(a) JK flip-flop
(b) RS flip-flop
(c) T flip-flop
(d) Ring counter
38. A 4-bit ripple counter and a 4-bit synchronous counter are made by flip-flops having a
propagation delay of 5ns each. If the worst case delay in the ripple counter and the
synchronous counter be R and S respectively, then
(a) R = 5 ns. S = 20 ns (b) R = 20 ns, S = 5 ns

(c) R = 15 ns. S = 5 ns (d) R = 5 ns, 8 = 5 ns

39. The following counter (negative edge triggered) has _____________ number of states.
40. Binary ripple counter is required to count upto 1638310 _______number of flip flops are
required.
41. The truth table shown below is to implement using JK flip-flop (FF). This can be achieved
by making
A B Q n 1
0 1 Qn
0 0 0
1 1 1
1 0 Qn
(a) A = J, B = K (b) A= J , B = K
(c) A = J. B = K (d) A= J , B = K
42. All the logic gates in the circuit shown below have finite propagation delay. The circuit
can be used as a clock generator. if X =______

.
43. __________Number of flip-flops will be complemented in a 10 bit binary ripple counter to
reach the next count after the count 1001100111.
44. In the circuit shown below, JK flip-flop are in master slave configuration.
with an input setup time t = 20 ns, hold time = 10 ns and a propagation delay of 70ns for
each flip- flop. The maximum clock frequency for reliable operation is
(a) 11.1 MHz (b) 10 MHz

(c) 33.3 MHz (d) 12.5 MHz
45. For the circuit given below
If input X = 1, 0, 1, with register initially cleared, then after three clock pulses the value of A,
B and C is
(a) 1, 0, 1 (b) 0, 1, 1
(c) 1, 1, 1 (d) 0, 1, 0

46. Consider the flip-flop circuit given below:
logic operation performed by logic circuit will be
(a) AND (b) OR

(c) EX-OR (d) EX-NOR
47. Consider the following statements
1. Latches are faster than flip-flops.

2. Latches are synchronous while flip-flops are Asynchronous devices.
3. Latches are level triggered
of these statements
(a) 1and 2 are correct (b) 2 and 3 are correct
(c) 1and 3 are correct (d) 1, 2 and 3 are correct
48. A ripple counter is to be operated at a maximum frequency of 10MHz. The propagation

delay of each flip-flop used in the counter is 20 nsec, number of stages in the counter are
given by
(a) 5 (b) 10
(c) 15 (d) 20

49. A sequential circuit using D flip-flop and logic gates is shown in the following figure,
where X and Y are the inputs and Z is the output. The circuit is
(a) S-R flip-flop with inputs X = R and Y = S

(b) S-R flip-flop with inputs X = S and Y = R
(c) J-K flip-flop with inputs X = J and Y = K
(d) J-K flip-flop with inputs X = K and Y = J
50. A SISO shift register may be used to introduce time delay T = 200 ns in digital signals.
Assume this shift registers is manufactured by 'N' number of D flip-flops having clock
frequency 50MHz. The required value of 'N' is_____.

Solutions
1. Ans: (c)
Solution: Preset, clear are asynchronous inputs
2. Ans: (a)
3. Ans: (b)
Solution:
F changes when clock goes from ‘1’ to ‘0’
Hence circuit works as a negative edge detector
4. Ans: (d)
f
Solution: Output frequency of toggle mode FF=
2
f 5
The frequency ‘f0’ at output: = =1.25 kHz
4 4
5. Ans: (d)
Solution: Characteristic equation of a standard JKFF is Q(t+1)=JQ+KQ
But here k=K , So new Characteristic equation will be Q(t+1)=JQ+KQ
6. Ans: 40
Solution: Clock period T  20 + 5 ns  
1
T  25ns  f  9
Hz
25  10
fmax =40 MHz

7. Ans: (d)
Solution: The outputs after IIIrd, IVth & VIth cycles respectively are 1000, 1100, 0111
8. Ans: (b)
Solution: Truth Table
b3 b2 b1 b0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
Total number of states T = 10
Number of states for which b2 = 1 is 4
TON  4
TON 4
Duty cycle    40%
T 10
9. Ans: 5
Solution: The maximum Frequency is
1 1 1
fmax    109   103  106
n(tpd )  Ts 4(40)  40 200
fmax  5MHz
10. Ans: 10
Solution: We have to determine the value of N is needed so that 2N  1000 , 9 FFS will not
be enough. 210  1024 , so 10 FFs would produce a counter that could count as high as
(1023)10. Therefore, we must have 10 flip-flops.
11. Ans: (a)

12. Ans: (d)
13. Ans: (c)

Solution: Q(t  1)  X  Q
This is similar to characteristic equation of T FF.
14. Ans: (b)

Solution: On the rising edge of the clock, output of mux 1 is X
On the falling edge of the clock, output of mux 2 is X
Thus, it is a Master—Slave D-FF
15. Ans: (d)

Solution: It is 7-Bit ring counter, whose counting efficiency is 7 :1
16. Ans: (c)

Solution:
Clk QA QB QA QB TA TB
0 0 0 1 1 0 1
1 0 1 1 0 1 1
2 1 0 0 1 1 0
3 0 0 1 1 0 1

17. Ans: (a)

Solution:
X A(t) B(t) JA KA JB KB A(t+1) B(t+1)

0 0 0 0 0 0 1 0 0
0 0 1 0 1 0 1 0 0
0 1 0 0 0 0 0 1 0
0 1 1 0 1 0 0 0 1
1 0 0 1 0 1 1 1 1
1 0 1 1 1 1 1 1 0
1 1 0 1 0 1 0 1 1
1 1 1 1 1 1 0 0 1
A(t  1)  xA(t)  A(t)B

B(t  1)  A(t)B(t)  xB(t)
18. Ans: (b)

Solution: This is a Johnson counter and number of state is 2N
Where N= Number of Flip Flops=2
So that the number of state=4=MOD4

Q 0 Q1  00-10-11-01-00
Number of states completed=727= 181  4  3
The logic gate after 727th CLK pulse is Q 0 Q1  01
19. Ans: 3.7 to 4.1

100  103
Solution: At a, f   10KHz
10
10  103
At b, f   500Hz
20
500
At c, f  Hz  31.25Hz
16
31.25
At d, f   3.9Hz
8
20. Ans: (a)

fc
Solution: Q1  C1 will toggle every clock pulse fc 
1 2
fc
f
And Q2  C2 will toggle every cycle of C1 fc  2 
2 2 4
21. Ans: 5
1
Solution: Fmax  ; tpd  50  10 9 sec
Ntpd
1 1000  106
Fmax    5MHz
4  50  109 200
22. Ans: (d)
23. Ans: (c)
24. Ans: (c)

1 1 f
Solution: The given data is fout  ; fin  and fout  in
100s 10s 10
25. Ans: (d)

1 1 100
Solution: N   
fmax  tpd 10  10  12  10
6 9
12
N  8 MOD counter= 2N  256
26. Ans: (b)

Solution: Total number of state possible with 11 flip flops= 211  2048
Required states=2014
Number of state to be eliminated=2048-2014=34

27. Ans: 5
Solution:
After 5 clock pulse Q A QB QC will be 011.

28. Ans: (c)
Solution: Race around condition never occurs in dynamic edge triggering. Static shift
registers are made up of flip flops while dynamic shift registers are made up of CMOS.
29. Ans: 2
Solution:
QA QB QC
0 0 0
0 0 1
0 1 0
1 0 0
1 0 1
1 1 0
0 0 0
Total number of possible states= 23  8

Used states=6
Unused state=8-6=2

30. Ans: 48 to 49
Solution:
999  511
Duty cycle of MSB=  100 = 48.8%
1000
31. Ans: (b)
Solution: In pulse triggered or master-slave type flip-flop the data is entered on the leading
edge but output does not reflect the input until falling edge.
32. Ans: (d)

Solution: D-flip flop changes its output according to input and clock pulse applied to it. The
flip flop is positive edge triggered so the output modifies at every positive edge of clock
according to the input.
33. Ans: 11
Solution: After 78 clock pulse
Output of counter C1 = (1110)2
Output of counter C2 = (0010)2
7 segment display a b c d e f g Enable
1 1 1 0 0 0 1 0
Data displayed on 7 segment is ‘11’

34. Ans: (d)

Solution:
A B Q n 1 J K
0 0 Qn 1 0
0 1 1 1 0
1 0 Qn 0 0
1 1 0 0 1
J  A , K=AB
Hence (d) is correct option
35. Ans: (b)

Solution: Each shift resistors take 4 clock cycles to shift the input to output.
Hence 12 clock cycles required to get same input at output.
36. Ans: 17
Solution: All the counters are positive edge triggered. In 10 clock pulses MSB of counter C1
goes from low to high once. LSB of counter C1 goes from low to high 5 times.
Output C1
After 9 clock pulse

Counter of C2 =9
Counter of C3 =5
After 17 clock pulse
Counter of C2 =9
Counter of C3 =9
Minimum 17 clock pulses are required to make A=B high again

37. Ans: (c)

Solution: Input to the D flip-flop can be written as Dn  Qn  Y
For a D flip-flop output is Qn1  Dn  Qn  Y
This is similar to T flip flop
38. Ans: (b)

Solution: In ripple counter, delay = 4 Td = 20 ns
In synchronous counter all the flip flops are clocked simultaneously, So in worst case its delay
will be equal to 5 ns.
39. Ans: 3
Solution:
So, state diagram of the counter will be
it has 3-states

40. Ans: 14
Solution: Total count M =2n-1= (16383)10
Number of required flip-flops (n)  log2 (M 1)
n  log2 (16383  1) 
 log10 (16384) 

log2 (16384)  
n  log2 (16384) 
 log10 2  
n  14
So, 14 flip-flops are required.
41. Ans: (c)

Solution: Characteristic Table
A B Q n 1 J K
0 1 Qn 0 0
0 0 0 0 1
1 1 1 1 0
1 0 Qn 1 1
So, A = J and B= K
42. Ans: 1
Solution: Clock generator means alternate 0 and 1witlh a fix time period as shown below.
We will get this if output of XOR gate is inverted every time and final output will be getting
after some delay due to 2 NOT gates. That is XOR gate must work as inverter for Y and this is
possible if X = 1, Y  1  Y
43. Ans: 4
Solution: Count is 1001100111
+1
Next count is 1001101000
So, number of flip-flops to be complement =4

44. Ans: (b)

Solution:
Tmin  tsetup  thold  tpd  20  10  70  100ns
For reliable operation,
1 1
fmax    10MHz
Tmin 100  109
45. Ans: (a)

Solution: X=1, 0, 1
After 3 clock pulses ABC=101
46. Ans: (c)

Solution:
T Qn Q n 1
0 0 0
0 1 1
1 0 1
1 1 0
So logic operation is EX-OR
47. Ans: (c)
48. Ans: (a)

Solution: For ripple counter
1
Tc  nTPD   107 sec
10MHz
107
So, n  5
20  109

49. Ans: (d)

Solution: D  XZ  YZ
For JK flip flop Qn+1  KQ  JQ
Compare with JK flip flop Characteristic equation
We get, Y = J, X = K, D = Qn+1 (for D flip-flop)
50. Ans: 10
Solution: Given that, t  200ns
fCLK  50MHz  50  106 Hz
1
t  N  T  N  Where, ‘N’=number of FFs
fCLK
N  t  fCLK  200  109  50  106  103  10  10 3
N = 10

We recommend you to take the Chapter Test first and then

check the Solutions.

Chapter Test Solutions
1. Ans: (c)
Solution: Pre-settable down counter counting sequence = 6, 5, 4, 3, 2, 1
So input clock frequency will be divided by 6
2. Ans: 9
Solution: For Q3Q 2Q1Q 0 =1 0 0 1
Flip-Flops are cleared.
It counts from 0000, ... ... 1000, 0000, ....
Its modulus = 9.
3. Ans: (c)
Solution: x3=LI, x2=L+C, x1=Lx3 = L+LI=L+LI = L+I
JA=x1x2=(L+C)(L+I) = LI+LC+IC
Applying consensus Theorem
JA =LI+LC
K A=x2x3=(L+C)(LI) = (L+C)(L+I)=LI+LC+IC
Applying consensus Theorem
K A =LI+LC
4. Ans: (a)
Solution: 00  No change
10  0 to 1 transition
01  1 to 0 transition
It is a SR FF
5. Ans: (b)
Solution: It is mod - 3 Counter.
After every 3 pulses the output will go back to 00 and after 333rd clock pulse output will be
10.

6. Ans: (c)

Solution: clock period T  20+10 ns
T  30 ns
1
f
30  10 9
fmax = 33.3 MHz
7. Ans: (b)
Solution: Truth table
A B Q(t) Q(t+1)
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
Q(t  1)  NQ(t)  PQ(t)
8. Ans: (d)
Solution: This is the standard asynchronous MOD7 up counter. Hence the count sequence
is 000 to 110
9. Ans: (c)
Solution: Characteristic Table for the given system
Present State Input Next State
QA QB TA TB QA Q B
0 0 0 1 0 1
0 1 1 1 1 0
1 0 1 0 0 0
From the table it is clear that it counter three different numbers. It is a MOD-3 counter

10. Ans: (c)

Solution: Number of flip-flops required=4
Maximum delay=4  10nsec=40nsec
11. Ans: (c)

Solution:
Q3 Q2 Q1
0 0 0  Initial state
0 0 1 1st clock pulse
0 1 1 2nd clock pulse
1 0 1 3rd clock pulse
0 0 0 4th clock pulse
Modulus of the counter is 4, After 7 clock pulses Q 3 Q 2 Q 1 will be 101
12. Ans: (b)

Solution: Initially Q0  Q1  0 , Y0  0
J-K flip-flop is cleared Q A  0 , Q A  1
As clock pulse is applied counter starts up counting
As counter reaches Q1  1,Q0  1 after 3 clock pulses J-K flip flop is preset
QA  1 QA  0
Counter starts down counting until Y0 is low and this repeats
So output Q 1 Q 0 in decimal form is 0,1,2,3,2,1,0,1......

13. Ans: (c)

Solution:
By checking all the options, Option(c) correctly matches
14. Ans: 100

Solution: At t1 and t 2 v1 (t)  v 2 (t)
2sin(0.1 t)  1  4sin(0.1 t)
5 25 5
t , ,........ => t1  sec
3 3 3
25
t2  sec
3

5
For 0<t< , V1 > V2 So, clock doesn’t reach the counter
3
5 25
For <t< V2 > V1 So, 4 clock edges (t= 2, 4 , 6 , 8) reach the counter
3 3
So, Output of counter is 100
15. Ans: (b)

Solution: Maximum time taken for FFs to stabilize  8  75  50  650 ns
1
Maximum frequency of operation fmax = = 1.53MHz
650  109

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Digital Electronics (Sequential Circuits)

1. Which of the following is not a synchronous input with reference to Flip-Flops

2. The decoding glitches are more likely to occur in case of

3. Which of the following is true of the following circuit

(a) Positive edge detector

4. Find the output frequency ‘f0’ of the following sequential circuit

5. The characteristic equation of the following flip-flop is

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13. The digital circuit shown in the ﬁgure works as a

14. Identify the following circuit, constructed using multiplexers

(a) 2-Bit counter

(b) Master-Slave D-FF

(d) 2-Bit Johnson counter

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16. The function performed by the circuit shown in figure is

(a) A counter with repeated sequence of 00, 10, 11

(b) A(t  1)  xA(t)  A(t)B(t) , B(t  1)  A(t)B(t)  xB(t)

(c) A(t  1)  A(t)B(t)  xB(t) , B(t  1)  xA(t)  A(t)B

(d) A(t  1)  xA(t)  A(t)B , B(t  1)  A(t)B(t)  xB(t)

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20. In the circuit shown below, find the frequencies of C1 and C2 .

(a) 5 KHz & 2.5 KHz

(b) 5 KHz & 5 KHz

(c) 2.5 KHz & 5 KHz

(d) 2.5 KHz & 2.5 KHz

22. A Johnson counter is a normal ring counter except

(a) The output of last counter connected to its own input

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(a) Divide by - 5 circuit

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28. Which of the following statements is/are true.

(i) Race around condition occurs in dynamic triggering.

(a) The clock and inputs must be pulse shaped.

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33. Consider the circuit given below

If Enable = 0 ; 7 segment display 11 (b = c = e = f = 1)

The combination logic is

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36. Consider the circuit given below

37. The digital circuit shown in the figure works as

(d) Ring counter

(a) R = 5 ns. S = 20 ns (b) R = 20 ns, S = 5 ns

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(a) 11.1 MHz (b) 10 MHz

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46. Consider the flip-flop circuit given below:

logic operation performed by logic circuit will be

(a) AND (b) OR

47. Consider the following statements

1. Latches are faster than flip-flops.

48. A ripple counter is to be operated at a maximum frequency of 10MHz. The propagation

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(a) S-R flip-flop with inputs X = R and Y = S

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F changes when clock goes from ‘1’ to ‘0’

Hence circuit works as a negative edge detector

But here k=K , So new Characteristic equation will be Q(t+1)=JQ+KQ

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11. Ans: (a)