COA UNIT 2 ,3 & 4 Short Notes

Amit Yadav , NIET Gr Noida

 ADDER- HALF ADDER
• Half Adder is a combinational logic circuit that adds two 1-bit digits.
• Half adder is a combinational arithmetic circuit that adds two numbers and produces a sum
bit(S) and carry bit (C) as the output.
• If A and B are the input bits ,then sum bit(S) is the X-OR of A and B and the carry bit (C) will
be the AND of A and B.

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 Full Adder
• Full adder is developed to overcome the drawbacks of Half Adder circuit.
• full adder in digital logic which adds three inputs and produces two outputs, the first two
inputs are A and B, the third input is Cin
• The full adder is a three input and two output combinational circuit

Block Diagram:

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 Full Adder

Truth Table :

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 Full Adder

Full Adder using two half adders :

Sum = = A XOR B XOR Cin

Carry = AB + Cin (A xor B)

Circuit diagram of full adder

Amit 11/22/2023
Yadav , NIET Gr Noida AMIT YADAV Computer Organisation & Architecture Unit 2 5
 Parallel Adder

• Parallel Adder is a digital circuit that efficiently adds more than 1 bit binary numbers.

• A n bit parallel adder requires n full adders to perform the operation.

• 4- bit Parallel Adder is designed using 4 Full Adders FA0, FA1, FA2, FA3 .

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 Carry-Look-ahead Adder

A carry Look-ahead adder is a fast parallel adder as it reduces the propagation delay by more
complex hardware, hence it is costlier.

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 Carry-Look-ahead Adder

• If we define two variables as carry generate Gi and carry propagate Pi then,

Pi = Ai ⊕ Bi
Gi = Ai Bi

• The sum output and carry output can be expressed as

Si = Pi ⊕ Ci
C i+1 = Gi + Pi Ci

• Where Gi is a carry generate

• Pi is a carry propagate and it is associate with the propagation of carry from Ci to Ci+1.

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 Carry-Look-ahead Adder

The carry output Boolean function of each stage in a 4 stage carry Look-ahead adder can be
expressed as

C1 = G0 + P0 C0
C2= G1 + P1 C1
= G1 + P1 G0 + P1 P0 C0
C3 = G2 + P2 C2
= G2 + P2 G1+ P2 P1 G0 + P2 P1 P0 C0

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 IEEE Standard for Floating Point Numbers

•The IEEE Standard for Floating-Point Arithmetic (IEEE 754) is a technical standard for floating-point
computation which was established in 1985 by the Institute of Electrical and Electronics Engineers
(IEEE).

IEEE 754 has 3 basic components:

• The Sign of Mantissa –

0 represents a positive number while 1 represents a negative number.
• The Biased exponent –
A bias is added to the actual exponent in order to get the stored exponent.
• The Normalized Mantissa –
A normalized mantissa is one with only one 1 to the left of the decimal.

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 IEEE Standard for Floating Point Numbers

• IEEE 754 numbers are divided into two based on the above three components: single
precision and double precision.

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 IEEE Standard for Floating Point Numbers

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 IEEE Standard for Floating Point Numbers

NORMALISED
TYPES SIGN BIASED EXPONENT BIAS
MANTISA

Single precision 1(31st bit) 8(30-23) 23(22-0) 127

Double precision 1(63rd bit) 11(62-52) 52(51-0) 1023

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 Multiplier

• A basic multiplier can consist of three parts:

• Partial product generation

• Partial product addition and
• Final addition

• Several types of multipliers are studied: array multipliers, Wallace tree multipliers, booth
multiplier.

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 Array Multiplier

• An array multiplier is a digital combinational circuit used for multiplying two binary
numbers by employing an array of full adders and half adders.

• Array multiplier is common in multiplier design due to its regular and compact structure.

• The structure of array multiplier is organized by several stages of adders and AND-gates.

• It generates all the partial products after only one AND-gate delay. Then, it sums up all partial
products sequentially.

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 Array Multiplier

• The multiplication of two 2-bit numbers as shown in figure. The multiplicand bits are b1 and b0, the
multiplier bits are a1 and a0, and the product is -

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 Array Multiplier

Partial product = the multiplicand * multiplier bit

4*4 bit multiplication :-

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 Array Multiplier

Disadvantages of 4×4 Array Multiplier

• The disadvantages of array multiplier are as
follows,
• High power consumption
• More digital gates resulting in large areas.

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 Array Multiplier

• 4 bit Array multiplier B=b3 b2 b1 b0 and A= a2 a1 a0.

For k multiplicands & j multipliers bits , we

needs

• (j x k) AND gates
• (j-1 )x k bit adders produce
• A product of j + k bits

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 Booth Multiplier

• The Booth multiplication algorithm defines a multiplication algorithm that can multiply two signed
binary numbers in two’s complement.

• Booth’s algorithm cuts the number of required partial products in half.

• This increases the speed by reducing the total number of partial product sums that must take place.

Bits Operation Performed :-

• 00 no arithmetic operation
• 01 add multiplicand to left half of product
• 10 subtract multiplicand from left half of product
• 11 no arithmetic operation

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 Booth Multiplier

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 Booth Multiplier

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 Booth Multiplier

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 Control Unit (CU)

▪ Control Unit is the part of the computer’s central processing unit (CPU), which directs the
operation of the processor.

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 Functions of the Control Unit

➢It coordinates the sequence of data movements into, out of, and between a processor’s many sub-
units.
➢It controls data flow inside the processor.
➢It receives external instructions or commands to which it converts to sequence of control signals.
➢It also handles multiple tasks, such as fetching, decoding, execution handling and storing results.

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 Control Unit

A control unit can be implemented by basically two techniques:

1. Hardwired control unit

2. Micro programmable control unit.

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 Control Unit (CU)
•Control unit of Basic Computer

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 Hardwired Control Unit

Hardwired control unit

➢It In the hardwired organization, the control logic is implemented with gates, flip-flops, decoders,
and other digital circuits.
➢ Because of the use of combinational circuits to generate signals, Hardwired Control Unit is fast.

➢ Faster than micro- programmed control unit.

➢ It does not require control memory.

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 Microprogrammed Control Unit

➢In the micro programmed organization, the control information is stored in a control memory.
➢The control memory is programmed to initiate the required sequence of micro-operations

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 Hardwired/Microprogrammed

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 Instruction Format

There are several types of instruction formats, including zero, one, two, and three-address instructions.

What are the Different Types of Filed in Instruction?

The most common fields are:

• The operation field specifies the operation to be performed like addition.

• Address field which contains the location of the operand, i.e., register or memory location.
• Mode field which specifies how operand is to be founded.

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 Instruction Format

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 Instruction Format

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 Instruction Format

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 Instruction Cycle & Sub Cycle

•In Basic Computer, a machine instruction is executed in the following cycle:\

–Fetch an instruction from memory

–Decode the instruction
–Read the effective address from memory if the instruction has an indirect
address
–Execute the instruction

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 Instruction Cycle
Instruction Cycle

•The time period during which one instruction is fetched from memory and executed when a computer is
given an instruction in machine language.

•There are typically four stages of an instruction cycle that the CPU carries out:

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 Instruction Cycle & Sub Cycle

Instruction Cycle is subdivided into following Sub Cycles:

1. Fetch instruction from memory : At the beginning of the fetch cycle, the address of
the next instruction to be executed is in the Program Counter(PC)

2. Decode the instruction: Decode the instruction.

3. Read the effective address from memory.

4. Execute the instruction(Microcode for the instruction, selected by the decoder output
line, is executed by the ALU.)

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 Micro operations

The operations performed on the data stored in registers known as micro-operations.

Example: Shift, Count Clear and Load. The micro-operations are classified as follows:

1. Register transfer micro-operations:

These type of micro operations are used to transfer from one register to another binary information.

2. Arithmetic micro-operations :
These micro-operations are used to perform on numeric data stored in the registers some arithmetic operations.

3. Logic micro-operations:
These micro operations are used to perform bit style operations / manipulations on non numeric data.

4. Shift micro operations:

As their name suggests they are used to perform shift operations in data store in registers.

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 Arithmetic Micro operations

Example Description
R3 ← R1 + R2 Addition
R3 ← R1 - R2 (R1 + R2' + 1) Subtraction
Complement (really a logic
R2 ← R2'
operation)
R2 ← -R2 (R2' + 1) Negation
R1 ← R1 + 1 Increment
R1 ← R1 - 1 Decrement

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 Logic Micro operations

Logic Micro-Operations:

Individual bits of registers are operated with other corresponding register bits. Example:
the XOR of R2 and R1 is symbolized by
P: R1 ←R1 ⊕R2
Example: R1 = 1010 and R2 = 1100
1010
Content of R1
1100
Content of R2
0110
Content of R1 after P = 1

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 Shift Micro-operations

Shift Micro-Operations: – these operations are used for serial transfer of data. They are also used in
conjunction with arithmetic, logic, and other data-processing operation.

The content of register can be shifted to the left or to the right. At the same time the bits are shifted,
the flip flop receives the binary information from the serial input.

There are three types of shift micro operation-

1. Logic shift 2. Circular shift 3. Arithmetic shift

Logical Shift:- The symbol “shl” is used for logical shift left and “shr” is used for logical shift right.

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 Shift Micro-operations

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 Shift Micro-operations

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 Concept of Horizontal and Vertical
Microprogramming

Micro-programmed control unit

Micro-programmed control unit can be classified into two types based on the type of
Control Word stored in the Control Memory.
• Horizontal micro-programmed control unit
• Vertical micro-programmed control unit

Horizontal micro-programmed control unit, the control signals are represented in the
decoded binary format, i.e., 1 bit/CS. Here ‘n’ control signals require n bit encoding.

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 Vertical Micro-programmed Control Unit

Vertical Micro-programmed Control Unit, the control signals are represented in the encoded
binary format. Here ‘n’ control signals require log2n bit encoding

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 Program Control
HALT – It brings the processor to an orderly halt, remaining in an idle state until restarted
by interrupt, trace, reset or external action.
Interrupt Instructions:
Interrupt is a mechanism by which an I/O or an instruction can suspend the normal execution
of processor and get itself serviced.

RESET – It reset the processor. This may include any or all setting registers to an initial
value or setting program counter to standard starting location.

TRAP – It is non-maskable edge and level triggered interrupt. TRAP has the highest priority
and vectored interrupt.

INTR – It is level triggered and maskable interrupt. It has the lowest priority. It can be
disabled by resetting the processor.

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 Pipelining

➢Pipelining is a technique where multiple instructions are overlapped during execution.

➢Pipelining is the process of accumulating instruction from the processor through a pipeline.

Pipeline Stages
RISC processor has 5 stage instruction pipeline to execute all the instructions in the
RISC instruction set.
Stage 1 (Instruction Fetch):
In this stage the CPU reads instructions from the address in the memory whose value is
present in the program counter.

Stage 2 (Instruction Decode):

In this stage, instruction is decoded and the register file is accessed to get the values from the
registers used in the instruction.

Stage 3 (Instruction Execute):

In this stage, ALU operations are performed.
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 Pipelining

Stage 4 (Memory Access:)

In this stage, memory operands are read and written from/to the memory that is present in the
instruction.

Stage 5 (Write Back):

In this stage, computed/fetched value is written back to the register present in the instructions

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 Pipelining

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 Memory

• A Memory Unit is a collection of storage cells together with associated circuits needed to transfer
information in and out of storage.

• The memory stores binary information(1's and 0's) in groups of bits called words. A storage
element is called a Cell.

• A group of eight bits is called a byte. Most computer memories use words whose number of bits
is a multiple of 8.

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 Classification of Memory

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 Memory Hierarchy

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 Memory Hierarchy

•RAM (Random Access Memory) is a part of computer’s Main Memory which is directly
accessible by CPU.

•RAM is used to Read and Write data into it which is accessed by CPU randomly. RAM is
volatile in nature.

• RAM is used to store the data that is currently processed by the CPU.

Integrated RAM chips are available in two form:

SRAM(Static RAM)
DRAM(Dynamic RAM)

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 2D and 2.5D Memory organization

2D Memory organization

In 2D organization memory is divides in the form of rows and columns. Each row contains a
word now in this memory organization there is a decoder.

A decoder is a combinational circuit which contains n input lines and 2n output lines.

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 2D Memory organization

2D Memory organization

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 2.5 D Memory organization

• In 2.5D Organization the scenario is the same but we have two different decoders one is column
decoder and another is row decoder.

• Column decoder used to select the column and row decoder is used to select the row. Address
from the MAR will go in decoders’ input.

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 Page Replacement Algorithm

• Page replacement is a process of swapping out an existing page from the frame of a main
memory and replacing it with the required page.
Page Replacement Algorithms-

• Page replacement algorithms help to decide which page must be swapped out from the main
memory to create a room for the incoming page.

• FIFO Page Replacement Algorithm

• LIFO Page Replacement Algorithm
• LRU Page Replacement Algorithm
• Optimal Page Replacement Algorithm

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 FIFO Page Replacement Algorithm

FIFO Page Replacement Algorithm-

• As the name suggests, this algorithm works on the principle of “First in First out“.
• It replaces the oldest page that has been present in the main memory for the longest time. It is
implemented by keeping track of all the pages in a queue.

Example:
A system uses 3 page frames for storing process pages in main memory. It uses the FIFO page
replacement policy. Assume that all the page frames are initially empty. What is the total number of
page faults, hit ratio and miss ratio and page reference string given below-
4 , 7, 6, 1, 7, 6, 1, 2, 7, 2

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 Solution-
Total number of references = 10

Total number of page faults occurred = 6

Total number of page hits
= Total number of references – Total number of page misses or page faults
= 10 – 6 = 4
Thus, Hit ratio = 4 / 10 = 0.4 or 40%, Miss ratio = 6 / 10 = 0.6 or 60%

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