Low Power Design Flow Based on Unified Power Format and Synopsys Tool Chain
Venkatesh Gourisetty1, Hamid Mahmoodi1, Vazgen Melikyan2,3, Eduard Babayan2, Rich Goldman4, Katie
Holcomb4, and Troy Wood4
1
School of Engineering, San Francisco State University, San Francisco, CA, USA
2
Synopsys Armenia CJSC, Yerevan, Republic of Armenia
3
State Engineering University of Armenia, Yerevan, Republic of Armenia
4
Synopsys Inc., Mountain View, CA, USA
Abstract
Unified Power Format (UPF) is an industry wide power
format specification to implement low power techniques in a
design flow. UPF is designed to reflect the power intent of a
design at a relatively high level. UPF scripts help describe
power intent such as: which power rails to be routed to
individual blocks, when blocks are expected to be powered
up or shut down, how voltage levels should be shifted
between two different power domains, and type of measures
taken for retention registers and memory cells contents if the
primary power supply to a domain is removed, hence helping
the design to be more efficient. With power becoming an
important factor in today's electronic systems, there is a need
for a more systematic approach to reduce power in complex
designs; and UPF is developed to address this need. We have
developed the complete UPF based low power design flow
from high level behavioral description to physical layout. The
design flow is accompanied by an example-driven and self-
study tutorial suitable for hands-on teaching. The examples
cover a variety of low power methods such as clock-gating,
multi-voltage, power gating, and the combination of multi-
voltage and power gating. This design flow is implemented
using Synopsys electronic design automation tools and tested
on Synopsys generic 90nm and 32/28nm libraries. The
synthesis scripts are setup in ‘tcl’ format that are compatible
with the Synopsys synthesis and physical design tools.
Keywords: Electronic Design Automation, Low Power,
Unified Power Format.
1. Introduction
Reducing power consumption in today’s technologies is
an important aspect of Integrated Circuit (IC) design. In the
previous generations of IC design, timing and area were the
major parameters of concern. Electronic Design Automation
(EDA) tools were designed to maximize speed and minimize
area at the same time. However, with technology scaling and
increasing need for complex electronic devices, power
consumption has grown to become a major challenge in
modern designs, demanding a new low power design
methodology. CMOS technology was considered to be a low
power technology at the relatively low clock frequencies of
old days with negligible leakage current. However, over the
years, device densities and clock frequencies have been
increasing dramatically in CMOS devices, thereby increasing
power consumption. At the same time, supply voltages and
transistor threshold voltages have been lowered, causing
leakage current to become a significant cause of power
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dissipation. As a result, power consumption has reached its
acceptable limits with changing trends; hence power has
become as important as timing and area in the design flow.
There is an array of effective low power design methods
that have been developed over years. These include
techniques such as clock gating, multi-voltage design, power
gating, and a combination of these [1]. Traditionally, such
design techniques were implemented in a custom fashion and
typically at the back-end phase of the design. With increasing
complexity of the design, custom application of such design
methods has become cumbersome and prohibitive. Unified
Power Format (UPF) has recently emerged as a standard for
specifying the power intent and such low power methods in
an early phase of the design and at high levels of abstraction
[1]. The automated design flow tool chain offered by
Synopsys Inc [2] supports UPF and allows designer to fully
automate the process of integration of low power design
methods into the design process.
To reflect such an emerging low power design
methodology in educational programs, we have developed an
example drive tutorial that guides students through the
different steps of the low power flow from high level
specification of power intent to low level physical design.
2. Unified Power Format (UPF)
UPF is the popular name of the Institute of Electrical and
Electronic Engineers (IEEE) 1801 standard for specifying
power intent in power optimization of electronic design
automation. UPF addresses the need for a common standard
to describe low power design intent. It helps improve the way
complex integrated circuits can be designed, verified, and
implemented. The purpose of the UPF is to
provide portability of low power design specifications that
can be used with a variety of commercial products
throughout an electronic system design.
The open standard provided by IEEE 1801 permits all EDA
tool providers to implement latest tool features which help
enable the design for low power ICs. The design begins at the
Register Transfer Level (RTL) and progresses into the
detailed stages of implementation and verification. UPF
facilitates as an interoperable, multi-vendor tool and ensures
consistency throughout the design process.
Synopsys tools are designed to follow the IEEE 1801 (UPF)
standard approved by the IEEE Standards Association in
March 2009. This standard is supported by a large number of
EDA companies, including Synopsys tools that support a
large subset of the commands in the IEEE 1801 (UPF)
28 Interdisciplinary Engineering Design Education Conference
 standard. In addition, Synopsys tools support some UPF-like
power intent commands that are not part of the standard.
3. Low Power Design Flow
Fig. 1 shows the UPF based low power design flow using
Synopsys synthesis and physical implementation EDA tools.
The flow starts with the register-transfer level (RTL)
description of the logic of the design, together with a separate
UPF description of the power intent of the design. The RTL
and UPF descriptions are contained in separate files so that
they can be maintained and modified separately. Synopsys
Design Compiler reads in the RTL logic and original UPF
power intent descriptions, and based on their contents, Fig 2: DC logic structure
synthesizes a gate-level netlist and an updated UPF file
(UPF’). The UPF’ file contains the original UPF information 3.2 Physical Synthesis Flow:
plus explicit supply net connections for special cells created The basic structure for ICC script is given in Fig 3. As
during synthesis. discussed, ICC script is split in two segments. First- design
planning and second- place & route. In first segment we
setup logical and physical libraries, followed by DC results
(netlist, UPF and SDC files). Once we setup design
constrains and power intent; physical layout, floor planning
and finally placement & routing are synthesized. A complete
gate level design is achieved.

Fig. 1: UPF design flow based on Synopsys EDA tool

IC Compiler reads in the gate-level netlist and UPF power

description files, and based on the file contents, performs
physical implementation (placement and routing), producing
a modified gate-level netlist, a complete power and ground
(PG) netlist, and an updated UPF file, UPF’’ (UPF double-
prime). The UPF’’ file contains the UPF’ information plus
any modifications to low-power circuit structures resulting
from physical implementation, such a power switches. Once
chip planning is done successfully, placement and routing is
initiated. This design flow has been tested with both the
90nm and 32/28nm Synopsys Generic Libraries available
through the Synopsys University Program [2, 3].
3.1 Logic synthesis flow:
The basic structure of a DC script is illustrated in Fig 2. First
target and link libraries are setup followed by RTL code.
Later, we define power intent by reading the UPF script (.upf
file) and setup design constraints by reading .sdc file. After
initial setup, optimization and compiling options are given to
perform DC synthesis. The compiler synthesizes and
produces gate level netlist and synthesized UPF script. The
results are saved to a separate directory.
Fig 3: Physical Synthesis Flow
4. Design Example
The purpose of the developed flow and tutorial is to show by
example how UPF is used in practice to implement designs
for low power. The chosen design example is small processor
block called ChipTop. ChipTop is a processor architecture
that features the Unified Power Format (UPF) for advanced
low power designs. A Top level representation of ChipTop is
shown in Fig. 4. The power domains of the ChipTop design
are shown in Fig. 5. This processor consists of five important
blocks, namely, Instruction Decoder (InstDecode), General
Purpose Registers (GPRs), Multiplier
(MULT), Generate Partial Products for 32x32 Multiplier
(GENPP), and Power Controller. GENPP is within the
Multiplier block; hence we can say it is under hierarchy of
Multiplier. This processor consists of 5 different power
domains: a default domain TOP; MULT, INST, and GPRS
that are Top-level domains; and GENPP which is inside a
logical hierarchy called top/Multiplier.

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 change to the RTL is required to implement this style of
clock gating. Fig 6 shows the physical layout obtained for
clock gating.

Fig. 4: ChipTop Top Level view

Fig. 6: Clock Gating Physical Layout

2. Multi Voltage: To simply UPF concepts, only one part
of the design example has been implemented i.e., GPRS
block. Multi Voltage Low Power technique is the most basic
form of power reducing approach when internal logic of the
chip is partitioned into multiple voltage regions or power
domains, each provided with its own supply. The GPRS
block will run lower voltage and TOP is set to higher voltage.
Fig. 5: ChipTop Power Domains It can be illustrated in Fig 7.
The three power domains in TOP are independently
switchable, using header switches. However, the logical
location of the power switches is different for each of the
power switches. The default TOP power domain and the
GENPP power domains are always-ON. The power intent for
this design can be captured from flat (top down), although
hierarchical UPF (bottom up) is advised for re-use purposes.
5. Low Power Methods Used:
This tutorial demonstrates the following Low Power
Methodologies.
1. Clock Gating Fig 7: Multi Voltage Design
2. Multi Voltage
3. Power Gating Supply voltages for the blocks are 1.08 and 0.7 for TOP and
4. MV with Power Gating GPRS power domains. The two domains will share common
1. Clock Gating: A significant part of the dynamic power VSS. To drive signals between distinct power domains with
in a chip is in the distribution network of the clock. Up to 50 radically different power rails, we need special buffers, level
% of the dynamic power can be spent in the clock buffers. shifters that have the ability to shift a signal coming in at one
These buffers have the highest toggle rate in the system and voltage level and drive an output at a different voltage level.
they often have high drive strength to minimize clock delay.
In addition, the flops receiving the clock dissipate some
dynamic power even if the input and output remain the same.
The most common way to reduce this power is to turn clocks
off when they are not required.
Clock gating is a well-established power-saving technique
that has been used for years. Synthesis tools such as Power
Compiler can detect low-throughput data paths where clock
gating can be used with the greatest benefit, and can
automatically insert clock-gating cells in the clock paths at
the appropriate locations. Fig 8: Multi Voltage Physical Layout
Today, most libraries include specific clock gating cells that
are recognized by the synthesis tool. The combination of Typically level shifters are placed in the receiving domain –
explicit clock gating cells and automatic insertion makes in the lower domain for High-to- Low shifters, in the higher
clock gating a simple and reliable way of reducing power. No domain for Low- High shifters. So, as the GPRS block

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 operates at lower voltage, High-to-Low level shifters will be
inserted in GPRS power domain and the Low-to-High level
shifters will be placed in TOP domain. The physical layout
for Multi Voltage is given in Fig 8.
3. Power Gating: The basic strategy of power gating is to
provide two different power modes: a low power mode and
an active mode. The goal is to switch between these modes at
the appropriate time and in the appropriate manner to
maximize power savings while minimizing impact to
performance. The concept of power gating example on
ChipTop design is illustrated in Fig 9.
Fig 11: MV with Power Gating

In this example, our objective is to use both techniques, Multi

Voltage and Power Gating. In our example we apply low
power techniques only on GPRS block. Hence, we have
defined two power domains, TOP and GPRS and two supply
ports VDD (1.2) and VDDG (0.7). The TOP operates at High
Voltage and GPRS block operates at Low Voltage. If the
device is set in sleep mode the GPRS is turned OFF or power
gated using a switch. The physical layout is depicted in
Fig 12.
Fig 9: Power Gating Design
In this design, we have two power domains, first is the
domain TOP runs on high voltage (1.2) and the other block
GPRS which switches between two states, 1.2 (when ON)
and turned OFF in standby mode. A switch is designed to
switch deliberately between these two operating modes.
The physical layout is given in Fig 10.

Fig 12: MV with Power Gating Physical Layout

6. Conclusions
A low power design flow based on the UPF standard and
using the Synopsys EDA tools is developed and tested in
Synopsys generic 90nm and 32/28nm libraries. An example
driven tutorial is developed to self-guide student through the
design flow.
Fig 10: Power Gating Physical Layout
7. Acknowledgment
The authors would like to acknowledge Synopsys Inc. for
4. MV and Power Gating: The final example is the
electronic design automation tools and technical support.
combination of MV and Power Gating. Partitioning a design
into separate power domains introduces new interfaces
between each power domain. These added interfaces may References
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are known, predictable and well understood. During design http://www.synopsys.com
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impact on these critical paths and make sure that any new kit: capabilities, deployment and future", IEEE Int.
critical paths were not created. Conference on Microelectronic Systems Education, pp.
20-24, 2009.

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