High PSR LDO with Adaptive-EFFRC for Wearable

Biomedical Application
Cipriano Rey Hipolito IV Angelito Silverio Renan Nuestro
Graduate School Graduate School Analog IC Design
2021 IEEE International Symposium on Circuits and Systems (ISCAS) | 978-1-7281-9201-7/20/$31.00 ©2021 IEEE | DOI: 10.1109/ISCAS51556.2021.9401677

University of Santo Tomas University of Santo Tomas Analog Devices, Inc.- Gen. Trias
Manila, Philippines Manila, Philippines Cavite, Philippines
reyhipolito.cipriano.gs@ust.edu.ph aasilverio@ust.edu.ph Renan.Nuestro@analog.com

Abstract—An analog capped low-dropout regulator (LDO)

with a high-power supply rejection (PSR) and low quiescent
current consumption (IQ) is presented and designed in TSMC’s 180
nm technology. The LDO is intended for wearable biomedical
applications due to its low power consumption and simple
topology. The high PSR performance in the DC to medium
frequency range is achieved by adapting the embedded feed-
forward ripple cancellation (EFFRC) technique. Additionally, the
PSR enhancement of 30 to 50 dB is maintained across different
loading conditions and input voltages by utilizing the proposed
adaptive feed-forward gain solution. The best simulated PSR from
DC to 250 Hz is no less than -90 dB at a load current (ILOAD) of 200
mA and 100 mA, -78.7 dB at 500 μA, and -75.2 dB at no-load. The
LDO has an external load capacitor of 4.7 μF and a minimum IQ of
6.5 μA. It achieved a line regulation and load regulation of 8.27
mV/V @ 200 mA-ILOAD and 30 mV/mA @ 2.7-VIN, respectively.
Keywords— Low-dropout regulator (LDO), power-supply
rejection (PSR), wearable biomedical application, low power,
embedded feed-forward ripple cancellation (EFFRC), adaptive feed-
forward gain
I. INTRODUCTION
In wearable biomedical systems, non-invasive methods are
applied for heart rate monitoring [1]. These systems utilize
modern sensors for measuring the signals created by cardiac
muscle activity. These sensors are paired with analog front ends
(AFE) for electrocardiogram (ECG) and photoplethysmogram
(PPG) signal acquisition [2-3]. These AFEs are composed of
circuit components that demand a very low, clean, and regulated
voltage supply level due to the progressions made in CMOS
technology [4]. Therefore, a power management block is usually
required to bridge the battery and the interior components of the
system. The block is to derive a very low, clean, and regulated
voltage supply level from a high, noisy, and unregulated voltage
provided by the battery. The perfect circuit to be used for the
power management block is a Low-Dropout Voltage Regulator
(LDO) [5].
One important specification for an LDO is the Power Supply
Rejection (PSR). It is the ability of a system to reject supply
variations from the power supply over a wide frequency range
[6]. A low PSR will result in ripples and noise penetrating
through the LDO and reducing the integrity of the load system.
Fig. 1. Block Diagram of the Proposed LDO
These ripples and noise originate due to the processes required
inside the battery to provide power and they dwell in the DC to
low frequency domain [7].
To improve PSR performance, best existing studies on feed-
forward ripple cancellation (FFRC) adaptation have been
already proposed utilizing a voltage mode FFRC [8], adaptive
supply ripple cancellation (ASRC) [9], and current mode FFRC
[10]. However, all these mentioned adaptations require high-
bandwidth op-amps to perform the function of a feed forward
amplifier. This will require additional quiescent current (IQ) for
operation and will restrict the lowest possible IQ consumption of
the LDO. To solve this, an op-amp-less approach for the feed-
forward path is presented in [11] which is called an embedded
feed-forward ripple cancellation (EFFRC). It merges the feed-
forward amplifier and the summation amplifier into a single
buffer stage which reduces the complexity of design and static
power consumption while still improving the PSR. However, all
existing EFFRC methods [11-13] achieves the target PSR
enhancement only in a limited range of load current (ILOAD) and
input voltage (VIN).
Based on the above considerations, an adaptive embedded feed
forward ripple cancellation (A-EFFRC) is proposed. The
proposed structure removes the constraints set by the output
current and headroom voltage for the effectivity of the PSR
enhancement. This will be done by producing a current
difference across the transistors in the buffer stage and this
current will make the feed-forward gain adaptive. Results will

This work was fully supported by a thesis grant from Analog Devices, Inc.
– General Trias, Cavite, Philippines

978-1-7281-9201-7/21/$31.00 ©2021 IEEE

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 Fig. 2. Equivalent PSR Signal Flow Graph from EFFRC Fig. 3. Topology for the Proposed Solution

show that the PSR improvement in the LDO at DC to medium signal flow from the topology will provide the graph in figure
frequencies will be maintained at all the target ILOADs and VINs. 6. The embedded feed-forward path is the branch with the gain
of gm2/gm1 which is the feed-forward gain (AFF).
II. TOPOLOGY OF THE PROPOSED ADAPTIVE-EFFRC Deriving the equivalent PSR transfer function from Fig. 2.
will provide:
A. Embedded Feed-Forward Ripple Cancellation 𝑔
1+𝑔𝑚,𝑝 𝑟𝑑𝑠,𝑝 (1− 𝑚2 )
𝑣𝑜𝑢𝑡 (𝑠) 𝑔𝑚1
As shown in Fig. 1, the buffer stage is composed of M1 and 𝑃𝑆𝑅𝐸𝐹𝐹𝑅𝐶 = = 𝑟𝑑𝑠,𝑀𝑝 𝑟𝑑𝑠,𝑀𝑝 𝑅𝐹2 𝑔𝑚,𝑝 𝑟𝑑𝑠,𝑝 𝐴𝑒𝑜 (1)
𝑣𝑖𝑛 (𝑠) 1+ + +
M2. These transistors simultaneously function as the feed- 𝑍𝐿 (𝑠) 𝑅𝐹1 +𝑅𝐹2 (𝑅 +𝑅 )(1+ 𝑠 )
𝐹1 𝐹2 𝑤𝑒
forward amplifier and the summing stage. M2 is to act as the where gm,MP is the transconductance of the pass transistor, and
feed-forward amplifier by acting as a common-gate amplifier rds,MP is the drain to source resistance of the pass transistor. For
passing through the supply variations with a corresponding the ideal PSR enhancement, the numerator is set to zero and
feed-forward gain (AFF) of gm2/gm1. It performs as a feed- will give the feed-forward gain requirement (AFF-PSR):
forward amplifier due to the low-pass filter (LPF) shunting its
gate to the AC ground. Both M1 and M2 act as the summing 𝑔𝑚2
≈
1+𝑔𝑚,𝑝 𝑟𝑑𝑠,𝑝
=
1+𝐴𝑂
(2)
stage wherein they merge the feed-forward path and the main- 𝑔𝑚1 𝑔𝑚,𝑝 𝑟𝑑𝑠,𝑝 𝐴𝑂
feedback loop of the LDO. The merging is possible by the
addition of the feed-forward signal and the feedback signal are where AO is the intrinsic gain of the pass transistor. Ideally,
performed in current form. AFF-PSR is always unity and therefore, AFF is fixed to unity [11-
13]. However, in different loading conditions and headroom
Different from the designs in [11-13], an additional current
voltages, AFF-PSR becomes greater than 1.
branch is added at the gate of MPASS which pulls an adaptive
current depending on the ILOAD and the VIN. This is to ensure that The effect of the ILOAD and VIN on the intrinsic gain can be
the PSR enhancement from EFFRC adaptation will be effective seen by expressing the intrinsic gain (AO) in terms of drain
across all loading conditions and all possible headroom voltages. current (ID) and drain to source (VDS):

B. Adaptive Biasing Circuit and Adaptive Zero 1 𝑊

𝐴𝑂 = 𝑔𝑚 𝑟𝑑𝑠 = √2𝐼𝐷 𝑘𝑃 (1 + 𝜆𝑉𝐷𝑆 ) (3)
The topology for the adaptive biasing circuit in [10] is used 𝜆𝐼𝐷 𝐿
to control the variable current source and the adaptive zero [14]
based on the ILOAD, and to adaptively bias the error-amplifier. From (3), as VDS increases, the AO increases and causes the
The purpose of using the adaptive biasing topology is to feed-forward gain requirement to approach 1 and vice versa.
effectively lower the standby current consumption of the LDO, Also, as ID increases, AO decreases and causes AFF-PSR to
to maintain the system’s stability, and to contribute to sustaining approach 1 and vice versa. These inconsistencies in the AFF-PSR
the ideal PSR for EFFRC adaptation across all ILOADs caused by changing load condition and headroom voltage gives
rise to ILOAD and VIN restrictions in achieving the PSR
enhancement [11-13].
C. CMOS Voltage Subtractor
A CMOS voltage subtractor provides an output which is
equal to the difference in its input gates [15]. The main purpose B. Proposed LDO with an Adaptive-EFFRC
of the CMOS voltage subtractor is to control the adaptive To address the inconsistencies in AFF-PSR, AFF is proposed to be
current source depending on VIN. This topology will contribute made adaptive based on the ILOAD and the VIN. This will be achieved
to sustaining the PSR enhancement of the EFFRC across all by creating a difference in the currents across each transistor in the
headroom voltages which will be discussed later. buffer stage as shown in Fig. 3.
The current pulled (IPULL) by the proposed adaptive current
III. PRINCIPLE OF THE PROPOSED LDO WITH ADAPTIVE-EFFRC source will create a gm difference between M1 and M2 to
achieve the target AFF. This can be seen by expanding AFF:
A. EFFRC Ideal PSR Enhancement
𝑊
In the EFFRC adaptation (ignoring the variable current 𝑔𝑚2
√2𝐼𝐷2 𝑘𝑃
𝐿2
𝑊
𝐼𝐷2 𝐿
source) as seen in Fig. 1, the PSR signal flow graph can be 𝐴𝐹𝐹 = = =√ 𝑊
2
(4)
𝑔𝑚1 𝑊 𝐼𝐷1
√2𝐼𝐷1 𝑘𝑃
derived as shown in Fig. 2 [11]. Deriving the equivalent PSR 𝐿1 𝐿1

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 Fig. 4. Proposed IPULL-ILOAD-VIN Scheme
Fig. 5. Core Schematic of the Proposed LDO
Fig. 6. Current-Mode Bandgap Voltage Reference
wherein traditionally, ID2 and ID1 is equal due to the cascode
structure of the buffer stage. To produce a current difference,
the proposed additional current branch will sink the current IPULL
from the gate of the pass transistor. This can be seen by performing
a KCL at the gate of the pass transistor and plugging the result into
(5) will show the proportional response of I PULL with the feed-
forward gain:
𝑔𝑚2 𝐼𝑃𝑈𝐿𝐿
𝑊
𝐿2
𝐴𝐹𝐹 = = √1 + √ 𝑊 (5)
𝑔𝑚1 𝐼𝐷1
𝐿1
The current IPULL will depend on the VIN and the ILOAD as
shown in Fig. 4. As discussed in section A in this chapter, as the
ILOAD increases, the feed-forward gain requirement becomes
greater than unity. To follow this movement, the feed-forward
gain is increased by increasing IPULL. As the ILOAD is decreased,
the requirement approaches unity. To follow this movement, the
feed-forward gain is decreased by decreasing IPULL.
As discussed also in section A in this chapter, as the VIN
increases, the maximum AFF-PSR decreases and vice versa. At the
minimum VIN, AFF-PSR tends to move within a wider range. At
the maximum VIN, the movement AFF-PSR becomes negligible.
The range of AFF-PSR’s drift will be tracked by changing the
maximum AFF as the VIN changes. As the VIN increases, the
maximum achievable AFF is decreased and vice versa.
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Fig. 7. Topology for the Adaptive Biasing Circuit
Fig. 8. Topology for the Adaptive Current Branch
IV. CIRCUIT IMPLEMENTATION
The core schematic of the proposed LDO is shown in Fig.
5. It consists of a modified folded-cascode error amplifier, a
buffer stage, a LPF, and an adaptive zero.
A. Bandgap Voltage Reference
In the system, a bandgap voltage reference (BGR) will be
utilized to perform two functions: provide the voltage
references for the LDO and the CMOS voltage subtractor and
provide the biasing current for the EA and the buffer stage. The
BGR topology used is the current mode bandgap reference as
shown in Fig. 6 [16].
B. Error Amplifier for the LDO
The topology to be utilized for the error-amplifier is shown
in Fig. 5 [17]. In finding the PSR small signal model for the
topology, it can be derived that its output will be independent
from the supply or VIN.
C. Buffer Stage and Low-Pass Filter
The buffer stage is composed of MP2 and MP1 and the gate
of MP2 will be biased by the LPF composed of MPfilter and Cfilter
as seen in Fig. 5. MP2 and MP1 will be sized to have equal gms
to achieve the ideal AFF-PSR of 1.
The LPF is set to have a very low cut-off frequency to
maintain the gate of MP2 at AC ground across the frequency
spectrum. Therefore, a diode connected PMOS (MPfilter) is used
for the LPF to have a virtually infinite resistance.
D. Adaptive Biasing Circuit
The adaptive biasing circuit, as explained in section B
chapter II, has three main functions: to control the effective
resistance for the adaptive zero, to control the biasing currents
for the error-amplifier, and to assist in controlling the adaptive
current source.
E. Adaptive Current
To realize the proposed solution in section B chapter III, an
additional current branch, which is composed of MN32 and
MN33, was introduced at the gate of the pass transistor as seen
in Fig. 8. As ILOAD increases, the current across MN30 will
increase. The voltage at the node adaptive will increase and
cause MN32 to pull more current. As I LOAD decreases, the
 TABLE I. PERFORMANCE COMPARISON
Fig. 9. PSR Performance of the LDO w/o EFFRC
TABLE II. PSR OF AN EFFRC W/ FIXED AFF @ VIN,MIN
TABLE III. PSR OF AN EFFRC W/ FIXED AFF @ ILOAD,MAX
opposite of the mentioned process will occur. This causes MN32
to sink the current IPULL depending on the ILOAD. IPULL will cause
a current difference in the buffer stage that will make A FF
approximately equal to AFF-PSR across varying ILOADs. MN33 will
limit the maximum IPULL depending on the VIN or headroom
voltage. Therefore, the transistor’s input is from the CMOS
voltage subtractor’s output which is dependent on the voltage
supply’s movement. The subtractor’s output decreases as the
voltage supply level increases and vice versa. With this action,
MN33 will start to decrease the maximum value of IPULL as the
voltage supply starts to increase and vice versa. This will cause
the AFF virtually equal to the AFF-PSR across different voltage
supply levels.
V. SIMULATION RESULTS AND DISCUSSION
The PSR performance of a traditional LDO across all the
loading conditions and input voltages is shown in Fig. 9. The
PSR within the DC to medium frequencies maintains a value of
41 dB. In adapting EFFRC, the PSR can be effectively enhanced
by a value of 27 to 50 dB as shown in TABLES II and III. In
TABLES II and III, the second column contains the
corresponding fixed AFF of the buffer stage and the third column
contains the corresponding AFF-PSR for ideal PSR enhancement.
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Fig. 10. PSR Performance of the Proposed LDO
Fig. 11. Transient Response of the Proposed LDO
TABLE II contains the PSR performance of adapting an
EFFRC technique and it can be seen that a fixed AFF will
produce a PSR less than 70 dB with changing load conditions.
Fixing the AFF to achieve the target AFF-PSR at one of the ILOADs
will lower the effectivity of the PSR enhancement when the
ILOAD changes.
TABLE III is similar to TABLE II but the headroom voltage
is being varied. It can be also seen that a fixed A FF will give a
PSR less than 70 dB with changing headroom voltages. Fixing
AFF to achieve the target AFF-PSR at one of the input voltages will
lower the effectivity of the PSR enhancement when the pass
transistor’s headroom voltage changes.
The proposed LDO was designed in LTspice XVII by using
TSMC’s 180-nm model file obtained from MOSIS wafer test
runs. The LPF’s capacitance value was 20 nF, and the
capacitance and resistance for compensation are 3 pF and 1
MΩ, respectively. The load capacitance utilized was 4.7 µF
with an ESR 7 mΩ and an ESL 130 pH. The target VOUT is 1.8
V and the VIN ranges from 2.3 V to 3 V. The dropout voltage is
450 mV at the maximum ILOAD of 200 mA. The minimum IQ
consumption of the LDO is 6.5 µA. The achieved line
regulation and load regulation are 8.27 mV/V @ 200 mA-ILOAD
and 30 mV/mA @ 2.7-VIN, respectively.
Fig. 10 indicates the PSR enhancement is maintained under
all loading conditions and input voltages. The worst achieved
PSR is 70.85 dB and the best achieved PSR is 91.52 dB. The
load transient performance of the LDO with a rise and fall time
of 250 ns and VIN of 2.5 V is shown in Fig. 11. The typical
undershoot voltage is 15 mV with a settling time of 1.7 µs.
 Table I shows the performance comparison between the
mentioned studies for FFRC adaptation and the proposed LDO.
Making a direct comparison between the proposed LDO of this
study and of those in the mentioned table is difficult. Therefore,
a FOM by J. Guo et al. [11] was utilized which considers the
design’s technology, minimum IQ, dropout voltage, and PSR at
the frequency of interest. The lower the FOM, the better the
LDO suppresses supply noise with a lower power consumption,
dropout voltage, and technology dependence. Based on the
mentioned table, the proposed LDO has the best FOM at the
frequency range of DC to the medium frequencies which is the
domain where the system focuses on removing supply ripples
and noise. However, the proposed LDO’s FOM at higher
frequencies becomes the worst.
VI. CONCLUSION AND FUTURE WORK
A high PSR low quiescent current analog PMOS capped-
LDO is proposed by utilizing an embedded feed-forward ripple
cancellation technique with an adaptive AFF. Making the AFF
adaptive and equal to AFF-PSR maintains the PSR enhancement
across all loading conditions and headroom voltages. It utilizes
a simple topology and has a low power consumption which can
be applied in wearable biomedical systems.
Due to the limitations of LTspice XVII, the proposed LDO
was not able to undergo Monte Carlo simulations and PVT
variations. After gaining access to Cadence Virtuoso, it will be
utilized to perform the previously mentioned simulations and
variations and acquire realistic results.
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ACKNOWLEDGMENT
The authors would like to thank Analog Devices, Inc. –
General Trias, Cavite, Philippines for fully sponsoring and
supporting this study.

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