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    x86 Translation and Registers

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    rlxazibiffaylchmvp
    The document summarizes the process of protected-mode address translation in Intel CPUs. It involves three levels of translation: 1) A segment selector and offset from the logical address are used to lookup a linear address in the GDT or LDT table. 2) The linear address is used to lookup a physical page number and offset using the page directory and page table. 3) The physical page number and offset give the full physical address in RAM. Control registers like CR0, CR2, CR3 and flags determine properties of address translation and memory protection.

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    x86 Translation and Registers

    Uploaded by

    rlxazibiffaylchmvp
    7 views2 pages
    The document summarizes the process of protected-mode address translation in Intel CPUs. It involves three levels of translation: 1) A segment selector and offset from the logical address are used to lookup a linear address in the GDT or LDT table. 2) The linear address is used to lookup a physical page number and offset using the page directory and page table. 3) The physical page number and offset give the full physical address in RAM. Control registers like CR0, CR2, CR3 and flags determine properties of address translation and memory protection.

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    The document summarizes the process of protected-mode address translation in Intel CPUs. It involves three levels of translation: 1) A segment selector and offset from the logical address are used to lookup a linear address in the GDT or LDT table. 2) The linear address is used to lookup a physical page number and offset using the page directory and page table. 3) The physical page number and offset give the full physical address in RAM. Control registers like CR0, CR2, CR3 and flags determine properties of address translation and memory protection.

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    7 views2 pages

    x86 Translation and Registers

    Uploaded by

    rlxazibiffaylchmvp
    The document summarizes the process of protected-mode address translation in Intel CPUs. It involves three levels of translation: 1) A segment selector and offset from the logical address are used to lookup a linear address in the GDT or LDT table. 2) The linear address is used to lookup a physical page number and offset using the page directory and page table. 3) The physical page number and offset give the full physical address in RAM. Control registers like CR0, CR2, CR3 and flags determine properties of address translation and memory protection.

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    of 2

    Protected-Mode Address Translation

    x GB

    Selector Linear Physical


    Segment Address Page Address
    CPU Offset Translation Translation
    Logical
    Address
    0
    RAM

    Logical Address Linear Address Physical Address


    16 32 10 10 12 20 12

    Selector Offset Dir Table Offset PPN Offset

    32 20 12 20 12

    1023
    PPN Flags
    16
    8 Base Limit Flags 20 12
    0 1023
    GDT/LDT 1
    0
    Page Table
    PPN Flags

    1
    0
    CR3
    Page Directory

    31 12 11 10 9 8 7 6 5 4 3 2 1 0

    A
    P Present
    P C W
    Page table physical page number V G
    S
    0 A
    D T
    U W P W Writable
    L
    U User
    PDE WT 1=Write-through, 0=Write-back
    CD Cache disabled
    A Accessed
    31 12 11 10 9 8 7 6 5 4 3 2 1 0
    D Dirty
    PS Page size (0=4KB, 1=4MB)
    A P C W
    Physical page number V G A D A U W P PAT Page table attribute index
    L D T
    T G Global page
    PTE AVL Available for system use
    31 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

    I
    V V
    I A V R N O O D I T S Z A P C
    EFLAGS D
    I I
    V M F
    0
    T P F F F F F F
    0
    F
    0
    F
    1
    F
    P F
    L

    Status flags Control flags RF Resume flag


    CF Carry flag DF Direction flag VM Virtual-8086 mode
    PF Parity flag System flags AC Alignment check
    AF Auxiliary carry flag TF Trap flag VIF Virtual intr. flag
    ZF Zero flag IF Interrupt enable flag VIP Virtual intr. pending
    SF Sign flag IOPL I/O privilege level ID ID flag
    OF Overflow flag NT Nested task

    31 30 29 28 19 18 17 16 15 6 5 4 3 2 1 0

    P C N A W N E T E M P
    CR0 G D W M P E T S M P E

    PE Protection enabled ET Extension type NW Not write-through


    MP Monitor coprocessor NE Numeric error CD Cache disable
    EM Emulation WP Write protect PG Paging
    TS Task switched AM Alignment mask

    31 0

    CR2 Page fault virtual address

    31 12 11 5 4 3 2 0

    P P
    CR3 Page-Directory-Table Base Address C W
    D T

    PWT Page-level writes transparent PCT Page-level cache disable

    31 11 10 9 8 7 6 5 4 3 2 1 0

    O O
    P P M P P T P V
    S S D
    CR4 X F
    C G C A S
    E
    S V M
    E E E E E D I E
    M X

    VME Virtual-8086 mode extensions MCE Machine check enable


    PVI Protected-mode virtual interrupts PGE Page-global enable
    TSD Time stamp disable PCE Performance counter enable
    DE Debugging extensions OSFXSR OS FXSAVE/FXRSTOR support
    PSE Page size extensions OSXMM- OS unmasked exception support
    PAE Physical-address extension EXCPT

    15 3 2 1 0

    R
    CS/DS/ES T TI Table index (0=GDT, 1=LDT)
    Selector index P
    FS/GS/SS I
    L RPL Requester privilege level

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