Electronics Lab Part 3-1

Prerana Educational and Social Trust (R.
)
PES INSTITUTE OF TECHNOLOGY AND MANAGEMENT
NH-206, Sagar Road, Shivamogga-577204, Karnataka, India.
Affiliated to VTU, Belagavi, Approved by AICTE, New Delhi, Recognised by Govt.
of Karnataka
An ISO 9001:2015 Certified Institute
Department of Electronics and Communication Engineering
EXPERIMENT NO: 01
A) Bridge Rectifier with Capacitor Input Filter.
AIM:
To design and test bridge rectifier with capacitor input filter and obtain the ripple factor &
efficiency
COMPONENTS REQUIRED:
1) Resistor – 1 K Ω
2) Diode – BY127
3) Capacitor - 470 µF
4) Transformer
5) CRO
THEORY:
Rectifier is device which converts AC voltage to Pulsating DC voltage using one or more p-n
junction diode. Basically, rectifier are classified into two categories depending upon the period
of conduction.
1) Half Wave Rectifier
2) Full Wave Rectifier
 Centre tapped full wave rectifier
 Bridge rectifier
A device is capable of converting a sinusoidal input waveform into a unidirectional waveform
with non zero average component is called a rectifier. The Bridge rectifier is a circuit, which
converts an ac voltage to dc voltage using both half cycles of the input ac voltage. The Bridge
rectifier has four diodes connected to form a Bridge. The load resistance is connected between
the other two ends of the bridge. For the positive half cycle of the input ac voltage, diode D1 and
D3 conducts whereas diodes D2 and D4 remain in the OFF state. The conducting diodes will be
ELECTRONIC PRINCIPLES AND CIRCUITS (BEC303)Page 1

Prerana Educational and Social Trust (R.)
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in series with the load resistance RL and hence the load current flows through RL . For the
negative half cycle of the input ac voltage, diode D2 and D4 conducts whereas diodes D1 and D3
remain in the OFF state. The conducting diodes will be in series with the load resistance RL and
hence the load current flows through RL in the same direction as in the previous half cycle. Thus
a bidirectional wave is converted into a unidirectional wave.
CIRCUIT DIAGRAM:
(a) Circuit diagram (b) Input / Output waveform

Full wave Bridge Rectifier with capacitor input Filter
CALCULATION:
1) V m = ________ Volts
2) V r ( p− p) = ________ Volts
V r (p− p )
3) V r −rms = =¿________ Volts
2 √3
4) V rms =√ V 2dc + V 2r−rms
V r ( p− p)
V dc =V m −
2
5) Ripple Factor:

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V r−rms
γ=
V dc
6) Efficiency:
2
V dc
η= x 100 %
V rms
PROCEDURE:
 Components/ Equipment are tested for their good working condition.
 Connections are made as shown in the circuit diagram.
 Observe the input and output wave forms on CRO.
 Measure Vdc using multimeter in DC mode and Vm on CRO.
 Calculate the Vrms from Vm using the formula.
 Calculate the efficiency and ripple factor.
RESULT:
Bridge rectifier with Capacitor input filter is designed and its input-output waveforms are
verified.
Ripple Factor=
Efficiency=

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B) Zener voltage regulator
AIM: To Design and test a simple Zener voltage regulator and determine line and load regulation
1) Zener diode
2) Transistor 2N3055
3) Resistor – 100 Ω
4) Rheostat
5) DC regulated power supply
6) Multimeters
THEORY:
A zener diode is always operated in its reverse biased condition. A voltage regulator circuit can
be designed using a zener diode to maintain a constant DC output voltage across the load in spite
of variations in the input voltage or changes in the load current.
CIRCUIT DIAGRAM:
Figure: Circuit Diagram

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Tabular column for line regulation:
IL = mA
Vi in Volts Vo in Volts
Nature of graph:
Figure: Line Regulation
Percentage of line regulation:

ΔV 0
= Δ V i 100%=

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Tabular column for load regulation:
Vi  15V
I L in mA VO in Volts
Nature of graph:
Fig.3. 5 Load Regulation
VNL =____________
Percentage of load regulation:

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V NL−V F L
V R= X 100 %
V NL
V R= _________%
PROCEDURE:
1) Set up the circuit as shown in the circuit diagram.
2) Vary the input voltage from 10v to 20v in steps of 1v and note down the output voltage.
Plot the line regulation characteristics with Vi along x-axis and V0 along Y-axis.
Calculate percentage line regulation using expression
ΔV 0
Δ V i X 100%
3) Keep the input voltage at 15V and note down output voltage by varying the load current in
equal steps using a rheostat. Plot the load regulation characteristics with I L along X-axis and V 0
along y-axis.
4) Measure the full load voltage V FLby adjusting the rheostat until ammeter reads maximum
current.
5) Remove the rheostat and measure the output voltage to get no load voltage V NL.
6) Mark V NL and V FLon the load regulation characteristics and calculate load regulation as per
equation
V −V FL
V R= NL X 100 %
V NL
RESULT:
1) Line regulation =
2) Load regulation=

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EXPERIMENT: 2
A) CLIPPERS
AIM: To Design and Test Biased Clippers

1. Positive
2. Negative
3. Positive-Negative
2) Diode – IN4007
3) Power Supply
4) CRO
5) Signal Generator
THEORY:
Clipper: The clippers have the ability to remove signal voltages above or below a specified level & hence
change the wave shape of the I/P signal. Most of the clippers employ diodes & are known as diode
clippers.
Different type of clippers are
Positive & Negative clipper: A circuit that removes +ve half-cycle of the signal is called +ve clipper.
Sometimes, it is required to remove the –ve half cycle of the I/P signal, the only thing to be done is to
reverse the polarity of the diode connected across load, such a clipper is known as a –ve clipper.
Biased clipper: A clipper used to remove a small portion of +ve or –ve half cycle of the signal Voltage is
called a biased clipper. A diode is employed in series with a battery of different volts depending upon the
requirement.
Combination clipper (Positive – Negative Clipper): In this circuit small portion of +ve as well as small
portion of –ve half Cycle of the signal voltage is removed.
CIRCUIT DIAGRAM:

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Combination clipper (Positive – Negative Clipper):
PROCEDURE:

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1) Components / Equipment are tested for their good working condition.

2) Connections are made as shown in the circuit diagram
3) Apply a sine wave of amplitude greater than the designed clipping level with frequency 500
Hz. Observe the output wave form on the CRO
4) Observe the transfer characteristic curve on CRO by applying input waveform to channel –
X and output waveform to channel – Y.
5) Measure the clipped voltage and compare with the designed value.
RESULT:
Output waveforms and transfer characteristics are verified.

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B) CLAMPER CIRCUIT
AIM: To design Positive and Negative Clampers with and without Reference.
2) Diode – IN4007
3) Capacitor - 0.1 µF
4) Power Supply
5) CRO
6) Signal Generator
THEORY:
Clamper is a circuit which adds DC level to an AC waveform. There are two types of
clampers namely positive clampers and negative clampers. In positive clampers positive DC level
will be added to the AC waveform or the negative peak will be clamped to some other level. In
Negative peak clampers negative DC level will be added to the AC waveform or the positive peak
will be clamped to some other level.
Clampers are very much used in communication systems for example clampers are used in
analog television receivers for the purpose of restoring the dc component of the video signal prior
to its being fed to the picture tube.
CIRCUIT DIAGRAM:
Positive Clamper Circuit:

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Positive clamper with +ve reference voltage Vr:
Positive clamper with -ve reference voltage Vr:
Negative Clamper Circuit:

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Negative Clamper Circuit with +ve reference voltage Vr:
Negative Clamper Circuit with -ve reference voltage Vr:
PROCEDURE:
1) Connect the circuit as per circuit diagram.
2) A sinusoidal signal of 1kHz and amplitude of 12Vp-p is applied as input from the
Signal generator.
3) Observe output waveforms on the CRO and verify it with the given output
waveform.
RESULT:
Output waveforms are verified.
EXPERIMENT 3:
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Characteristics of Junction Field Effect Transistor (JFET)
AIM: To Plot the transfer and drain characteristics of a JFET and calculate its drain resistance,
mutual conductance and amplification factor.
1) JFET- BFW10
2) Ammeter – 0-20mA / 200mA
3) Resistor – 1KΩ
4) Power Supply – 0-30V
5) Digital multimeter
THEORY:
The junction gate field-effect transistor (JFET or JUGFET) is the simplest type of field-effect
transistor. They are three-terminal semiconductor devices that can be used as electronically-
controlled switches, amplifiers, or voltage-controlled resistors.
Unlike bipolar transistors, JFETs are exclusively voltage-controlled in that they do not need a
biasing current. Electric charge flows through a semiconducting channel between source and
drain terminals. By applying a reverse bias voltage to a gate terminal, the channel is "pinched",
so that the electric current is impeded or switched off completely. A JFET is usually on when
there is no potential difference between its gate and source terminals. If a potential difference of
the proper polarity is applied between its gate and source terminals, the JFET will be more
resistive to current flow, which means less current would flow in the channel between the source
and drain terminals. Thus, JFETs are sometimes referred to as depletion-mode devices.
JFETs can have an n-type or p-type channel. In the n-type, if the voltage applied to the gate is
less than that applied to the source, the current will be reduced (similarly in the p-type, if the
voltage applied to the gate is greater than that applied to the source). A JFET has a large input
impedance (sometimes on the order of 1010 ohms), which means that it has a negligible effect on
external components or circuits connected to its gate.

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CIRCUIT DIAGRAM:
GRAPH:
Tabular Column

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Drain
Characteristics Transfer Characteristics
At VGS =___V At VGS = ___V At VDS =___V At VDS = ___V
VGS VGS
VDS (V) ID (mA) VDS (V) ID (mA) (V) ID (mA) (V) ID (mA)
Procedure:
1. Check the components for their working condition.
2. Connect the components as shown in the circuit diagram.
To plot drain characteristics:
3. Keep the voltage VGS at constant value (say 0 V) by varying VDS supply.
4. Vary the voltage VGS by varying VDS in steps of 0.5 V and note down ID.
5. Repeat the same procedure for different values of VGS.
6. Plot the graph VDS v/s ID.
To plot Transfer characteristics:
1. Keep the voltage VDS at constant value (say 2 V) by varying VDD supply.
2. Vary the voltage VGS in increments of 1 V and note down ID.

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3. Repeat the same procedure for different values of VDS.
4. Plot the graph VGS v/s ID.
Calculations:
1. Transconductance gm = ID / VGS = ____________
2. Drain Resistance rd = VDS / ID = _____________
3. Amplification factor µ=gm×rd=_____________.
Results:
1. The transconductance gm = ______________
2. The drain resistance rd = _______________
3. The amplification factor µ=_____________.
EXPERIMENT: 4

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N-CHANNEL MOSFET
AIM: Plot the transfer and drain characteristics of n-channel MOSFET and calculate its
parameters, namely; drain resistance, mutual conductance and amplification factor.
1) MOSFET (IRF 540)

2) Milliammeter - 0-20/200mA
3) Multimeter
THEORY:
The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS

FET) is a type of transistor used for amplifying or switching electronic signals. Although the
MOSFET is a four-terminal device with source (S), gate (G), drain (D), and body (B) terminals, the
body (or substrate) of the MOSFET is often connected to the source terminal, making it a three-
terminal device like other field-effect transistors. Because these two terminals are normally
connected to each other (short-circuited) internally, only three terminals appear in electrical
diagrams. The MOSFET is by far the most common transistor in both digital and analog circuits,
though the bipolar junction transistor was at one time much more common.
The main advantage of a MOSFET over a regular transistor is that it requires very little current to
turn on (less than 1mA), while delivering a much higher current to a load (10 to 50A or more).
CIRCUIT DIAGRAM:

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GRAPH:
Procedure:
Transfer Characteristics:
1. Check the components / Equipment for their working condition.
2. Connections are made as shown in the circuit diagram-5.
3. Initially both RPS-1 and RPS-2 are kept at zero output position.

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4. By varying the RPS-2, set VDS around 3V
5. Now increase VGS by varying the RPS-1 gradually and note down the corresponding drain
current.
6. Repeat the steps 4 and 5 for some other VDS value
7. Draw the graph between VGS and ID
Tabular Column:
Transfer Characteristics:
Output/Drain Characteristics:

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Output Characteristics:
1. Check the components / Equipment for their working condition.
2. Connections are made as shown in the circuit diagram-5.
3. Both RPS-1 and RPS-2 should be in zero output position and supply switch is ON
4. By varying RPS-1, set VGS to some value (slightly greater than the Threshold voltage
determined from the transfer characteristics)
5. Now increase the VDS by varying the RPS-2 gradually and note down the corresponding
drain current.
6. Repeat the steps 4 and 5 for some other VGS value.
7. Graph between VDS Vs ID is plotted
Calculations:
1. Trans conductance gm = ID / VGS = ____________
2. Drain Resistance rd = VDS / ID = _____________
3. Amplification factor µ=gm×rd=_____________.
Results:
The transconductance gm = ______________
The drain resistance rd = _______________
The amplification factor µ=gm×rd =_____________.

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EXPERIMENT: 5
A. EMITTER FOLLOWER
AIM: To Design and test an Emitter follower Circuit.
i. Measure the gain
ii. Plot its input and output waveforms
1. Resistors: 1KΩ, 2.2KΩ,10KΩ, 22KΩ, 33KΩ
2. Capacitor - 1μF
3. Transistor – BC107
4. Function Generator
5. CRO
6. Multimeter
7. Bread board
8. Connecting Wires
THEORY:
Emitter follower is the popular name for common collector amplifier. Its voltage gain is approximately
unity (without RL voltage gain is unity). It has high input impudence and low output impedance. Thus
emitter follower has less loading effect and is suitable for impedance matching. Since collector is
directly connected to dc source, it appears to be grounded for ac signal. Output is taken from the emitter
terminal. The output voltage is in phase and is equal to the input signal. Since the amplitude and phase
of the output (emitter) follows the input (base), the circuit is called emitter follower. In this circuit
voltage divider biasing is used for base bias. RE acts as the load for signal at the output circuit.RE also
provides a negative feedback in the circuit.
CIRCUIT DIAGRAM:

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Figure: Circuit diagram of Emitter follower amplifier
OBSERVATIONS:
DC Condition (millimeter)
VCC =
VCE =
VBE =
Note : At proper biased condition, VBE should be 0.6V to 0.7V, VCE should be approximately half of VCC

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INPUT/ OUTPUT WAVEFORMS:
CALCULATIONS:
(i) Without load (RL = ∞)
VO = 1V
Gain = = 1
(ii) Voltage gain with 10 K load
VO =
Gain =
(iii) Voltage gain with 1 KΩ load
VO =
Gain =
PROCEDURE:
1) Test the components
2) Assemble the circuit
3) Measure the dc condition using multimeter and verify whether the transistor is in active
Region
4) Apply 1Vpp,1 KHz sinusoidal signal as input

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5) Observe the voltages at input point (Vin), at base, at emitter and at the output point(VO)
without RL
6) Measure the amplitudes and dc levels
7) Plot the waveforms
8) Observe and measure VO with RL = 10 KΩ and RL = 1KΩ
9) Calculate the voltage gain for the above three conditions of R L
RESULT:
Emitter Follower Circuit is designed and its input / output waveforms are analyzed and its Gain
is Measured.
1. Without Load Resistor;
Output Voltage: Vo= Volts
Voltage Gain: Av =
2. With Load Resistor;
Output Voltage: Vo= Volts
Voltage Gain: Av =

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B. DARLINGTON CONNECTION
Aim: Realize BJT Darlington Emitter follower with and without bootstrapping and determine the
gain, input and output impedances.
1. Transistor SL 100 (Q1)and 2N3055(Q2)
2. Resistors & Capacitors
3. Multi meter
4. CRO probes
5. DRB
6. Spring board and connecting wires
THEORY:
When high input impedance and low output impedance requirements are to be met the
natural choice is common collector configuration the common collector configuration of transistor
has high input impedance, low output impedance and high current gain although no phase
inversion. The common collector transistor amplifies is termed as emitter follower for the simple
reason that the o/p voltage follows the input voltage ( A V=1 ). The important application of emitter
follower is as buffer amplifier for impedance matching. A single stage emitter follower provides an
input impedance of 500kΩ . But for the requirement of i/p impedance beyond 500 kΩ we employ
Darlington emitter follower. The voltage gain of Darlington Emitter Follower is less than but very
nearly equal to unity. The coupling of the two stages of emitter follower amplifier, this cascaded
connection of two emitter follower is called Darlington connections. In this connection, since two
stages of transistor are connected it improves the current gain and input resistance of the circuit. In
Darlington connections of two transistor emitter of the first transistor is directly connected to the
base of the second transistor. The leakage current of the first transistor is amplified by the second
transistor and overall leakage current may be high which is not desired. For further high i/p
impedance requirement bootstrapping can be employed. Bootstrap circuit is an arrangement of
components used to boost the input impedance of a circuit by using a small amount of positive
feedback, usually over two stages.
Circuit Diagram: With boot strapping

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SL 100
Circuit to find input impedance ( Zi ) :

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Circuit to find output impedance ( Zo ) :
Procedure: (With and without bootstrapping)
1. Check all the components and equipments for their good working condition.
2. Connections are made as shown in the circuit diagram.
3. By keeping the voltage knobs in minimum position and current knob in maximum position
switch on the power supply.
4. By disconnecting the AC source measure the quiescent point (VEC2 and IE2 = VRE / RE)
To find frequency response:
1. Connect the AC source. Keeping the frequency of the Ac source in mid band region (say 10
kHz) adjust the amplitude to get the distortion less output. Note down the amplitude of the
input signal.
2. Keeping the input amplitude constant, Vary the frequency in suitable steps and note down
the corresponding output amplitude.
3. Calculate AV and gain in decibels. Plot a graph of frequency Vs gain in dB. From the graph
calculate f L, f H and band width.

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4. Calculate figure of merit.
To find the input impedance ( Zi ) :
1. Connections are made as shown in the diagram.
2. Keeping the DRB in its minimum position, apply input signal at mid band frequency (say
10 kHz) and adjust the amplitude of the input signal to get distortion less output. Note down
the output amplitude.
3. Vary the DRB until the output amplitude becomes half of its previous value. The
corresponding DRB value gives the input impedance.
To find the output impedance ( Zo ) :
1. Connections are made as shown in the diagram.
2. Keeping the DRB in its maximum position, apply input signal at mid band frequency (say
10 kHz) and adjust the amplitude of the input signal to get distortion less output. Note down
the output amplitude.
3. Vary the DRB until the output amplitude becomes half of its previous value.
4. The corresponding DRB value gives the output impedance.
Tabular Column: Vi = ___________ V
F in Hz Vo in Volt AV = Vo / Vi Gain in dB = 20*log AV

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Ideal Graph:
Gain in dB fL fH f in Hz
3dB
Band Width
f L = Lower cutoff frequency f H = Higher cutoff frequency
Applications:
1. Impedance matching.
2. LED and Display drivers: Darlington transistor arrays contained within IC packages are
widely used for driving loads from standard logic families.

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3. Audio power output stages: Sometimes audio amplifier power output stages may require
significant levels of current gain to enable them to drive low impedance speakers.
4. The Darlington circuit configuration is ideal for use in linear power regulators.
5. End applications for Darlington transistor devices include inverter circuits, AC motor
control, DC motor control circuits and emergency power supplies, etc.,
Result:
Without bootstrapping
1. Quiescent point : VEC2 = ____ V, IE = _____ mA.
2. Voltage Gain ( AV ) = __________ ( in mid band region )
3. Bandwidth (BW) = ___________ HZ
4. figure of merit ( FM = AV * BW ) = ____________ Hz
5. Input impedance (Zi) = ____________ , Output Impedance (Zo) = __________
With bootstrapping
1. Input impedance (Zi) = ____________
EXPERIMENT:6
COMMON SOURCE JFET/MOSFET

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AIM: To Design and plot the frequency response of Common Source JFET/MOSFET amplifier.
1) FET BFW 10
2) Resistors & Capacitors
3) CRO Probes
4) Multi meter
5) DRB
6) Spring board and connecting wires
THEORY:
An amplifier is a circuit which increases the voltage, current or power level of i/p signal where the
frequency is maintained constant from o/p to i/p signal. In FET amplifier the output current ( I D ) is a
function of input voltage VGS. That is as VGS varies the drain current varies. VGS varies as input signal
varies in turn the drain current varies hence amplification takes place. In R C coupled FET amplifier RD
and RS are selected in such a way that FET operates in active region and the operating point will be in
the middle of active region. Coupling capacitors C C1 and CC2 are used to block dc current flow through
load and the source. The source by-pass capacitor CS is connected to avoid negative feedback.
An amplifier in which resistance-capacitance coupling is employed between stages and at the input
and output point of the circuit is known as RC coupled amplifier. A capacitor provides a path for
signal currents between stages, with resistors connected from each side of the capacitor to the
power supply or to ground.
CIRCUIT DIAGRAM:

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Design
Given VDD = 10 V, VGS(off) = -4 V
IDSS (max) = 12 mA
RG = 2 M
Formula:
2
ID = IDSS.(1 – VGS / VGS (off)) -------------------------------------(1)
When VG = 0, Then VS = -VGS
But VS = ID . RS
When VG = 0, ID = IDSS
VS = IDSS.RS
IDSS.RS = -VGS (off)
RS = -(-4) / 12mA = 333
Choose RS = 330
From (1)

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2
ID = IDSS.(1 – ID.RS / VGS (off))
2 2
ID = IDSS.(1 + ID .RS / 16 - ID.RS /2)
-3 2 2
ID = 12 x 10 x (1 + ID .330 / 16 - ID.330 /2)
2 -3
81.675ID - 2.98ID +12 x 10 = 0
ID = 4.6 mA or ID = 31.9 mA
Since ID cannot be greater than IDSS, Choose
ID = 4.6 mA
Assume VDS = 50 % VDD ---- VDS = 5V
Applying KVL to output circuit
VDD = ID . RD + VDS + ID .RS

-3 -3
RD = (10 – 5 – 4.6 x 10 x 330) / 4.6 x 10
RD = 756
Choose RD = 820
XCS < < RS
XCS = RS / 10
1 / ( 2 f CS ) = 470 / 10 Let f = 100 Hz
CS = 33 F Choose CS = 47 F
Choose CC1 = CC2 = 0.1 F
Tabular Column : Vi = ___________ V

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f in Hz Vo in Volt AV = Vo / Vi Gain in dB = 20*log AV
Procedure:
1. Components / Equipment are tested for their good working condition.
2. Connections are made as shown in the circuit diagram.
3. By keeping the voltage knobs in minimum position and current knob in maximum position
switch on the power supply.
4. By disconnecting the AC source measure the quiescent point (VDS and ID = VRD / RD)
Applications:
1. FET amplifiers are low noise amplifiers used for front-end applications.
2. They are used in Oscillators.
3. These are faster and are less noisy compared to BJT amplifiers.
To find frequency response:

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 Connect the AC source. Keeping the frequency of the AC source in mid band region (say 10
kHz) adjust the amplitude to get the distortion less output. Note down the amplitude of the
input signal.
 Keeping the input amplitude constant, Vary the frequency in suitable steps and note down
the corresponding output amplitude.
 Calculate AV and gain in decibels. Plot a graph of frequency Vs gain in dB. From the graph
calculate f L, f H and band width.
 Calculate figure of merit.
IDEAL GRAPH:
Result:
1. Quiescent point : VDS = ____ V, ID = _____ mA, VGS = ____________ V

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2. Voltage Gain ( AV ) = __________ ( in mid band region )
3. Bandwidth (BW) = ___________ Hz
4. Figure of merit ( FM = AV * BW ) = ____________ Hz
EXPERIMENT: 7
COMPARATOR
AIM: Test the Opamp Comparator with zero and non zero reference and obtain the Hysteresis
curve.

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1. IC741
2. Resistors as per design
3. Function generator
4. Regulated power supply
5. IC bread board trainer
6. CRO/Patch cards/CRO probes
THEORY:
A voltage comparator is a two-input circuit that compares the voltage at one input to the voltage
at the other input. Usually one input is a reference voltage and the other input a time varying
signal. If the time varying input is below or above the reference voltage, then the comparator
provides a low or high output accordingly (usually the plus or minus power supply voltages,
since the op-amp is used in the open loop configuration, a small difference(−) makes the output
to saturate).
CIRCUIT DIAGRAM:
GRAPH:

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PROCEDURE:
 Set up the circuit as shown in the diagram.

 Set the input voltage 10 V peak to peak, 1 kHz in function generator, and apply this as
input signal to the circuit. Observe the output waveform in CRO.
 Obtain the response for different Vr (say, Vr = 0V,±2V). Also, obtain the transfer
characteristics
RESULT:
Opamp Comparator with zero and non zero reference is designed and its input / output
waveforms are verified.
EXPERIMENT: 8

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FULL WAVE CONTROLLED RECTIFIER USING RC TRIGGERING
AIM: To Design and test Full wave Controlled rectifier using RC triggering circuit.
1) Auto Transformer
2) Isolation Transformer
3) Lamp Load 230 V, 50W
4) Resistors 100 K Pot
5) Capacitor 0.1 micro F
6) Diodes BY127
7) SCR TY604 /TY6004
THEORY:
An SCR is a 4-layer, 3-junction, 3-terminal device. When anode is positive w.r.t cathode, the
curve between VAK and IA is called the forward characteristics. During forward bias condition,
the junction J2 is reverse biased and when across J2 above break over voltage (VBO), J2 breaks
down and heavy current will flow in the device. Hence a load resistance is always connected in
series with the SCR to limit the anode current to safe value. Latching current is the minimum
anode current required to turn ON SCR without gate current. Holding current is the maximum
anode current at which SCR turns OFF from ON condition, with gate open. SCR is used as
protection circuits, current limiting circuit and control circuits.
The Performance of FWR is significantly improved compared with that of a HWR. During the
positive half-cycle of the input voltage power is supplied to the load through diodes D1 & D2.
During negative half- cycle diode D3 & D4 conducts.
During +ve half cycle diodes D1 and D4 are forward biased and capacitor charges via these 2
diodes and potentiometer. When it charges to gate triggering voltage of SCR, it goes to
conducting state and voltage appears across the load. During – ve half cycle diodes D2 and D3
conduct and capacitor charges via these diodes and pot (R) and when it charges to gate triggering
voltage of SCR, it goes to conducting state and voltage appear across the load. Thus SCR is
triggered during both the positive and negative half cycles and the power fed to the load is
controlled by varying firing angle and hence the controlled Full wave rectifier.
CIRCUIT DIAGRAM:

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Figure: Circuit diagram for Controlled Full wave rectifier using RC Triggering
NATURE OF GRAPH;

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TABULAR COLUMN:
Sl no  in deg ress V0 (Pr actial) V 0 (Theoretical) =

Vm
(1+ cosα)
π
RESULT:
1. The working of full wave circuits using RC triggering is analyzed.

2. It is found that triggering angle can be varied from 0 to 180 degrees in both the cases.
EXPERIMENT: 8

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PRECISION RECTIFIER USING OP-AMP
AIM: Design and test Precision Half wave and full wave rectifiers using Opamp
1. Dual power supply,
2. CRO,
3. Function generator,
4. Bread board,
5. Op-amp (2 nos),
6. Diodes 1N4007, and
7. Resistors (10KΩ 4nos).
THEORY:
In a normal diode rectifier, the cut in voltage across the diode will result in reduction of
output voltage and inaccuracy of rectification. If ideal rectifier is needed in an
application, a precision rectifier as shown Figure may be used. In the circuit, when the
input is greater than zero, D1 will conduct and D2 is OFF, so the output is zero because
the other end of R2 is connected to the virtual ground and there is no current through R2.
When the input is less than zero, D2 is on, and D1 is off, and the output is similar to that of
an inverting amplifier with gain (–R2/ R1). The value of R1 and R2 are selected in such a
way that the circuit has reasonable level of input impedance and the gain is unity. Diode
D1 and D2 are signal diodes.
CIRCUIT DIAGRAM:
Half Wave Precision Rectifier:

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Waveform:
Full Wave Precision Rectifier:
Waveform:

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PROCEDURE:
 Set up the circuit as shown in figure. Give a sine wave of ±5V peak magnitude
and 1 kHz frequency at the input and observe the input and output simultaneously on
CRO.
 Put the CRO into X-Y mode and connect input signal to X and output signal to Y.
Select suitable volt per division in both channels and observe the characteristics.
RESULT:
Precision HW & FW rectifiers using op-amp is tested.
EXPERIMENT NO: 10
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RC PHASE SHIFT OSCILLATOR
AIM: To Design and test RC phase shift oscillator

1) Bread board
2) Transistor - BC 107B
3) Resistors
4) Capacitors
5) VRPS - 0-30Vdc 3A
6) Signal generator - 10Hz to 1Mhz
7) CRO
8) Probes, wires
9) POT- 10k,100k
THEORY:
RC phase shift Oscillator basically consists of an amplifier and feedack network consisting of
resistors and capacitors in ladder fashion. The basic RC circuit is as shown below The current I
is in phase with Vo, whereas the capacitor voltage Vc lags the current I by φ (90 0→Ideal
value).OR the output voltage Vo leads the I/P voltage Vi by angle φ is adjusted in practice,
equal to 600 .RC network is used in feedback path. In Oscillator, feedback network must
introduce a phase shift of 1800 to obtain total phase shift around a loop as 3600 .Thus three Rc
network each provide 60 phase shift is cascaded, so that it produces total 1800 phase shift. The
Oscillator circuit consisting amplifier and Rc feedback network is as shown below
CIRCUIT DIAGRAM:

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Design Procedure:
Select transistor BC107b having the following specifications,
Ie=Ic= 2mA;ß=215; Vce=5v; Vcc=2Vce =>10v

To find RE:
Choose Ve =Vcc/10=10/10 =1 v
Ve = Ie*Re =>Re=Ve / Ie
Re = 1 / Ie =1 / 2mA = 0.5K Ω
Select Re = 560 Ω
To find Rc:
Choose Vce = Vcc / 2 =10/2=5 v

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Apply KVL in CE loop:

Vcc- (IcRc) - Vce - Vre=0 10v-(2mA* Rc) – 5v – 1v=0
Rc = (10v-5v-1v) / 2mA Rc = 2K Ω
Select Rc= 2.2K Ω
To find R1 and R2:
Vb = Vbe + Ve => 0.7v + 1v = 1.7v
Vb=(Vcc*R2) / ( R1 + R2 )
1.7v = (10v*R2) / ( R1 + R2 )
=> R2/(R1+ R2)=1.7v/10v
10 R2= 1.7 R1 +1.7 R2
R1= 4.8* R2
Select R2 =4.7K Ω
R1 = 4.8 * 4.7K Ω => R1 = 22.56K Ω
Select R1 = 27K Ω
To find Bypass capacitor Ce:
Let Xce = Re / 10, at f = 100 Hz;

1/(2π*f*Ce) = Re / 10
Therefore Ce=10 / (2π*100 Hz *560 Ω)
=31.8 micro farad
Choose Ce=50 micro F (electrolytic)
To find Cc1 and CC2:

Assume CC1 & CC2 = 0.47 micro F (ceramic)
To design:
Xcc1 = (Hie||Rb)/10,
Xcc1 =1/ (2π*f*Cc1), Cc1=?

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Xcc2 = (Rc||Rl)/10,
Xcc2 =1/ (2π*f*Cc2), Cc2=?
Design of phase shifting network:
The frequency of oscillator is determined by phase shifting network.
The oscillating frequency for the above circuit is given by
f = 1/ (2ΠRC√ (6+4K))
Where K = Rc/R which is usually less than 1. Let f = 10K HZ and R = 10KΩ
k = (2.2K Ω/10K Ω) = 0.22
f = 1/ (2ΠRC√ (6+4K))10K = 1/ (2Π*10K*C√ (6+4(0.22)))
=> C = 0.006 μ F [choose C = 0.0047 μ F]
NOTE
The last resistor in the phase shifting network is chosen to be a 10K POT. This is done to get an
overall phase shift of 180º at frequency of oscillations.
The minimum hfe required for the transistor to oscillate is hfe min = 23 + 29(R/Rc) +
4(Rc/R)
Where Rc = 1K Ω and R = 2.2K Ω (Phase shifting network) Therefore hfe (min) = 23 +
29(2.2K/1K) +4 = (1K/2.2K) = 89.
The transistor should be chosen to have a value hfe of greater than 89.
Procedure:
1. Make the circuit connection as shown in fig. a

2. The output Vo is obtained on CRO.

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3. The 10K POT is adjusted to get a stable out on the screen of CRO.
4. The frequency of oscillations is measured using CRO is then compared with theoretical values.
5. We can see the phase shift at each point being 60º, 120º & 180º
Result:
Theoretical Frequency=
Practical Frequency=

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Prerana Educational and Social Trust (R.

ELECTRONIC PRINCIPLES AND CIRCUITS (BEC303)Page 1

(a) Circuit diagram (b) Input / Output waveform

ELECTRONIC PRINCIPLES AND CIRCUITS (BEC303)Page 2

ELECTRONIC PRINCIPLES AND CIRCUITS (BEC303)Page 3

B) Zener voltage regulator

Figure: Circuit Diagram

Tabular column for line regulation:

Figure: Line Regulation

Percentage of line regulation:

ELECTRONIC PRINCIPLES AND CIRCUITS (BEC303)Page 5

Tabular column for load regulation:

Fig.3. 5 Load Regulation

Percentage of load regulation:

ELECTRONIC PRINCIPLES AND CIRCUITS (BEC303)Page 7

AIM: To Design and Test Biased Clippers

ELECTRONIC PRINCIPLES AND CIRCUITS (BEC303)Page 8

Combination clipper (Positive – Negative Clipper):

ELECTRONIC PRINCIPLES AND CIRCUITS (BEC303)Page 9

1) Components / Equipment are tested for their good working condition.

Output waveforms and transfer characteristics are verified.

ELECTRONIC PRINCIPLES AND CIRCUITS (BEC303)Page 10

Positive Clamper Circuit:

ELECTRONIC PRINCIPLES AND CIRCUITS (BEC303)Page 11

Positive clamper with +ve reference voltage Vr:

Positive clamper with -ve reference voltage Vr:

Negative Clamper Circuit:

ELECTRONIC PRINCIPLES AND CIRCUITS (BEC303)Page 12

Negative Clamper Circuit with +ve reference voltage Vr:

Negative Clamper Circuit with -ve reference voltage Vr:

Output waveforms are verified.

Characteristics of Junction Field Effect Transistor (JFET)

ELECTRONIC PRINCIPLES AND CIRCUITS (BEC303)Page 14

ELECTRONIC PRINCIPLES AND CIRCUITS (BEC303)Page 15

At VGS =___V At VGS = ___V At VDS =___V At VDS = ___V

1. Check the components for their working condition.

2. Connect the components as shown in the circuit diagram.

To plot drain characteristics:

5. Repeat the same procedure for different values of VGS.

6. Plot the graph VDS v/s ID.

To plot Transfer characteristics:

2. Vary the voltage VGS in increments of 1 V and note down ID.

ELECTRONIC PRINCIPLES AND CIRCUITS (BEC303)Page 16

3. Repeat the same procedure for different values of VDS.

4. Plot the graph VGS v/s ID.

1. The transconductance gm = ______________

2. The drain resistance rd = _______________

3. The amplification factor µ=_____________.

ELECTRONIC PRINCIPLES AND CIRCUITS (BEC303)Page 17

1) MOSFET (IRF 540)

The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS

ELECTRONIC PRINCIPLES AND CIRCUITS (BEC303)Page 18

1. Check the components / Equipment for their working condition.

2. Connections are made as shown in the circuit diagram-5.

ELECTRONIC PRINCIPLES AND CIRCUITS (BEC303)Page 19

4. By varying the RPS-2, set VDS around 3V

7. Draw the graph between VGS and ID

ELECTRONIC PRINCIPLES AND CIRCUITS (BEC303)Page 20

1. Check the components / Equipment for their working condition.

2. Connections are made as shown in the circuit diagram-5.

7. Graph between VDS Vs ID is plotted

1. Trans conductance gm = ID / VGS = ____________

2. Drain Resistance rd = VDS / ID = _____________

At VGS =_V At VGS = _V At VDS =_V At VDS = _V

1. Quiescent point : VEC2 = V, IE = _ mA.

5. Input impedance (Zi) = __ , Output Impedance (Zo) =

1. Quiescent point : VDS = __ V, ID = _ mA, VGS = __________ V