2020 IEEE Region 10 Symposium (TENSYMP), 5-7 June 2020, Dhaka, Bangladesh

A high-performance low-power two-stage OPAMP

realized in 90nm CMOS process for biomedical
application
Suva Banik1, Tanjir Mahmud2, M.M.H Rasel3, Md. Hasanuzzaman4
Dept. of Electrical and Electronic Engineering (EEE)
United International University (UIU)
United City, Madani Avenue, Badda
Dhaka-1212, Bangladesh
1
sbanik153003@bseee.uiu.ac.bd, 2tanjir059@gmail.com, 3rasel.eee133075@gmail.com, 4hasanuzzaman@eee.uiu.ac.bd

Abstract— The functionality of modern system on chip
(SOC) technology is realized by integrating both digital and
analog components. To realize complex analog circuitry,
designers need digital-to-analog converter (DAC), analog-to-
digital converter (ADC), filters, bias voltage generator,
switched-capacitor circuit etc. where optimization of power,
performance, area, noise etc. are the design target. A two-stage
OPAMP is the core component of many high-performance
analog system. The target performance parameters of an
OPAMP are power, gain, phase margin, CMRR, offset voltage,
SQNR, slew rate, GBW and so on. In this paper, we discuss
about our designed OPAMP for bio-medical applications, which
is implemented in 90nm CMOS process and supplied by 1.5
Volt. The CADENCE spectra simulation results show that the
circuit dissipates 0.21mW power with 71.3dB gain, 66.30 phase
margin, 45.2dB SNR, 103dB CMRR, and 50ns delay. The circuit
has the unity GBW of 3.3 GHz and the slew rate of 34.7V/µs.
Keywords— DAC, ADC, GBW, Gain, Phase Margin,
ICMR, SNR, Slew Rate and Offset voltage.
I. INTRODUCTION
In a bio-amplifier, the most critical part is recording the
bio-signals as these signals have very low amplitude as well
as low frequency. Generally, the amplitude range fluctuates
within few milli-volts and the frequency varies from 0.1 Hz
to 10 kHz. The medical electronics-based health caring
devices are designed using ADC, OTA, S/H and LPF.
However, to make the biomedical electronics able to measure
bio-signals engineers need a high common mood rejection
ratio (CMRR) and high-precision amplifier to abate the input
noise and amplify the bio signals [1]. Operational amplifier
(OPAMP or op-amp) is such an ordinary building block
which is used in many electronics system, which may not
need introduction. However, an OPAMP is a voltage
amplifier where some feedback components are presented,
such as resistor and capacitor between input and output
nodes. The gain is generally high and input stage is
differential. This low-noise and high-precision analog system
can be designed by applying self-biased differential
amplifier. A practical OPAMP has some basic features, for
example offset voltage, CMRR, slew rate (SR), input
common mode range (ICMR-), output voltage swing, gain
bandwidth (GBW), open loop gain, gain and phase margin,
power consumption and input referred noise [2]. Generally,
an OPAMP has higher gain than that of general amplifiers
such as common source (CS) amplifier. The architecture of
an OPAMP may be discerned by the block diagram shown in
Fig.1, from where the following point can be observable:
1. The first stage of the OPAMP consists of a differential
amplifier.
2. The second stage is comprised of gain stage such as
common source stage with compensation capacitor Cc which
plays a vital role for the closed-loop stability [3].
3. Finally, there is an output buffer stage. It should be
noted that if the load of an OPAMP is a capacitive load, the
output buffer stage is neglected.
Previously, OPAMPs have been designed by some
researchers. The work of Shruit et al. presented the structure
of two stage OPAMP, where 3.3V power supply is applied
for tsmc 0.35µm CMOS process. The design achieves around
86 dB gain with moderate phase and gain bandwidth (7.85
MHz) and also attains 240µW power. But for increasing the
range of operating region, GBW should increase and need a
tradeoff between gain and power. This architecture also
illustrated, how performance varies with aspect ratio and
voltage level [4]. The work of C. L. Kavyashree et al.
realized two stage CMOS operational amplifier using 90nm
process, where the design consumes low power of around
38µW. The circuit drives a 20pF load capacitance.
Fig. 1. Block diagram of two stage OPAMP

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Circuit’s performance may degrade, if there is any fault in
laying out a big capacitor. Regarding the design, this
architecture achieves 84 dB gain and 560 phase margin at +/-
1V power supply [5].
In [6], A. Gupta et al. presented two OPAMP architectures
(two stage and three stage). For two stage OPAMP, four p-
type MOSFETs have been employed as biasing string and the
three stage OPAMP uses NMC amplifier. The two stage
OPAMP attains 75 dB gain and a good CMRR (90 dB). On
the other hand, power supply and power consumption should
be reduced for long battery life. The three stage OPAMP has
higher gain and GBW, but other performance parameters are
poor, for example power has increased six times (300µW) at
the same power supply +/-1.8V.
The paper includes the following sections. Section II & III
describes the proposed architecture and working principle of
different building blocks, while section IV illustrates the
simulation results. The concluding remarks are presented in
section V.
II. PROPOSED STRUCTURE OF OPERATIONAL AMPLIFIER
Fig. 3. MOSFET selection according to specification [5]
A. Differential Input Stage
This stage consists of four MOSFETs M1, M2, M3 and M4.
The gates of MOSFETs M1 and M2 are inverting and non-
inverting terminals respectively. According to the gain of the
first stage (differential stage) the differential input signal will
be amplified. The gain of the stage depends on the trans-
conductance of M2 times the total output resistance measured
at the drain of M2. Because of three distinct advantages the
current mirror (CM) load has been applied here. First of all,
output resistance of CM load is high. Secondly, the process
of differential input to single-ended output conversion can be
performed by using CM topology and finally, it also helps to
improve CMRR. The CM load consists of M3 and M4.
B. Second Stage (Output)
The actual goal of this stage is not only to improve additional
gain but also output voltage swing of the amplifier. The
second stage, a common-source (CS) configuration, which
consists of transistor M6 and M7, receives the output from
the drain node of M2. The output of the first stage is amplified
by M6 and M7. Again, similar to the first stage an active
transistor M7 behaves like a load for M6 transistor. The gain
of this stage can be calculated as the Gm (transconductance)
of M6 multiplied by the output resistances of M6 and M7
MOSFETs.

IV. CADENCE CIRCUIT & SIMULATION RESULTS

Fig. 2. Topology choose for Two Stage Op-amp

III. CIRCUIT WORKING PRINCIPLE

Two MOSFETs M1 and M2 are in saturation region and are

assigned to receive differential inputs. The M3 and M4 also
operate in saturation region and work as a current mirror. The
bias voltage is applied to the gate of M5 MOSFET, which
provides the tail current. A basic op-amp may become
unstable at higher frequency. This issue can be resolved by
applying different compensation techniques with the aid of
capacitors. and sometimes both resistors and capacitors
between different stages of the op-amp [7]. There are many
compensation topologies, such as miller capacitor
compensation, self-compensating and so on [8].
Fig. 4. Two stage opamp schmatic in CADENCE

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 Fig. 5. Common-mode voltage gain

Fig. 9. Opamp as an analog buffer

Fig. 6. Differential gain and phase margin (AC analysis)

Fig. 10. Output noise curve (Noise analysis)

Fig.7. Settling time (Transient analysis)

Fig. 11. Power analysis of Op-amp

From Fig. 5 and Fig. 6, it is clear that, the circuit has high
CMRR and differential gain. From Fig. 7, it reveals that the
circuit also attains its desire value within smallest possible
time. The other figures also illustrate the quality of this
architecture such as the inverting and non-inverting property
of OPAMP, while working as an analog buffer. To calculate
SNR, noise analysis curve is shown in Fig. 10, and Fig. 11
shows the power analysis for battery long life, which ensures
that the circuit dissipates low power.
Fig. 8. Inverting and non-inverting property

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 TABLE I. PERFORMANCE COMPARISION REFERENCES
Parameter This [4] [5] [6] [12] [15]
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All the simulations have been done using Cadence in 90nm Engineering Research and Applications, ISSN : 2248-9622, vol.
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ACKNOWLEDGEMENT power two stage op-amp using sub-20nm CMOS,” International
conference on system environment, 2019.
At first and foremost, we wish to express all of our devotion
to the almighty, most merciful beneficent creator who has
enabled us to perform this work. Authors would like to thank
also to the Department of Electrical and Electronic
Engineering, United International University for the technical
support.

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