INTEGRATED MODULAR AVIONICS FOR

MISSILE APPLICATIONS
T Venkata Mani SaswataMaitra P BhanuSrinivas
Head OBCD, DNEC OBCD, DNEC OBCD, DNEC
RCI-DRDO RCI-DRDO RCI-DRDO
Hyderabd, India Hyderabd, India Hyderabd, India
venkata.mani@rcilab.in saswatamaitra1978@rediffmail.com pbhanu_s@gmail.com

K L Raja Sekhar S Vijaya Lakshmi Raja Manikanta Guptha

OBCD, DNEC OBCD, DNEC OBCD, DNEC
RCI-DRDO RCI-DRDO RCI-DRDO
Hyderabd, India Hyderabd, India Hyderabad, India
kl.rajasekhar@rcilab.in vijayalakshmi@rcilab.in rmkguptha@gmail.com

Abstract—conventionally, the avionics architectures tracking of target, acquisition of missile data and
implemented in military/aviation industry are of federated telemetering to ground stations, switching power to sub-
nature. Federated Architectures are based on dedicated systems, initiating the warhead, interfacing with launch
computational modules or processing units distributed platform and other functions etc. These systems have to
across the vehicle. The major advantage of Federated
ensure a large variety of important requirements, i.e.
architectures is their inherent fault containment, and the
major disadvantage is massive use of resources which results safety, robustness to equipment failures, determinism, and
in increase in power consumption, size, weight and cost. It is real-time. Fig. 1 shows interaction of various sub-systems
a great challenge for the designers to reduce the weight and developed for tactical missiles based on federated
power consumption for their new systems, with reduced architectures.
development expenses and design cycle times. Making use of
the advancements in the hardware and software
technologies, the military/aviation industry is gradually
moving towards the use of Integrated Modular Avionics
(IMA). The central idea of IMA is the sharing of resources,
leading to multiple avionics functions in a single hardware.
This paper discusses the approach followed, criticalities
addressed, complexities involved in the development of
integrated avionics for missile applications.

Keywords—Federated, Integrated Modular Avionics,

Architecture, Missile, Line Replaceable Unit

I. INTRODUCTION

Sub-systems realized for Missile applications are based on

Federated architectures which make use of distributed
avionics functions that are packaged as self-contained
units, namely Line Replaceable Units (LRUs).Federated
architecture has great advantage of inherent fault
containment.

With the emerging requirements for Tactical Missiles,
Guided Rockets and Bombs from Armed Services with
long ranges, more lethality and higher accuracies, there is
a need to miniature the missile avionics. This paved way
for Integrated Modular Avionics (IMA) architectures for
missile applications that employ a high-integrity,
partitioned environment that hosts multiple avionics
functions of different criticalities on a shared computing
platform making use of advancements in technologies.
II. CONVENTIONALMISSILE AVIONICS ARCHITECTURES
Missile sub-systems carry out various critical
functionalities, such as navigation, guidance, control,
Fig 1. Conventional Missile Avionics Architecture
Generally, each module hosts one single application
within the avionics system. The disadvantage of this kind
of technology is the fact that each box has a specific
function, with specifically developed hardware and
software. Each system is more or less developed from
scratch, with the lack of technology re-use. Especially the
hardware components suffer from obsolescence issues.
Another disadvantage is the increased weight and power
consumption due to the fact that each unit carries the
burden of environmental protection and inherent power
dissipation issues. Fig 2: shows the Standalone Systems in
Federated Architecture.

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Fig 2: Standalone Systems in a Federated Architecture
III. INTEGRATED MISSILE AVIONICS ARCHITECTURES
In the present scenario there is a need for designers to
adhere to the following requirements during realization of
sub-systems for missile applications. Sub-Systems with:
 Lower power, size and weight
 Lower overall acquisition costs
 Shorter software life cycles and development
schedules
 Much easier ability to upgrade the system
 More flexibility for changes
 Scalability for the desired redundancy and improved
safety
This challenge led industry to migrate from Federated
Architectures to Integrated Modular Avionics (IMA)
Architectures, wherein data/resources are shared among
various modules. Fig 3. Shows data sharing among
systems based on IMA.
Fig 3. Data Sharing in Systems based on IMA
The Integrated Modular Avionics (IMA) concept, which
replaces numerous separate processors and line
replaceable units (LRU) with fewer, more centralized
processing units, is promising significant weight reduction
and maintenance savings in the new generation systems.
IMA architectures utilize common hardware and software
building blocks that are shared between the vehicle
functions hosted in the system. In addition, all functions
within IMA are tied together via a common data network.
There are two types of IMA architectures that a system
architect can choose when they transition from federated
architectures to IMA architectures: “Open” and “Closed”.
An open IMA architecture utilizes interfaces that are non-
proprietary, and adhere to interface definitions available in
the public domain. Closed IMA architectures utilize
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proprietary interfaces that are custom implementations
that typically are optimized for the present applications.
Fig 4. Integrated Modular Avionics Architecture
Fig. 4 shows the integrated modular avionics architecture,
where four sub-systems are combined and their
functionalities are implemented in a single system based
on multi core processor. The following are the advantages
with Integrated Modular Architectures:
 Reduced size, weight and Power
 Competitiveness
 Portability and Reuse
 Incremental Certification
 Resource Allocation
 Reconfiguration and
 Robustness
The major disadvantage of IMA is Complex integration
process. Though Integrated Modular Avionics concept
exists from past few decades in aviation industry typically
with mother board and daughter board configuration,
multiple avionics modules were integrated in single rigid-
flexi-rigid PCB for missile applications, making use of
state-of-the-art technologies indigenously for the first
time.
IV. EVOLUTION OF MISSILE ARCHITECTURES
Various sub-systems of missile are integrated into single
hardware, sharing common resources like Processor,
FPGA, Memories, Power modules, serial communication
channels (RS 422, MIL-1553 bus, Ethernet, AFDX),
analog and discrete input/output channels etc. in different
phases. The numbers of modules integrated are based on
the power and form factor requirements for a particular
missile application.
Evolution of integrated missile avionics started with
integrating On-Board Computer (OBC) which executes
Control & Guidance algorithm, with Missile Interface
Unit (MIU), and there on with Navigation Electronics
(NE), Signal Conditioning Package (SCP), Pulse Code
Modulation (PCM) Encoder of Telemetry, Electrical
Interface Unit (EIU) and Inertial Measurement Unit
(IMU). Fig 5. shows the modules integrated for various
missile applications.
Figure 5: Modules integrated for Missile applications
Fig. 6 shows the resource optimization obtained by
integrating various modules. Three federated systems
namely On-Board Computer (OBC) – Missile Interface
Unit (MIU)which executes Control and Guidance, Inertial
Navigation System (INS) which does the function of
missile navigation and Telemetry System which acquires
the analog and digital data, and transmits the data to
ground stations as PCM frames are considered. These
federated systems make use of separate Processing and
Input/output (IO) resources, upon integration the
resources are optimized with single processing and IO
resources.
Figure 6: Resource Optimization
Due to technology advances high end and high
performance multi core processors, High end FPGA soft
IP cores (MIL-1553, SIO etc.) were developed.
Leveraging these advances in technologies integration of
various modules was conceived.
Integration of modules/sub-systems resulted in freeing up
of space in the missile and reduced weight. The freed up
space can be used for increasing the volume of either
warhead or propulsion which will improve range, as well
as the other performance parameters of the missile.
In distributed avionics architectures Telemetry sub-system
was placed in the warhead section of the missile during
developmental flight trials. However, during production or
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user trials telemetry sub-system is replaced by warhead.
Due to integration of modules/sub-systems, telemetry is
also part of deliverable configuration, which allows
monitoring the performance of the production missiles
during user trials.
In integrated missile avionics, certain level of fault
tolerance is incorporated by means of redundant Analog to
Digital Converter and Discrete interface circuits, and
making use of dual redundant MIL-1553B serial links,
however at present development is being carried out on
Avionics On Module with which a complete fault tolerant
mechanism is possible even with integrated missile
avionics systems.
V. DESIGN FLOW
It has to be properly analyzed that the computing
capabilities of processor, logic resources of FPGA, Power
module ratings etc. meet the requirements before
integration of modules. In case the existing configuration
doesn’t meet the integration requirements, the system was
re-designed with newer components having smaller
footprints, high computing capabilities (multi-core
processors), less power consumption along with
conformance to Thermal design, Signal Integrity,
Testability guidelines etc.
The typical design flow followed in realization of missile
sub-systems is shown in Fig 7.
Figure 7: Design flow
The selection of components has to be carried out based
on the sub-system functional requirements. Up on
selection, the power estimation analysis is carried out.
Power Estimation mainly drives package design,
network design and lower level power minimization.
Power Estimates are necessary at various stages of the
design in order to make correct architectural
implementation and cost tradeoffs. One of the challenges
in power integrity analysis is to predict accurate power
dissipation both average as well as peak design. Power
Estimation analysis is required for package thermal
analysis, power minimization and power grid design. As
part of power estimation analysis, the typical and
maximum power consumption ratings of active
components along with power dissipation of passive
components are considered and the total summation of
that shall be less than the power budget allocated for the
characteristics of the digital component, are used for
carrying out simulations. The analysis is carried out for
high-speed signals – clocks, address and data bus between
source (driver) and destination (receiver) to verify the
quality of the signals. The results are verified for signal
distortions in the form of ringing, over-shoot and
undershoot. As a rule of thumb, overshoot and undershoot
in the signals area acceptable upto 2% of Vcc for less than
20ns. Proper termination resistors are finalized based on
the analysis.
OSCILLOSCOPE
Design file: IOCPUCARDV6_BOARDSIM.HYP Designer: MANI
HyperLynx v8.2.1
Comment: SDR_CLK_W ITHOUT_TERMINATION

sub-system. In case it exceeds the allocation, re-selection

V [U11.38 (at pin)]
V [U9.38 (at pin)]
V [U1.G19 (at pin)]

3700.0

of the components is carried out. 3200.0

2700.0

Schematics are generated after finalization of the V

o
2200.0

components. Proper de-rating has to be provided for each

l
t
a
g 1700.0
e
-
m
V
-

part for a reliable product. De-rating of a part is the

1200.0

deliberate reduction in its applied stress with respect to its

700.0

200.0

rated stress, for the purpose of providing a margin -300.0

between the applied stress and the rated limit of the part’s -800.0
0.00 2.000 4.000 6.000 8.000 10.000
Time (ns)
12.000 14.000 16.000 18.000

capabilities, maintaining this De-rating margin brings Date: Friday May 1, 2015 Time: 14:57:23
Net name: SDR_CLK
Show Latest W aveform = YES

down the occurrence of stress related failures and helps to

ensure the part’s reliability for the specified operating Figure 8: Signal without resistor termination
envelope. The De-rating factor is the ratio of design
operating stress limit to parts maximum rated stress limit.
OSCILLOSCOPE
Design file: IOCPUCARDV6_BOARDSIM.HYP Designer: MANI
HyperLynx v8. 2.1
Comment: SDR_CLK_WITH_TERMINATION

De-rating is one of design processes, which can make a

V [U11.38 (at pin)]
V [U9.38 (at pin)]
V [U1.G19 (at pin)]

3700.0

significant contribution to Reliability. The selection of 3200.0

components of higher stress capability than required for 2700.0

nominal operation is an empirical but effective and well- V

o
2200.0

established method of reducing their failure rate. De-

l
t
a
g 1700.0
e
-
m
V
-

rating is effective because the failure rate model of most

1200.0

parts is stress and temperature dependent.

700.0

200.0

-300.0

In recent times with the advancement of technology, in -800.0

0.00 2.000 4.000 6.000 8.000 10.000
Time (ns)
12.000 14.000 16.000 18.000

mission critical scenario, various sub-systems, which Date: Friday May 1, 2015 Time: 14: 58:47
Net name: SDR_CLK
Show Latest W aveform = YES

operate at high speeds, are integrated to deliver compact

system with improved performance. The integration of
sub-systems to form a single system executing software
algorithms corresponding to different functionalities has
created a requirement of operation at high data rates. This
has led to use of SDRAM, DDR, DDR2 and DDR3
memories in the design to achieve data rates in the range
of 128MHz to 800MHz. This necessitates the Signal
Integrity analysis of high speed PCB design.
Figure 9: Signal with resistor termination
Thermal process plays an important role in design of
electrical devices. Material selection, design and further
development of electrical devices are evolved with respect
to thermal conditions. Thermal analysis is done to
evaluate the system performance under specified
temperature range.

The goal of signal integrity analysis is to ensure reliable

high-speed data transmission. At low speeds, the
frequency response has little influence on the signal,
unless the transmission medium is particularly long.
However, as speed increases, high-frequency effects take
over, and even the shortest lines can suffer from problems
such as ringing, crosstalk, reflections and ground bounce,
seriously hampering the response of the signal—thus
damaging signal integrity. In reality, these problems can
be overcome by good design technique and by following
proper layout guidelines. Fig. 8 and 9 shows the signal of
SDRAM data line with and without signal integrity Fig 10. Thermal profile of a PCB
resistor.
Thermal analysis should be carried out for operating
Hyperlynx simulation software is used for carrying out SI temperature envelope and also for free flight (kinetic
analysis. IBIS models, which describe the analog Heating) temperature range of the missile.Temperature

Authorized licensed use limited to: Auckland University of Technology. Downloaded on June 02,2020 at 05:45:07 UTC from IEEE Xplore. Restrictions apply.
should be recorded of components & circuit boards from Table I. Systems Optimization Table
all the directions.The temperature should be within the
components specified temperature range otherwise
remedial action shall be laid down by means of proper System Sub-
Sub-System Parameters
thermal conducting method. The analysis has to carried out Power Weight
Type Systems* Size (mm)**
(W) (Kg)
at PCB level, and then at system level. Fig. 10 shows the
L177
thermal profile of a PCB at 710C. OBC 14 2.0 W147
H 75
For proper thermal management, the guidelines specified L 276
Federated
in the datasheet of each component has to be meticuously Systems
MIU 14 3.0 W 221
followed during PCB layout. As numerous modules are H 83.5
L140
being integrated in single Rigid-Flexi-Rigid PCB, thermal
NE 8 0.2 W 120
layers are provided part of PCB layout and thereafter H 2.5
metallic thermal contacts are provided over the high power Diameter 170
OBC-MIU 15 2.0
dissipating components for heat conduction to the Height 106
chassis.To validate the model, sensors are mounted on the OBC-MIU-
11 2.0
Diameter 165
hot spots predicted by thermal analysis tool and thermal Integrated NE Height158
Systems OBC - MIU
measurement is carried out practically after realisation of
–NE – SCP Diameter 210
the sub-system. – PCM –
17 3.0
Height 90
EIU-IMU
Electronic packaging is the art of arranging, inter
connecting, mounting of electronic & electrical
components in a single unit.This packaging analysis is
done against the specified random vibration spectrum and *OBC – On-Board Computer, MIU – Missile Interface Unit
NE – Navigation Electronics, SCP – Signal Conditioning Package
suggests modifications meant for improvement. Fig. 11 PCM – Pulse Code Modulation, EIU – Electrical Interface Unit
shows the package considered for analysis, based on the IMU – Inertial Measurement Unit,
analysis it is recommended to mount Sensor Package on **L – Length, W – Width, H - Height
isolators and stiffner to be added in between PCBs. These
metallic stiffners also act as thermal mass for conduction.
The analysis is validated after realisation of the sub-system From the table it is apparent that making use of integrated
practically also. modular architectures resulted in optimizing power,
weight and size of missile sub-systems. The other major
advantage due to integrated electronics is drastic decrease
in communication latency, which gives higher margin for
the execution of control and guidance algorithm.
In addition, the overall reliability of the missile increases
with integration of multiple federated systems, due to
obvious reduction in number of sub-systems/components.

VII. CONCLUSION

With growing demand for higher computational loads,

Fig11. Packaging Analysis of a missile sub-system
The inputs obtained from various analyses are
incorporated in the design of the sub-system and it
subsequently undergoes Qualification and Acceptance
Tests (QT & AT) after realization of hardware.
small form factors and low power consumption, the
missile technologies migrated towards integrated avionics
architectures making use of energy efficient processors.
We were able to realize systems with multiple modules
sharing common resources with optimal form factors and
were also successfully flight tested. At present integration
of Seeker Electronics & Data Link modules along with
On-Board Computer, Navigation and Telemetry modules
in single package is under progress.

Though there is certain level of complexity involved with REFERENCES

regard to manufacturing of single integrated avionics
system with multiple modules, but it is still a better [1] Byron Birkedahl & Ted Bonk. System Engineering &
approach compared to manufacturing multiple high Integration Lessons Learned from Commercial Aircraft
quality federated systems. Integrated Modular Avionics Systems as they apply to
Applications in Space Vehicles. AIAA SPACE 2010
Conference & Exposition.
VI. RESULTS

The following table shows the power, weight and size [2] Gitsuzo B. S. Tagawa & Marcelo Lopes de Oliveira e
optimizations obtained with integrated missile avionics Souza. An Overview of the Integrated Modular Avionics
architectures. Concept, DINCON 2011

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