BG77&BG770A-GL

Compatible Design

LPWA Module Series

Version: 1.1

Date: 2022-02-16

Status: Released

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 LPWA Module Series

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Copyright © Quectel Wireless Solutions Co., Ltd. 2022. All rights reserved.

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About the Document

Revision History

Version Date Author Description

Besson RONG/
- 2021-01-28 Creation of the document
Ben JIANG

1.0 2021-11-26 Lex LI/Ben JIANG First official release

1. Reserved pins 2, 3, 34 & 35 (previously for PCM)

and pins 5 & 37 (previously for I2C) on
BG770A-GL, therefore deleted all information
involving voice/VoLTE functionality throughout the
document for BG770A-GL.
2. Updated the peak current and PSM current data
1.1 2022-02-16 Lex LI (Table 4).
3. Updated the power supply current requirement of
BG770A-GL (Chapter 4.1.1).
4. Updated the power-up timing and added the
restart timing of BG770A-GL (Chapter 4.2).
5. Updated the power-down timing of BG770A-GL
(Chapter 4.3).

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Contents

About the Document ................................................................................................................................... 3

Contents ....................................................................................................................................................... 4
Table Index ................................................................................................................................................... 5
Figure Index ................................................................................................................................................. 6

1 Introduction .......................................................................................................................................... 7
1.1. Special Mark................................................................................................................................ 7

2 General Description ............................................................................................................................. 8

2.1. Product Description ..................................................................................................................... 8
2.1.1. General Information ......................................................................................................... 8
2.1.2. Frequency Bands and GNSS Types ................................................................................ 9
2.2. Features Overview .................................................................................................................... 10

3 Pin Definition ...................................................................................................................................... 12

3.1. Pin Assignment ......................................................................................................................... 13
3.2. Pin Comparison......................................................................................................................... 15

4 Application Interfaces ....................................................................................................................... 21

4.1. Power Supply ............................................................................................................................ 21
4.1.1. Reference Design for Power Supply .............................................................................. 21
4.1.2. Voltage Stability Requirements ...................................................................................... 22
4.2. Turn-on ...................................................................................................................................... 23
4.3. Turn-off ...................................................................................................................................... 27
4.3.1. Turn off Module with AT Command ................................................................................ 27
4.3.2. Turn off Module with PWRKEY ...................................................................................... 28
4.4. Reset ......................................................................................................................................... 29
4.5. Network Status Indication ......................................................................................................... 31
4.6. Operating Status Indication ....................................................................................................... 31
4.7. UART Interfaces ........................................................................................................................ 32
4.8. USB Interface ............................................................................................................................ 33
4.9. PCM and I2C Interfaces............................................................................................................ 35
4.10. PON_TRIG ................................................................................................................................ 35
4.11. Antenna Interfaces .................................................................................................................... 36

5 Recommended Footprint .................................................................................................................. 38

5.1. Recommended Compatible Footprint ....................................................................................... 38
5.2. Installation Sketch Map ............................................................................................................. 40

6 Appendix References ........................................................................................................................ 41

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Table Index

Table 1: Special Mark ................................................................................................................................... 7

Table 2: General Information ........................................................................................................................ 8
Table 3: Frequency Bands and GNSS Types .............................................................................................. 9
Table 4: Features Overview ....................................................................................................................... 10
Table 5: I/O Parameters Definition ............................................................................................................. 12
Table 6: Pin Comparison Between BG77 and BG770A-GL....................................................................... 15
Table 7: Related Documents ...................................................................................................................... 41
Table 8: Terms and Abbreviations .............................................................................................................. 41

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Figure Index

Figure 1: BG77 & BG770A-GL Pin Assignment ......................................................................................... 13

Figure 2: Reference Design of External Power Supply (BG77/BG770A-GL)............................................ 21
Figure 3: Reference Design of Power Supply (BG77) ............................................................................... 22
Figure 4: Reference Design of Power Supply (BG770A-GL) .................................................................... 22
Figure 5: Turn on the Module with Driving Circuit (BG77/BG770A-GL) .................................................... 23
Figure 6: BG77 Power-up Timing ............................................................................................................... 24
Figure 7: BG770A-GL Power-up Timing (When VBAT is Stable for 100–200 ms) .................................... 25
Figure 8: BG770A-GL Power-up Timing (When VBAT is Stable for More than 250 ms) ........................... 26
Figure 9: BG770A-GL Restart Timing ........................................................................................................ 27
Figure 10: Power-down Timing by AT Command & PON_TRIG (BG770A-GL) ........................................ 28
Figure 11: Power-down Timing by PWRKEY (BG77) ................................................................................ 28
Figure 12: Power-down Timing by PWRKEY & PON_TRIG (BG770A-GL) .............................................. 29
Figure 13: Reference Design of RESET_N with Driving Circuit (BG77/BG770A-GL) .............................. 29
Figure 14: Reference Design of RESET_N with Button (BG77/BG770A-GL)........................................... 30
Figure 15: Reset Timing (BG77) ................................................................................................................ 30
Figure 16: Reset Timing (BG770A-GL) ...................................................................................................... 30
Figure 17: Reference Design of NET_STATUS ......................................................................................... 31
Figure 18: Reference Design of STATUS .................................................................................................. 31
Figure 19: Main UART Reference Design (Translator Chip) ..................................................................... 33
Figure 20: Reference Design of USB Interface ......................................................................................... 34
Figure 21: Reference Design of PCM Application with Audio Codec (BG77) ........................................... 35
Figure 22: Reference Design of PON_TRIG for BG77/BG770A-GL ......................................................... 36
Figure 23: Reference Design of Main Antenna Interfaces ......................................................................... 36
Figure 24: Reference Design of GNSS Antenna Interface (BG77) ........................................................... 37
Figure 25: Reference Design of GNSS Antenna Interface (BG770A-GL) ................................................. 37
Figure 26: Bottom Views of BG77 & BG770A-GL ..................................................................................... 38
Figure 27: Recommended Compatible Footprint of BG77/BG770A-GL (Top View).................................. 39
Figure 28: Installation Sketch Map for BG77/BG770A-GL ........................................................................ 40

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1 Introduction
Quectel LTE Cat M1/Cat NB2 module BG77 is compatible with Quectel BG770A-GL. This document
briefly describes the compatible design between BG77 and BG770A-GL modules.

1.1. Special Mark

Table 1: Special Mark

Mark Definition

Unless otherwise specified, when an asterisk (*) is used after a function, feature, interface,
pin name, AT command, or argument, it indicates that the function, feature, interface, pin,
*
AT command, or argument is under development and currently not supported; and the
asterisk (*) after a model indicates that the sample of such model is currently unavailable.

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2 General Description

2.1. Product Description

BG77 is an embedded IoT (LTE Cat M1/Cat NB1/Cat NB2) wireless communication module. It provides
data connectivity on LTE-FDD network, and supports half-duplex operation in LTE network. It also
provides GNSS and voice 1 functionality to meet your specific application demands. For more details,
see document [1].

BG770A-GL is an embedded IoT (LTE Cat M1/Cat NB1/Cat NB2*) wireless communication module. It
provides data connectivity on LTE-FDD network, and supports half-duplex operation in LTE network. It
also provides GNSS functionality to meet your specific application demands. For more details, see
document [2].

The compatible design guideline ensures a smooth migration between BG77 and BG770A-GL modules.
You can choose a suitable module according to specific application requirements.

2.1.1. General Information

Table 2: General Information

Module Appearance Packaging Dimensions (mm) Description

LTE Cat M1/

BG77 94 LGA pins 14.9 × 12.9 × 1.7
Cat NB1/Cat NB2

1 BG77 supports VoLTE (Voice over LTE) under LTE Cat M1.

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LTE Cat M1/

BG770A-GL 94 LGA pins 14.9 × 12.9 × 1.9
Cat NB1/Cat NB2*

2.1.2. Frequency Bands and GNSS Types

Table 3: Frequency Bands and GNSS Types

Module Supported Bands Power Class GNSS

Cat M1:
LTE HD-FDD:
B1/B2/B3/B4/B5/B8/B12/B13/B18/B19/
GPS, GLONASS,
B20/B25/B26/B27/B28/B66/B85* Power Class 5
BG77 BeiDou, Galileo,
Cat NB1/NB2: (21 dBm)
QZSS
LTE HD-FDD:
B1/B2/B3/B4/B5/B8/B12/B13/B18/B19/
B20/B25/B28/B66/B71/B85*
Cat M1:
LTE HD-FDD:
B1/B2/B3/B4/B5/B8/B12/B13/B18/B19/
B20/B25/B26/B27/B28/B66 Power Class 3
BG770A-GL GPS, GLONASS
Cat NB1/NB2*: (23 dBm ± 2.7 dB)
LTE HD-FDD:
B1/B2/B3/B4/B5/B8/B12/B13/B17/B18/
B19/B20/B25/B28/B66

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2.2. Features Overview

The general features of BG77 and BG770A-GL modules are compared in the table below.

Table 4: Features Overview

Feature BG77 BG770A-GL

⚫ Supply voltage: 2.6–4.8 V ⚫ VBAT_BB: 2.2–4.35 V, Typ. 3.3 V

Power Supply
⚫ Typical supply voltage: 3.3 V ⚫ VBAT_RF: 3.1–4.2 V, Typ. 3.3 V

Peak Current About 600 mA About 750 mA

PSM Current Avg. 3.44 µA Avg. 1.4 µA

0.508 mA @ Rock Bottom 45 µA @ Rock Bottom

LTE Cat M1: LTE Cat M1:
1.61 mA @ DRX = 1.28 s 1.1 mA @ DRX = 1.28 s
0.67 mA @ e-I-DRX = 81.92 s 0.07 mA @ e-I-DRX = 81.92 s
Sleep Current @ PTW = 2.56 s, DRX = 1.28 s @ PTW = 2.56 s, DRX = 1.28 s
LTE Cat NB1: LTE Cat NB1:
1.55 mA @ DRX = 1.28 s 2.2 mA @ DRX = 1.28 s
0.66 mA @ e-I-DRX = 81.92 s 0.12 mA @ e-I-DRX = 81.92 s
@ PTW = 2.56 s, DRX = 1.28 s @ PTW = 2.56 s, DRX = 1.28 s
Operating temperature range: Operating temperature range:
-35 °C to +75 °C 2 -35 °C to +75 °C 2
Temperature Extended temperature range: Extended temperature range:
Range -40 °C to +85 °C 3 -40 °C to +85 °C 3
Storage temperature range: Storage temperature range:
-40 °C to +90 °C -40 °C to +90 °C
Main UART: Main UART:
⚫ Used for data transmission and AT ⚫ Used for data transmission and AT
command communication command communication
⚫ 115200 bps baud rate by default ⚫ 115200 bps baud rate by default
UART
⚫ The default frame format is 8N1 (8 ⚫ The default frame format is 8N1 (8
Interfaces
data bits, no parity, 1 stop bit) data bits, no parity, 1 stop bit)
⚫ RTS and CTS hardware flow control ⚫ RTS and CTS hardware flow control
Debug UART: Debug UART:
⚫ Used for software debugging and log ⚫ Used for firmware upgrade, software

2Within the operating temperature range, the module meets 3GPP specifications.
3Within the extended temperature range, the module remains the ability to establish and maintain functions such as voice
(BG770A-GL does not support voice functionality), SMS and data transmission, without any unrecoverable malfunction.
Radio spectrum and radio network are not influenced, while one or more specifications, such as Pout, may exceed the
specified tolerances of 3GPP. When the temperature returns to the operating temperature range, the module meets 3GPP
specifications again.

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output debugging, log output and NMEA

⚫ 115200 bps baud rate
GNSS UART:
⚫ Used for GNSS NMEA sentences
output
⚫ 115200 bps baud rate by default
Signal level: 1.8 V
sentences output.
⚫ 115200 bps baud rate by default
⚫ The default frame format is 8N1 (8
data bits, no parity, 1 stop bit)
⚫ RTS and CTS hardware flow control
Auxiliary UART:
⚫ Used for RF calibration and log
output
⚫ 921600 bps baud rate by default
⚫ The default frame format is 8N1 (8
data bits, no parity, 1 stop bit)
⚫ RTS and CTS hardware flow control

Signal level: 1.8 V

Digital Audio PCM Not supported

I2C Interface Supported Not supported

ADC Two ADC interfaces Two ADC interfaces

(U)SIM Card
Supported Supported
Detection
⚫ USB 2.0 (slave only)
⚫ High speed, ⚫ USB 2.0*
USB Interface
full-speed, ⚫ Full-speed mode only
low-speed
USB interface*
Firmware USB interface
DFOTA
Upgrade DFOTA
Debug UART interface

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3 Pin Definition
The I/O parameters of BG77 and BG770A-GL modules are defined in the table below.

Table 5: I/O Parameters Definition

Type Description

AI Analog Input

AIO Analog Input/Output

DI Digital Input

DO Digital Output

DIO Digital Input/Output

OD Open Drain

PI Power Input

PO Power Output

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3.1. Pin Assignment

The following figure shows the pin assignment of BG77 and BG770A-GL.

32 31 30 29 28 27 26
ANT_GNSS GND GND RESERVED GND GND ANT_MAIN

56 55 54 53
1 GND GND GND GND 25
GPIO1 GND

33 52
GPIO4 GND

2 72
57 PON_TRIG 71 24
PCM_DIN/
GPIO6 RESERVED GND
RESERVED
34 51
73 84
PCM_DOUT/ RESERVED/
GND GND
RESERVED DBG_CTS
3 70
58 85 94 23
PCM_CLK/ RESERVED/
GND GND GRFC2 GND
RESERVED AUX_CTS
35
74 83 50
PCM_SYNC/
GND GRFC1 RESERVED
RESERVED
4 59 93
86 69 22
GNSS_RXD/ RESERVED/ RESERVED/
GND RESERVED GND
RESERVED AUX_RTS AUX_TXD
36 82
75 49
GNSS_TXD/ RESERVED/
GND RESERVED
RESERVED AUX_RXD
5 87 92
60 68 21
I2C_SDA/ USB_BOOT/ RESERVED/
DBG_TXD RESERVED VDD_EXT
RESERVED RESERVED DBG_RTS
37 76 81 48
I2C_SCL/
MAIN_RI RESERVED RESERVED
RESERVED
20
6 61 88 91 67
VBAT/
MAIN_RXD DBG_RXD GND RESERVED RESERVED
VBAT_RF

38 77 80 47
MAIN_RTS AP_READY RESERVED GND

19
7 62 89 90 66
VBAT/
MAIN_TXD MAIN_DTR GND MAIN_DCD GND
VBAT_BB
79
39 78 46
NET_
MAIN_CTS STATUS PWRKEY
STATUS

8 63 64
65 18
GPIO2 GPIO7 USBPHY_ USIM_GND ADC1
3P3_EN
40 45
GPIO5 RESET_N

9 42 17
GPIO3 41 43 44 ADC0
USBPHY_
W_DSIABLE# GND USIM_DET
3P3

10 11 12 13 14 15 16
USB_DM USB_DP USB_VBUS USIM_CLK USIM_DATA USIM_RST USIM_VDD

Figure 1: BG77 & BG770A-GL Pin Assignment

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NOTE

1. Pins in green and grey are compatible pins on BG77 and BG770A-GL with the same functionality.
2. Pins in yellow are compatible pins on BG77 and BG770A-GL, which have different functions.
3. Pin names in red are defined for BG77, and that in blue are defined for BG770A-GL.

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3.2. Pin Comparison

The pin functions and I/O of BG77 and BG770A-GL modules are compared in the following table.

Table 6: Pin Comparison Between BG77 and BG770A-GL

BG77 BG770A-GL

Pin No. Pin Name I/O Description Pin No. Pin Name I/O Description

1 GPIO1 DIO General-purpose input/output 1 GPIO1 DIO General-purpose input/output

2 PCM_DIN DI PCM data input 2 RESERVED - -

3 PCM_CLK DO PCM clock 3 RESERVED - -

4 GNSS_RXD DI GNSS UART receive 4 RESERVED - -

5 I2C_SDA OD I2C serial data (for external codec) 5 RESERVED - -

6 MAIN_RXD DI Main UART receive 6 MAIN_RXD DI Main UART receive

7 MAIN_TXD DO Main UART transmit 7 MAIN_TXD DO Main UART transmit

8 GPIO2 DIO General-purpose input/output 8 GPIO2 DIO General-purpose input/output

9 GPIO3 DIO General-purpose input/output 9 GPIO3 DIO General-purpose input/output

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USB differential data (-). USB differential data (-).

10 USB_DM AIO 10 USB_DM* AIO
Require differential impedance of 90 Ω. Require differential impedance of 90 Ω.
USB differential data (+). USB differential data (+).
11 USB_DP AIO 11 USB_DP* AIO
Require differential impedance of 90 Ω. Require differential impedance of 90 Ω.

12 USB_VBUS AI USB connection detect 12 USB_VBUS* AI USB connection detect

13 USIM_CLK DO (U)SIM card clock 13 USIM_CLK DO (U)SIM card clock

14 USIM_DATA DIO (U)SIM card data 14 USIM_DATA DIO (U)SIM card data

15 USIM_RST DO (U)SIM card reset 15 USIM_RST DO (U)SIM card reset

16 USIM_VDD PO (U)SIM card power supply 16 USIM_VDD PO (U)SIM card power supply

General-purpose ADC interface General-purpose ADC interface

17 ADC0 AI 17 ADC0 AI
0.1–1.8 V 0–1.8 V
General-purpose ADC interface General-purpose ADC interface
18 ADC1 AI 18 ADC1 AI
0.1–1.8 V 0–1.8 V
Power supply for the module’s baseband
part
19 19 VBAT_BB PI
Power supply for the module Supply voltage: 2.2–4.35 V
VBAT PI Supply voltage: 2.6–4.8 V Typ. 3.3 V
Typ. 3.3 V Power supply for the module’s RF part
20 20 VBAT_RF PI Supply voltage: 3.1–4.2 V
Typ. 3.3 V

21 VDD_EXT PO Provide 1.8 V for external circuits 21 VDD_EXT PO Provide 1.8 V for external circuit

22–25 GND - Ground 22–25 GND - Ground

26 ANT_MAIN AIO Main antenna interface 26 ANT_MAIN AIO Main antenna interface

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27–28 GND - Ground 27–28 GND - Ground

29 RESERVED - - 29 RESERVED - -

30, 31 GND - Ground 30, 31 GND - Ground

32 ANT_GNSS AI GNSS antenna interface 32 ANT_GNSS AI GNSS antenna interface

33 GPIO4 DIO General-purpose input/output 33 GPIO4 DIO General-purpose input/output

34 PCM_DOUT DO PCM data output 34 RESERVED - -

35 PCM_SYNC DO PCM data frame sync 35 RESERVED - -

36 GNSS_TXD DO GNSS UART transmit 36 RESERVED - -

37 I2C_SCL OD I2C serial clock (for external codec) 37 RESERVED - -

DTE request to send signal from DCE DTE request to send signal from DCE
38 MAIN_RTS DI 38 MAIN_RTS DI
(Connects to DTE’s RTS) (Connects to DTE’s RTS)
DTE clear to send signal from DCE DTE clear to send signal from DCE
39 MAIN_CTS DO 39 MAIN_CTS DO
(Connects to DTE’s CTS) (Connects to DTE’s CTS)

40 GPIO5 DIO General-purpose input/output 40 GPIO5 DIO General-purpose input/output

41 W_DISABLE# DI Airplane mode control 41 W_DISABLE# DI Airplane mode control

42 USBPHY_3P3 PI Power supply for USB PHY circuit 42 USBPHY_3P3* PI Power supply for USB PHY circuit

43 GND - Ground 43 GND - Ground

44 USIM_DET DI (U)SIM card hot-plug detect 44 USIM_DET DI (U)SIM card hot-plug detect

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45 RESET_N DI Reset the module 45 RESET_N DI Reset the module

46 PWRKEY DI Turn on/off the module 46 PWRKEY DI Turn on/off the module

47 GND - Ground 47 GND - Ground

48–50 RESERVED - - 48–50 RESERVED - -

DTE request to send signal from DCE

51 RESERVED - - 51 DBG_CTS DO
(Connects to DTE’s CTS)

52–56 GND - Ground 52–56 GND - Ground

57 GPIO6 DIO General-purpose input/output 57 GPIO6 DIO General-purpose input/output

58 GND - Ground 58 GND - Ground

DTE request to send signal from DCE

59 RESERVED - - 59 AUX_RTS DI
(Connects to DTE’s RTS)

60 DBG_TXD DO Debug UART transmit 60 DBG_TXD DO Debug UART transmit

61 DBG_RXD DI Debug UART receive 61 DBG_RXD DI Debug UART receive

62 MAIN_DTR DI Main UART data terminal ready 62 MAIN_DTR DI Main UART data terminal ready

63 GPIO7 DIO General-purpose input/output 63 GPIO7 DIO General-purpose input/output

USBPHY_3P3 USBPHY_3P3_
64 DO External LDO enable control for USB 64 DO External LDO enable control for USB
_EN EN*

65 USIM_GND - Specified ground for (U)SIM card 65 USIM_GND - Specified ground for (U)SIM card

66 GND - Ground 66 GND - Ground

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67–69 RESERVED - - 67–69 RESERVED - -

DTE request to send signal from DCE

70 RESERVED - - 70 AUX_CTS DO
(Connects to DTE’s CTS)

71 RESERVED - - 71 RESERVED - -

Used for main UART function control and

72 PON_TRIG DI Wake up the module from PSM 72 PON_TRIG DI for entering/exiting e-l-DRX, PSM, sleep
and power off modes

73–75 GND - Ground 73–75 GND - Ground

76 MAIN_RI DO Main UART ring indication 76 MAIN_RI* DO Main UART ring indication

77 AP_READY DI Application processor ready 77 AP_READY* DI Application processor ready

78 STATUS DO Indicate the module's operation status 78 STATUS DO Indicate the module's operation status

Indicate the module's network activity Indicate the module's network activity
79 NET_STATUS DO 79 NET_STATUS DO
status status

80–81 RESERVED - - 80–81 RESERVED DIO General-purpose input/output

82 RESERVED - - 82 AUX_RXD DI Auxiliary UART receive

83 GRFC1 DO Generic RF controller 83 GRFC1* DO Generic RF controller

84–86 GND - Ground 84–86 GND - Ground

Force the module into emergency

87 USB_BOOT DI 87 RESERVED - -
download mode

88–89 GND - Ground 88–89 GND - Ground

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90 MAIN_DCD DO Main UART data carrier detect 90 MAIN_DCD DO Main UART data carrier detect

91 RESERVED - - 91 RESERVED - -

DTE request to send signal from DCE

92 RESERVED - - 92 DBG_RTS DI
(Connects to DTE’s RTS)

93 RESERVED - - 93 AUX_TXD DO Auxiliary UART transmit

94 GRFC2 DO Generic RF controller 94 GRFC2* DO Generic RF controller

NOTE

Pins in blue: the footprint is compatible but the functions are different on BG77 and BG770A-GL.

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4 Application Interfaces
The following chapters describe the compatible design between BG77 and BG770A-GL on main
functions.

4.1. Power Supply

4.1.1. Reference Design for Power Supply

Power design for a module is critical to its performance. BG77 and BG770A-GL are LPWA modules
requiring low quiescent and leakage current.

The power supply should be able to provide sufficient current of 0.7 A at least for BG77, and 0.8 A at
least for BG770A-GL. And it is recommended to select a DC-DC converter chip or an LDO chip with
ultra-low leakage current and current output no less than 1.0 A for the power supply design.

The external power supply reference design of BG77/BG770A-GL is presented in the following figure.

R4 100K 1 %

A2 TPS 620 88 B1
DC_IN VIN PG

C1 R1 L1 330 nH VBAT
C2 B2
4.7 μF 100 nF 51K A1 SW
EN C3 C4 C5 C6
R2
C1
453K 1% 120 pF 22 μF 100 nF 33 pF
R5 4.7K FB
Q1
MCU_POWER_ON/OFF R3
100K 1%
GND

R6 47K
C2

VBAT = (R2 / R3 + 1) × 0.6

Figure 2: Reference Design of External Power Supply (BG77/BG770A-GL)

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4.1.2. Voltage Stability Requirements

To decrease voltage drop, a bypass capacitor of about 100 µF with low ESR should be used, and a multi-
layer ceramic chip capacitor (MLCC) array should also be reserved due to its low ESR. It is
recommended to use three ceramic capacitors (100 nF, 33 pF, 10 pF) for composing the MLCC array,
and place these capacitors close to VBAT pins. The width of VBAT trace should be no less than 1 mm. In
principle, the longer the VBAT trace is, the wider it will be.

For BG77, it is suggested to use a TVS with low leakage current and suitable reverse stand-off voltage to
get a stable power source, while for BG770A-GL, it is suggested to use two TVS components with low
leakage current and suitable reverse stand-off voltage to get a stable power source, and also it is
recommended to place the TVS component(s) as close to the VBAT pins as possible. The following
figures show the power supply reference design for the two modules.

VBAT
Module

R1 0R
VBAT
+
D1 C1 C2 C3 C4
TVS
100 μF 100 nF 33 pF 10 pF

Figure 3: Reference Design of Power Supply (BG77)

VBAT

R1 0R
VBAT_RF

R2 0R
VBAT_BB
D1 D2 + +
C1 C2 C3 C4 C5 C6 C7 C8

TVS TVS 100 μF 100 nF 33 pF 10 pF 100 μF 100 nF 33 pF 10 pF

Module

Figure 4: Reference Design of Power Supply (BG770A-GL)

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NOTE

1. For BG77, for every VBAT transition/re-insertion from 0 V, the minimum power supply voltage should
be higher than 2.7 V. After the module starts up normally, the minimum safety voltage is 2.6 V. To
ensure full function mode, the minimum power supply voltage should be higher than 2.8 V.
2. For BG770A-GL, when the module starts up normally, in order to ensure full function mode, the
minimum power supply voltage should be higher than 3.1 V. For every VBAT transition/re-insertion
from 0 V, VBAT slew rate is less than 25 mV/μs. In order to ensure that the module can start
normally, pull down PWRKEY to turn on the module after VBAT remains stable for at least 100 ms.

4.2. Turn-on

When BG77/BG770A-GL module is in power off mode, driving PWRKEY low for 500–1000 ms and then
releasing it will turn on the module. It is recommended to use an open drain/collector driver to control the
PWRKEY.

A simple reference design of turn-on circuit for BG77 and BG770A-GL is illustrated in the following figure.

500–1000 ms
PWRKEY

Turn on pulse
4.7K
GPIO
10 nF
47K
Q1

MCU Module

Figure 5: Turn on the Module with Driving Circuit (BG77/BG770A-GL)

BG77:

The power-up timing of BG77 is illustrated in the figure below.

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NOTE

VBAT 500–1000 ms

PWRKEY
RESET_N VIL 0.45 V

About 30 ms

VDD_EXT
200 ms. After the time, the BOOT_CONFIG pins can
be set to high level through an external circuit.
BOOT_CONFIG/
USB_BOOT pin

2.1 s
STATUS
(DO)

2.5 s

UART Inactive Active

2.55 s

USB Inactive Active

Figure 6: BG77 Power-up Timing

NOTE

Make sure that the VBAT is stable for at least 30 ms before pulling down PWRKEY on BG77.

BG770A-GL:

For BG770A-GL, drive PON_TRIG high before you turn on the module by driving PWRKEY low,
otherwise the main UART interface will be inaccessible.

PON_TRIG of BG770A-GL must be designed to allow an external MCU to control the turn-on/off of the
module. For more detailed information of PON_TRIG usage on BG770A-GL, see document [2].

The power-up timing of BG770A-GL varies with the VBTA stable duration before you drive PWRKEY low.

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1) Drive PON_TRIG high and then drive PWRKEY low when VBAT is stable for 100–200 ms,
BG770A-GL will be turned on immediately, and in this case, the power-up timing is shown below.

100–200 ms

VBAT
500–1000 ms

PWRKEY
VIL ≤ 0.3 V
T ≤ 50 ms
PON_TRIG

VDD_EXT
≥ 4.35 s
STATUS

≥ 7.9 s
UART Inactive Active

Figure 7: BG770A-GL Power-up Timing (When VBAT is Stable for 100–200 ms)

2) Drive PON_TRIG high and then drive PWRKEY low when VBAT is stable for more than 250 ms,
BG770A-GL will also be turned on immediately, and in this case, the power-up timing is shown below.

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About 250 ms

VBAT
500–1000 ms

PWRKEY VIL 0.3 V

T 50 ms
PON_TRIG
About 1 ms
VDD_EXT
4.3 s

STATUS
6.42 s

UART Inactive Active

Figure 8: BG770A-GL Power-up Timing (When VBAT is Stable for More than 250 ms)

After BG770A-GL is turned off with the PWRKEY and PON_TRIG solution or the AT command and
PON_TRIG solution, VBAT will keep powered on all the time until the main power supply is disconnected.
In this case, drive PON_TRIG high and then drive PWRKEY low will restart the module, and the restart
timing is shown below.

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VBAT
500–1000 ms

PWRKEY VIL ≤ 0.3 V

T ≤ 50 ms

PON_TRIG

About 1 ms
VDD_EXT
≥ 2.05 s

STATUS

≥ 2.08 s
UART Inactive Active

Figure 9: BG770A-GL Restart Timing

NOTE

1. After VBAT is powered on, BG770A-GL requires an internal program loading time of about 250 ms.
2. Before you turn on or restart BG770A-GL by driving PWRKEY low, drive PON_TRIG high; otherwise
the main UART interface will be inaccessible.

4.3. Turn-off

4.3.1. Turn off Module with AT Command

There are several ways to turn off BG77/BG770A-GL. It is recommended to turn off the module through
AT+QPOWD (see document [3]/[4] for details), which is a safe way. The command will make the
module log out from the network and allow the firmware to save important data before completely
disconnecting the power supply.

For BG77, PON_TRIG has been internally pulled down by default, so there is no need for any external
pull-down.

While for BG770A-GL, after the AT+QPOWD is sent, you have to pull down PON_TRIG within 200 ms,
after which the module will execute the power-down procedure.

Additionally, after BG770A-GL is turned off or enters PSM, do not pull up any I/O pin of the module.

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Otherwise, the module will have additional power consumption and may have damaged pins.

VBAT

MAIN_RXD
AT+QPOWD
200 ms
PON_TRIG

VDD_EXT

2s
STATUS

10 s
Module Running Power-down procedure OFF
Status

Figure 10: Power-down Timing by AT Command & PON_TRIG (BG770A-GL)

4.3.2. Turn off Module with PWRKEY

BG77 can be powered down by driving PWRKEY low for 650–1500 ms and then releasing it. The power-
down scenario is illustrated in the figure below.

VBAT

650–1500 ms

PWRKEY
≥ 1.3 s
VIL ≤ 0.45 V
STATUS

Module Running Power-down procedure OFF

Status

Figure 11: Power-down Timing by PWRKEY (BG77)

BG770A-GL can be powered down by driving PWRKEY low for 650–1500 ms and then releasing it, and
then pulling down PON_TRIG within 200 ms. The power-down timing is illustrated in the figure below.

BG77&BG770A-GL_Compatible_Design 28 / 42
 LPWA Module Series

VBAT
650–1500 ms

PWRKEY
VIL 0.3 V
200 ms
PON_TRIG

VDD_EXT

2s
STATUS

10 s
Module Runnin Power-down procedure OFF
Status g

Figure 12: Power-down Timing by PWRKEY & PON_TRIG (BG770A-GL)

4.4. Reset

BG77 can be reset by driving RESET_N low for 2–3.8 s; BG770A-GL can be reset by driving RESET_N
low at least 100 ms.

The recommended circuit is similar to the PWRKEY control circuit. An open drain/collector driver or
button can be used to control RESET_N.

2–3.8 s (BG77)
≥ 100 ms (BG770A-GL)
RESET_N

Reset pulse
4.7K
GPIO
47K 10nF
Q1

MCU Module

Figure 13: Reference Design of RESET_N with Driving Circuit (BG77/BG770A-GL)

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 LPWA Module Series

S2

RESET_N

Reset pulse
TVS

Close to S2 Module

Figure 14: Reference Design of RESET_N with Button (BG77/BG770A-GL)

VBA T 3.8 s

2s
RESET_N
VIL 0.45 V

Module
Running Resetting Restart
Status

Figure 15: Reset Timing (BG77)

VBAT

≥ 100 ms
RESET_N
VIL ≤ 0.3 V

Module
status Running Resetting Restart

Figure 16: Reset Timing (BG770A-GL)

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 LPWA Module Series

NOTE

Ensure that there is no large capacitor on PWRKEY and RESET_N pins.

4.5. Network Status Indication

BG77/BG770A-GL provides one network status indication pin: NET_STATUS. The pin is used to drive a
network status indication LED. A reference circuit is shown in the following figure.

VBAT
Module

2.2K

4.7K
BG77/BG770A-GL
NET_STATUS
47K

Figure 17: Reference Design of NET_STATUS

4.6. Operating Status Indication

The STATUS pin indicates the operation status of the modules. It outputs high level when the module
powers on. The following figure shows a reference circuit of STATUS.

VBAT
Module

2.2K

BG77/BG770A-GL 4.7K
STATUS

47K

Figure 18: Reference Design of STATUS

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 LPWA Module Series

4.7. UART Interfaces

BG77 provides three UART interfaces: main UART, debug UART and GNSS UART interfaces. Features
of them are illustrated below:

⚫ The main UART interface supports 9600, 19200, 38400, 57600, 115200, 230400, 460800 and
921600 bps baud rates, and the default baud rate is 115200 bps. It is used for data transmission and
AT command communication, and supports RTS and CTS hardware flow control. The default frame
format is 8N1 (8 data bits, no parity, 1 stop bit).
⚫ The debug UART interface supports a fixed baud rate of 115200 bps, and is used for software
debugging and log output.
⚫ The GNSS UART interface supports 115200 bps baud rate by default, and is used for GNSS NMEA
sentences output.

BG770A-GL provides three UART interfaces: main UART, debug UART and auxiliary UART interfaces.
Features of them are illustrated below:

⚫ The main UART interface supports 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600
and 3000000 bps baud rates, and the default is 115200 bps. It is used for data transmission and AT
command communication, and supports RTS and CTS hardware flow control. The default frame
format is 8N1 (8 data bits, no parity, 1 stop bit).
⚫ The debug UART interface supports 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600
and 3000000 bps baud rates, and the default is 115200 bps. It is used for firmware upgrade,
software debugging, log and NMEA sentences output, and supports RTS and CTS hardware flow
control. The default frame format is 8N1 (8 data bits, no parity, 1 stop bit).
⚫ The auxiliary UART interface supports 921600 bps baud rate by default. It is used for RF calibration
and log output, and supports RTS and CTS hardware flow control. The default frame format is 8N1
(8 data bits, no parity, 1 stop bit).

Since the power domains of BG77 and BG770A-GL UART interfaces are 1.8 V, a voltage-level translator
should be used if your application is equipped with a 3.3 V UART interface.

For BG77, it is recommended to use a level conversion chip (with or without internal pull up), such as
TXS0108EPWR.

For BG770A-GL, it is recommended to use a level conversion chip without internal pull-up, such as
TXB0108PWR.

The following figure shows a reference design of the main UART interface:

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 LPWA Module Series

VDD_EXT VCCA VCCB VDD_MCU

0.1uF 0.1uF

10K
120K
OE GND
MAIN_RI A1 B1 RI_MCU
MAIN_DCD A2 B2 DCD_MCU
MAIN_CTS A3 Translator B3 CTS_MCU
MAIN_RTS A4 B4 RTS_MCU
MAIN_DTR A5 B5 DTR_MCU
MAIN_TXD A6 B6 TXD_MCU
MAIN_RXD A7 B7 RXD_MCU
51K 51K
A8 B8

Figure 19: Main UART Reference Design (Translator Chip)

Visit http://www.ti.com for more information.

⚫NOTE
On BG770A-GL, the main UART interface should be disconnected in PSM and power off modes.
Otherwise, the module will have additional power consumption and may have damaged pins.

4.8. USB Interface

BG77 provides one integrated Universal Serial Bus (USB) interface which complies with the USB 2.0
specification, and it supports operation at low-speed (1.5 Mbps), full-speed (12 Mbps) and high-speed
(480 Mbps) modes. The USB interface is used for AT command communication, data transmission,
software debugging and firmware upgrade.

BG770A-GL provides one integrated Universal Serial Bus (USB) interface which complies with the USB
2.0 specification and supports operation at full-speed mode only.

The following figure shows a reference design of USB interface for BG77/BG770A-GL.

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 LPWA Module Series

VDD_EXT

Module
1.8 V
Typical 5.0 V VDD_EXT
R1 0R USB_DET USB_DET
Connector USB_VBAT USB_VBUS
R4 R5
100K 100K
USB_VBAT
USB_VBAT

USB_DM R2 0R USB_DM

USB_DP R3 0R USB_DP
Close to module
ESD Array

USB_VBAT 3.3 V
GND IN OUT USBPHY_3P3
R6 10K
USB_DET EN GND
R7 NM-0R LDO USBPHY_3P3_EN
USBPHY_3P3_EN USBPHY_3P3_EN

GND

Figure 20: Reference Design of USB Interface

To ensure the integrity of USB data signals, resistors R2 and R3 should be placed close to the module.
The extra stubs of trace must be as short as possible.

To meet USB 2.0 specification, comply with the following principles while designing the USB interface.

⚫ It is important to route the USB signal traces as differential pairs with ground surrounded. The
impedance of USB differential trace is 90 Ω.
⚫ Do not route signal traces under crystals, oscillators, magnetic devices and RF signal traces. It is
important to route the USB differential traces in inner-layer of the PCB, and surround the traces with
ground on that layer and with ground planes above and below.
⚫ Junction capacitance of the ESD protection device might cause influences on USB data traces, so
pay attention to the selection of the device. Typically, the stray capacitance should be less than 2 pF.
⚫ Keep the ESD protection devices as close to the USB connector as possible.

NOTE

The USB interface of BG770A-GL is under development presently.

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4.9. PCM and I2C Interfaces

BG770A-GL does not support PCM and I2C interfaces.

BG77 provides one PCM digital interface and one I2C interface for VoLTE only. A reference design of
PCM and I2C interfaces with an external codec IC is shown below.

MICBIAS

Module INP

BIAS
INN
PCM_CLK BCLK
PCM_SYNC WCLK
PCM_DIN ADC
PCM_DOUT DAC
LOUTP
I2C_SCL SCL
I2C_SDA SDA LOUTN
4.7K

4.7K

Codec

1.8V

Figure 21: Reference Design of PCM Application with Audio Codec (BG77)

4.10. PON_TRIG

On BG77, PON_TRIG is internally pulled down by default. When the pin detects a rising edge and keeps
at high level for at least 30 ms, the module will wake up from PSM.

On BG770A-GL, PON_TRIG is not pulled up/down internally by default. Drive PON_TRIG high and
remain it high, the module will wake up from PSM. The main functions of PON_TRIG on BG770A-GL are
summarized below:

⚫ Control the module to enter or exit e-l-DRX, PSM mode and sleep mode.
⚫ Enable/disable the main UART interface communication function.
⚫ Used for the turn-on/off application of the module.

The following figure shows a reference design of PON_TRIG on BG77/BG770A-GL.

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VDD_1V8

PON_TRIG

100K

0R

100K
For BG770A-GL only
PON_TRIG_MCU

100K
Figure 22: Reference Design of PON_TRIG for BG77/BG770A-GL

NOTE

VDD_1V8 is provided by an external LDO.

4.11. Antenna Interfaces

BG77/BG770A-GL includes a main antenna interface and a GNSS antenna interface. The impedance of
antenna ports is 50 Ω.

It is recommended to reserve a π-type matching circuit for better RF performance, and the π-type
matching components (R1/C1/C2) should be placed as close to the antenna as possible. The capacitors
are not mounted by default. A reference design for the main antenna interface is shown below.

Module
R1 0R
ANT_MAIN

C1 C2

NM NM

Figure 23: Reference Design of Main Antenna Interfaces

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BG77/BG770A-GL supports GNSS function through the ANT_GNSS pin. Reference designs of BG77
and BG770A-GL GNSS antenna interfaces are presented below.

VDD

0.1uF GNSS
10R
Antenna
Module

47nH

0R 100pF
ANT_GNSS

NM NM

Figure 24: Reference Design of GNSS Antenna Interface (BG77)

NOTE

1. An external LDO can be selected to supply power according to the active antenna requirement.
2. If the module is designed with a passive antenna, then the VDD circuit is not needed.

Passive
GNSS
Module Antenna
0R
ANT_GNSS

NM NM NM

NM

Figure 25: Reference Design of GNSS Antenna Interface (BG770A-GL)

NOTE

The module is designed with a built-in LNA, and supports passive GNSS antenna only. Active antenna
and external LNA are not supported.

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 LPWA Module Series

5 Recommended Footprint
This chapter mainly describes the recommended footprint and stencil design for BG77 and BG770A-GL
modules. All dimensions are measured in mm, and the tolerances for dimensions without tolerance
values are ±0.2 mm.

5.1. Recommended Compatible Footprint

The following figure shows the bottom views of BG77 and BG770A-GL.

Figure 26: Bottom Views of BG77 & BG770A-GL

The following figure shows the recommended compatible footprint of BG77 and BG770A-GL.

BG77&BG770A-GL_Compatible_Design 38 / 42
 LPWA Module Series

Figure 27: Recommended Compatible Footprint of BG77/BG770A-GL (Top View)

NOTE

1. For easy maintenance of the module, keep a distance of about 3 mm between the module and
other components on the motherboard.
2. All RESERVED pins must be kept open.
3. For stencil design requirements of the module, see document [5].

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 LPWA Module Series

5.2. Installation Sketch Map

The following figure shows the sketch map of installation for BG77 and BG770A-GL.

Figure 28: Installation Sketch Map for BG77/BG770A-GL

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 LPWA Module Series

6 Appendix References

Table 7: Related Documents

Document Name

[1] Quectel_BG77_Hardware_Design

[2] Quectel_BG770A-GL_Hardware_Design

[3] Quectel_BG95&BG77&BG600L_Series_AT_Commands_Manual

[4] Quectel_BG770A-GL&BG95xA-GL_AT_Commands_Manual

[5] Quectel_Module_Secondary_SMT_Application_Note

Table 8: Terms and Abbreviations

Abbreviation Description

ADC Analog-to-Digital Converter

CTS Clear to Send

DRX Discontinuous Reception

DCE Data Communications Equipment

DTE Data Terminal Equipment

ESD Electrostatic Discharge

ESR Equivalent Series Resistance

FDD Frequency Division Duplex

GLONASS Global Navigation Satellite System (Russia)

GNSS Global Navigation Satellite System

GPS Global Positioning System

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 LPWA Module Series

kbps Kilo Bits Per Second

LDO Low-dropout Regulator

LGA Land Grid Array

LED Light Emitting Diode

LNA Low Noise Amplifier

LPWA Low Power Wide Area

LTE Long Term Evolution

MLCC Multi-layer Ceramic Chip

NEMA NMEA (National Marine Electronics Association) 0183 Interface Standard

PCB Printed Circuit Board

PCM Pulse Code Modulation

PHY Physical

PSM Power Saving Mode

RF Radio Frequency

RTS Request to Send

RXD Receive Data

SMS Short Message Service

TXD Transmitting Data

UART Universal Asynchronous Receiver & Transmitter

USB Universal Serial Bus

USIM (Universal) Subscriber Identity Module

VoLTE Voice over LTE

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