Serial in/serial out shift registers

• 4 bit register
• It needs 4 clock pulses to store 4 bits
• Example:
– Illustrate entry of the 4 bits 1010 into the register.
– Illustrate serially shifting the 4 bits out of the register, i.e. clearing the
register.
Serial in/parallel out shift registers
• Data bits are entered serially as illustrated before
• Once the data are stored, the output of each stage is
available on its output line.
Serial in/parallel out shift registers
• 4-bit register
Serial in/parallel out shift registers
• Example: Show the state of the 4-bit register foe the
data input and clock waveforms. The register initially
contains all 1s.
Serial In/Parallel Out Shift Registers
• 8-bit serial in/parallel out
Parallel In/Serial Out Shift Registers
• The bits are entered simultaneously into their respective
stages.
• The serial output appears bit by bit per clock pulse.
• To store 4 bits, we need 1 clock pulse
• To shift them out them, we need another 3 clock pulses.
• 4-bit parallel in/serial out
Parallel In/Serial Out Shift Registers
4-bit parallel in/serial out
• 4-bit parallel in/serial out
Parallel In/Parallel Out Shift Registers
• The bits are entered simultaneously into their respective
stages.
• Immediately, the bits appear on the parallel outputs.

4-bit version
Parallel In/Parallel Out Shift Registers
• 4-bit version
4-bit version
Example: Show the states of the 5-bit shift register for the specified
data input and clock waveforms. The registered is initially cleared.
Bidirectional Shift Register
• A bidirectional shift register is one in which the data
can be shifted either left or right.

4-bit version
A basic shift register is simply a chain of D flip-flops with a common clock.

serial D Q D Q D Q D Q
serial
input output

A B C D
clock

Each flip-flop transfers its D input to its Q output at a clock transition.

• The effect is to transfer data along the register, one flip-flop per clock
cycle.

This type of register is called a serial input-serial output (SISO).

 A basic shift register is simply a chain of D flip-flops with a common clock.

Basic shift register

serial input D Q D Q D Q D Q
serial
01001110 output

A B C D
clock
input QA QB QC QD
The table shows the contents of the
0 0 0 0 0
register after successive clock transitions.
The assumption is that the register is 1 1 0 0 0
initially clear.

clock pulses
1 1 1 0 0
• The number of clock pulses needed to
fill the register is equal to the number of 1 1 1 1 0
flip-flops used to make the register. 0 0 1 1 1
• This is a 4 bit register. 0 0 0 1 1
1 1 0 0 1
0 0 1 0 0
 Timing for a shift register
clock

input

QA

QB

QC

QD tpd

The pattern in successive flip-flops moves to the right with each clock
cycle to shift the pattern into and out of the register.
 Timing for a shift register
clock

input

QA

QB

QC input QA QB QC QD
0 0 0 0 0
QD tpd
1 1 0 0 0
1 1 1 0 0
1 1 1 1 0
0 0 1 1 1
It is desired to design a binary ripple counter of the type shown in previous slide that is capable of counting
the number of items passing on a conveyor belt. Each time an item passes a given point, a pulse is
generated that can be used as a clock input. If the maximum number of items to be counted is 6000,
determine the number of flip-flops required.

• The counter should be able to count a maximum of 6000 items.

• An N-flip-flop would be able to count up to a maximum of 2N - 1 counts.

• On the 2Nth clock pulse, it will get reset to all 0s.

Now, 2N - 1 should be greater than or equal to 6000.

• That is, 2N - 1 ≥ 6000, which gives N ≥ log 6001/log 2 ≥

3.778/0.3010 ≥ 12.55.

• The smallest integer that satisfies this condition is 13.

Pre-settable Counter
Timing Diagram
Cascading
Cascading Two BCD Counters
• This presettable counter has been wired as a DOWN counter.
• The preset data input is 0110.
• Therefore, the modulus of the counter is 6 (the decimal equivalent of 0110).
Now, the counter is initially in the 0110 state.
• Therefore, at the end of the sixth clock pulse, immediately after the leading
edge of the sixth clock pulse, the counter will be in the 0000 state.
• A HIGH-to-LOW transition at the TCD output, coinciding with the trailing
edge of the sixth clock pulse, loads 0110 to the counter output.
• Therefore, immediately after the leading edge of the eighth
clock pulse, the counter will be in the 0100 state.
Design a T-type Counter with states 0,3,5,6
Architecture of a frequency counter