Pin diagram of 8086 microprocessor

Pin diagram of 8086 microprocessor is as given below:

Intel 8086 is a 16-bit HMOS microprocessor. It is available in 40 pin DIP chip. It uses a 5V DC supply
for its operation. The 8086 uses a 20-line address bus. It has a 16-line data bus. The 20 lines of the
address bus operate in multiplexed mode. The 16-low order address bus lines have been multiplexed
with data and 4 high-order address bus lines have been multiplexed with status signals.

AD0-AD15: Address/Data bus. These are low order address bus. They are multiplexed with data.
When AD lines are used to transmit memory address the symbol A is used instead of AD, for
example A0-A15. When data are transmitted over AD lines the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.

A16-A19: High order address bus. These are multiplexed with status signals.

S2, S1, S0: Status pins. These pins are active during T4, T1 and T2 states and is returned to passive
state (1,1,1 during T3 or Tw (when ready is inactive). These are used by the 8288 bus controller for
generating all the memory and I/O operation) access control signals. Any change in S2, S1, S0 during
T4 indicates the beginning of a bus cycle.

S2 S1 S0 Characteristics

0 0 0 Interrupt acknowledge

0 0 1 Read I/O port

0 1 0 Write I/O port

0 1 1 Halt

1 0 0 Code access

1 0 1 Read memory

1 1 0 Write memory

1 1 1 Passive state

A16/S3, A17/S4, A18/S5, A19/S6 : The specified address lines are multiplexed with corresponding
status signals.

A17/S4 A16/S3 Function

0 0 Extra segment access

0 1 Stack segment access

1 0 Code segment access

1 1 Data segment access

HE’/S7: Bus High Enable/Status. During T1 it is low. It is used to enable data onto the most significant
half of data bus, D8-D15. 8-bit device connected to upper half of the data bus use BHE (Active Low)
signal. It is multiplexed with status signal S7. S7 signal is available during T2, T3 and T4.

RD’: This is used for read operation. It is an output signal. It is active when low.

READY : This is the acknowledgement from the memory or slow device that they have completed the
data transfer. The signal made available by the devices is synchronized by the 8284A clock generator
to provide ready input to the microprocessor. The signal is active high(1).

INTR : Interrupt Request. This is triggered input. This is sampled during the last clock cycles of each
instruction for determining the availability of the request. If any interrupt request is found pending,
the processor enters the interrupt acknowledge cycle. This can be internally masked after resulting
the interrupt enable flag. This signal is active high(1) and has been synchronized internally.

NMI : Non maskable interrupt. This is an edge triggered input which results in a type II interrupt. A
subroutine is then vectored through an interrupt vector lookup table which is located in the system
memory. NMI is non-maskable internally by software. A transition made from low(0) to high(1)
initiates the interrupt at the end of the current instruction. This input has been synchronized
internally.

INTA : Interrupt acknowledge. It is active low(0) during T2, T3 and Tw of each interrupt acknowledge
cycle.

MN/MX’ : Minimum/Maximum. This pin signal indicates what mode the processor will operate in.

RQ’/GT1′, RQ’/GT0′ : Request/Grant. These pins are used by local bus masters used to force the
microprocessor to release the local bus at the end of the microprocessor’s current bus cycle. Each of
the pin is bi-directional. RQ’/GT0′ have higher priority than RQ’/GT1′.
LOCK’ : Its an active low pin. It indicates that other system bus masters have not been allowed to
gain control of the system bus while LOCK’ is active low(0). The LOCK signal will be active until the
completion of the next instruction.

TEST’ : This examined by a ‘WAIT’ instruction. If the TEST pin goes low(0), execution will continue,
else the processor remains in an idle state. The input is internally synchronized during each of the
clock cycle on leading edge of the clock.

CLK : Clock Input. The clock input provides the basic timing for processing operation and bus control
activity. Its an asymmetric square wave with a 33% duty cycle.

RESET : This pin requires the microprocessor to terminate its present activity immediately. The signal
must be active high(1) for at least four clock cycles.

Vcc : Power Supply( +5V D.C.)

GND : Ground

QS1,QS0 : Queue Status. These signals indicate the status of the internal 8086 instruction queue
according to the table shown below:

QS1 QS0 Status

0 0 No operation

0 1 First byte of op code from queue

1 0 Empty the queue

1 1 Subsequent byte from queue

=DT/R : Data Transmit/Receive. This pin is required in minimum systems, that want to use an 8286
or 8287 data bus transceiver. The direction of data flow is controlled through the transceiver.

DEN: Data enable. This pin is provided as an output enable for the 8286/8287 in a minimum system
which uses transceiver. DEN is active low(0) during each memory and input-output access and for
INTA cycles.
HOLD/HOLDA: HOLD indicates that another master has been requesting a local bus .This is an active
high(1). The microprocessor receiving the HOLD request will issue HLDA (high) as an
acknowledgement in the middle of a T4 or T1 clock cycle.

ALE : Address Latch Enable. ALE is provided by the microprocessor to latch the address into the 8282
or 8283 address latch. It is an active high(1) pulse during T1 of any bus cycle. ALE signal is never
floated, is always integer.

Assembly Language Program Development Tools

1. Editor

- An editor is a program which allows you to create a file containing the assembly
language statements for your program.

Example: PC-Write, Wordstar.

- As you type in your program, the editor stores the ASCII codes for the letters and
numbers in successive RAM locations.

- When you have typed in all your program, you then save the file on the hard disk.
This file is called source file and the extension is .asm.

2. Assembler

- An assembler program is used to translate the assembly language mnemonics for

instructions to corresponding binary codes. When you run the assembler, it reads
the source file of your program from the disk where you have saved it after editing.

- On the first pass through the source program, the assembler determines the
displacement of named data items, the offset of labels, etc. And puts this
information in a symbol table.

- On the second pass through the source program, the assembler produces the binary
code for each instruction and inserts the offsets, etc. That it calculated during the
first pass.
 - The assembler generates 2 files on the floppy disk or hard disk. The first file is called
object file (.obj).

- The second file generated by assembler is called the assembler list file and is given
extension (.lst).

3. Linker

- A linker is a program used to join several object files into one large object file.

- The linker produces a link file which contains the binary codes for all the combined
modules. The linker also produces a link map file which contains the address
information about the linked files (.exe).

4. Locator

- A locator is a program used to assign the specific address of where the segments of
object code are to be loaded into memory.

- A locator program called EXE2BIN comes with the IBM PC Disk Operating System
(DOS). EXE2BIN converts a .exe file to a .bin file which has physical addresses.

5. Debugger

- A debugger is a program which allows you to load your object code program into
system memory, execute the program and troubleshoot or debug it.

- The debugger allows you to look at the contents of registers and memory locations
after your program runs.
 - It allows you to change the contents of registers and memory locations and re-run
the program.

- Some debuggers allow you to stop execution after each instruction so that you can
check or alter after each register contents.

- A debugger also allows you to set a breakpoint at any point in your program. If you
insert a breakpoint at any point in your program, the debugger will run the program
up to the instruction where you put the breakpoint and then stop the execution.

6. Emulator

- An emulator is a mixture of hardware and software.

- It is used to test and debug the hardware and software of an external system, such
as the prototype of a microprocessor based instrument. Part of the hardware of an
emulator is a multiwire cable which connects the host system to the system being
developed.

- Features of 8086 of microprocessor

-
- Architecture of 8086 microprocessor

- 8086 Microprocessor is divided into two functional units, i.e., EU (Execution Unit)
and BIU (Bus Interface Unit).

- EU (Execution Unit)
- Execution unit gives instructions to BIU stating from where to fetch the data and
then decode and execute those instructions. Its function is to control operations on
data using the instruction decoder & ALU. EU has no direct connection with system
buses as shown in the above figure, it performs operations over data through BIU.
-
- Let us now discuss the functional parts of 8086 microprocessors.
-
- ALU
- It handles all arithmetic and logical operations, like +, −, ×, /, OR, AND, NOT
operations.
-
- Flag Register
- It is a 16-bit register that behaves like a flip-flop, i.e. it changes its status according
to the result stored in the accumulator. It has 9 flags and they are divided into 2
groups – Conditional Flags and Control Flags.
-
- Conditional Flags
- It represents the result of the last arithmetic or logical instruction executed.
Following is the list of conditional flags –
-
- Carry flag – This flag indicates an overflow condition for arithmetic operations.
-
- Auxiliary flag – When an operation is performed at ALU, it results in a carry/barrow
from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), then this flag is set,
i.e. carry given by D3 bit to D4 is AF flag. The processor uses this flag to perform
binary to BCD conversion.
-
- Parity flag – This flag is used to indicate the parity of the result, i.e. when the lower
order 8-bits of the result contains even number of 1’s, then the Parity Flag is set. For
odd number of 1’s, the Parity Flag is reset.
-
- Zero flag – This flag is set to 1 when the result of arithmetic or logical operation is
zero else it is set to 0.
-
- Sign flag – This flag holds the sign of the result, i.e. when the result of the operation
is negative, then the sign flag is set to 1 else set to 0.
-
- Overflow flag – This flag represents the result when the system capacity is exceeded.
-
- Control Flags
- Control flags controls the operations of the execution unit. Following is the list of
control flags –
-
- Trap flag – It is used for single step control and allows the user to execute one
instruction at a time for debugging. If it is set, then the program can be run in a
single step mode.
-
- Interrupt flag – It is an interrupt enable/disable flag, i.e. used to allow/prohibit the
interruption of a program. It is set to 1 for interrupt enabled condition and set to 0
for interrupt disabled condition.
-
- Direction flag – It is used in string operation. As the name suggests when it is set
then string bytes are accessed from the higher memory address to the lower
memory address and vice-a-versa.
-
- General purpose register
- There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH, and DL. These
registers can be used individually to store 8-bit data and can be used in pairs to store
16bit data. The valid register pairs are AH and AL, BH and BL, CH and CL, and DH and
DL. It is referred to the AX, BX, CX, and DX respectively.
 -
- AX register – It is also known as accumulator register. It is used to store operands for
arithmetic operations.
-
- BX register – It is used as a base register. It is used to store the starting base address
of the memory area within the data segment.
-

CX register – It is referred to as counter. It is used in loop instruction to store the loop

counter.

DX register – This register is used to hold I/O port address for I/O instruction.

Stack pointer register

It is a 16-bit register, which holds the address from the start of the segment to the memory location,
where a word was most recently stored on the stack.

BIU (Bus Interface Unit)

BIU takes care of all data and addresses transfers on the buses for the EU like sending addresses,
fetching instructions from the memory, reading data from the ports and the memory as well as
writing data to the ports and the memory. EU has no direction connection with System Buses so this
is possible with the BIU. EU and BIU are connected with the Internal Bus.

It has the following functional parts –

Instruction queue – BIU contains the instruction queue. BIU gets upto 6 bytes of next instructions
and stores them in the instruction queue. When EU executes instructions and is ready for its next
instruction, then it simply reads the instruction from this instruction queue resulting in increased
execution speed.

Fetching the next instruction while the current instruction executes is called pipelining.

Segment register – BIU has 4 segment buses, i.e. CS, DS, SS& ES. It holds the addresses of
instructions and data in memory, which are used by the processor to access memory locations. It
also contains 1 pointer register IP, which holds the address of the next instruction to executed by the
EU.
CS – It stands for Code Segment. It is used for addressing a memory location in the code segment of
the memory, where the executable program is stored.

DS – It stands for Data Segment. It consists of data used by the program andis accessed in the data
segment by an offset address or the content of other register that holds the offset address.

SS – It stands for Stack Segment. It handles memory to store data and addresses during execution.

ES – It stands for Extra Segment. ES is additional data segment, which is used by the string to hold
the extra destination data.

Instruction pointer – It is a 16-bit register used to hold the address of the next instruction to be
executed.