RPM PMIC Software Driver Overview: Qualcomm Technologies, Inc

RPM PMIC Software Driver Overview
Qualcomm Technologies, Inc.
80-NN255-1 B
Confidential and Proprietary – Qualcomm Technologies, Inc.
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PAGE 2 80-NN255-1 B September 2015 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
Revision History
Revision Date Description
A April 2014 Initial release
B September 2015 Updated slides 21, 23-28, 32, and 37-38
Contents
 Introduction
 RPM Firmware – PMIC Software Driver Support
 Communication – SPMI
 Configurations
 Target
 NPA
 Other Drivers
 References
 Questions?
Objectives
 At the end of this presentation, you will understand RPM PMIC driver
usage.
Introduction
RPM Firmware – PMIC Software Driver Support
 In the Resource Power Manager

(RPM), the PMIC driver is available at
rpm_proc\core\systemdrivers\pmic.
 One main function of the RPM
processor is to control PMIC voltage
regulators (VREG) and clocks (CLK).
 All shared VREG and CLK requests from
the apps, modem, and other processors
are handled by the RPM.
 After the requests are received by the
RPM, it configures the PMIC peripherals
in accordance with the aggregation
algorithm in the RPM PMIC software.
 Two APIs available in the RPM PMIC
software can be called when a device
goes in and out of RPM-assisted
sleep.
 Customers can use these functions to
configure PMIC VREGs to low power
settings.
RPM Firmware – PMIC Software Driver Support (cont.)
 Application processor (apps

processor)
 In most cases, routes requests
for shared power and clock
resources to RPM
 Interacts directly with PMIC for
dedicated resources
 Modem processor
 Routes requests for shared
power and clock resources to
RPM
 Interacts directly with PMIC for
dedicated resources
 RPM processor
 Receives and processes
requests from apps and modem
processors for PMIC resources
RPM Firmware – PMIC Software Driver
Support
PMIC Software Drivers
 PMIC drivers – Accessible from RPM

 Boost voltage – Boost
 Clock – CLK
 LDO-type regulator – LDO
 Power-on – PON
 PWR – Supports LDO, Switch mode power supply (SMPS), and VS drivers
 Real-Time Clock – RTC
 Switch mode power supply – SMPS
 Voltage Switches – VS
PMIC Software Drivers (cont.)
RPM
Power
Railway driver Sleep Watchdog
PMIC
NPA Target
CLK LDO SMPS Boost VS Other (RTC, PON, etc.)
PWR
SPMI
PMIC hardware
CLK Driver
 Customer header files

 \rpm_proc\core\api\systemdrivers\pmic\pm_clk.h
 \rpm_proc\core\api\systemdrivers\pmic\pm_clk_sleep.h
 Source files
 rpm_proc\core\systemdrivers\pmic\drivers\clk\src\Pm_clk_driver.c
 rpm_proc\core\systemdrivers\pmic\drivers\clk\src\Pm_clk_sleep.c
 APIs available
 Sleep clock
 pm_clk_sleep_src_status() – Returns on/off (enable/disable) status of the sleep clock,
32 K XTAL oscillator
 For driver strength, use API in SBL1 as a one-time initialization setting
 Use node power architecture (NPA) to control CLK enable and pin control
functions
CLK XO
 Customer header file

 \rpm_proc\core\api\systemdrivers\pmic\ pm_clk_xo.h
 Source file
 APIs available
 pm_clk_xo_set_warmup_time() – Configures the temperature-compensated
crystal oscillator (TCXO) warmup delay time; delay time is the number of sleep
(32 KHz) clock cycles to wait for the XO clock warmup time
 Reference – For Xtal init, \rpm_proc\core\power\mpm\hal\source\common\HALmpm.c
PON Driver
 Customer header files

 \rpm_proc\core\api\systemdrivers\pmic\pm_clk.h
 \rpm_proc\core\api\systemdrivers\pmic\pm_clk_sleep.h
 Source files
 rpm_proc\core\systemdrivers\pmic\drivers\clk\src\Pm_clk_sleep.c
 Important APIs
 PMIC watchdog – Configured in RPM; RPM is responsible for periodically
petting the watchdog
 pm_pon_wdog_cfg() – Configures PMIC watchdog
 pm_pon_wdog_enable() – Enables watchdog
 Reference – Initializes PMIC WD – \rpm_proc\core\power\rpm\dog.c
 pm_pon_wdog_pet() – Pets watchdog
 Reference – Periodically pets, \rpm_proc\core\bsp\rpm\src\main.c
 Reference – Pets before sleep, \rpm_proc\core\power\sleep\src\lpr_definition_uber.c
Boost Driver
 Customer header file – None

 Source file
 rpm_proc\core\systemdrivers\pmic\drivers\boost\src\Pm_boost_driver.c
 Boost enable should be performed through NPA; enable and voltage
status algorithms are used by NPA
 Communication and system power management interface (SPMI) occur in
the power driver
LDO Driver

 \rpm_proc\core\api\systemdrivers\pmic\pm_ldo.h
 Source file
 rpm_proc\core\systemdrivers\pmic\drivers\ldo\src\Pm_ldo.c
 APIs available
 pm_ldo_sw_enable_status() – Gets the status of enable or disable of a
regulator or voltage switcher
 pm_ldo_calculate_vset() – Gets VSET for LDO
 Other APIs in the header file are not defined
 LDO enable, mode, voltage, pull-down (PD), and pin control (PC) should
be performed through NPA
 Communication and SPMI occur in the power driver
SMPS Driver

 \rpm_proc\core\api\systemdrivers\pmic\pm_smps.h
 Source file
 \rpm_proc\core\systemdrivers\pmic\drivers\smps\src\pm_smps_driver.c
 APIs
 pm_smps_calculate_vset() – Gets VSET for SMPS
 pm_smps_sw_mode_status_raw() – Obtains mode status, i.e., HPM, LPM, etc.,
at an instance
 All other APIs in the header file are not defined
 SMPS enable, mode, Quiet mode, voltage, frequency, PD, and PC should
be performed through NPA
 Communication and SPMI occur in the power driver
VS Driver

 \rpm_proc\core\api\systemdrivers\pmic\pm_vs.h
 Source file
 \rpm_proc\core\systemdrivers\pmic\drivers\vs\src\pm_vs_driver.c
 APIs
 Other APIs in the header file are not defined
 VS enable, mode, PD, and PC control should be performed through NPA
PWR Driver
 Low-level driver for SMPS, LDO, and VS drivers; communication and

SPMI occur here
 Customer header file – None
 Source file
 \rpm_proc\core\systemdrivers\pmic\drivers\pwr\src
Communication – SPMI
SPMI R/W
 It is not recommended performing direct register writes to PMIC except during sleep
entry/exit.
 APIs
 Reads 1 byte from address – pm_spmi_lite_read_byte (uSlaveId, address, data, priority)
 Reads unmasked bits from address – pm_spmi_lite_read_byte_mask (uSlaveId, address, mask,
data, priority)
 Reads numBYtes bytes from address – pm_spmi_lite_read_byte_array (uSlaveId, addr ,
numBYtes, data, priority)
 Writes 1 byte from address – pm_spmi_lite_write_byte (uSlaveId, address, data, priority)
 Writes unmasked bits from address – pm_spmi_lite_write_byte_mask (uSlaveId, address,
NumBytes, data, priority)
 Writes numBYtes bytes from address – pm_spmi_lite_write_byte_array (uSlaveId, address,
NumBytes, data, priority)
 uSlaveId :
 0 for register address < 0x10000 on PM89xx
 1 for register address > 0x10000 on PM89xx
 2 for register address < 0x10000 on PMI89xx
 3 for register address > 0x10000 on PMI89xx
 4 for register address < 0x10000 on PM8841
 5 for register address > 0x10000 on PM8841
 Address – Low 16 bits of address, e.g, 0x4B09 for register – 0x14B09
 Set priority = 0
 Example
 pm_spmi_lite_write_byte(1, 0x4746, 0x00, 0);
Configurations
Power Dependency
 There is a dependency in LDO and SMPS; see the power grid for
dependencies in PM8841 and PM8941 Power Management Design
Guidelines (80-NA555-5).
 Source file, which lists the dependency between regulators
 rpm_proc\core\systemdrivers\pmic\config\<chipset>_pm_config_npa_dep.c
static pm_pwr_resource *<chipset>_smps1_a_child_dep[] static pm_pwr_resource *<chipset>_boost1_a_child_dep[] ={
={ &<chipset>_vs_a[4],
&<chipset>_ldo_a[1], &<chipset>_vs_a[5],};
&<chipset>_ldo_a[3],
};
typedef struct pm_pwr_resource_dependency_info
static pm_pwr_resource {
*<chipset>_smps2_a_child_dep[] ={ pm_pwr_resource *parent_source_dependency; // parent
&<chipset>_ldo_a[12], resource
&<chipset>_ldo_a[14], pm_pwr_resource
&<chipset>_ldo_a[15], **child_resource_dependents; // array of child
&<chipset>_ldo_a[5], resources
&<chipset>_ldo_a[6], unsigned
&<chipset>_ldo_a[7], parent_source_dependency_client_handle; // internal
}; client handle to make calls to the parent resource
}pm_pwr_resource_dependency_info;
static pm_pwr_resource
*<chipset>_smps3_a_child_dep[] ={
&<chipset>_vs_a[1],
&<chipset>_vs_a[2],
&<chipset>_vs_a[3],
};
RPM NPA Nodes
 A node can have one or several resources, depending on the number of

physical blocks/ports that are supported. A node can request one or
several client NPA resources.
 This file contains initialization functions for NPA and node definitions.
 Source file
 rpm_proc\core\systemdrivers\pmic\config\<chipset>_pm_config_rpm_npa_node_rsrcs.c
 This file defines RPM local NPA clients.
 LPDDR client
 PMIC resource dependency for this client, e.g., <chipset> resources – L1, S1, S3
<chipset>_pm_rpm_proc_client_dev_deps_lpddr [] = {
{RPM_LDO_A_REQ, 1, PM_RPM_NPA_CLIENT_LDO_A_REQ, 0 },
{RPM_SMPS_A_REQ, 1, PM_RPM_NPA_CLIENT_SMPS_A_REQ, 0 },
{RPM_SMPS_A_REQ, 3, PM_RPM_NPA_CLIENT_SMPS_A_REQ, 0 }, };
RPM NPA Nodes – RPM INIT
 RPM INIT client

 PMIC resources needed for RPM operation
<chipset>_pm_rpm_proc_client_dev_deps_rpm_init [] = {
{RPM_CLK_BUFFER_A_REQ, 1, PM_RPM_NPA_CLIENT_CLK_BUFFER_A_REQ,
0 }, // Resource Name, Maximum value, Resource Attributes
{RPM_LDO_A_REQ, 6, PM_RPM_NPA_CLIENT_LDO_A_REQ, 0 },
{RPM_SMPS_B_REQ, 3, PM_RPM_NPA_CLIENT_SMPS_B_REQ, 0 }, };
<chipset>_pm_rpm_proc_client_dev_deps_rpm_init_info =
{
NPA_ARRAY_SIZE(<chipset>_pm_rpm_proc_client_dev_deps_rpm_init),
<chipset>_pm_rpm_proc_client_dev_deps_rpm_init
};
RPM NPA PAM Table
 PAM table has information about settings, e.g., voltage of PMIC

resources, i.e., SMPS, corresponding to each PMIC NPA client and its
modes
 The PAM table has PMIC resource settings for RPM NPA local clients.
 LPDDR
 RPM INIT
 Each processor has its own PAM table based on NPA nodes on the
processor, e.g.:
modem_proc\core\systemdrivers\pmic\target\<chipset>\modemproc\npa\
protected\pm_modem_proc_pam.c.
 Open source – Customers can modify this table, but it is strongly
recommended that customers discuss proposed changes with the QTI
PMIC CE team.
 For more information, see Presentation: Non-HLOS PMIC NPA Overview
(80-NG006-1).
Target-Specific PMIC Resource Configurations
 This file contains customizable, target-specific driver settings, and PMIC

registers. Because VREG and CLK configuration and control is dictated
by the PAM/NPA, the RPM sets programmable limits for the SMPS and
LDO VREGs.
 Source file
 rpm_proc\core\systemdrivers\pmic\config\<chipset>\pm_config_target.c
 It is strongly recommended that customers discuss proposed changes with the
QTI PMIC CE team.
 LDO configuration
 The upper limit of the programmable range of LDOs is listed in the right-most
column of the ldo_rail_a table.
pm_rpm_ldo_rail_info_type <chipset>_ldo_rail_a[<chipset>_NUM_OF_LDO_A] =
{
10, // LpHpCurrentThreshold in mA
25, //SafetyHeadRoom in mV
0, // IsSawControlled:1; 0 - not SAW controlled
1, // 0 – NO NPA Access; 1 – NPA Access Granted
1, // 0 - allow to be turned off; 1 - always on
PM_NPA_SW_MODE_LDO__IPEAK, // SW Mode LDO Type -
PM_NPA_SW_MODE_LDO__IPEAK, PM_NPA_SW_MODE_LDO__NPM, PM_NPA_SW_MODE_LDO__INVALID
1200, //MinVoltage in mV
1225 //MaxVoltage in mV
};
Target-Specific PMIC Resource Configurations (cont.)
 SMPS configuration – The upper limit of the programmable range of

SMPSs is listed in the right-most column of the smps_rail_a table
pm_rpm_smps_rail_info_type <chipset>_smps_rail_a[<chipset>_NUM_OF_SMPS_A] = {
100, //LpHpCurrentThreshold:16; // in mA
0, //IsSawControlled:1 , 0 - not SAW controlled
1, //AccessAllowed:1, 0 – NO NPA Access; 1 – NPA Access Granted
1, //AlwaysOn:1, 0 - allow to be turned off
PM_NPA_SW_MODE_SMPS__AUTO, // 0 - AUTO, 1- IPEAK, 2 - NPM
PM_CLK_1p6_MHz, // MinFreq 1 - 9.6M, 2 - 6.4M, 3 - 4.8M, 5 - 3.2M, etc
PM_CLK_1p6_MHz,// MaxFreq1 - 9.6M, 2 - 6.4M, 3 - 4.8M, 5 - 3.2M, etc
1200, //MinVoltage in mV
1500 //MaxVoltage in mV
};
 Boost/VS/CLK configuration
pm_rpm_boost_rail_info_type <chipset>_boost_rail_a[<chipset>_NUM_OF_BOOST_A] = {
1, // 0 – NO NPA Access; 1 – NPA Access Granted,
0 // 0 - allow to be turned off; 1 - always on
};
pm_rpm_vs_rail_info_type <chipset>_vs_rail_a[<chipset>_NUM_OF_VS_A] = {
1, // 0 – NO NPA Access; 1 – NPA Access Granted,
0 // 0 - allow to be turned off; 1 - always on
};
pm_rpm_clk_info_type <chipset>_clk_info_a[<chipset>_NUM_OF_CLK_A]= {
{0, 1}
};
RPM PMIC Init
 Source file
 rpm_proc\core\systemdrivers\pmic\npa\src\rpm\pm_rpm_npa_device.c.c
pm_rpm_device_init(void) {
Resource Count Info
Initialize all Device A Resources Types
Initialize all Device B Resources Types
Initialize all Device A Resources Types dependencies
Initialize all Device B Resources Types dependencies
}
Target
LED APP
 Source file – Pm_app_led.c

 Contains algorithms for diming LPG and controlling light
 Used by RPM firmware for the low-power LED debug feature
RPM Sleep/Wake Config
 It is recommended that PMIC sleep and wake-up sequences are

performed in programmable boot sequence (PBS) RAM.
 Customer-specific PMIC registers configurations/sequence during sleep
can be made by adding a sleep_enter_info[] table that executes the listed
register writes before entering sleep. The register writes to revert these
sleep settings can be made by adding a sleep_exit_info[] that executes
the listed register writes after exiting sleep.
 The register writes go in order from top to bottom and the tables must end
with {0, 0xFFFF, 0x00}.
 Source file
 Core\systemdrivers\pmic\target\<chipset>\src\pm_rpm_proc_npa_device_cfg.c
 Sleep_enter_info and sleep_exit_info tables should be defined/added at
core\systemdrivers\pmic\config\<chipset>_pm_config_target.c
 The following are APIs that can be used:
 pm_npa_rpm_enter_sleep()
 pm_npa_rpm_exit_sleep()
RPM Sleep/Wake Config (cont.)
 sleep_enter_info[] and sleep_exit_info[] for MSM8x10 – Example

sleep_register_type sleep_enter_info[] =
{
{1, 0x4545, 0x10}, //Set LDO6 (1.8V I/O) to follow sleep_b
{1, 0x4145, 0x10}, //Set LDO2 (LPDDR2) to follow sleep_b
{1, 0x4946, 0x00}, //Disable LDO10
{1, 0x1A41, 0x44}, //Set S3 to 1.225V (range 0) (input to 1.2V LDO for LPDDR2)
{1, 0x1D41, 0x0C}, //Set S4 to 1.85V (range 1) (input to 1.8V LDO for I/O)
{1, 0x1A45, 0x00}, //Set S3 to PFM mode
{1, 0x1D45, 0x00}, //Set S4 to PFM mode
//------------------------------------------------------------------
{0, 0xFFFF, 0x00}, // invalid setting, used to check the end of the array.
};
sleep_register_type sleep_exit_info[] =
{
{1, 0x1A45, 0x40}, //Set S3 to Automode
{1, 0x1D45, 0x40}, //Set S4 to Automode
{1, 0x1A41, 0x4E}, //Set S3 to 1.35V (range 0)
{1, 0x1D41, 0x18}, //Set S4 to 2.15V (range 1)
{1, 0x4946, 0x80}, //Enable LDO10
//Temp fix for SPMI INT MISS
//INT_INT_RESEND_ALL => 0x540 (register)
//INT_RESEND_ALL => 0x1 (field)
{0 , 0x540, 0x01},
//SPMI_INT_LATCHED_CLR => 0x614 (register)
//SPMI_INT_LATCHED_CLR =>0x1 (field)
{0 , 0x614, 0x01},
//--------------------------------------------------------------------
{0, 0xFFFF, 0x00}, // invalid setting, used to check the end of the array.
};
NPA
RPM NPA
 NPA framework is built into the Core Board Software/Support Package

(Core BSP)
 Provides power abstraction via modes
 Applies
 Aggregation
 Predependency analysis
 Execute driver
 Postdependency analysis
 Source file
 rpm_proc\core\systemdrivers\pmic\Npa\src\rpm\pm_rpm_XXX_trans_apply.c
 For more details on NPA, see Presentation: Non-HLOS PMIC NPA
Overview (80-NG006-1)
Other Drivers
RPM Railway Driver
 Railway driver controls

 CX = S2B
 MX = S1B
 GFX = S4B
 See the power grid for CX/MX/GFX rails in PM8841 and PM8941 Power
Management Design Guidelines (80-NA555-5).
 CX can never be greater than MX; they are both interdependent
 Railway driver
 Corners voltages, corners used, rails power CX/MX/GFX in the config file are
defined.
 Source files
 rpm_proc\core\power\railway_v2\src\<chipset>\railway_config.c
 rpm_proc\core\power\railway_v2\src\railway.c
 PMIC – Railway driver support
 APIs it uses for the configuration are defined in rpm_proc\core\systemdrivers\
pmic\npa\src\rpm\pm_rpm_railway.c
 These pm_rpm_railway APIs call PMIC APIs to make SMPS settings; located at
\rpm_proc\core\systemdrivers\pmic\drivers
RPM Rapid Bridge Core Power Reduction (RBCPR)
 RBCPR uses adaptive voltage scaling (AVS); it sets the initial operating
voltages by AVS fuse bits and then dynamically adjusts the operating
voltages by AVS controller via RPM, based on internal sensors
 The steps are as follows:
 RPM firmware reads eFuses
 RPM firmware sets initial voltages in PMIC.ef
 PMIC outputs updated voltage to MSM
 Updated voltage affects AVS sensors
 AVS sensors generate AVS data
 AVS controller computes voltage readjustment and
interrupts the RPM
 RPM firmware writes voltage readjustment to PMIC
 PMIC outputs updated voltage to MSM
 Updated voltage affects AVS sensors
 Source file
 rpm_proc\core\power\rbcpr\src\target\<chipset>\rbcpr_bsp.c
 Due to RBCPR, voltage at the corner might be different from set voltage
References
Documents

Presentation: Non-HLOS PMIC NPA Overview 80-NG006-1
Adaptive Voltage Scaling (AVS) Application Note 80-N8715-14
PM8841 and PM8941 Power Management Design Guidelines 80-NA555-5
Acronyms
Term Definition
apps processor application processor
AVS adaptive voltage scaling
Core BSP core board software/support package
LDO low dropout
NPA node power architecture
PBS programmable boot sequence
PC pin control
PD pull-down
PON power-on
RBCPR RPM Rapid Bridge Core Power Reduction
References (cont.)
Acronyms
Term Definition
RPM Resource Power Manager
RTC real-time clock
SMPS switch mode power supply
SPMI system power management interface
TCXO temperature-compensated crystal oscillator
VREG voltage regulator
VS voltage switches
Questions?
https://createpoint.qti.qualcomm.com

RPM PMIC Software Driver Overview: Qualcomm Technologies, Inc

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RPM PMIC Software Driver Overview: Qualcomm Technologies, Inc

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RPM PMIC Software Driver Overview

Qualcomm Technologies, Inc.

Confidential and Proprietary – Qualcomm Technologies, Inc.

Restricted Distribution: Not to be distributed to anyone who is not an employee of either

Revision Date Description

A April 2014 Initial release

B September 2015 Updated slides 21, 23-28, 32, and 37-38

 In the Resource Power Manager

 Application processor (apps

 PMIC drivers – Accessible from RPM

Railway driver Sleep Watchdog

CLK LDO SMPS Boost VS Other (RTC, PON, etc.)

 Customer header files

 Customer header file

 Customer header files

 Customer header file – None

 Customer header file

 Customer header file

 Customer header file

 Low-level driver for SMPS, LDO, and VS drivers; communication and

 A node can have one or several resources, depending on the number of

 RPM INIT client

 PAM table has information about settings, e.g., voltage of PMIC

 This file contains customizable, target-specific driver settings, and PMIC

 SMPS configuration – The upper limit of the programmable range of

 Source file – Pm_app_led.c

 It is recommended that PMIC sleep and wake-up sequences are

 sleep_enter_info[] and sleep_exit_info[] for MSM8x10 – Example

 NPA framework is built into the Core Board Software/Support Package

 Railway driver controls

Qualcomm Technologies, Inc.

Adaptive Voltage Scaling (AVS) Application Note 80-N8715-14

PM8841 and PM8941 Power Management Design Guidelines 80-NA555-5

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