Digital System Design

Chapter 3
Describing Logic Circuits
Thái Truyển Đại Chấn
 Introduction
• Boolean algebra  mathematic tool
• Truth tables  data organization tools
• Schematic symbols  drawing tools
• Timing diagrams  graphing tools
• Language  universal description tool
 Boolean Constants and Variables
• Boolean variable:
• 0 or 1
• Not represent actual number
• Logic level
• Use letter symbols to represent, e.g., A
• 3 basic logic operations: OR, AND, NOT
 Truth Tables

x= -(A*B) + A*-B

The number of input combinations will equal 2N for an N-input truth table
OR
 OR
• Example
 OR
• Example
• Determine the OR gate output for 2 inputs
• Determine the OR gate output for 3 inputs
AND
 AND

Control

Inhibit condition Enable condition

Does not allow Allow
 NOT
bù
• NOT operation = inversion = complementation
• NOT circuit = inverter

bubble
 NOT
• Application
Summary of OR, AND, and NOT
 Summary of OR, AND, and NOT
• Example
• Derive the truth table for this circuit

A
D
B
C

• Draw the timing diagram of D for given timing diagrams of

A, B, C
Describing Logic Circuits Algebraically
Implementing Circuits from Boolean Expressions
 NOR Gates and NAND Gates
• NOR Gate
 NOR Gates and NAND Gates
• NAND Gate
Boolean Theorems
Boolean Theorems
 Boolean Theorems
• Exercises: simplify
• 𝐴(𝐴 + 𝐴𝐵)
• 𝐴𝐶 + 𝐴𝐵𝐶 + 𝐴𝐶 + 𝐴𝐵𝐶
• 𝐴 + 𝐶 𝐴𝐷 + 𝐴𝐷 + 𝐴𝐶 + 𝐶
• 𝐴 𝐴 + 𝐵 + 𝐵 + 𝐴 (𝐴 + 𝐵)
 Boolean Theorems
• Exercises: simplify
• 𝐴(𝐴 + 𝐴𝐵) = A
• 𝐴𝐶 + 𝐴𝐵𝐶 + 𝐴𝐶 + 𝐴𝐵𝐶 = 𝐴 + 𝐵
• 𝐴 + 𝐶 𝐴𝐷 + 𝐴𝐷 + 𝐴𝐶 + 𝐶 = 𝐴 + 𝐶
• 𝐴 𝐴 + 𝐵 + 𝐵 + 𝐴 (𝐴 + 𝐵) = 𝐴 + 𝐵
 Boolean Theorems
• Proving a Boolean equation
• Deriving using theorems
• Using truth tables
• (Different from general algebra, only limited
values/combination in Boolean algebra)
• Using your reasoning
 DeMorgan’s Theorems

• Example

• Extended to more than 2 variables

 DeMorgan’s Theorems
• Example
• Transmit a packet of n bits from a transmitter to a
receiver.
• The packet is in error when 1 bit is in error.
• The bit error rate (BER) is b.
• a. Using DeMorgan’s calculate the packet error rate (PER).
• b.
• Calculate PER when b = 10-5, n = 1000.
• Prove that PER = 1 – (1 – b)n ≈ bn when b is small and n is large
 DeMorgan’s Theorems
• Equivalent circuits
 DeMorgan’s Theorems
• Equivalent circuits
bubble

simplify the converter with the bubble

 Universality of NAND Gates and NOR Gates
Can use this as reference

• Any expression can be implemented using AND, OR, and NOT.

• NAND gates can be used to implement any Boolean function
 Universality of NAND Gates and NOR Gates
• NOR gates can be used to implement any Boolean function
 Universality of NAND Gates and NOR Gates
• Example: Conveyor belt
• A = the belt speed is too fast
• B = the end of the belt is full
• C = the belt tension is too high
• D = the manual override if off
• x = AB + CD
 Universality of NAND Gates and NOR Gates
• ICs available for Example
• Quad NAND gate
 Universality of NAND Gates and NOR Gates

2 gates from 74LS08 and 1 gate from 74LS32.
The number in () at inputs and outputs are
ICs' pin numbers.
after eliminating double inversions
N If we put the NOR gate to the NAND gate
NOR we have ( NAND= NOR+ AND) => we have
2 NOR connect to each other
=> NOR+ NOR = AND gate
 Alternate Logic-Gate Representations
Standard symbols Alternate symbols
Same physical circuit

Non-converting gates

Converting gates
 Alternate Logic-Gate Representations
• Active logic levels
• Active-HIGH: no bubble on
• Active-LOW: bubble on
• Example: NAND gate
• Standard

The output is active only when all

inputs are active
• Alternate

The output is active whenever any input is

active
 Which Gate Representation to Use
Alternate 1

Alternate 2

Standard
 Which Gate Representation to Use
• Output Z will go HIGH whenever either A
= B = 1 or C = D = 1. Alternate 1

• Output Z will go LOW only when A or B is

LOW and C or D is LOW Alternate 2

• Depends on particular function

• Both states are active
 Which Gate Representation to Use
Alternate 1
• Whenever possible, choose gate
symbols so that
Bubble outputs are connected to
bubble inputs, and non-bubble outputs
to non-bubble inputs Alternate 2
 Which Gate Representation to Use
• Example: E has an active LOW. Modify the circuit to represent more
effectively
A
E
B
C
D
A
E
B
C
D
 Which Gate Representation to Use
• Example: to activate the memory ICs in a microcomputer

read
Which Gate Representation to Use
 Which Gate Representation to Use
• Asserted levels

• Labeling active-LOW logic signals

• Labeling bistate signals

 IEEE/ANSI Standard Logic Symbols
• IEEE
• Institute of Electrical and Electronics Engineers
• The world's largest association of technical professionals
• Electrical and electronic engineering, telecommunications, computer
engineering and allied disciplines
• ANSI
• American National Standards Institute
• Oversees the development of voluntary consensus standards
• For products, services, processes, systems, and personnel in the United
States
IEEE/ANSI Standard Logic Symbols
 Hardware Description Languages (HDLs)
• Very high speed integrated circuit (VHSIC) hardware
description language (VHDL)
• By the Department of Defense in the early 1980s
• Primary high-level HDL for designing and implementing digital
circuits
• Altera hardware description language (AHDL)
• By the Altera Corporation
• Programmable logic devices (PLDs)
• Not intended to be used as a universal language for describing any
logic circuit
• Other HDLs
 Implementing Logic Circuits with PLDs
• Programmable logic devices (PLDs) 
implement many digital circuits
• Different from microcomputers/microcontrollers
• Which “run” the program of instructions
• Internal circuits are “wired” electronically to form a
logic circuit by
• Connected
• Not connected
Implementing Logic Circuits with PLDs
 Implementing Logic Circuits with PLDs
• HLDs provide a concise and convenient way
• To describe the operation of the circuit
• Compiler in the computer translates
• From HDL  grid of 1s and 0s  load into the PLD
 HDL Format and Syntax
• The basic format involves two elements:
• What goes into it and what comes out of it
• How the outputs respond to the inputs
 HDL Format and Syntax
• Mode: defines whether it is input, output, or both
• Type: refers to the number of bits, e.g.,
• Single bit: 0 or 1
• Four-bit binary number from a keypad: 00002-11112
 HDL Format and Syntax
• Boolean description using VHDL

• Concurrent assignment statement

• All statements are evaluated constantly and concurrently
 Intermediate Signals
• Neither inputs or outputs
• Schematic diagram: test points/nodes
• HDL: buried nodes/local signals
 Intermediate Signals
• VHDL local signals