DXT Plug-In Unit Descriptions: DN0420278 Issue 1-3

Nokia
DXT Plug-in Unit Descriptions
SW128B
DN0420278
Issue 1-3
SW128B
The information in this document applies solely to the hardware/software product (“Product”) specified
herein, and only as specified herein. Reference to “Nokia” later in this document shall mean the respective
company within Nokia Group of Companies with whom you have entered into the Agreement (as defined
below).
This document is intended for use by Nokia's customers (“You”) only, and it may not be used except for the
purposes defined in the agreement between You and Nokia (“Agreement”) under which this document is
distributed. No part of this document may be used, copied, reproduced, modified or transmitted in any form
or means without the prior written permission of Nokia. If You have not entered into an Agreement
applicable to the Product, or if that Agreement has expired or has been terminated, You may not use this
document in any manner and You are obliged to return it to Nokia and destroy or delete any copies thereof.
The document has been prepared to be used by professional and properly trained personnel, and You
assume full responsibility when using it. Nokia welcomes your comments as part of the process of
continuous development and improvement of the documentation.
This document and its contents are provided as a convenience to You. Any information or statements
concerning the suitability, capacity, fitness for purpose or performance of the Product are given solely on
an “as is” and “as available” basis in this document, and Nokia reserves the right to change any such
information and statements without notice. Nokia has made all reasonable efforts to ensure that the
content of this document is adequate and free of material errors and omissions, and Nokia will correct
errors that You identify in this document. Nokia's total liability for any errors in the document is strictly
limited to the correction of such error(s). Nokia does not warrant that the use of the software in the Product
will be uninterrupted or error-free.
NO WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO
ANY WARRANTY OF AVAILABILITY, ACCURACY, RELIABILITY, TITLE, NON-INFRINGEMENT,
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, IS MADE IN RELATION TO THE
CONTENT OF THIS DOCUMENT. IN NO EVENT WILL NOKIA BE LIABLE FOR ANY DAMAGES,
INCLUDING BUT NOT LIMITED TO SPECIAL, DIRECT, INDIRECT, INCIDENTAL OR CONSEQUENTIAL
OR ANY LOSSES, SUCH AS BUT NOT LIMITED TO LOSS OF PROFIT, REVENUE, BUSINESS
INTERRUPTION, BUSINESS OPPORTUNITY OR DATA THAT MAY ARISE FROM THE USE OF THIS
DOCUMENT OR THE INFORMATION IN IT, EVEN IN THE CASE OF ERRORS IN OR OMISSIONS
FROM THIS DOCUMENT OR ITS CONTENT.
This document is Nokia proprietary and confidential information, which may not be distributed or disclosed
to any third parties without the prior written consent of Nokia.
Nokia is a registered trademark of Nokia Corporation. Other product names mentioned in this document
may be trademarks of their respective owners.
Copyright © 2016 Nokia. All rights reserved.
f Important Notice on Product Safety

This product may present safety risks due to laser, electricity, heat, and other sources of danger.
Only trained and qualified personnel may install, operate, maintain or otherwise handle this
product and only after having carefully read the safety information applicable to this product.
The safety information is provided in the Safety Information section in the “Legal, Safety and
Environmental Information” part of this document or documentation set.
Nokia is continually striving to reduce the adverse environmental effects of its products and services. We
would like to encourage you as our customers and users to join us in working towards a cleaner, safer
environment. Please recycle product packaging and follow the recommendations for power use and proper
disposal of our products and their components.
If you should have questions regarding our Environmental Policy or any of the environmental services we
offer, please contact us at Nokia for any additional information.
2 © 2016 Nokia DN0420278 Issue: 1-3

SW128B
Table of Contents
This document has 36 pages
1 Summary of changes .................................................................... 6

1.1 Changes between issues 1-3 and 1-2............................................6
1.4 Changes for issue 1-0.................................................................... 6
2 SW128B overview..........................................................................7
3 Capacity of SW128B...................................................................... 9
4 Structure of SW128B................................................................... 10
4.1 Mechanical structure.................................................................... 10
4.2 Logical structure...........................................................................10
4.2.1 Incoming serial buses...................................................................11
4.2.2 Outgoing serial buses...................................................................11
4.2.3 Branching interface.......................................................................11
4.2.4 Control bus interface.................................................................... 12
4.2.5 PCM IF FPGA.............................................................................. 12
4.2.6 Incoming data bus IF FPGA.........................................................15
4.2.7 SW1A ASIC 0 and SW1A ASIC 1................................................ 15
4.2.8 Configuration interface of the FPGAs.......................................... 16
4.2.9 Clocks.......................................................................................... 16
4.2.10 Power........................................................................................... 16
4.3 Interfaces of SW128B.................................................................. 16
4.4 Start-up and reset........................................................................ 20
5 Operation of SW128B.................................................................. 21
6 Power consumption of SW128B.................................................. 23
7 SW128B C108487....................................................................... 24
8 Connector maps of SW128B........................................................29

8.1 Backplane connectors..................................................................29
DN0420278 Issue: 1-3 © 2016 Nokia 3

SW128B
List of Figures
Figure 1 Operating environment of the SW128B in the GSW1KB (maximum
equipping).............................................................................................8
Figure 2 Block diagram of the SW128B............................................................ 11
Figure 3 The external interfaces of the SW128B..............................................17
Figure 4 A symmetrical current-controlled interface......................................... 18
Figure 5 The principle of the Control bus interface...........................................19
Figure 6 The front panel of the SW128B.......................................................... 21
Figure 7 Connectors, micro switch and settings of the SW128B......................24
4 © 2016 Nokia DN0420278 Issue: 1-3

SW128B
List of Tables
Table 1 4M/8M mode selection....................................................................... 12
Table 2 Description of interface signals...........................................................17
Table 3 PCM mode settings on SW128B (S2)................................................ 24
Table 4 Switches and their function in micro switch package S3.................... 25
Table 5 Setting the ICC codes on SW128B (S3).............................................25
Table 6 PCM mode settings on SW128B (S2) in BSC3i................................. 26
Table 7 Pin descriptions.................................................................................. 29
Table 8 Connector J5 B(22) type female.........................................................30
Table 9 Connector J4 AB(25) type female...................................................... 31
Table 12 Connector J1 AB(25) type female...................................................... 35
DN0420278 Issue: 1-3 © 2016 Nokia 5

Summary of changes SW128B
1 Summary of changes
Changes between document issues are cumulative. Therefore, the latest document
issue contains all changes made to previous issues.
1.1 Changes between issues 1-3 and 1-2

Hotlink information removed.

In Section SW128B C108487 has been updated to include BSC3i specific settings.

In Section SW128B C108487, a new table has been added to indicate the settings of the
Interchangeability code (ICC code).
1.4 Changes for issue 1-0

This is the first issue of SW128B.
6 © 2016 Nokia DN0420278 Issue: 1-3

SW128B SW128B overview
2 SW128B overview
Main functions of SW128B
The Switching network for 128 PCMs (SW128B plug-in unit) is the core of the Group
Switch (GSW1KB). The GSW1KB is a congestion-free, full-availability single-step
switching network based on time-space architecture. It consists of a maximum of eight
SW128B plug-in units with a combined capacity of 1024 PCM lines. A maximum-sized
GSW1KB switching network can be equipped in a single SW10C-A or SW10C cartridge.
The GSW1KB switches 8 kbit/s channels but supports also switching of channels that
consist of more broadband 8 kbits/s sequential channels.
The SW128B plug-in unit supports not only the current 4 Mbit/s serial bus connections
but also 8Mbit/s serial bus connections thus decreasing the number of PCM cables
needed in the network.
Operating environment
The operation of the GSW1KB is controlled by the switch processor unit SWCOP-A or
SWCOP-S. The SWCOP-A or SWCOP-S is connected to Host CPU unit using
CompactPCI or DMC bus. The maximum length of the control bus is 10 meters.
The SW128B receives the basic timing signals (16M, 8k) distributed by the SWCOP-A or
SWCOP-S, supervises them and initiates an alarm to the SWCOP-A or SWCOP-S in the
event of failure, and turns on the red LED indicator on the front panel.
The SWCOP-A or SWCOP-S can start the sending of the through-connection test to the
input direction channel for one SW128B at a time, and branch the output direction serial
bus to receive the data. For the comparison test, the SWCOP-A or SWCOP-S branches
the input and output direction serial bus from the SW128B.
The figure below presents the GSW1KB interfaces with the other functional blocks in a
DX 200 network element or exchange.
DN0420278 Issue: 1-3 © 2016 Nokia 7

SW128B overview SW128B
Figure 1 Operating environment of the SW128B in the GSW1KB (maximum

equipping)
Controlbus0 32x8Mbit/s serial interface OR

SWCOP SW128B 32x4Mbit/s,16x8MBit/s serial interfaces OR
64x4Mbit/sserialinterface
-S/A Controlbus1 1
cPCI/DMCBUS
32x8Mbit/s serial interface OR

SW128B 32x4Mbit/s,16x8MBit/s serial interfaces OR
Incoming
databus
2
CLITG
3

CP 64x4Mbit/sserialinterface
4
Controlbus: 32x8Mbit/s serial interface OR

AD7:0,PAR 64x4Mbit/sserialinterface
CLK8K,CLK16M 5
PCMTC,PCMRC
PWALP,_PWTST,
CGS 32x8Mbit/s serial interface OR
6

7

8
dn0498178
For more information on capacity, structure, operation, power consumption, jumper

settings, and connector maps, see Capacity of SW128B, Structure of SW128B,
Operation of SW128B, Power consumption of SW128B, SW128B C108487, and
Connector maps of SW128B.
8 © 2016 Nokia DN0420278 Issue: 1-3

SW128B Capacity of SW128B
3 Capacity of SW128B
The SW128B has 64 serial bus interfaces with total capacity of 128 bidirectional 2.048
Mbit/s internal PCM lines, that is, twice the capacity of the SW64B.
The capacity of one internal 2M PCM line is 256 time-division multiplexed 8 kbit/s
channels, yielding a maximum capacity of 65536 channels for one SW128B.
Internal serial bus interfaces
The capacity of the internal serial bus interfaces can selected from the following
alternatives:
• Up to 64 internal 4.096Mbit/s serial bus interfaces, or

• Up to 32 internal 4.096Mbit/s serial bus interfaces and up to 16 internal 8.192Mbit/s
serial bus interfaces, or
• Up to 32 internal 8.192Mbit/s serial bus interfaces.
DN0420278 Issue: 1-3 © 2016 Nokia 9

Structure of SW128B SW128B
4 Structure of SW128B
4.1 Mechanical structure

The PWB dimensions of the SW128B are 220 mm x 233.4 mm. The front panel of the
SW128B is a M98 mechanics compatible front panel. There are two LED indicators
(green one and a red one) in the front panel. The SW128B connects to the backplane
with five Hard Metric connectors (J5, J4, J3, J2 and J1).
4.2 Logical structure

The SW128B consist of the following logical blocks:
• Incoming serial buses

• Outgoing serial buses
• Test Interface
• Control Bus Interface
• PCM IF FPGA
• Incoming data bus IF FPGA
• SW1A ASIC 0 and SW1A ASIC 1 (reserved for future use)
• Configuration interface of the FPGAs
• Clocks
• Power.
The figure below presents the block diagram of the SW128B.
10 © 2016 Nokia DN0420278 Issue: 1-3

SW128B Structure of SW128B
Figure 2 Block diagram of the SW128B

UA3 16MfromSWCOP-A/S
32M
8K 8KfromSWCOP-A/S
SWCOP-A/S CLOCKS
-5V 16M 8Ktoslots0...15
+5V SCBUS PCMRC PCMTC 32Mtoslots0...15
-48V POWER 3.3V 32M 16
2.5V 66M 32MfromSW128Bslot0
1.8V CONTROL BUS BRANCHING 98M
INTERFACE INTERFACE
INCOMING OUTGOING
4M/8MSERIAL BUSES 4M/8MSERIAL BUSES
64bit
0 SCBUS PCMRC PCMTC 0
64bit 4Mbit/s
SERIAL SERIAL
4Mbit/s 8Mbit/s
BUSES BUSES
8Mbit/s TxSERIAL BUSIF
INPUT OUTPUT
INTERFACE RxSERIAL BUSIF INTERFACE
63 63
PCMIF
FPGA
DIN1DIN0 DA AD DOUT
8bit/32MHz
8bit/32MHz 8bit/32MHz 11bit/32MHz
Configuration
IFofthe 15bit/32MHz
FPGAs
18bit/32MHz
DOUT DA AD DOUT DA AD DIN 8bit/32MHz

0 LVTTL
SW1A SW1A INCOMING
ASIC ASIC DATA BUS
1 0 IFFPGA
DIN DIN DOUT0 DOUT115 LVTTL
8bit/32MHz
64bit/32MHz
64bit/32MHz
DN0498181
4.2.1 Incoming serial buses

The SW128B has 64 internal serial bus interfaces with total capacity of 128 PCM lines.
The MAX9201E type comparator is used in the serial bus interface as a line receiver. It
converts the incoming serial data in the differential signal to a single-end TTL signal,
which is taken to the FPGA chip. There are termination resistors in the SW128B unit.
4.2.2 Outgoing serial buses

The SW128B has 64 internal serial bus interfaces with total capacity of 128 PCM lines.
The 26LV31 type differential line driver is used in the serial bus interface as a line
transmitter. It converts the incoming serial data in the single-end TTL signal to a
differential signal, which is taken to the back connector. There are serial resistors in the
SW128B unit.
4.2.3 Branching interface

The SW128B has two internal 2Mbit/s serial bus interfaces for branching. The 26LV31
type differential line driver is used in the branching interface as a line transmitter. It
converts the incoming serial data in the single-end TTL signal to a differential signal,
which is taken to the back connector. There are serial resistors in the SW128B unit.
DN0420278 Issue: 1-3 © 2016 Nokia 11

4.2.4 Control bus interface

The control bus interface is a symmetrical voltage-controlled bi-directional parallel bus
interface. It includes the multiplexed address and data bus (CAD0...CAD7), the parity bit
(CPAR), the address latch enable signal (CALE), the write signal (_CWR) and the read
signal (_CRD). Differential line driver and comparator type receivers are used in the
control bus interface.
4.2.5 PCM IF FPGA

The device used as the PCM IF FPGA is Xilinx XC2S300E in PBGA456 package. The
PCM IF FPGA consist of following logical blocks:
• Incoming data path block (4M serial bus interface, 8M serial bus interface,
Multiplexer, test data generator, PCMRC IF)
• Outgoing data path block (4M serial bus interface, 8M serial bus interface,
Multiplexer)
• Control bus interface block.
Incoming data path block: 4M serial bus interface
Up to 64 incoming 4M serial buses (R0...R63) can be connected to the SW128B plug-in
unit. The 4M internal serial interface is a 4.096 Mbit/s serial bus with two 2.048 Mbit/s
PCM circuits multiplexed together by bit-interleaving.
The Rx 4Mbit/s IF block multiplexes the data of its incoming 4M serial buses into eight
32.768 Mbit/s signals with eight 4M serial buses multiplexed into one 32.768 Mbit/s
signal by byte interleaving.
Incoming data path block: 8M serial bus interface
Up to 32 incoming 8M serial buses (R0...R15, R32…R63) can be connected to the
SW128B plug-in unit. The 8M internal serial bus interface is an 8.192 Mbit/s serial bus
with four 2.048 Mbit/s PCM circuits multiplexed together by byte-interleaving.
The Rx 8Mbit/s IF block multiplexes the data of its incoming 8M serial buses into eight
32.768 Mbit/s signals with four 8M serial buses multiplexed into one 32.768 Mbit/s signal
by byte interleaving.
Incoming data path block: Multiplexer
The Multiplexer block connects data from incoming serial buses to the data out port.
Connections are made according the tables below.
Table 1 4M/8M mode selection.
4M/8M bit 1 4M/8M bit 0
4M 4M R0...R64 → PCM0...PCM127
4M 8M R0...R16 → PCM0...PCM63;
R32...R63 → PCM64...PCM127
12 © 2016 Nokia DN0420278 Issue: 1-3

Table 1 4M/8M mode selection. (Cont.)
4M/8M bit 1 4M/8M bit 0
8M 4M R0...R31 → PCM0...PCM63;
R32...R47 → PCM64...PCM127
8M 8M R0...R16 → PCM0...PCM63;
R32...R47 → PCM64...PCM127
Incoming data path block: test data generator

In the through-connection test, the SWCOP-A or SWCOP-S starts the transmission of
test data. Test data is an 8-bit string that is sent to the N x 8 kbit/s channel of the input
direction in place of the data coming from the serial buses. The sending of test data is
started with an I/O operation of the SWCOP-A or SWCOP-S: the test string and the
number of the 8 kbit/s channels (N= 1…256) are given first and then the channel is
chosen by two operations. Seven bits are used to indicate the serial bus for the input
direction and eight bits to indicate the input direction channel. After that, the test is
activated by write operation into the Test Data Control register. The transmission begins
in the next frame following the last operation.
Continuous transmission is also available in which an 8-bit string is sent until the
transmission is cancelled.
Incoming data path block: PCMRC IF
The branching logic is used in the comparison test. The branching logic allows the
branching of one incoming 2Mbit/s PCM line data to the branching interface. The
branching logic works in the following way: the data of one 2Mbit/s PCM line is written in
the dualport memory one frame at a time, and the data is branched from the memory
only after the entire frame has been written in it. Therefore, enough memory for two
frames is needed; one memory block is used to read the data of the previous frame while
the second memory block is used to write data to the next frame. The size of the
required dual-port memory is 2 x 32 x 8 bits.
For the comparison test, the SWCOP-A or SWCOP-S branches one incoming internal
2Mbit/s PCM line to the SWCOP-A or SWCOP-S. The branching is done by an I/O
operation of the SWCOP-A or SWCOP-S: the input PCM is chosen by one operation.
Seven bits are used to indicate the internal 2Mbit/s PCM line, and after that the
branching is activated by write operation into the Test Data Control register.
When the test is completed, the branching must be released with a separate I/O
operation.
The branching interface is divided into blocks of 512 internal 2 Mbit/s PCM lines, and
only one incoming internal 2Mbit/s PCM line can be branched at a time in the block.
Outgoing data path block: 4M serial bus interface
Up to 64 outgoing 4M serial buses (T0...T63) can be connected to the SW128B plug-in
unit. The internal 4M serial bus interface is a 4.096 Mbit/s serial bus with two 2.048
Mbit/s PCM circuits multiplexed together by bit-interleaving.
The figure below shows a timing diagram of the outgoing 4M serial buses.
DN0420278 Issue: 1-3 © 2016 Nokia 13

TheTx 4Mbit/s IF block demultiplexes data of its incoming eight 32M serial buses into 64
internal 4M serial buses.
Outgoing data path block: 8M serial bus interface
Up to 32 outgoing 8M serial buses (T0...T15, T32…T63) can be connected to the
SW128B plug-in unit. The internal 8M serial buses interface is an 8.192 Mbit/s serial bus
with four 2.048 Mbit/s PCM circuits multiplexed together by byte-interleaving.
The Tx 8Mbit/s IF block demultiplexes data of its incoming eight 32M serial buses into 32
internal 8M serial buses.
Outgoing data path block: Multiplexer
Incoming data bits from SW1A ASICs are selected according the content of the
Multiplexer control memory. The logic of the Control Bus Interface block updates the
content of the Multiplexer control memory when a connection is established. The size of
the required dual-port memory is 4096 times 8 bits.
Outgoing data path block: PCMTC IF
The branching logic is used in comparison and connection tests. The branching logic
allows for branching one outgoing 2Mbit/s PCM line data to the branching interface. The
branching logic works in the following way: the data of one 2Mbit/s PCM line is written in
the dualport memory one frame at a time, and the data is branched from the memory
only after the entire frame has been written in it. Therefore, enough memory for two
frames is needed; one memory block is used to read the data of the previous frame while
the second memory block is used to write data to the next frame. The size of the
required dual-port memory is 2 x 32 x 8 bits.
For the comparison and connection tests, the SWCOP-A or SWCOP-S branches one
outgoing internal 2Mbit/s PCM line to the SWCOP-A or SWCOP-S. The branching is
done by an I/O operation of the SWCOP-A or SWCOP-S: the output PCM line is chosen
by one operation. Seven bits are used to indicate the internal 2Mbit/s PCM line and after
that the branching is activated by write operation into the Test Data Control register.
When the test is completed, the branching must be released with a separate I/O
operation.
Branching interface is divided into blocks of 512 internal 2 Mbit/s PCM lines, and only
one outgoing internal 2Mbit/s PCM line can be branched at a time in that block.
Control bus interface block
The control logic block handles address decoding and starts the task required by each
operation. The control logic also handles parity check of incoming data.
The control bus interface is a symmetrical voltage-controlled bi-directional parallel bus
signal (_CRD).
The SWCOP-A or SWCOP-S reads from and writes into the control memory and
registers of the SW128B plug-in unit via the parallel control bus. The SW128B registers
are located in the I/O space of the SWCOP-A or SWCOP-S.
14 © 2016 Nokia DN0420278 Issue: 1-3

When writing into the control memory, the SWCOP-A or SWCOP-S first writes the output
data of the connection into the address registers, in two parts, and then the input data of
the connection into the data registers, in three parts. The logic of the SW128B updates
the control memory location in question after the last operation. The width of the
connected channel is defined in the N x 8kbit/s Channel register.
When the connection has been established, the SWCOP-A or SWCOP-S can check the
contents of the control memory at any time. This check reading is conducted by first
writing the address of the memory location to be checked into the SW128B registers,
and then by reading the contents of the memory location from the SW128B registers.
The write operations performed by the SWCOP-A or SWCOP-S on the control bus are
supervised with a parity check. If the SW128B detects a parity error in the data, the
writing into the control memory or registers is disabled. If a parity error occurs in the
address, the decoding of the write/read operation in the control memory or registers is
completely disabled. The parity error alarm can be read from the status register. The
alarm is cancelled after a successful status register read operation.
The SWCOP-A or SWCOP-S can test parity alarm logic with an I/O operation by which
the parity is set "wrong", causing a parity alarm from all control bus operations.
4.2.6 Incoming data bus IF FPGA

The SW128B plug-in units are interconnected by incoming data bus. The device used for
Incoming data bus IF (INBUSIF) FPGA is Xilinx XC2S300E in PBGA456 package. The
incoming data bus is a synchronous 32.768MHz, 128 bit data bus, and LVT type I/O
drivers are used.
The incoming data are taken to all SW128B plug-in units (maximum sixteen units) via a
128-bit wide bus. Every SW128B controls its own 8-bit section of the bus. The 4-bit unit
address of the SW128B selects the part of the bus to which the SW128B in question is
connected.
All data from incoming data bus are connected to DOUT0 interface. Data from PCMs
0...1023 are connected to DOUT0 interface.
4.2.7 SW1A ASIC 0 and SW1A ASIC 1

Switching is performed according one stage time-space switching structure by the SW1A
ASIC circuit.
Switching data bus to the SW1A is 32,768 MB/s and the logic level is 2.5V. Control
signals are 3.3V LVCMOS logic level signals.
Incoming parallel data from the incoming data bus are written cyclically to the SW1A's
switching memory.
Outgoing parallel data is controlled by SW1A's control memory. The control memory
gives a read address to the switching memory so that the incoming channels are
connected to the correct outgoing channels.
The SW1A can switch 1024 PCM signals data. It has eight 4k x 8 nine port switching
memory blocks. One port is used for writing and the other eight for reading.
The SW128B has two SW1A ASIC circuits with eight control memories, whose size is 4k
x 18. ASIC 0 handles PCMs 0 to 1023 and ASIC 1 handles PCMs 1024 to 2046
(reserved for future use). The PCM IF FPGA controls the ASIC circuits.
DN0420278 Issue: 1-3 © 2016 Nokia 15

The SW1A ASICs support JTAG boundary scan.
4.2.8 Configuration interface of the FPGAs

The PCM IF FPGA and the incoming data bus IF FPGA are SRAM based FPGAs, which
need to be configured each time the plug-in unit is powered up. FPGAs are configured
from the configuration serial prom memory or by software through the FPGA
Configuration register. The Configuration registers are located in the I/O space of the
SWCOP-A or SWCOP-S. One 2 Mbit configuration serial prom memory is used for both
FPGAs.
4.2.9 Clocks
The SW128B plug-in unit receives the basic timing signals (16M and 8K) from the
SWCOP-A or SWCOP-S. The interface is a symmetrical current-controlled interface.
The SW128B unit also needs the clock signals 32,768 MHz, 65,536 MHz and 98,064
MHz, which are generated by using phase-locked loops. 32,768 MHz is generated from
incoming basic timing signal 16,384 MHz with MC88915 PLL and distributed to the unit
with MPC940L clock distribution buffer. 65,536 MHz and 98,064 MHz signals are
generated and distributed from 32,768 MHz with MPC972 PLL.
The SW128B supervises the basic timing signals by counting the number of pulses in the
32M signal during one cycle of the 8K signal. An alarm is activated, if the number of
pulses is incorrect or if one synchronisation signal is missing.
4.2.10 Power
Incoming voltage of -48V is drawn through backplane connectors. The following
operating voltages needed by the SW128B are converted in the power block:
• ±5V for the line receiver

• +3,3V for the line transmitters, ASICs, and FPGAs
• +2,5V for the ASICs
• +1,8V for the FPGAs.
4.3 Interfaces of SW128B

The external interfaces of the SW128B are presented in the figure below and the signals
are described in the table below.
16 © 2016 Nokia DN0420278 Issue: 1-3

Figure 3 The external interfaces of the SW128B

TIMING 16M R0...R63 4/8Mbit/s
INTERFACE 8K T0...T63 SERIAL BUS INTERFACE
(SWCOP)
INBUS7...0
INBUS15...8
INCOMING
DATA BUS INBUS19...112 UA0..UA3 SETTINGOFUNIT ADDRESS
INTERFACE INBUS27...120
(SW128B) PCMRC BRANCHINGINTERFACE
CLK_32M
CLK_32M0...15 SW128B PCMTC (SWCOP)
TESTRST SETTING SIGNALS

CAD0...CAD7
_PWTST
CONTROL CPAR PWAL ALARMIF(SWCOP)
BUS CALE CCLAL
INTERFACE _CWR
(SWCOP) JTAG
_CRD
-48V
CGS 5V POWERSUPPLY
DN0498193
Table 2 Description of interface signals
Signal Description
16M 16 MHz clock signa
8K 8 kHz clock signal
R0...R63 Receive PCM line signal
T0...T63 Transmit PCM line signal
INBUS0...INBUS127 Incoming data bus
CLK_32M Clock signal
CLK_32M0...CLK_32M15 Clock signals
CAD0...CAD7 Data signals of Control bus
CPAR Parity signal of control bus
CALE Address latch enable signal of Control bus
_CWR Write signal of Control bus
_CRD Read signal of Control bus
CGS Matrix changeover signal
UA0...UA3 Unit address
PCMRC 2Mbit/s serial bus for comparison and

through-connection tests
DN0420278 Issue: 1-3 © 2016 Nokia 17

Table 2 Description of interface signals (Cont.)
Signal Description
PCMTC 2Mbit/s serial bus for comparison testst
TESTRST Test reset
_PWTST Test signal for power alarm
PWAL Power alarm signal
CCLAL Clock or parity alarm signal
JTAG Test interface signal
-48V Power supply
Timing interface
The SWCOP-S or SWCOP-A unit distributes the 16.384 MHz and 8 kHz clock signals to
the SW128B units. The timing interface is a symmetrical current-controlled interface (see
the figure below) and it is connected to the back connector of the plug-in unit.
Figure 4 A symmetrical current-controlled interface

A
IN OUT
B
R R R R
IN A B OUT
DN0174087
The comparator-type receiver (MAX9201E) is used in the interface. 1 kOhm serial

resistors are used in the basic timing signal inputs.
The timing interface does not have termination resistors on the SW128B, because the
termination resistors are in the cartridge at end of the line.
Incoming data bus interface
The SW128B plug-in units are interconnected by incoming data bus. Incoming data bus
is a synchronous 32.768MHz, 128 bit data bus and it is connected to the back connector
of the plug-in unit.
The Incoming data bus requires 10 Ohm serial resistor (stub termination) to every pin of
the connector except to CLK signal.
Control bus interface
The control bus interface is a symmetrical current-controlled bi-directional parallel bus
signal (_CRD). Control bus is connected to the back connector of the plug-in unit.
18 © 2016 Nokia DN0420278 Issue: 1-3

The control bus interface does not have termination resistors on SW128B, because the
termination resistors are in the cartridge at end of the control bus.
The MAX9201E type comparator is used in the control bus interface as a line receiver.
The 26LV31 type differential line driver is used in the control bus interface as a line
transmitter. There are 390 Ohm serial resistors in the differential outputs of the control
bus line-transmitter.
The principle of the Control bus interface is presented in the figure below.
Figure 5 The principle of the Control bus interface
A
CALE,CWR,CRD CALE,CWR,CRD
B
RD_EN
390ohm
EN
CAD7...0_OUT,CPAR_OUT
390ohm
A
CAD7...0,CPAR
CAD7...0_IN,CPAR_IN B
DN0498209
4 and 8Mbit/s serial bus interface
64 internal serial buses are connected to the back plane.
The MAX9201E type comparator is used in the serial bus interface as a line receiver.
There is a 2.2 kOhm pull-up in the A-line of the differential input of serial line-receiver,
and there are 68 Ohm pull-down termination resistors in the differential inputs of serial
line-receiver.
transmitter. There are 390 Ohm serial resistors in the differential outputs of the serial
line-transmitter.
Unit address UA bits
Unit Address (UA) bits are used to indicate the slot number to the SW128B plug-in units.
The UA bits are hardwired in the cartridge.
Branching interface
The branching interfaces (PCMRC, PCMTC) are symmetrical voltage-controlled 2Mbit/s
interfaces.
transmitter.
The branching interface does not have termination resistors on the SW128B, because
the termination resistors are in the cartridge at end of the bus.
Alarm interface
DN0420278 Issue: 1-3 © 2016 Nokia 19

The power alarm signal (PWAL) is an open-collector type signal. It is activated, if the
supply voltages drop below specified level. It is possible to test power alarm interface by
activating the _PWTST signal.
Clock alarm signal (CCLAL) is an open-collector type signal. It is activated, if a clock
error or parity error is detected. It is possible to test power alarm interface by writing into
the Status register.
JTAG test interface
There is one TAP chain on the SW128B. The JTAG interface is buffered in the SW128B
unit, and signal lines are terminated both before and after buffering. There are AC
terminations in the connector side of the buffers and AC or series terminations in the unit
side. The termination in the unit side is important for TMS and TCK signals. TDI/TDO
signals are buffered by the chain and do not need termination. The TMS and TCK
signals go through every pin without branches. There is a 10 kOhm pull-up in each TDI-
input.
The TAP goes to FPGAs and SW1A ASICs. The JTAG interface is connected to the
PWB with 2 x 4 and 2 x 6 pin headers.
4.4 Start-up and reset

Start-up
The PCM IF FPGA and the Incoming data bus IF FPGA are SRAM based FPGAs, which
need to be configured each time the plug-in unit has been powered up. The FPGAs can
be configured by software through the FPGA Configuration register.
The Configuration registers are located in the I/O space of the SWCOP-A or SWCOP-S.
Reset
The SW128 is reset either because of power-up reset or because of software reset.
In case of power up, all devices are reset. During the power up, the reset logic
guarantees that the RESET signals remain active long enough to ensure that the power
supply is stable the time required by the logic.
SW128B is restarted by software through the FPGA Configuration register. The FPGA
Configuration register is located in the I/O space of the SWCOP-A or SWCOP-S. After
the power up reset, the plug-in unit is in reset state.
20 © 2016 Nokia DN0420278 Issue: 1-3

SW128B Operation of SW128B
5 Operation of SW128B
The front panel of the SW128B is a M98 mechanics compatible front panel. There are
two LED indicators in the front panel; see the figure below.
Figure 6 The front panel of the SW128B
OPR
DN0498212
LED indicators
The front panel of the SW128B plug-in unit contains two LED indicators, a green one and
a red one. The green LED is controlled by software green and it indicates the active
matrix half; the red LED indicates an alarm which is activated, if the alarm (CCLAL)
signal of the SW128B is active.
Backplane connectors
The SW128B is connected to backplane with five 5-row EMC shielded female Hard
Metric connectors, that is, with pressfit connectors J5, J4, J3, J2 and J1:
• 22-pin B-type female connector (connector J5)

• 25-pin AB-type female connector (connector J4)
• 19-pin B-type female connector (connector J3)
• 22-pin B-type female connectors (connector J2)
• 25-pin AB-type female connector (connector J1).
DN0420278 Issue: 1-3 © 2016 Nokia 21

Operation of SW128B SW128B
Connectors J1 and J2 are used to interface unit to the incoming data bus; connector J2
is used to interface unit to the control bus, and connectors J3, J4 and J5 are used to
interface internal serial buses to other units. The -48V operating voltage is connected
through connector J4.
For the connector maps, see Connector maps of SW128B.
22 © 2016 Nokia DN0420278 Issue: 1-3

SW128B Power consumption of SW128B
6 Power consumption of SW128B

The power consumption of the SW128B is less than 13 W. The estimated power
consumption presented in the table below.
Operational voltage Current Power
+3.3V 1.7A 5.61W
±5V 0.5A 2.5W
+2.5V 1.5 A 3.75W
+1.8V 1A 1.8W
DN0420278 Issue: 1-3 © 2016 Nokia 23

SW128B C108487 SW128B
7 SW128B C108487
Figure 7 Connectors, micro switch and settings of the SW128B
J5
J4
S1 S2 S3
J3
8 7 6 5
ON
J2
OFF
1 2 3 4
J1
DN0498224
The SW128B has three micro switch packages containing four switches each. The
switches are used for setting PCM mode and Interchangeability code.
PCM mode settings (S2)
The PCM mode set up is made with micro switches as follows:
• 4M/8M mode for serial buses R0...R31, T0...T31

Table 3 PCM mode settings on SW128B (S2).
Switch Default Function

setting
1-8 OFF (4M) 4M/8M mode for PCM circuits 0...63

OFF: 4M mode selected - PCM circuits 0...63 are
connected through R0...R31, T0...T31 serial buses
ON: 8M mode selected - PCM circuits 0...63 are
2-7 OFF (4M) 4M/8M mode for PCM circuits 64...127

OFF: 4M mode selected - PCM circuits 64...127 are
24 © 2016 Nokia DN0420278 Issue: 1-3

SW128B SW128B C108487
Table 3 PCM mode settings on SW128B (S2). (Cont.)

setting
ON: 8M mode selected - PCM circuits 64...127 are

3-6 Reserved
4-5 Reserved
Interchangeability code settings (S3)

The setting of the interchangeability code (ICC code) is presented in the tables below.
Table 4 Switches and their function in micro switch package S3.

setting
1-8 OFF Interchangeability code bit 3
The first interchangeability code A corresponds to all switches OFF. After that, the
settings start to roll for each interchangeability code change as shown in the table below.
Table 5 Setting the ICC codes on SW128B (S3).
ICC code Setting
1-8 2-7 3-6 4-5
A OFF OFF OFF OFF
B ON OFF OFF OFF
C OFF ON OFF OFF
D ON ON OFF OFF
E OFF OFF ON OFF
F ON OFF ON OFF
DN0420278 Issue: 1-3 © 2016 Nokia 25

SW128B C108487 SW128B
Table 5 Setting the ICC codes on SW128B (S3). (Cont.)
ICC code Setting
G OFF ON ON OFF
H ON ON ON OFF
J OFF OFF OFF ON
K ON OFF OFF ON
L OFF ON OFF ON
M ON ON OFF ON
N OFF OFF ON ON
P ON OFF ON ON
R OFF ON ON ON
g Note: The use of letters I, O and Q as ICC codes is not allowed.
SW128B jumper settings in BSC3i

The following information is specifically for BSC3i network elements.
PCM mode settings (S2)
The PCM mode set up is made with micro switches as follows:

Table 6 PCM mode settings on SW128B (S2) in BSC3i.
Slot Switch Default

setting
F 01 1-8 OFF (4M) 4M/8M mode for internal PCM

circuits 0...63
OFF: 4M mode selected - PCM
circuits 0...63 are connected
through R0...R31, T0...T31
serial buses
F 01 2-7 OFF (4M) 4M/8M mode for external PCM

circuits 64...127
26 © 2016 Nokia DN0420278 Issue: 1-3

SW128B SW128B C108487
Table 6 PCM mode settings on SW128B (S2) in BSC3i. (Cont.)
Slot Switch Default

setting

through R32...R63, T32...T63
serial buses
F 02 1-8 OFF (4M) 4M/8M mode for internal PCM

circuits 0...63
serial buses
F 02 2–7 OFF (4M) 4M/8M mode for external PCM

circuits 64...127
through R32...R63, T32...T63
serial buses
F 03 1-8 OFF (4M with 4M/8M mode for internal PCM

ET2 PIUs) / circuits 0...63
ON (8M with OFF: 4M mode selected - PCM
ET4 PIUs circuits 0...63 are connected
serial buses
ON: 8M mode selected - PCM
serial buses
F 03 2-7 OFF (4M with 4M/8M mode for external PCM

through R32...R63, T32...T63
serial buses
through R32...R47, T32...T47
serial buses
F 04 1-8 OFF (4M with 4M/8M mode for internal PCM

serial buses
DN0420278 Issue: 1-3 © 2016 Nokia 27

SW128B C108487 SW128B
Table 6 PCM mode settings on SW128B (S2) in BSC3i. (Cont.)
Slot Switch Default

setting

serial buses
F 04 2-7 OFF (4M with 4M/8M mode for external PCM

through R32...R63, T32...T63
serial buses
through R32...R47, T32...T47
serial buses
28 © 2016 Nokia DN0420278 Issue: 1-3

SW128B Connector maps of SW128B
8 Connector maps of SW128B

The SW128B has five backplane connectors. The connector maps are presented in the
section below.
8.1 Backplane connectors

The table below presents the pin descriptions of the backplane connectors.
Table 7 Pin descriptions.
Pin Decription
R00x...R63x Differential, Receive PCM line signal
T00x...T63x Differential, Transmit PCM line signal
16M0x Differential, 16 MHz clock signal
8k0x Differential, 8 kHz clock signal
CAD7x…CAD0x Differential, data signals of Control bus
CALEx Differential, address latch enable signal of

Control bus
CWRx Differential, write signal of Control bus
CRDx Differential, read signal of Control bus
CGS Matrix changeover signal
_PWTST Test signal for power alarm
PWAL Power alarm signal
CCLAL Clock/parity alarm signal
PCMTCx Differential, 2Mbit/s serial bus for comparison

and through-connection tests
PCMRCx Differential, 2Mbit/s serial bus for comparison

tests
CLK32M15…CLK32M0 32.768 MHz clock signal of Incoming data

bus; output from slot 01
CLK32M_IN 32.768 MHz clock signal of Incoming data bus

input
DN0420278 Issue: 1-3 © 2016 Nokia 29

Connector maps of SW128B SW128B
Table 7 Pin descriptions. (Cont.)
Pin Decription
FSP8K_OUT 8KHz frame synchronisation pulse; output

from slot 01
FSP8K_IN 8KHz frame synchronisation pulse; input
UA3…UA0 Unit Address
TESTRST Test reset
INBUS0…INBUS127 Incoming data bus
-UB -48V supply voltage
B0V 0V reference for -48V
Connector J5
Table 8 Connector J5 B(22) type female.
Pin F E D C B A
1 GND T 00 B T 00 A GND R 00 B R 00 A
2 GND T 01 B T 01 A GND R 01 B R 01 A
3 GND T 02 B T 02 A GND R 02 B R 02 A
4 GND T 03 B T 03 A GND R 03 B R 03 A
5 GND T 04 B T 04 A GND R 04 B R 04 A
6 GND T 05 B T 05 A GND R 05 B R 05 A
7 GND T 06 B T 06 A GND R 06 B R 06 A
8 GND T 07 B T 07 A GND R 07 B R 07 A
9 GND T 08 B T 08 A GND R 08 B R 08 A
10 GND T 09 B T 09 A GND R 09 B R 09 A
11 GND T 10 B T 10 A GND R 10 B R 10 A
12 GND T 11 B T 11 A GND R 11 B R 11 A
13 GND T 12 B T 12 A GND R 12 B R 12 A
30 © 2016 Nokia DN0420278 Issue: 1-3

Table 8 Connector J5 B(22) type female. (Cont.)
Pin F E D C B A
14 GND T 13 B T 13 A GND R 13 B R 13 A
15 GND T 14 B T 14 A GND R 14 B R 14 A
16 GND T 15 B T 15 A GND R 15 B R 15 A
17 GND T 16 B T 16 A GND R 16 B R 16 A
18 GND T 17 B T 17 A GND R 17 B R 17 A
19 GND T 18 B T 18 A GND R 18 B R 18 A
20 GND T 19 B T 19 A GND R 19 B R 19 A
21 GND T 20 B T 20 A GND R 20 B R 20 A
22 GND T 21 B T 21 A GND R 21 B R 21 A
Rows 1 to 18 = 4Mbit/s PCM circuits or 8Mbit/s PCM circuits

Rows 19 to 22 = 4Mbit/s PCM circuits
Connector J4
Table 9 Connector J4 AB(25) type female.
Pin F E D C B A
1 GND T 22 B T 22 A GND R 22 B R 22 A
2 GND T 23 B T 23 A GND R 23 B R 23 A
3 GND T 24 B T 24 A GND R 24 B R 24 A
4 GND T 25 B T 25 A GND R 25 B R 25 A
5 GND T 26 B T 26 A GND R 26 B R 26 A
6 GND T 27 B T 27 A GND R 27 B R 27 A
7 GND T 28 B T 28 A GND R 28 B R 28 A
8 GND T 29 B T 29 A GND R 29 B R 29 A
9 GND T 30 B T 30 A GND R 30 B R 30 A
10 GND T 31 B T 31 A GND R 31 B R 31 A
DN0420278 Issue: 1-3 © 2016 Nokia 31

Table 9 Connector J4 AB(25) type female. (Cont.)
Pin F E D C B A
11 GND
12 -UB -UB B0V B0V
13 -UB -UB B0V B0V
14
15 GND T 32 B T 32 A GND R 32 B R 32 A
16 GND T 33 B T 33 A GND R 33 B R 33 A
17 GND T 34 B T 34 A GND R 34 B R 34 A
18 GND T 35 B T 35 A GND R 35 B R 35 A
19 GND T 36 B T 36 A GND R 36 B R 36 A
20 GND T 37 B T 37 A GND R 37 B R 37 A
21 GND T 38 B T 38 A GND R 38 B R 38 A
22 GND T 39 B T 39 A GND R 39 B R 39 A
23 GND T 40 B T 40 A GND R 40 B R 40 A
24 GND T 41 B T 41 A GND R 41 B R 41 A
25 GND T 42 B T 42 A GND R 42 B R 42 A
Rows 1 to 16 = 4Mbit/s PCM circuits

Connector J3
Pin F E D C B A
1 GND T 43 B T 43 A GND R 43 B R 43 A
2 GND T 44 B T 44 A GND R 44 A R 44 A
3 GND T 45 B T 45 A GND R 45 A R 45 A
4 GND T 46 B T 46 A GND R 46 B R 46 A
32 © 2016 Nokia DN0420278 Issue: 1-3

Pin F E D C B A
5 GND T 47 B T 47 A GND R 47 B R 47 A
6 GND T 48 B T 48 A GND R 48 B R 48 A
7 GND T 49 B T 49 A GND R 49 B R 49 A
8 GND T 50 B T 50 A GND R 50 B R 50 A
9 GND T 51 B T 51 A GND R 51 B R 51 A
10 GND T 52 B T 52 A GND R 52 B R 52 A
11 GND T 53 B T 53 A GND R 53 B R 53 A
12 GND T 54 B T 54 A GND R 54 B R 54 A
13 GND T 55 B T 55 A GND R 55 B R 55 A
14 GND T 56 B T 56 A GND R 56 B R 56 A
15 GND T 57 B T 57 A GND R 57 B R 57 A
16 GND T 58 B T 58 A GND R 58 B R 58 A
17 GND T 59 B T 59 A GND R 59 B R 59 A
18 GND T 60 B T 60 A GND R 60 B R 60 A
19 GND T 61 B T 61 A GND R 61 B R 61 A

Rows 9 to 19 = 4 Mbit/s PCM circuits
Connector J2
Pin F E D C B A
1 GND T 62 B T 62 A GND R 62 B R 62 A
2 GND T 63 B T 63 A GND R 63 B R 63 A
3 GND CCLAL PWAL _PWTST CGS
4 GND 16MB 16MA 8kB 8kA
DN0420278 Issue: 1-3 © 2016 Nokia 33

Pin F E D C B A
5 GND CAD1B CAD1A PCMTCA CAD0B CAD0A
6 GND CAD3B CAD3A PCMTCB CAD2B CAD2A
7 GND CAD5B CAD5A PCMRCA CAD4B CAD4A
8 GND CAD7B CAD7A PCMRCB CAD6B CAD6A
9 GND CPARB CPARA CALEB CALEA
10 GND _CRDB _CRDA _CWRB _CWRA
11 GND GND
12 GND GND
13 GND CLK32M0 CLK32M1 GND CLK32M2 CLK32M3
17 GND GND CLK32M_IN FSP8K_OUT FSP8K_IN +5V_OUT
18 GND UA3 UA2 UA1 UA0 TESTRST
19 GND INBUS0 INBUS1 GND INBUS2 INBUS3
20 GND INBUS4 INBUS5 INBUS6 INBUS7 INBUS8
Rows 1 and 2 = 4 Mbit/s PCM circuits

Rows 5 to 8 = Control bus interface
Rows 13 to 17 = Clock signals of incoming data bus, from slot 0
Rows19 to 22 = Incoming data bus
Connector J1
34 © 2016 Nokia DN0420278 Issue: 1-3

Table 12 Connector J1 AB(25) type female.
Pin F E D C B A
12 INBUS67 INBUS68 INBUS69 INBUS70 INBUS71
13 GND INBUS72 GND INBUS73 GND
14 INBUS74 INBUS75 INBUS76 INBUS77 INBUS78
DN0420278 Issue: 1-3 © 2016 Nokia 35

Table 12 Connector J1 AB(25) type female. (Cont.)
Pin F E D C B A
Rows 1 to 25 = Incoming data bus
36 © 2016 Nokia DN0420278 Issue: 1-3

DXT Plug-In Unit Descriptions: DN0420278 Issue 1-3

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

DXT Plug-In Unit Descriptions: DN0420278 Issue 1-3

Uploaded by

Copyright:

Available Formats

Nokia

DXT Plug-in Unit Descriptions

Copyright © 2016 Nokia. All rights reserved.

f Important Notice on Product Safety

2 © 2016 Nokia DN0420278 Issue: 1-3

1 Summary of changes .................................................................... 6

6 Power consumption of SW128B.................................................. 23

8 Connector maps of SW128B........................................................29

DN0420278 Issue: 1-3 © 2016 Nokia 3

4 © 2016 Nokia DN0420278 Issue: 1-3

DN0420278 Issue: 1-3 © 2016 Nokia 5

1.1 Changes between issues 1-3 and 1-2

1.2 Changes between issues 1-2 and 1-1

1.3 Changes between issues 1-1 and 1-0

1.4 Changes for issue 1-0

6 © 2016 Nokia DN0420278 Issue: 1-3

DN0420278 Issue: 1-3 © 2016 Nokia 7

Figure 1 Operating environment of the SW128B in the GSW1KB (maximum

Controlbus0 32x8Mbit/s serial interface OR

32x8Mbit/s serial interface OR

32x8Mbit/s serial interface OR

Controlbus: 32x8Mbit/s serial interface OR

32x8Mbit/s serial interface OR

32x8Mbit/s serial interface OR

For more information on capacity, structure, operation, power consumption, jumper

8 © 2016 Nokia DN0420278 Issue: 1-3

• Up to 64 internal 4.096Mbit/s serial bus interfaces, or

DN0420278 Issue: 1-3 © 2016 Nokia 9

4.1 Mechanical structure

4.2 Logical structure

• Incoming serial buses

The figure below presents the block diagram of the SW128B.

10 © 2016 Nokia DN0420278 Issue: 1-3

Figure 2 Block diagram of the SW128B

8bit/32MHz 8bit/32MHz 11bit/32MHz

DOUT DA AD DOUT DA AD DIN 8bit/32MHz

4.2.1 Incoming serial buses

4.2.2 Outgoing serial buses

4.2.3 Branching interface

DN0420278 Issue: 1-3 © 2016 Nokia 11

4.2.4 Control bus interface

4.2.5 PCM IF FPGA

Table 1 4M/8M mode selection.

4M/8M bit 1 4M/8M bit 0

12 © 2016 Nokia DN0420278 Issue: 1-3

Table 1 4M/8M mode selection. (Cont.)

4M/8M bit 1 4M/8M bit 0

Incoming data path block: test data generator

DN0420278 Issue: 1-3 © 2016 Nokia 13

14 © 2016 Nokia DN0420278 Issue: 1-3

4.2.6 Incoming data bus IF FPGA

4.2.7 SW1A ASIC 0 and SW1A ASIC 1

DN0420278 Issue: 1-3 © 2016 Nokia 15

The SW1A ASICs support JTAG boundary scan.

4.2.8 Configuration interface of the FPGAs

• ±5V for the line receiver

4.3 Interfaces of SW128B

16 © 2016 Nokia DN0420278 Issue: 1-3

Figure 3 The external interfaces of the SW128B

TESTRST SETTING SIGNALS

Table 2 Description of interface signals

16M 16 MHz clock signa

Controlbus0 32x8Mbit/s serial interface OR

Controlbus: 32x8Mbit/s serial interface OR