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    Assignment 1

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    vatsanirudh28
    This document contains Verilog code and test benches for basic logic gates - NOT, AND and NAND gates. It includes the code for each gate module and a test bench module to test the gate's functionality by applying different input patterns and observing the output. Specifically, it provides the code for a NOT gate module and test bench, an AND gate module and test bench, and a NAND gate module and test bench.

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    Assignment 1

    Uploaded by

    vatsanirudh28
    4 views6 pages
    This document contains Verilog code and test benches for basic logic gates - NOT, AND and NAND gates. It includes the code for each gate module and a test bench module to test the gate's functionality by applying different input patterns and observing the output. Specifically, it provides the code for a NOT gate module and test bench, an AND gate module and test bench, and a NAND gate module and test bench.

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    Sher?usjnebd sp

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    This document contains Verilog code and test benches for basic logic gates - NOT, AND and NAND gates. It includes the code for each gate module and a test bench module to test the gate's functionality by applying different input patterns and observing the output. Specifically, it provides the code for a NOT gate module and test bench, an AND gate module and test bench, and a NAND gate module and test bench.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as docx, pdf, or txt
    4 views6 pages

    Assignment 1

    Uploaded by

    vatsanirudh28
    This document contains Verilog code and test benches for basic logic gates - NOT, AND and NAND gates. It includes the code for each gate module and a test bench module to test the gate's functionality by applying different input patterns and observing the output. Specifically, it provides the code for a NOT gate module and test bench, an AND gate module and test bench, and a NAND gate module and test bench.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as docx, pdf, or txt
    of 6

    Digital Design

    Assignment
    Name : Anirudh Vats
    Enrollment : E23CSEU0064

    1)
    2)

    3)
    Verilog Code – Not Gate:
    module not_gate(
    input a,
    output y);
    assign y = ~a;
    endmodule
    Test Bench For Not Gate :
    module tb_not_gate;
    reg A;
    wire Y;
    not_gate a1 (.a(A),.y(Y));
    initial
    begin
    A=0;#5;
    A=1;#5;
    end
    initial
    begin
    $dumpfile("dump.vcd");
    $dumpvars(1);
    end
    endmodule
    4)

    Verilog Code – And Gate:


    module and_gate(
    input a,b,
    output y);
    assign y = a & b;
    endmodule
    Test Bench For Not Gate :
    module tb_and_gate;
    reg A,B;
    wire Y;
    and_gate a1 (.a(A),.b(B),.y(Y));
    initial
    begin
    A=0; B=0;#5;
    A=0;B=1;#5;
    A=1; B=0;#5;
    A=1;B=1;#5;
    end
    initial
    begin
    $dumpfile("dump.vcd");
    $dumpvars(1);
    end
    endmodule
    5)

    Verilog Code – And Gate:


    module nand_gate(
    input a,b,
    output y);
    assign y = ~(a & b);
    endmodule
    Test Bench For Not Gate :
    module tb_nand_gate;
    reg A,B;
    wire Y;
    nand_gate a1 (.a(A),.b(B),.y(Y));
    initial
    begin
    A=0; B=0;#5;
    A=0;B=1;#5;
    A=1; B=0;#5;
    A=1;B=1;#5;
    end
    initial
    begin
    $dumpfile("dump.vcd");
    $dumpvars(1);
    end
    endmodule

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