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  • Adder Compo

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    bhslegion1498
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    The document describes a design for a 4-bit adder circuit using lower level components like half adders and full adders. It includes the entity and architecture definitions for half adders, OR gates, full adders, 4-bit adders, and a top level 4-bit adder component that handles carry inputs.

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    adder_compo

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    The document describes a design for a 4-bit adder circuit using lower level components like half adders and full adders. It includes the entity and architecture definitions for half adders, OR gates, full adders, 4-bit adders, and a top level 4-bit adder component that handles carry inputs.

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    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
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    7 views4 pages

    Adder Compo

    Uploaded by

    bhslegion1498
    The document describes a design for a 4-bit adder circuit using lower level components like half adders and full adders. It includes the entity and architecture definitions for half adders, OR gates, full adders, 4-bit adders, and a top level 4-bit adder component that handles carry inputs.

    Copyright:

    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as txt, pdf, or txt
    of 4

    ----------------------------------------------------------------------------------

    -- Company:
    -- Engineer:
    --
    -- Create Date: 15:08:58 02/11/2016
    -- Design Name:
    -- Module Name: adder - Behavioral
    -- Project Name:
    -- Target Devices:
    -- Tool versions:
    -- Description:
    --
    -- Dependencies:
    --
    -- Revision:
    -- Revision 0.01 - File Created
    -- Additional Comments:
    --
    ----------------------------------------------------------------------------------
    ----------------------------------------------------------------------------------
    -- Company:
    -- Engineer:
    --
    -- Create Date: 14:15:05 02/11/2016
    -- Design Name:
    -- Module Name: adder - Behavioral
    -- Project Name:
    -- Target Devices:
    -- Tool versions:
    -- Description:
    --
    -- Dependencies:
    --
    -- Revision:
    -- Revision 0.01 - File Created
    -- Additional Comments:
    --
    ----------------------------------------------------------------------------------
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    ---- Uncomment the following library declaration if instantiating


    ---- any Xilinx primitives in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;

    entity half_adder is
    Port ( a : in STD_LOGIC;
    b : in STD_LOGIC;
    s : out STD_LOGIC;
    c : out STD_LOGIC);
    end half_adder;

    architecture Behavioral of half_adder is

    begin
    s <= a xor b;
    c <= a and b;

    end Behavioral;

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    ---- Uncomment the following library declaration if instantiating


    ---- any Xilinx primitives in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;

    entity OR_1 is
    Port ( a : in STD_LOGIC;
    b : in STD_LOGIC;
    c : out STD_LOGIC);
    end OR_1;

    architecture Behavioral of OR_1 is

    begin
    c <= a or b;

    end Behavioral;

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    ---- Uncomment the following library declaration if instantiating


    ---- any Xilinx primitives in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;

    entity full_adder is
    Port ( x : in STD_LOGIC;
    y : in STD_LOGIC;
    z : in STD_LOGIC;
    sum : out STD_LOGIC;
    carry : out STD_LOGIC);
    end full_adder;

    architecture Behavioral of full_adder is


    component half_adder
    Port ( a : in STD_LOGIC;
    b : in STD_LOGIC;
    s : out STD_LOGIC;
    c : out STD_LOGIC);
    end component;

    component OR_1
    Port ( a : in STD_LOGIC;
    b : in STD_LOGIC;
    c : out STD_LOGIC);
    end component;

    signal s1, s2, s3:STD_LOGIC;

    begin
    h_a_1 : half_adder port map (x, y, s1, s2);
    h_a_2 : half_adder port map (z, s1, sum, s3);
    or_3 : OR_1 port map (s2, s3, carry);

    end Behavioral;

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    ---- Uncomment the following library declaration if instantiating


    ---- any Xilinx primitives in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;

    entity adder is
    Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
    B : in STD_LOGIC_VECTOR (3 downto 0);
    c_in : in STD_LOGIC;
    sum : out STD_LOGIC_VECTOR (3 downto 0);
    carry_adder : out STD_LOGIC);
    end adder;

    architecture Behavioral of adder is


    component full_adder
    Port ( x : in STD_LOGIC;
    y : in STD_LOGIC;
    z : in STD_LOGIC;
    sum : out STD_LOGIC;
    carry : out STD_LOGIC);
    end component;

    signal c1, c2, c3:STD_LOGIC;


    begin
    full_adder_1 : full_adder port map (a(0), b(0), c_in, sum(0), c1);
    full_adder_2 : full_adder port map (a(1), b(1), c1, sum(1), c2);
    full_adder_3 : full_adder port map(a(2), b(2), c2, sum(2), c3);
    full_adder_4 : full_adder port map (a(3), b(3), c3, sum(3), carry_adder);
    end Behavioral;

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    ---- Uncomment the following library declaration if instantiating


    ---- any Xilinx primitives in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;

    entity compo_adder is
    Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
    B : in STD_LOGIC_VECTOR (3 downto 0);
    c_input: in STD_LOGIC;
    Sum : out STD_LOGIC_VECTOR (3 downto 0);
    Carry_comp : out STD_LOGIC);
    end compo_adder;

    architecture Behavioral of compo_adder is

    component adder
    Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
    B : in STD_LOGIC_VECTOR (3 downto 0);
    c_in : in STD_LOGIC;
    sum : out STD_LOGIC_VECTOR (3 downto 0);
    carry_adder : out STD_LOGIC);
    end component;

    signal C: STD_LOGIC_VECTOR (3 downto 0);

    begin
    C(0) <= B(0) xor c_input;
    C(1) <= B(1) xor c_input;
    C(2) <= B(2) xor c_input;
    C(3) <= B(3) xor c_input;
    adder_6 : adder port map (A, C, c_input, Sum, Carry_comp);
    end Behavioral;

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