library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FA_bhvr is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end FA_bhvr;

architecture Behavioral of FA_bhvr is

begin

sum : process(A, B, Cin)

variable s1 : STD_LOGIC_VECTOR (2 downto 0);

begin
s1 := A & B & Cin;

if (s1 = "000" or s1 = "011" or s1 = "101" or s1 = "110") then

S <= '0';
else
S <= '1';
end if;
end process;

carry : process (A, B, Cin)

variable s2 : STD_LOGIC_VECTOR (2 downto 0);

begin
s2 := A & B & Cin;

if (s2 = "000" or s2 = "001" or s2 = "010" or s2 = "100") then

Cout <= '0';
else
Cout <= '1';
end if;
end process;

end Behavioral;