Rev E: Seedy

8 7 6 5 4 3 2 1
CK ENG
SEEDY
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD APPD
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. REV ZONE ECN DESCRIPTION OF CHANGE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. DATE DATE
E 385505 PRODUCTION RELEASED
REV E
06/13/05 ?
06/13/05
D D
CSA PDF CIRCUIT BLOCK CSA PDF CIRCUIT BLOCK
1 1 TABLE OF CONTENTS 51 43 GPU CORE POWER
2 2 SYSTEM BLOCK DIAGRAM 52 44 GPU FRAME BUFFER
3 3 POWER BLOCK DIAGRAM 53 45 FRAME BUFFER TERMINATION
4 4 REVISION HISTORY 54 46 GRAPHICS DDR SDRAM A GRAPHICS
5 5 TABLE ITEMS 55 47 GRAPHICS DDR SDRAM B
6 6 FUNC TEST 56 48 GPU STRAPS
7 7 POWER CONNECTOR / POWER ALIAS 58 49 GPU DVI & DACS
8 8 SIGNAL ALIAS 59 50 EXT VGA & TMDS
9 9 2.5V VREG 60 51 U3LITE HYPERTRANSPORT
10 10 1.2V VREG TOP 62 52 SHASTA HYPERTRANSPORT HT
11 11 3.3V/5V PWRON SWITCHING 64 53 HYPERTRANSPORT LA CONNECTORS
12 12 VESTA POWER 73 54 PCI SERIES TERMINATION
C 13 13 SMU 74 55 SHASTA PCI C
14 14 CPU LOGIC ANALYZER CONNECTOR 75 56 BOOT ROM PCI
16 15 FAN 0, 1 AND SYSTEM TEMP SENSOR 76 57 AIRPORT EXTREME & BLUETOOTH
17 16 FAN 2 AND HARD DRIVE TEMP SENSOR 77 58 USB2 PCI
18 17 I2C CONNECTIONS 80 59 SHASTA DISK
21 18 INDICATOR LED / AMBIENT LIGHT SENSOR 83 60 DISK CONNECTORS
DISK
22 19 1.5V VREG / U3LITE CORE 84 61 SHASTA ETHERNET
23 20 SHASTA CORE 86 62 VESTA ETHERNET PHY ETHERNET
24 21 U3LITE MISC 87 63 ETHERNET CONNECTOR
25 22 SHASTA SERIAL 88 64 SHASTA FIREWIRE
26 23 PULSAR POWER 89 65 VESTA FIREWIRE PHY FIREWIRE
27 24 PULSAR CLOCKS 90 66 FIREWIRE CONNECTORS
28 25 U3LITE APPLE PI 91 67 USB HOST INTERFACE
B 29 26 NEO APPLE PI 92 68 USB DEVICE INTERFACE USB B
30 27 CPU STRAPS 94 69 MODEM CONNECTOR MODEM
31 28 NEO POWER & BYPASS PROCESSOR 95* 70 PCM3052A AUDIO CODEC
32 29 CPU BYPASS 96* 71 LINE IN AMP
33 30 CPU VREG 98* 72 LINE OUT AMP
34 31 CPU VREG 100* 73 SPEAKER AMP
AUDIO
35 32 CPU VREG OUTPUT CAPS 101* 74 AUDIO CONNECTORS
36 33 CPU DIODE CONDITIONER 102* 75 AUDIO POWER SUPPLIES
37 34 U3LITE MEMORY
38 35 SERIES TERMINATION
40 36 DIMMS MEMORY
44 37 PARALLEL TERMINATION DIMENSIONS ARE IN MILLIMETERS
Apple Computer Inc.
METRIC
45 38 PARALLEL TERMINATION XX
A 46 39 VTT VREG X.XX

DRAFTER DESIGN CK NOTICE OF PROPRIETARY PROPERTY A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
48 40 U3LITE AGP X.XXX
ENG APPD MFG APPD
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
49 41 GPU AGP GRAPHICS ANGLES
QA APPD DESIGNER
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
50 42 GRAPHICS VREGS DO NOT SCALE DRAWING

TITLE
RELEASE SCALE SCH,MLB,SEEDY

NONE
SIZE DRAWING NUMBER

* PAGES WHERE MASTER PAGE IS IN A DIFFERENT SCHEMATIC MATERIAL/FINISH
NOTED AS D 051-6772 REV.
E
THIRD ANGLE PROJECTION APPLICABLE SHT 1 OF 102
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www.vinafix.vn
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FREQUENCIES LISTED ARE MAXIMUM DATA TRANSFER RATES SUPPORTED BY U3LITE
U2900
CPU
NEO 10S U1300
U1301
PAGE 29
J5900, J5901
J5902, J5903 SMU RTC
17",20" INVERTER
PAGE 13
TMDS 32-BIT PAGE 13
EXT VGA APPLE PI
D PAGE 59 ELASTIC INTERFACE D
1.2V/900MHZ
J4000
J4001
APPLE PI
MAIN MEMORY
PAGE 28
U5400, U5401
U4900
U3 SERIES
DIMMS PARALLEL
GPU
PAGE 37
64/128-BIT
AGP
FRAME 64-BIT
32-BIT MAIN MEMORY TERM TERM
BUFFER A
FRAME BUFFER
2.6V/400MHZ
8X AGP
PAGE
U3LITE 2.6V/400MHZ
PAGE 38 PAGES 44&45
RV351LE 0.8V/533MHZ
48 CORE
PAGE 54 4X = 1.5V
I/O = 1.5V
PAGE 22
PAGE 49 PAGE 40 J9210/J9220/J9230
MISC HYPERTRANSPORT
PAGE 24 PAGE 60
USB
64-BIT
FRAME BUFFER
CONNECTORS
PAGE 92
2.6V/400MHZ 8-BIT
HYPERTRANSPORT
1.2V/800MHZ
CONTROL = 2.5V
U2600 U5500, U5501
PULSAR FRAME
POWER CLOCKS BUFFER B I2C J6400
J6401
J9240
BLUETOOTH
C PAGE 26 PAGE 27 PAGE 55
PAGE 18
J6402
1 2 3 4 5
CONNECTOR
C
HT USB PAGE 92
DEBUG PAGE 91
PAGE 64 U7700
U7500 J7600
AIRPORT USB 2.0

BOOTROM EXTREME uPD720101
CONNECTOR PCI
PAGE 75 PAGE 76 PAGE 77
JXXXX
SATA HYPERTRANSPORT
SATA1
PAGE 74
HARD DRIVE
CONNECTOR SATA/150
PCI
PAGE 62
1.2V/1.5GHZ
PAGE 80
SATA
PAGE 83 32-bit PCI (5V-3.3V/33MHz)
U2300
J8302
SATA DEV
SATA2
GPIO/PCI64
FOR DEVELOPMENT ONLY
CONNECTOR SATA/150
SHASTA
PAGE 25
1.2V/1.5GHZ
PAGE 83
J8301
PAGE 80
UATA
J9401
B UATA UATA/133 CORE NCs CTL-LESS / B
OPTICAL
CONNECTOR 3.3V/133MHZ PAGE 23 PAGE 91
SOFT MODEM
PAGE 83 ETHERNET FIREWIRE
I2S CONNECTOR
PAGE 25
PAGE 94
PAGE 84 PAGE 88 SCCA SCCB
I2S0 I2S1 I2S2
1394 OHCI (3.3V/98MHz)
8-bit TX & 8-bit RX
GMII (3.3V/125MHz)
8-bit TX/RX
U9500
S/PDIF OPTICAL OUT
J9803
AUDIO CODEC COMBO OUT
CONNECTOR
PCM3052A LINE OUT
PAGE 98
U8600
AMP LINE OUT
VESTA PAGE 95 PAGE 97
J9801
GIG ETHERNET FIREWIRE A SPEAKER SYSTEM BLOCK DIAGRAM
PAGE 86 PAGE 89
AMP
SPEAKER
A 0 1 LINE IN
AMP
PAGE 97
CONNECTOR
PAGE 98
SYNC_MASTER=N/A
NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=N/A
A
PAGE 97
4 Diff pairs 2 Diff pairs
J8700 J9000, J9001
J9800 J9802 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
ETHERNET FIREWIRE A LINE IN MIC II NOT TO REPRODUCE OR COPY IT
CONNECTOR CONNECTORS CONNECTOR CONNECTOR
PAGE 87 PAGE 90
SIZE DRAWING NUMBER REV.
PAGE 98 PAGE 98
D 051-6772 E
APPLE COMPUTER INC.
SCALE SHT OF
NONE 2 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
SYS_POWERUP_L
SMU
POWER SEQUENCE PIN
PULSAR_POWER_DOWN SMU_PWRSEQ_P1_4 13
MAKE_BASE=TRUE
J700 SYS_POWERUP_L 27 =PULSAR_POWER_DOWN
PAGE 7
POWER CONNECTOR 10
TP_SMU_PWRSEQ_P1_0
MAKE_BASE=TRUE
TURN_ON_PP1V2_PWRON_L
SMU_PWRSEQ_P1_0
SMU_PWRSEQ_P1_1
13
13
D PP24V_RUN PP12V_RUN PP5V_RUN PP5V_ALL PP3V3_RUN SMU_PWRSEQ_P9_5 13 (PWR_GOOD_SB_CORE) D

FW CONN 20" PANEL POWER HDD & OPTICAL PCI BUS SMU_PWRSEQ_P9_6 13 (PWR_GOOD_PP2V5)
20" LCD INVERTER 20" LCD INVERTER AUDIO CODEC
SMU_PWRSEQ_P1_2 13 (TURN_ON_VTT)
5V
PP3V3_ALL PP1V2_ALL PP3V3_ALL
LINEAR SWITCHER IN
PAGE 11
PAGE 10 IRU3037ACS 1
R331
10K
3.3V FW PHY 1.2V VESTA CORE 5%
1/16W
SMU MF-LF
2 402
PWR_GOOD_SB_CORE
=PP5V_RUN_CPU 6 7 8 31
PP5V_RUN_AUDIO CPU CORE PP2V5_RUN_CPU_AVDD PP5V_PWRON PP3V3_PWRON GPU CORE PP2V5_GPU_A2VDD
C LINEAR SWITCHER ALIAS

CPU_AVDD_EN 31
LINEAR FET SWITCH FET SWITCH SWITCHER LINEAR C
PAGE 99 SC2643VX*1 PAGE 31 PAGE 11 PAGE 11 PAGE 50 IRU3037ACS PAGE 50
PAGE 33 SC1211*4
CPU AVDD USB CONN ENET PHY
5V HP/LINEOUT AMP
0.8~1.2V GPUL
2.8V 5V 3.3V USB2 HOST
1.20V RV351 GPU
MODEM & BT
3
11 RAIL_CTL_NEG 8 LM339A
V+ SOI
PP1V8_TPVDD PP1V5_VDDC_CT 14
PP4V5_RUN_AUDIO R330 U1100
LINEAR LINEAR 1
100K 2 COMPARE_SB_CORE 9 GND
LINEAR U3LITE CORE PP2V5_PWRON PAGE 50 GPU PAGE 50 GPU 5% 12
SWITCHER 1/16W
MF-LF
1 C330
PAGE 99
SWITCHER 402 0.01UF
20%
4.5V AUDIO CODEC PAGE 22 IRU3037CS PAGE 9 IRU3037CS
PP1V2_PWRON PP1V2_RUN
16V
2 CERM
SHASTA HT 402
1.53V U3LITE CORE 2.59V DDR DIMM FET SWITCH IN FET SWITCH IN
PP2V5_PWRON
PAGE 10 IN PAGE 10
IN
HT BUS
SHASTA CORE
PWRON_SD
PWRON_DISK_SB
PP2V5_RUN PP1V25_RAM_VTT PP1V5_PWRON 23 7 6 =PPVCORE_PWRON_SB
FET SWITCH LINEAR IN LINEAR PP5V_ALL
PAGE 9 PAGE 46 PAGE 50 PP3V3_ALL
RAM TERM
1.3V RAM VTT 1.5V PULSAR CORE 1
R342
B GRAPHIC FB
5%
150K 1
R341
B
1/16W
MF-LF 10K
2 402 3
5%
1/16W
6 LM339A MF-LF
PS_2V_REF 2 402
PP1V8_GPU PP1V5_RUN V+ SOI
1
R340 U1100 PWR_GOOD_PP2V5
LINEAR POWER SW 1
100K 2
COMPARE_PP2V5 7 GND
PAGE 50 PAGE 50 5% 12
1/16W
MF-LF 1 C340
GPU AGP BUS 402
0.01UF
1
R343
20%
16V 100K
2 CERM 5%
402 1/16W
MF-LF
2 402
46 TURN_ON_VTT
POWER BLOCK DIAGRAM

A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
APPLE COMPUTER INC.

D 051-6772 E
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DATE DESCRIPTION
10/20/04 CLONED DESIGN FROM GILA (Q45 A/B) REV G 11/15/04 ADDED REGULATOR FOR GPU TPVDD 12/16/04 FIXED I2C_TMDS_SDA/SCL ON P 6 03/25/05 (P 80) CHANGED CAPS TO 1UF, REMOVED 10UF THAT WOULD NOT FIT
CHECKIN 00002 ADDED POWER SEQUENCING FOR GRAPHICS REGULATORS (P 46) NOSTUFF RICHTEK VTT VREG (P 10) CHANGED R1003 TO 5.62K TO RAISE 1.2V REGULATOR TO 1.25
ADDED TEST POINTS TO GRAPHICS FOR EXOR TESTING (P 59) STUFFED TMDS CHOKES (P 6) ADDED NO_TEST PROPERTIES ON UNUSED SATA2 NETS
10/21/04 ADDED VESTA
REMOVED EXTERNAL S/PDIF TRANSMITTER (P 56) USING PWM FROM ATI GPU (P 50) CHANGED R5091 TO 61.9K TO INCREASE VDCC_CT TO ABOUT 1.54V
ADDED 1.2V REGULATOR FOR VESTA CORE
CHECKIN 01005 (P 38) FIXED MIN_NECK_WIDTH ON TD1 AND TD2 BOM RELEASE REV14, CHECKIN 14001
ADDED 2.5V LDO FOR VESTA
(P 92) ADDED NET_PHYSICAL_TYPE = USB2 TO TABLE
ADDED FW LATE VG PROTECTION 11/16/04 REMOVED P50 AIRPORT AND Q23 BLUETOOTH CONNECTORS, HOLES, 03/28/05 PVT RELEASE (REV A)
& STANDOFFS (P 7) ADDED BATTERY SAFETY BYPASS OPTION (NOSTUFF)
REMOVED BCM5231 ETHERNET PHY ADDED Q85 AIRPORT & BLUETOOTH CONNECTOR
D REMOVED FW802A FW PHY CHECKIN 01006
CHECKIN 05002
(P 50) ADDED Q5000 TO INPUT OF GPU VCORE VREG
04/06/05 (P 25,62) RESTUFFED C2500,C2520,C2530,C6200,C6210 FOR SHASTA POWER DECOUPLING
PVT RELEASE 2 (REV B)
D
REMOVED FW PORT POWER CIRCUITRY (PP 16,17) REPLACED FAN CONTROL WITH NEW CIRCUIT
(P 6) REMOVED SOME FUNC_TEST PROPERTIES
REMOVED MICRODASH CONNECTOR (P 76) FINISHED CONNECTING Q85 CONNECTOR 04/22/05 (P 5) ADDED BPL, BRL, AND BNA PROCESSORS TO TABLE
(P 50) GPU_VDCC_CT POWER SEQUENCING
CHECKIN 00003 (P 7) ADDED PLATED HOLE ZH710 FOR TMDS GROUNDING (P 50) CHANGED R5091 TO 56.2K TO INCREASE VDCC_CT TO ABOUT 1.65V
CHECKIN 05003
(P 7) TIED BOTH EI RAILS TO 1.5V REV C RELEASE
10/22/04 REMOVED NV18/34 GPU
(P 5) NEW BOOTROM P/N 12/17/04 (P 6) ADDED/REMOVED MORE FUNC_TEST PROPERTIES
REMOVED AGP VREG (VR5001) 04/25/05 (P 50) STUFFED R5020 0-OHM TO HELP ICT
(P 9) ADDED EXTRA 10UF INPUT CAP CHECKIN 05004
REMOVED GPU VTT VREG
(P 12) VESTA_ENET_LOWPWR UPDATE (P 50) GPU POWER SEQUENCING 06/07/05 (P 54,55) CHANGED HYNIX FRAME BUFFER TO 333S0341 (NEW HYNIX SCREEN, SAME PART)
ADDED 2.5V VREG FOR A2VDD
(P 18) <RADAR 3878118> MOVED SMU I2C E BUS CHECKIN 05005
REMOVED EXTERNAL TMDS TRANSMITTER 06/13/05 (P 6) ADDED 338S0263 AS ALTERNATE FOR U4900 (RV351 GPU WITH EUTECTIC BUMPING)
(P 22) CHANGED Q2250 TO 376S0143
ADDED RV351LE GPU 12/20/04 MINOR TEXT/COMMENT CHANGES REV E RELEASE
(P 46) SLEEP SIGNAL TURNS OFF VTT VREG
CHECKIN 00004 EVT RELEASE (REV 6)
(P 58) REPLACED THERMAL SENSOR WITH LM63
10/26/04 GPU CORE POWER UPDATES (P 59) TIED UNUSED BUFFER ENABLE PINS HIGH 01/11/05 (P 5) REMOVED BRA FROM PROCESSOR TABLE, REPLACED BPA WITH BNA
ADDED VESTA ETHERNET LOWPWR CIRCUIT (P 90) FIXED FW PORT NAMING (P 5) NEW SMU PART NUMBER
ADDED DEVELOPMENT LEDS FOR VESTA ENET (P 90) CHANGED R9090 TO 665 OHM
01/18/05 CHANGED SDF7601 TO PART 860-0567
CHECKIN 00005 (P 91) CHANGED USB2 CHIP GROUNDING
BOM RELEASE REV 7
(P 8) ALIASED VESTA JTAG TO TEST POINT NETS
10/28/04 CONNECTED FRAME BUFFER
(P 9) <RADAR 3848846> ADDED PAD FOR 1NF CAP TO GATE OF Q903 01/25/05 (P 5) CORRECTED 1.8GHZ CPU APPLE P/N FROM 337S2969 TO 337S2998
ADDED 1.8V GPU VREG
CHECKIN 01007 / BOM RELEASE REV 02 (P 12) NOSTUFF Q1250 TO DISCONNECT ENETFW_RESET FROM SHASTA GPIO
CONNECTED GPU TMDS AND VGA
(P 5) CORRECTED SMU PART NUMBER TO 341T1703
CONNECTED GPU POWER AND POWER FILTERS 11/18/04 ADDED PHYSICAL CONSTRAINTS
(P 16, 17) HAROLD’S FAN CIRCUIT CHANGES
CHECKIN 00006 AUDIO STUFFING CHANGES
CHECKIN 07002
CHECKIN 02001
11/01/04 ADDED VOLTAGE, LINE WIDTH, AND NECK WIDTH PROPERTIES FOR GRAPHICS
01/27/05 (P 25) REPLACED R2566 WITH 0 OHM TO ELIMINATE FW_LOWPWR GLITCH
TIED PPVCORE_NB DIRECTLY TO PP1V5_PWRON (REMOVED R707) 11/20/04 (P 36) CONNECTED NEW CPU DIODE REFERENCE
ADDED 0 OHM (R2570, NOSTUFF) TO BREAK FW_LOWPWR FROM SHASTA
REPLACED EMC FERRITES WITH 0 OHM RESISTORS FOR GRAPHICS AND FANS (P 77) USB2 IDESEL - NOW FROM USB2 SIDE
(P 56) STUFF R5610 TO PULL DOWN ATI_PWM SIGNAL TO ELIMINATE GLITCH
REMOVED VESTA CORE REGULATOR (P 56) ADDED BOMOPTIONS FOR MEMORY STRAPS
(P 27-29) CONNECTED CPU_APSYNC FROM U3LITE AND DISCONNECTED FROM PULSAR
C REPURPOSED 1.2V REGULATOR FOR VESTA AND SHASTA
CHANGED FW LATE VG CIRCUITRY TO MATCH Q78 & Q86
(PP 56, 58) CONNECTED PWM FROM RV351LEP & PUT IN PROTO WORKAROUND
(P 25) <RADAR 3849835> NEW SHASTA XTAL
NO STUFF: R2768,R2772,R2805,R2910
STUFF: R2806,R2911
C
CHECKIN 00007 (P 62) <RADAR 3849855> SHASTA HT_PLL FILTER COST REDUCTION
(P 11) CHANGED C1102 TO 16V FOR SUPPLY AND COST ISSUES
(P 91) <RADAR 3849858> USB CAP COST REDUCTION
11/03/04 <RADAR 3848831> MOVED SMU RESET BUTTON TO DEVELOPMENT BOM (P 5) ADDED KQA (337S3093) TO ALTERNATE PROCESSOR TABLE
(P 76) ADDED STANDOFFS FOR Q85 CARD
<RADAR 3849762> MOVED SMU DOWNLOAD CONNECTOR TO DEVELOPMENT BOM CHECKIN 07003
(PP 16,17) NEW FAN CIRCUIT CAPS (C1603, C1653, C1703)
<RADAR 3849798> REDUCED CAPACITANCE OF C1100 & C1102 (P 5) MODIFIED PROCESSOR TABLE TO MATCH IBM’S TABLE, AGAIN.
(P 50) <RADAR 3865344> VDDC_CT SET TO 1.50V
MASTER PAGE SYNC: BOM RELEASE REV 8
(P 50) <RADAR 3877855> TP_VDD SET TO 1.80V
FRAME BUFFER SWAPS FOR CLEANER ROUTING
(P 12) VESTA_ENET_LOWPWR UPDATE 02/01/05 (P 75) BOOTROM REFLASHING ISSUE FIX: CHANGED R7502 TO 470 OHM
REMOVED VESTA ROM
(PP 10, 22, 34, 50) USED COMPARATOR FOR LOW VOLTAGE RAIL LEDS (P 12) ADDED A CLAMP CIRCUIT FOR ENET_LOWPWR GLITCH
AUDIO COST REDUCTIONS <RADAR 3849747 & 3849751>
CHECKIN 02002 (P 10,22) SHASTA & U3LITE VCORE IMPROVEMENT: STUFF C1005 & C2205 WITH 2200PF
AUDIO 3052A CODEC
(P 13) CHANGED U1301 TO LEADED PART (353S0653) DUE TO SUPPLY
ADDED 1.55V VREG FOR GPU VDDC_CT 11/22/04 (P 49) CONNECTED AGPTEST RESISTOR TO VDDP
(P 5) ADDED 34S0284 AND 34S0282 AS U3LITE ALTERNATES (OLD LAM)
MOVED VTT VREG TO 2.5V PWRON TO REDUCE CURRENT THROUGH Q903 (P 56) ADDED PADS FOR STRAPPING RESISTORS TO GPU_GPIO<14>
BOM RELEASE REV 9
CHANGED FETS IN GPU CORE FOR COST REDUCTION (P 58) ADDED CONSTRAINT SETS
ADDED SPACING & PHYSICAL CONSTRAINTS TO FRAME BUFFER (P 59) STUFFED AROUND Q5900 PANEL PWR SEQUENCING 02/03/05 (P 28) CHANGED APSYNC SERIES TERMINATION R2806 TO 10 OHM
CHECKIN 00008 (P 59) LED 3 NOW DRIVEN FROM FPD_PWR_ON (P 5) ADDED LEAD FREE PARTS AS ALTERNATE FOR U1301 & VRA201 DUE TO SUPPLY
(P 3) CONNECTED SHASTA CORE POWER FOR POWER SEQUENCING (P 8) REMOVED SMU DOWNLOAD CONNECTOR FROM DEVELOPMENT BOM
11/04/04 REMOVED 1.6GHZ PROCESSORS
(P 76) FIXED PCI_CBE_L<1> CONNECTION (P 92) STUFFED USB COMMON MODE CHOKES FOR EMC
CHANGED VOLTAGE SETTING OF 2.5V VREG TO 2.588V FROM 2.62V
MORE PHYSICAL & SPACING UPDATES CHECKIN 09002
1.2V VREG COST REDUCTIONS - Q1002 TO NTD60N02R; C1002/3 TO 10UF CERM
(P 83) <RADAR 3890225> OPTICAL DRIVE CONNECTOR CHANGED TO 516S0235
U2850 - REMOVED MAXIM AS AN ALTERNATE 02/04/05 (P 50) <RADAR 3919121> NOSTUFF U5090 AND RELATED COMPONENTS
CHECKIN 02003
MOVED GPU ZENER DIODES TO VREG PAGE SINCE THEY SHOULD BE PLACED STUFFED R5092 FOR 1.5V GPU VDCC_CT
NEAR THE VREGS (P 56) ADDED OPTION OF USING PWM FROM SHASTA
ADDED 8MX32 GRAPHICS MEMORY
<RADAR 3849718, 3849767, 3849854> MADE ON & VISHAY FETS ALTERNATES 02/08/05 (P 7) REMOVED ZH701
ADDED GIGABIT ETHERNET CONNECTOR
(P5) ADDED U3L W/ NEW LAMINATE AS ALTERNATE (P 12) STUFF R1251, CHANGE C1250 TO 10UF, R1262=100K TO LENGTHEN
CHECKIN 00009
(P 16) C1653 - REPLACED WITH LOWER HEIGHT CAP VESTA RESET AND LOWPWR DELAY
11/06/04 ADDED GPU STRAPS CHECKIN 02004 (P 59) <RADAR 3849662> STUFFED PANEL POWER SEQUENCING FOR BOTH 17 AND 20 INCH
B CONNECTED GPU GPIOS

REMOVED ON BOARD POWER SUPPLY TEMP SENSOR
11/23/04 (P 76) TABLED IN NEW STANDOFFS FOR Q85 CARD
CHECKIN 09003
(P 92) <RADAR 3742725> CHANGED USB COMMON MODE CHOKES TO 120-OHM 155S0232
B
PROTO RELEASE (REV 3)
ADDED AMBIENT LIGHT SENSOR CONNECTOR (P 59) NOSTUFF R5950, STUFF R5923 FOR 17 INCH PANEL POWER FROM PP3V3_RUN
CONNECTED GPU TEMP SENSOR 12/02/04 (P 90) FIXED ALIAS PROBLEM WITH FW_TPB2_PD
02/09/05 CHECKIN 09004
REMOVED CPU VREG 4TH PHASE (P 90) FIXED FW_CPS SHORT
ADDED DEVELOPMENT LEDS TO REGULATORS (P 35) REMOVED DS3500 & DS3501 02/10/05 (P 59) <RADAR 3919083> CHANGED R5971 AND R5972 TO 33 OHMS
CHECKIN 00010 (P 83) REMOVED SECOND SATA CONNECTOR (P 56) <RADAR 3960901, 4000359> GPU GPIO GLITCH STUFFED: U5600, U5601
CHECKIN 03001 NOSTUFF: R5609, R5621
11/07/04 ADDED MORE GPU CONSTRAINTS
CONVERTED DISCRETES TO LEAD FREE DVT RELEASE (REV 10)
<RADAR 3616348, 3621390> CHANGED FL5900-2 TO 220 OHM
CHECKIN 03002 (P 56) <RADAR 3960901, 4000359> GPU GPIO GLITCH STUFFED: C5600, C5601
<RADAR 3848846> 2.5V RUN FET COST REDUCTION
<RADAR 3848859> 1.2V, 1.5V RUN FET COST REDUCTIONS 12/07/04 CHANGED U7700 BACK TO LEADED PART 02/15/05 (P 12) CHANGED C1250 TO 6.3V PART, TO MATCH A PART ALREADY ON THE BOM
<RADAR 3848887> 5V & 3.3V PWRON FET COST REDUCTIONS (P 5) REMOVED ORIGINAL U3LITE (NEW LAMINATE ONLY FOR C/D) (P 5) ADDED 353S0687 (LEADED) AS ALTERNATE FOR 353S0959 (LEAD FREE) U9800
<RADAR 3849622> STUFFED AROUND TMDS FILTERS (P 49) CHANGED GPU TO RV351LEP (338S0231)
02/16/05 ADDED PAGE TITLE PROPERTIES FOR SCHEMATIC REUSE WITH M23/M33
<RADAR 3849656> STUFFED AROUND RGB FILTERS (P 76) NOW HAVE CORRECT SYMBOL FOR STANDOFFS
<RADAR 3849806> CHEAPER SMU CRYSTAL (P 76) J7650 - NEW TO ALLOW 5MM CONNECTED HEIGHT 02/17/05 (P 12) YET ANOTHER VESTA RESET/LOWPWR STUFFING CHANGE
<RADAR 3849857> CHEAPER USB2 CRYSTAL BOM RELEASE REV 04 (P 16,17,36) ADDED SIGNAL ALIASES FOR SCHEMATIC REUSE WITH M23
BOM RELEASE REV 01 (P 50) RE-STUFFED GPU 1.5V VDCC_CT BECAUSE OF LEAKAGE WORRIES
12/09/04 CHANGED ALIASES TO SYNONYMS
BOM RELEASE REV 11
11/08/04 FRAME BUFFER PIN SWAPS CHANGED LINE AND NECK WIDTHS TO METRTIC
<RADAR 3848846> UPDATE OF 2.5V RUN FET COST REDUCTION CHECKIN 04001 03/07/05 (P 12) MADE CONNECTION FOR VESTA RESET FINAL FOR PVT
<RADAR 3849743> ADDED RESISTORS TO STUFF AROUND USB FILTERS (P 49) STUFFED 470 OHMS FOR R4912 TO AVOID PCI_RESET GLITCH FROM GPU
12/13/04 ADDED 2.0 GHZ AND ADDITIONAL 1.8 GHZ ALTERNATE PROCESSORS
CHECKIN 01001 (P 50) ADDED FET TO SPLIT 3.3V POWER TO GPU I/O
VESTA XTAL: R5815=249, R8609=332, R8921=332
(P 59) HACK FOR PANEL POWER SEQ.OPTION FROM SYS_SLEEP
11/09/04 <RADAR 3848850> REGULATOR COST REDUCTIONS VESTA ENET: R1262=10K, C1260=10U, R1251=NO STUFF, C1250=2.2U
(P 6, 58) ADDED TEST POINTS FOR NEC AND ATI
<RADAR 3849767>
<RADAR 3849772>
2.5V VREG COST REDUCTIONS
REMOVED OUTPUT CAP ON 1.2V_ALL VREG
FANS: NO STUFF DZ1601, DZ1651, DZ1701
STUFFED R1604, R1654, R1704
CHECKIN 11002 (03/11) E
A <RADAR 3849820>
<RADAR 3849854>
SHASTA FILTER COST REDUCTION
GPU CORE VREG COST REDUCTION
12/14/04
CHECKIN 04002
2.5 V REGULATOR - NEW NARROWER OUTPUT CAPS (C908, C909)

03/17/05 (P 50, 59) FINALIZED STUFFING OPTIONS FOR ATI POWER SEQUENCE HACK
BOM RELEASE REV 12, CHECKIN 12001
SYNC_MASTER=N/A

SYNC_DATE=N/A
A
<RADAR 3865344> SET GPU VDDC_CT VREG TO 1.55V
(P 46) REMOVED SEMTECH REGULATOR, ADDED RICHTEK AS ALTERNATE VTT 03/21/05 (P 8,12,89) CHANGED VESTA STRAP PULL UP/DOWN RES TO 1K PER BROADCOM
CHECKIN 01002 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
(P 16) CHANGED FAN1 OUTPUT CAP BACK TO THROUGH-HOLE (P 13) RELOADED Y1300 DUE TO LIBRARY CHANGE PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
11/10/04 CHANGED SOURCE OF Q1003 TO PP1V2_ALL (P 59) SWAPPED INVERTER CONNECTOR GENDER BOM RELEASE REV 13
RGB TERMINATION NOW CONNECTED TO DIGITAL GROUND CHECKIN 04003
03/22/05 (P 16) REMOVED OPTICAL TEMP SENSOR (U1602) FOR BETTER I2C BUS ROUTING II NOT TO REPRODUCE OR COPY IT
WHITE LED - CHANGED INDUCTORS TO 0 OHM RESISTORS (P 46) RICHTEK VTT UPDATES
CHECKIN 13001 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
UPDATED POWER BLOCK DIAGRAM BOM RELEASE REV 5
CHECKIN 01003
<RADAR 3848850> 2.5V VREG COST REDUCTION
CHECKIN 01004
12/15/04 (P 6) ADDED NO_TESET PROPERTIES
(P 12) VESTA ENET LOW POWER FIX
03/24/05 (P 5) ADDED LEADED ALTERNATE FOR VRA200, LM1117
(P 10,80) ADDED CAPS ON 1.2V RAIL TO REDUCE SATA POWER NOISE
CHECKIN 13002 APPLE COMPUTER INC.
SIZE
D 051-6772
DRAWING NUMBER
E REV.
CHECKIN 05001
SCALE
NONE 4 102
SHT OF
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
PROCESSORS ASICS
TABLE_5_HEAD
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION

TABLE_5_ITEM
343S0320 1 IC,U3LITE,NEW LAM,300MM,PBGA U3
QUALIFIED TABLE_ALT_HEAD
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

TABLE_11_HEAD PART NUMBER
PART # QTY DEVICE PACKAGE DESCRIPTION VALUE VOLT. WATT. TOL. REFERENCE DESIGNATOR(S) BOM OPTION TABLE_ALT_ITEM
TABLE_11_HEAD 343S0321 343S0320 U3 U3L,NEW LAM,200MM
D
337S3055
337S3060
1 PROCESSOR
CBGA-576-1MM IC,GPUL,DD3.1,2.0G,85C,KPA 2.0GHZ 1.20V
1 PROCESSOR
CBGA-576-1MM IC,GPUL,DD3.1,1.8G,85C,JPA 1.8GHZ 1.20V
42W
42W
?
?
U2900
U2900
CPU_2_0GHZ
CPU_1_8GHZ
TABLE_11_HEAD 343S0284 343S0320 U3 U3L,OLD LAM,300MM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
D
343S0282 343S0320 U3 U3L,OLD LAM,200MM
TABLE_ALT_HEAD
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: VOLTAGE
PART NUMBER
TABLE_ALT_ITEM
337S3061 337S3060 CPU_1_8GHZ U2900 IC,DD3.1,1.8G,JRA 1.25V

TABLE_ALT_ITEM TABLE_5_HEAD
337S2969 337S3060 CPU_1_8GHZ U2900 IC,DD3.0,1.8G,BPA 1.20V PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
TABLE_ALT_ITEM TABLE_5_ITEM
337S2970 337S3060 CPU_1_8GHZ U2900 IC,DD3.0,1.8G,BRA 1.25V 343S0283 1 IC,ASIC,SHASTA,V1.1,PBGA U2300

TABLE_ALT_ITEM
337S2981 337S3060 CPU_1_8GHZ U2900 IC,DD3.0,1.8G,BPL 1.20V

TABLE_ALT_ITEM
337S2982 337S3060 CPU_1_8GHZ U2900 IC,DD3.0,1.8G,BRL 1.25V TABLE_5_HEAD
TABLE_ALT_ITEM
337S2998 337S3060 CPU_1_8GHZ U2900 IC,DD3.0,1.8G,BNA 1.20V TABLE_5_ITEM
TABLE_ALT_ITEM
343S0324 1 IC,ASIC,VESTA,V1.3 U8600
337S3093 337S3055 CPU_2_0GHZ U2900 IC,DD3.1,2.0G,KQA 1.15V
TABLE_ALT_ITEM
337S3056 337S3055 CPU_2_0GHZ U2900 IC,DD3.1,2.0G,KRA 1.25V
MISC PARTS
TABLE_ALT_ITEM
337S3058 337S3055 CPU_2_0GHZ U2900 IC,DD3.0,2.0G,CPA 1.20V

TABLE_ALT_ITEM
337S3059 337S3055 CPU_2_0GHZ U2900 IC,DD3.0,2.0G,CRA 1.25V TABLE_5_HEAD

TABLE_5_ITEM
062-2082 1 SPEC,VENDOR PACKAGING PROCEDURE VPP1

TABLE_5_ITEM
820-1747 1 PCB,FAB,MLB MLB1

TABLE_5_ITEM
825-6447 1 BARCODE LABEL, MLB, Q45 LBL1
C
TABLE_5_ITEM
C 051-6772
341T1667
1
1
PCB,SCHEM,MLB
IC,FLASH,1MX8,3.3V,90NS
SCH1
U7500
TABLE_5_ITEM
TABLE_5_ITEM
341T1703 1 IC,SMU,Q45C/D U1300

TABLE_5_ITEM
CRITICAL 603-6015 1 HEAT SINK ASSEMBLY 17 IN MECH17 17_INCH_LCD

TABLE_5_ITEM
CRITICAL 603-6016 1 HEAT SINK ASSEMBLY 20 IN MECH20 20_INCH_LCD
ALTERNATES
TABLE_ALT_HEAD

PART NUMBER
LED700,LED702,LED5900 TABLE_ALT_ITEM
378S0119 378S0114 KINGBRIGHT LED

Q3310,Q3320,Q3410 TABLE_ALT_ITEM
376S0204 376S0130 MOSFET,N-CH,VISHAY

Q3311,Q3321,Q3411 TABLE_ALT_ITEM
376S0207 376S0146 MOSFET,N-CH,VISHAY

TABLE_ALT_ITEM
353S0960 353S0733 VRA201 MAX8510,L-F PART

TABLE_ALT_ITEM
353S0958 353S0653 U1301 DS1338, L-F PART

TABLE_ALT_ITEM
353S0687 353S0959 U9800 MAX9722 LEAD
B 353S0539 353S0898 VRA200 LM1117 LEAD

TABLE_ALT_ITEM
TABLE_ALT_ITEM
B
338S0263 338S0231 U4900 RV351 GPU EUTECTIC
TABLE ITEMS
A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
APPLE COMPUTER INC.

D 051-6772E
SCALE
NONE 5 102
SHT OF
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
PP12V_RUN PP5V_RUN PP24V_RUN
I307 NO_TEST=YES TP_FBBCS1_L 52 I434 NO_TEST=YES TP_RAM_CKE_R<3> 8 101 IN AUD_MIC_IN_N_CONN FUNC_TEST=TRUE PP5V_ALL PP3V3_RUN
10 TEST POINTS
I824 NO_TEST=YES AGP_CLK66M_GPU_R 27 I433 NO_TEST=YES TP_RAM_CKE_R<6> 8 101 IN AUD_MIC_IN_P_CONN FUNC_TEST=TRUE IN PP12V_RUN FUNC_TEST=YES
I825 NO_TEST=YES AGP_CLK66M_NB_R 6 27 I436 NO_TEST=YES TP_RAM_CKE_R<7> 8 90 IN FW_VP FUNC_TEST=TRUE 12 11 7 PP5V_ALL 5 TEST POINTS
FUNC_TEST=YES
IN
I826 NO_TEST=YES AUD_4V5_FB 102 I435 NO_TEST=YES TP_RAM_CS_L_R<10> 8 101 IN GND_AUDIO_MIC_CONN FUNC_TEST=TRUE
5 TEST POINTS
I828 NO_TEST=YES CPU_HTBEN_R 27 I437 NO_TEST=YES TP_RAM_CS_L_R<11> 8 18 17 IN I2C_HD_TEMP_SCL FUNC_TEST=TRUE 18 11 10 7 IN PP5V_RUN FUNC_TEST=YES
I829 NO_TEST=YES EI_CPU_SYNC_R 27 I439 NO_TEST=YES TP_RAM_CS_L_R<2> 8 18 17 IN I2C_HD_TEMP_SDA FUNC_TEST=TRUE 50 34 22 18 11 10 7 PP3V3_RUN 5 TEST POINTS
FUNC_TEST=YES
IN
I831 NO_TEST=YES AGP_CLK66M_NB_R 6 27 I438 NO_TEST=YES TP_RAM_CS_L_R<3> 8 25 18 IN I2C_SB_SCL FUNC_TEST=TRUE
5 TEST POINTS
I832 NO_TEST=YES EI_NB_SYNC_R 27 I440 NO_TEST=YES TP_RAM_MUXEN0 8 25 18 IN I2C_SB_SDA FUNC_TEST=TRUE IN PP24V_RUN FUNC_TEST=YES
I834 NO_TEST=YES ERROR_LED 8 I441 NO_TEST=YES TP_RAM_MUXEN4 8 36 33 31 IN KPGND2 FUNC_TEST=TRUE
5 TEST POINTS
I833 NO_TEST=YES HT_CLK66M_NB_R 27 I442 NO_TEST=YES TP_NB_PM_SLEEP0 24 36 33 31 IN KPVDD2 FUNC_TEST=TRUE 83 7 IN =PP5V_DISK FUNC_TEST=YES
I835 NO_TEST=YES HT_CLK66M_SB_R 27 I444 NO_TEST=YES TP_J4000_SJRESET_L 40 59 6 IN I2C_TMDS_SCL FUNC_TEST=YES =PP12V_DISK 5 TEST POINTS
FUNC_TEST=YES
D I838 NO_TEST=YES
NO_TEST=YES
HT_VREF_DEBUG
ITS_RUNNING
64
7
I443 NO_TEST=YES
NO_TEST=YES
TP_J4001_SJRESET_L
U2100_UNUSED
40
21
59 6 IN I2C_TMDS_SDA FUNC_TEST=YES 83 7 IN
12 TEST POINTS
D
I837
LED801_1
I781
PLS_CLK_66M_0_R
77 76 75 74 73 IN PCI_AD<31..0> FUNC_TEST=TRUE IN GND FUNC_TEST=YES
NO_TEST=YES 8 NO_TEST=YES 27
I836
NO_TEST=YES LED802_1 8
I809
NO_TEST=YES PLS_CLK_66M_1_R 27
77 76 74 73 IN PCI_CBE_L<3..0> FUNC_TEST=TRUE
I839
NO_TEST=YES PCI_CLK66M_SB_INT_R 27
I810
NO_TEST=YES SATA_CLK25M_R 27
8 IN PCI_CLK33M_AIRPORT FUNC_TEST=YES
I841
PCI_CLK_P3_R
I861
76 74 IN PCI_SLOTA_REQ_L FUNC_TEST=YES
NO_TEST=YES 27
I840
NO_TEST=YES PCI_CLK_P4_R 27
76 74 IN PCI_SLOTA_GNT_L FUNC_TEST=YES
I842
NO_TEST=YES PN1 33
76 25 IN PCI_SLOTA_INT_L FUNC_TEST=YES PP2V5_RUN PP5V_PWRON PP1V2_PWRON
I845
NO_TEST=YES PN2 33
74 56 8 IN PCI_RESET_L FUNC_TEST=YES
I844
NO_TEST=YES PN3 34 NO_TEST=YES SB_CLK25M_ATA_R 27
77 76 74 73 IN PCI_FRAME_L FUNC_TEST=YES PP1V5_RUN PP3V3_PWRON
I843
Q800_D
I866
TEK_HT_A7
77 76 74 73 IN PCI_TRDY_L FUNC_TEST=YES IN PP2V5_RUN FUNC_TEST=YES
I846
NO_TEST=YES Q800_G 8
I867
NO_TEST=YES TEK_HT_A9 64
77 76 74 73 IN PCI_IRDY_L FUNC_TEST=YES IN PP1V5_RUN FUNC_TEST=YES
I847
NO_TEST=YES Q801_B 8
I868
NO_TEST=YES TEK_HT_A10 64
77 76 74 73 IN PCI_STOP_L FUNC_TEST=YES 18 11 IN PP5V_PWRON FUNC_TEST=YES
I848
Q802_B
I869
TEK_HT_A12
77 76 74 73 IN PCI_DEVSEL_L FUNC_TEST=YES 58 27 18 11 IN PP3V3_PWRON FUNC_TEST=YES
I849
NO_TEST=YES Q802_E 8
I870
NO_TEST=YES TEK_HT_B10 64
77 76 74 73 IN PCI_PAR FUNC_TEST=YES IN PP1V2_PWRON FUNC_TEST=YES
I850
NO_TEST=YES Q803_B 8
I872
NO_TEST=YES TEK_HT_B12 64
76 IN PCI_SLOTA_IDSEL FUNC_TEST=YES 23 7 3 IN =PPVCORE_PWRON_SB FUNC_TEST=YES
I851
Q901_GATE
I871
TP_PCI_CLK_P4
76 75 74 IN ROM_CS_L FUNC_TEST=YES 13 8 7 IN =PP3V3_ALL_SMU FUNC_TEST=TRUE
I852
NO_TEST=YES Q902_DRAIN 9
I878
NO_TEST=YES U900_COMP 9
76 75 74 IN ROM_OE_L FUNC_TEST=YES 31 8 7 3 IN =PP5V_RUN_CPU FUNC_TEST=YES
I853
I876
NO_TEST=YES U900_GATE_H 9
76 75 74 IN ROM_WE_L FUNC_TEST=YES 22 IN PPVCORE_NB FUNC_TEST=YES
I854
NO_TEST=YES TP_AGP_MB_AGP8X_DET_L 48
I875
NO_TEST=YES U900_GATE_L 9
76 75 IN ROM_ONBOARD_CS_L FUNC_TEST=YES 35 34 33 7 IN PPVCORE_CPU FUNC_TEST=YES
I337
NO_TEST=YES TP_ATTENTION 29
I874
NO_TEST=YES U900_SS 9 GENZ SHOULD USE J1400 FOR THE FOLLOWING NETS:
76 IN AIRPORT_CLKRUN_L_PD FUNC_TEST=YES 34 33 IN PP12V_CPU FUNC_TEST=YES
I338
TP_AFN
I873
U900_VC EI_CPU_TO_NB_AD<0..43>
33 IN VCORE_SENSE_GND FUNC_TEST=YES
I344 NO_TEST=YES 29 NO_TEST=YES 9 NO_TEST=TRUE 14 28 29
NO_TEST=YES TP_PSRO1 29
I879
NO_TEST=YES U900_VC_D 9
I782
NO_TEST=YES EI_CPU_TO_NB_CLK_N 14 28 29
76 IN USB_BT_N FUNC_TEST=YES 33 IN VCORE_SENSE_VOUT FUNC_TEST=YES
I345
NO_TEST=YES TP_PSRO2 29
I880
NO_TEST=YES U900_VC_R 9
I784
NO_TEST=YES EI_CPU_TO_NB_CLK_P 14 28 29
76 IN USB_BT_P FUNC_TEST=YES 8 7 IN SMU_MANUAL_RESET_L 2 TEST POINTS FUNC_TEST=YES
I346
TP_PSYNCOUT
I881
U1000_FEEDBACK
I785
EI_CPU_TO_NB_SR_N<0..1>
13 7 IN SYS_POWER_BUTTON_L 2 TEST POINTS FUNC_TEST=YES
I347 NO_TEST=YES 29 NO_TEST=YES 10 NO_TEST=TRUE 14 28 29
NO_TEST=YES TP_USB2_PWREN<2> 92
I882
NO_TEST=YES UATA_DASP_L_DS 83
I786
NO_TEST=TRUE EI_CPU_TO_NB_SR_P<0..1> 14 28 29
92 IN USB2_PORT1_N_F FUNC_TEST=YES 7 IN POWER_BUTTON_L FUNC_TEST=YES
I348
NO_TEST=YES TP_USB2_PWREN<3> 92
I883 I787
NO_TEST=TRUE EI_NB_TO_CPU_AD<0..43> 14 28 29
92 IN USB2_PORT1_P_F FUNC_TEST=YES 7 IN RESET_BUTTON_L FUNC_TEST=YES
C
I350 I789
FUNC_TEST=YES FUNC_TEST=YES
C I349 NO_TEST=YES TP_USB2_PWREN<4> 92
NO_TEST=YES RFBD<1> 53 54
I788 NO_TEST=YES
NO_TEST=YES
EI_NB_TO_CPU_CLK_N
EI_NB_TO_CPU_CLK_P
14 28 29
14 28 29
92
92
IN
IN
USB2_PORT2_N_F
USB2_PORT2_P_F FUNC_TEST=YES
13 8
33 13 11 10 7
IN
IN
SMU_RESET_L
SYS_POWERUP_L FUNC_TEST=YES
I884
I790
NO_TEST=TRUE EI_NB_TO_CPU_SR_N<0..1> 14 28 29
92 IN USB2_PORT3_N_F FUNC_TEST=YES 50 46 22 11 10 9 8
59 IN SYS_SLEEP FUNC_TEST=YES
NO_TEST=YES TP_NEC_NTEST1 77
I885
I792
NO_TEST=TRUE EI_NB_TO_CPU_SR_P<0..1> 14 28 29
92 IN USB2_PORT3_P_F FUNC_TEST=YES 13 8 IN SYS_POWERFAIL_L FUNC_TEST=YES
I356
NO_TEST=YES TP_NEC_SMC 77
I886
I791
NO_TEST=YES CHKSTOP_L 8 14 29
92 IN PP5V_USB2_PORT1_F FUNC_TEST=YES
I357
TP_NEC_SMI_L
I887
RFBD<6>
I793
CPU_HRESET_L
92 IN PP5V_USB2_PORT2_F FUNC_TEST=YES 9 IN U900_FEEDBACK FUNC_TEST=YES
I358 NO_TEST=YES 77 NO_TEST=YES 53 54 NO_TEST=YES 14 29 30
NO_TEST=YES TP_NEC_SRCLK 77
I888
I794
NO_TEST=YES CPU_INT_L 14 25 29 30
92 IN PP5V_USB2_PORT3_F FUNC_TEST=YES 22 IN U2200_FEEDBACK FUNC_TEST=YES
I360 I890
I795
NO_TEST=YES CPU1_HTBEN 14
59 58 IN ANALOG_RED FUNC_TEST=YES
TP_NEC_SRMOD
I889
RFBD<9>
I796
EI_CPU1_CLK_N
94 25 IN I2S1_DEV_TO_SB_DTI 2 TEST POINTS FUNC_TEST=YES 59 58 IN ANALOG_GRN FUNC_TEST=YES
I362 NO_TEST=YES 77 NO_TEST=YES 53 54 NO_TEST=YES 14 27
NO_TEST=YES TP_NEC_TEB 77
I892
I797
NO_TEST=YES EI_CPU1_CLK_P 14 27
94 25 IN I2S1_SYNC 2 TEST POINTS FUNC_TEST=YES 59 58 IN ANALOG_BLU FUNC_TEST=YES
I363
NO_TEST=YES TP_NEC_TEST 77
I891
I798
NO_TEST=YES EI_QACK_L 14 28 29
94 25 IN I2S1_BITCLK 2 TEST POINTS FUNC_TEST=YES
I361
TP_PLS_CLK_66M_0
I893
RFBD<13>
I799
EI_QREQ_L
94 25 IN I2S1_MCLK 2 TEST POINTS FUNC_TEST=YES 101 25 IN AUDIO_LO_DET_L FUNC_TEST=YES
I364 NO_TEST=YES 27 NO_TEST=YES 53 54 NO_TEST=YES 14 28 29 30
NO_TEST=YES TP_PLS_CLK_66M_1 27
I895
I800
NO_TEST=YES EI_SE 14 28 29 30
94 25 IN I2S1_SB_TO_DEV_DTO 2 TEST POINTS FUNC_TEST=YES 75 IN ROM_WP_L FUNC_TEST=YES
I365
NO_TEST=YES TP_PLS_REF_CML 27
I894
I801
NO_TEST=YES I2C_SMU_A_SCL_OUT_L 13 14 18
94 25 IN I2S1_RESET_L 2 TEST POINTS FUNC_TEST=YES
I372
NO_TEST=YES TP_PLS_TEST1 27
I897
I802
NO_TEST=YES I2C_SMU_A_SDA_OUT_L 13 14 18
94 25 IN MODEM_RING2SYS_L 2 TEST POINTS FUNC_TEST=YES 83 80 IN UATA_DD<15..0> FUNC_TEST=TRUE
I373
NO_TEST=YES TP_PLS_TEST2 27
I896
I803
NO_TEST=YES MCP_L 14 29
83 80 IN UATA_DA<2..0> FUNC_TEST=TRUE
I371
TP_PLS_TEST3
I898
RFBD<21>
I804
RI_L
83 80 IN UATA_CS0_L FUNC_TEST=YES
I374 NO_TEST=YES 27 NO_TEST=YES 53 54 NO_TEST=YES 14 29 30
NO_TEST=YES TP_SB_FSTEST 25
I900
I805
NO_TEST=YES SYNCENABLE 14 29 30
83 80 IN UATA_CS1_L FUNC_TEST=YES
I375
NO_TEST=YES TP_SB_PLLTEST 25
I899
I806
NO_TEST=YES TP_PROC_TRIGGER_OUT 14 29
83 80 IN UATA_RESET_L FUNC_TEST=YES
I376
TP_VREF_CG
I902
RFBD<24>
I807
EI_CPU1_SYNC
83 IN UATA_DSTROBE_R FUNC_TEST=YES
I377 NO_TEST=YES 48 NO_TEST=YES 53 54 NO_TEST=YES 14 27
NO_TEST=YES TP_SB_NC_P7 91
I901
I808
NO_TEST=YES CPU1_HTBEN_R 14 27
59 58 IN TMDS_CKM FUNC_TEST=YES 83 80 IN UATA_HSTROBE FUNC_TEST=YES
I378
NO_TEST=YES TP_SB_NC_P8 91
I903
I827
NO_TEST=YES EI_CPU1_SYNC_R 14 27
59 58 IN TMDS_D1M FUNC_TEST=YES 83 806 6
83 80
IN UATA_STOP FUNC_TEST=YES
I380
TP_SB_NC_R3
I904
RFBD<28>
I830
83 IN UATA_DMARQ_R FUNC_TEST=YES
I379 NO_TEST=YES 91 NO_TEST=YES 53 54
NO_TEST=YES TP_SB_NC_R4 91
I905
59 IN PPVCC_TMDS FUNC_TEST=YES 83 80 IN UATA_DMACK_L FUNC_TEST=YES
I382
I906
59 IN PP3V3_DDC FUNC_TEST=YES 83 IN UATA_INTRQ_R FUNC_TEST=YES
I383
I907
59 IN TD0M FUNC_TEST=YES 83 IN UATA_IOCS16_PU FUNC_TEST=YES
I381 I908
TD0P FUNC_TEST=YES UATA_CSEL_PD FUNC_TEST=YES
B I384
I385
NO_TEST=YES
NO_TEST=YES
TP_SB_NC_R7
TP_SB_NC_R8
91
91
I909 NO_TEST=YES
NO_TEST=YES
RFBD<33>
RFBD<35>
53 54
53 54
59 IN 83
83
IN
IN UATA_DASP_L FUNC_TEST=TRUE B
NO_TEST=YES TP_SB_NC_T1 91
I910
59 IN TD1P FUNC_TEST=YES 36 31 IN TDIODE_NEG FUNC_TEST=YES
I386
I911
59 IN TD2M FUNC_TEST=YES
I388
TP_SB_NC_T3
I912
RFBD<38>
59 IN TD2P FUNC_TEST=YES
I387 NO_TEST=YES 91 I913 NO_TEST=YES 53 54
I390 NO_TEST=YES TP_SB_NC_T4 91 NO_TEST=YES RFBD<40> 53 54
I915
59 IN TCKP FUNC_TEST=YES
I389
TP_SB_NC_T6
I914
RFBD<43>
59 6 IN I2C_TMDS_SDA FUNC_TEST=YES
I916
59 6 IN I2C_TMDS_SCL FUNC_TEST=YES
I393
I917
59 7 IN GND_CHASSIS_TMDS FUNC_TEST=YES
I392 I919
I395 NO_TEST=YES TP_SB_NC_U1 91 NO_TEST=YES RFBD<47> 53 54
NO_TEST=YES TP_SB_NC_U2 91
I918
59 IN FILT_ANALOG_RED FUNC_TEST=YES
I394
TP_SB_NC_U3
I920
RFBD<49>
59 IN FILT_ANALOG_GRN FUNC_TEST=YES
NO_TEST=YES TP_SB_NC_U4 91
I921
59 IN FILT_ANALOG_BLU FUNC_TEST=YES
I398
I397 NO_TEST=YES TP_SB_NC_U5 91 NO_TEST=YES U2200_COMP 22
TP_SB_NC_U6
I922
U2200_GATE_H
59 IN VGA_HSYNC_R FUNC_TEST=YES
I399 NO_TEST=YES 91 NO_TEST=YES 22
NO_TEST=YES TP_SB_NC_V1 91
I923
NO_TEST=YES U2200_GATE_L 22
59 IN VGA_VSYNC_R FUNC_TEST=YES
I401 I925
I400 NO_TEST=YES TP_SB_NC_V2 91 NO_TEST=YES U2200_SS 22
TP_SB_NC_V3
I924
U2200_VC
59 58 IN MON_DETECT FUNC_TEST=YES
I403 NO_TEST=YES 91 I926 NO_TEST=YES 22
I402 NO_TEST=YES TP_SB_NC_V4 91 I927 NO_TEST=YES U2200_VC_D 22
I404 NO_TEST=YES TP_SB_NC_W1 91 NO_TEST=YES U2200_VC_R 22
NO_TEST=YES TP_SB_NC_W3 91
I928
NO_TEST=YES Q5001_GATE 50
59 IN PP24V_INV FUNC_TEST=YES
I405
NO_TEST=YES TP_SB_NC_Y1 91
I930
59 IN GND_20_INV FUNC_TEST=YES
I406
TP_SB_NC_Y3
I929
U3310_DRN
59 IN INV_20_LCD_PWM_ FUNC_TEST=YES
I408
I407 NO_TEST=YES TP_SATA_CLK25M 27
I931
I932 NO_TEST=YES U3320_DRN 33

59 IN INV_20_CUR_HI_F FUNC_TEST=YES FUNC TEST
I429 NO_TEST=YES TP_USB2_PWREN<0> 92 NO_TEST=YES U3410_DRN 34
I933
FUNC_TEST=YES
A I428 NO_TEST=YES
NO_TEST=YES
TP_USB2_PWREN<1>
TP_DUMMY_A
92
24
I934 NO_TEST=YES
NO_TEST=YES
U5000_COMP
U5000_FEEDBACK
50
50
59
59
IN
IN
GND_17_INV
PP5V_AGP_RL FUNC_TEST=YES
SYNC_MASTER=N/A

SYNC_DATE=N/A
A
I431
NO_TEST=YES TP_DUMMY_B 24
I935
NO_TEST=YES U5000_GATE_H 50
59 IN INV_17_LCD_PWM_F FUNC_TEST=YES
I430 I936
I432 NO_TEST=YES TP_RAM_CKE_R<2> 8 NO_TEST=YES U5000_GATE_L 50 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
NO_TEST=YES Q2201_GATE 22
I937
NO_TEST=YES U5000_SS 50
59 IN INV_17_CUR_HI_F FUNC_TEST=YES AGREES TO THE FOLLOWING
I855 I938
NO_TEST=YES Q2202_DRAIN 22 NO_TEST=YES U5000_VC 50
I856
NO_TEST=YES R904_P2 9
I939
33 8 IN CPU_VID_R<5..0> FUNC_TEST=TRUE II NOT TO REPRODUCE OR COPY IT
I858
NO_TEST=YES R2204_P2 22
I947 NO_TEST=YES TP_SATA_RXD_N2_C 83 36 IN KPVDD2_FMAX FUNC_TEST=YES III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I857
RAM_CLK66M_NB_R I948 NO_TEST=YES TP_SATA_RXD_P2_C 83 36 IN KPGND2_FMAX FUNC_TEST=YES
NO_TEST=YES 27 SIZE DRAWING NUMBER REV.
I860
NO_TEST=YES TP_SATA_TXD_N2 TDIODE_POS_FMAX FUNC_TEST=YES
I949
I950 NO_TEST=YES TP_SATA_TXD_P2

83
83
36
36
IN
IN TDIODE_NEG_FMAX FUNC_TEST=YES D 051-6772 E
36 33 IN CORE_ISNS_M FUNC_TEST=YES APPLE COMPUTER INC.
36 33 IN CORE_ISNS_P FUNC_TEST=YES SCALE
NONE 6SHT
102 OF
8 5 4 3 2 1
7 6
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8 7 6 5 4 3 2 1
PP12V_RUN PP5V_RUN PP24V_RUN
PP5V_ALL PP3V3_RUN PP12V_RUN PP5V_RUN
PP24V_RUN RUN RAILS
CRITICAL
ONLY ON IN RUN PWRON RAILS ALL RAILS
J700 VOLTAGE=24V =PP24V_GRAPHICS 59 ON IN RUN AND SLEEP ALWAYS ON WHEN UNIT HAS AC POWER (TRICKLE)
HM96110-P2 MIN_LINE_WIDTH=0.6MM PP5V_ALL
F-RT-TH MIN_NECK_WIDTH=0.25MM
MAKE_BASE=TRUE PP5V_PWRON
1 12
2 13 PP12V_RUN 12 11 6 PP5V_ALL =PP5V_ALL_CPU 36
VOLTAGE=5V
3 14
_PP5V_PWRON_USB 92 MIN_LINE_WIDTH=0.6MM
VOLTAGE=5V MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM =PP5V_PWRON_CPU 36 MAKE_BASE=TRUE
4 15 VOLTAGE=12V MIN_NECK_WIDTH=0.2MM
5 16
=PP12V_AGP 50 59 MAKE_BASE=TRUE =PP5V_PWRON_VESTA 12
MIN_LINE_WIDTH=0.6MM PP3V3_ALL =PP3V3_ALL_SMU
D 6
7
17
18
MIN_NECK_WIDTH=0.25MM
MAKE_BASE=TRUE
=PP12V_RUN_CPU
=PP12V_DISK
33
6 83
59 11 7
MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6MM
=PP3V3_ALL_CPU
6 8 13
36 D
MIN_NECK_WIDTH=0.2MM PP3V3_VESTA
8 POWER_GOOD 8 19
XW700
SM
PP3V3_PWRON
=PP3V3_ENET
12
86 87
9 20 1 2 PP12V_AUDIO_CODEC 102 =PP3V3_PWRON_SB 23 25 74 =PP3V3_FW 89 90
10 21 VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6MM =PPPCI64_PWRON_SB =PP3V3_ENETFW
11 22
XW704
SM
MAKE_BASE=TRUE =PPPCI32_PWRON_SB
23
23
89
1 2 _PP3V3_PWRON_MODEM 94 10 PP1V2_ALL PP1V2_VESTA 12

VOLTAGE=0V MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM =PP3V3_PWRON_USB VOLTAGE=1.2V =PP1V2_ENETFW
MIN_NECK_WIDTH=0.25MM XW701
SM _PP3V3_PWRON_BT
91
76
86 89
P/N 518-0159 1 2 PP12V_AUDIO_SPKRAMP 100 =PP3V3_PWRON_CPU 36

PIN 13,19,11,22 ARE DIFFERENCE FROM ATX .
=PP3V3_PWRON_EI
XW705
SM =PP3V3_PWRON_VESTA
28
12
GND RAILS
PP3V3_ALL 1 2 =PP3V3_PWRON_RAM
59 11 7 46
XW702
SM
PP5V_RUN PP2V5_PWRON GND_AUDIO 1 2
1 C700 102
CRITICAL 20%
0.1UF 18 11 10 6 PP5V_RUN VOLTAGE=5V =PP5V_PATA 83 =PP2V5_PWRON_SB 23 25 74 88 XW706
U700 2 10V
CERM
MAKE_BASE=TRUE
=PP5V_DISK 6 83
VOLTAGE=2.5V
MIN_LINE_WIDTH=0.6MM =PP2V5_PWRON_RAM 26 37 40 46
1
SM
2
74LCX125 402 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
14 MIN_NECK_WIDTH=0.25MM =PP5V_AGP 50 59 MAKE_BASE=TRUE =PP2V5_HT 60 64
33 13 11 10 6 SYS_POWERUP_L 2 3 SYS_POWERUP_L_BUF =PP5V_RUN_CPU 3 6 8 31 =PP2V5_PWRON_HT 62
7
125
1 TSSOP
PP5V_AUDIO 101 =PP2V5_ENET 87 XW703
SM
102 100 GND_AUDIO_SPKRAMP 1 2
PP1V5_PWRON
PP3V3_RUN XW707
SM
=PP1V5_PWRON_NB_AVDD 28 37 48 60
VOLTAGE=3.3V MAKE_BASE=TRUE 1 2
50 34 22 18 11 10 6 PP3V3_RUN =PP3V3_AGP 48 50 56 59 =PPVCORE_PWRON_PULSAR 26
MIN_LINE_WIDTH=0.3MM VOLTAGE=1.5V
PP5V_ALL PP3V3_PWRON PP3V3_RUN MIN_NECK_WIDTH=0.2MM PP3V3_AUDIO 95 100 101 102 MIN_NECK_WIDTH=0.25MM =PPVCORE_NB 22
C R710 R700
DEVELOPMENT
MAKE_BASE=TRUE
=PP3V3_RUN_CPU 33
CHASSIS GND C
330 330 R701 =PP3V3_PATA 83
ZH700
1 2 ITS_PLUGGED_IN 1 2 ITS_ALIVE
1
330 2 ITS_RUNNING
=PP3V3_SB_PCI 74
5% 5%
6
=PP3V3_PCI 25 74 75 76 77
315R138
1/10W 1/10W 5% 102 101 GND_CHASSIS_AUDIO_EXTERNAL 1
MF-LF 1 MF-LF 1 1/10W DEVELOPMENT =PPVIO_PCI_USB2 77 MIN_NECK_WIDTH=0.25MM
603 LED702 603 LED700 MF-LF 1
MAKE_BASE=TRUE
GREEN GREEN
603 LED701 =PP3V3_DISK 83 VOLTAGE=0
2.0X1.25A 2.0X1.25A GREEN MIN_LINE_WIDTH=0.6MM
2 2
2.0X1.25A PP1V2_PWRON
2
PP2V5_RUN
SILKSCREEN:1 SILKSCREEN:2 SILKSCREEN:RUN MAKE_BASE=TRUE 59 GND_CHASSIS_VGA
=PP1V2_PWRON_HT 62
VOLTAGE=2.5V MIN_LINE_WIDTH=0.6MM 92 GND_CHASSIS_USB
PP2V5_GPU 52 54 55 MIN_NECK_WIDTH=0.25MM =PP1V2_PWRON_DISK_SB 80
MAKE_BASE=TRUE VOLTAGE=1.2V 90 GND_CHASSIS_FIREWIRE
=PP1V2_PWRON_SB
L700 MIN_LINE_WIDTH=0.6MM =PP2V5_RUN_CPU 31
=PPVCORE_PWRON_SB
25
FERR-EMI-100-OHM MIN_NECK_WIDTH=0.25MM
=PP2V5_RUN_RAM 44 45
3 6 23
1 2 SYS_PWR_BTN_FILT CRITICAL
13 7 6 SYS_POWER_BUTTON_L 59 6 GND_CHASSIS_TMDS
SM SW703 MIN_NECK_WIDTH=0.25MM
PWR-BUTT VOLTAGE=0 ZH710
ST-SM3 PP1V5_RUN 315R138
1
1 C703 1 SILKSCREEN:POWER
=PP1V5_AGP
ZH702
0.1UF 3 VOLTAGE=1.5V
48 49 50 7R4.15
20% MAKE_BASE=TRUE =PPVCORE_PULSAR 26 87 GND_CHASSIS_RJ45 1
10V 2
2 CERM 516S0248 MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM
MIN_NECK_WIDTH=0.25MM =PP1V2_EI_CPU MIN_LINE_WIDTH=0.6MM
402 FOXCONN
=PP1V2_EI_NB
14 18 29 30 31
VOLTAGE=0 SH700
L701 4 5
14 18 28
GND_CHASSIS_AUDIO_INTERNAL
FERR-EMI-100-OHM 101
MAKE_BASE=TRUE 1 4
1 2 SHLD-IO-CONN
GND_SYS_PWR_BTN_FILT 21 GND_CHASSIS_LED Q45-TH1
2 3
SM
35 34 33 6 PPVCORE_CPU =PPVCORE_CPU 29 31 32 36
MAKE_BASE=TRUE
B ZH703 805-5664
B
6.00MM-PTH
PP1V2_RUN 59 GND_CHASSIS_17_INCH_INVERTER 1
VOLTAGE=0 NOSTUFF
=PP1V2_HT 24 60
VOLTAGE=1.2V
MAKE_BASE=TRUE SDF700
MIN_LINE_WIDTH=0.5MM =PP1V2_PULSAR 26 HSK-NUT-6.5MM
MIN_NECK_WIDTH=0.25MM TH
R713
1K
NOSTUFF
R720 59 GND_CHASSIS_20_INCH_INVERTER 1
13 7 6 SYS_POWER_BUTTON_L 1 2 POWER_BUTTON_L 6 0 MIN_LINE_WIDTH=0.6MM
1 2 PPVCORE_GPU 22 50 51 VOLTAGE=0
5% SDF700 IS USED FOR CPU HEATSINK MOUNTING
DEVELOPMENT 1/16W 5%
MF-LF 1/8W
R712 402 MF-LF
805
13 SYS_RESET_BUTTON_L 1
1K 2 RESET_BUTTON_L 6
NOSTUFF RTC BATTERY
5%
DEVELOPMENT R703 ALWAYS ON (TRICKLE)
1/16W
MF-LF
SW701 SW702 1
0 2
402 SPST SPST CRITICAL
SM SM 5%
1 2 1 2
1 C705 1 C704 DS700 1/16W
MF-LF
R702 J702
0.1UF 0.1UF SOD-123 402 BB10209-A5
20% 20% 2 1PP3V3_ALL_BATT_SAFETY 1
1K 2
10V 10V 13 =PP3V3_ALL_RTC PP3V3_ALL_RTC PP3V3_ALL_BATT 1 2
2 CERM 2 CERM VOLTAGE=3.3V VOLTAGE=3.3V VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6MM MIN_LINE_WIDTH=0.6MM 5% MIN_LINE_WIDTH=0.6MM
402 402 MIN_NECK_WIDTH=0.2MM B0530WXF MIN_NECK_WIDTH=0.2MM 1/16W MIN_NECK_WIDTH=0.2MM TH
3 4 3 4 MAKE_BASE=TRUE MF-LF
402
RESET POWER
POWER CONN / ALIAS
A 8 6 SMU_MANUAL_RESET_L
DEVELOPMENT
SYNC_MASTER=N/A

SYNC_DATE=N/A
A
SW700
SPST THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
SM PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
1 2 AGREES TO THE FOLLOWING
3 4
D 051-6772 E
APPLE COMPUTER INC.
SMU RESET SCALE SHT OF
NONE 7 102
8 5 4 3 2 1
7 6
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8 7 6 5 4 3 2 1
PCI CLOCKS
TP_NB_THMI NB_THMI 24 PCI_CLK33M_USB2 PCI_CLK_GP0 27
MAKE_BASE=TRUE MAKE_BASE=TRUE
TP_THMO NB_THMO 24 =PCI_CLK33M_USB2 77 ELECTRICAL_CONSTRAINT_SET NET_SPACING_TYPE DIFFERENTIAL_PAIR
MAKE_BASE=TRUE
6 TP_RAM_CKE_R<2> RAM_CKE_R<2> 37 I246 SMU_RESET P25MM SYS_COLD_RESET_L 13 24
MAKE_BASE=TRUE TP_PCI_CLK_GP1 PCI_CLK_GP1 27
MAKE_BASE=TRUE I247 SMU_RESET P25MM SYS_WARM_RESET_L 8 25 74 77
6 TP_RAM_CKE_R<3> RAM_CKE_R<3> 37
MAKE_BASE=TRUE 6 PCI_CLK33M_AIRPORT PCI_CLK_P3 27
MAKE_BASE=TRUE
6 TP_RAM_CKE_R<6> RAM_CKE_R<6> 37 _PCI_CLK33M_AIRPORT 76
MAKE_BASE=TRUE
6 TP_RAM_CKE_R<7> RAM_CKE_R<7> 37 6 TP_PCI_CLK_P4 PCI_CLK_P4 27
6 TP_RAM_MUXEN0 RAM_MUXEN0 37 74 27 PCI_CLK33M_SB_EXT PCI_CLK_P1 27
MAKE_BASE=TRUE MAKE_BASE=TRUE PP2V5_PWRON
D 6 TP_RAM_MUXEN4 RAM_MUXEN4 37 D
6
MAKE_BASE=TRUE
TP_RAM_CS_L_R<2> RAM_CS_L_R<2> 37
SMU
MAKE_BASE=TRUE
TP_ALS0_OUT ALS0_OUT 13
R870
1
6 TP_RAM_CS_L_R<3> RAM_CS_L_R<3> 37 MAKE_BASE=TRUE 4.7K DEVELOPMENT

MAKE_BASE=TRUE 5%
6 TP_RAM_CS_L_R<10>
MAKE_BASE=TRUE
RAM_CS_L_R<10> 37 TP_ALS1_OUT
MAKE_BASE=TRUE
ALS1_OUT 13
1/16W
MF-LF U700 J800
2 402 14 74LCX125 U.FL-R_SMT
6 TP_RAM_CS_L_R<11> RAM_CS_L_R<11> 37 TP_ALS_GAIN_BOOST ALS_GAIN_BOOST 13 F-ST-SM
MAKE_BASE=TRUE MAKE_BASE=TRUE 13 8 SMU_WARM_RESET_L 9 8 SYS_WARM_RESET_L 8 25 74 77
3
TP_SMU_ONEWIRE SMU_ONEWIRE 13
125
PP5V_ALL MAKE_BASE=TRUE 7 10 TSSOP
24 NB_PMR_OBSV 1
TP_SYS_SLOT_PWR SYS_SLOT_PWR
DIAG LED MAKE_BASE=TRUE
13
U700
R850
1 TP_SMU_PWRSEQ_P1_3 SMU_PWRSEQ_P1_3 13 14 74LCX125 2
MAKE_BASE=TRUE
180 13 SMU_SLEEP 5 6 SYS_SLEEP 6 9 10 11 22 46 50 59
5% TP_SYS_DOOR_AJAR_L SYS_DOOR_AJAR_L 13
125 518S0104
1/16W MAKE_BASE=TRUE
MF-LF 7 4 TSSOP
2 402
TP_FAN_PWM8 FAN_PWM8 13
MAKE_BASE=TRUE
LED850P1
TP_SYS_DRIVE_BAY_INT_L
MAKE_BASE=TRUE
SYS_DRIVE_BAY_INT_L 13 U700
1 14 74LCX125
LED850 13 8 SMU_WARM_RESET_L
MAKE_BASE=TRUE
NB_WARM_RESET_L 24
NB_SUSPEND_ACK_L 12 11 NB_SUSPENDACK_L
RED-4.0MCD 24 13
SM 125
2 7 13 TSSOP
74 56 6 PCI_RESET_L PCI_AIRPORT_RESET_L 76
LED850P2 MAKE_BASE=TRUE
R851 3
GPU_RESET_L
=PCI_ROM_RESET_L
49
75
SMU ANALOG VREF POWER_FAIL_L
13 DIAG_LED 1
1K 2 DIAG_LED_R 1 Q850 =PCI_USB2_RESET_L 77 CONNECTION
MAKE_BASE=TRUE PP3V3_ALL_SMU_AVCC
5% 2N3904LF 13
PP3V3_ALL
1/16W SOT23
MF-LF
402
2 PP3V3_RUN DOWNLOAD 7 POWER_GOOD
NOSTUFF
C CONNECTOR NOSTUFF 1
R813 1R812
430 10K
C
R818
1
5% 5%
CPU VID<0:5> PP3V3_ALL 200
1%
1/16W
1/16W
MF-LF
2 402
1/16W
MF-LF
2 402
1
R814 1
R816 1
R817 1
R808 R809
1 1
R804 J802
HC17051
MF-LF
2 402
VID CONTROLLED BY SMU 10K 10K 10K 10K 10K 10K M-ST-TH R826 SYS_POWERFAIL_L 6 13
5% 5% 5% 5% 5% 5% PPVREF_SMU =PPVREF_SMU 13
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 100 MAKE_BASE=TRUE
MF-LF
2 402
MF-LF
2 402
MF-LF
2 402
MF-LF
2 402
MF-LF
2 402
MF-LF
2 402
1 2 J802_2 2 1 SMU_BOOT_BUSY 13 NOSTUFF 1
R860
R819 13 SMU_BOOT_SCLK 3 4 5%
1/16W
SMU_BOOT_RXD 13 C801 1
R802 5%
4.7K POWER_GOOD IS A 5V DRIVEN
0 13 SMU_BOOT_CE 5 6 J802_6 MF-LF (SMU_BOOT_EPM) 2.2UF 0 1/16W SIGNAL FROM POWER SUPPLY
13 CPU_VID<0> 1 2 CPU_VID_R<0> 6 33 402 20% 1 2 PPVREF_SMU_ADC_REF 36 MF-LF
7 8 SMU_MANUAL_RESET_L 10V NOSTUFF
6 7 8 CERM 2 2 402
5%
R820 5%
1
SMU_BOOT_CNVSS 9 10 SMU_BOOT_TXD 805
VR801
1/16W 13 13 1/16W 2K PULLUP INSIDE P/S
MF-LF 0 MF-LF
SSOT-23
2.5V
13 CPU_VID<1> 402 1 2 CPU_VID_R<1> 6 33 402
NOSTUFF NOSTUFF
R821 5%
1/16W R8061 1NOSTUFF
R807
518-0158
R805 1 1
R803 1 C802
0 MF-LF
0.47UF
13 CPU_VID<2> 1 2 402 CPU_VID_R<2> 6 33 10K5%
10K
5% 5%
0 10K
5% 20%
2
3
10V
5%
1/16W R822 1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
2 CERM
603
MF-LF 0 402 2 2 402 402 2 2 402
13 CPU_VID<3> 402 1 2 CPU_VID_R<3> 6 33
R823 5%
1/16W
GND_SMU_AVSS 13 33 36
CPU_VID<4> 1
0 2
MF-LF
402 CPU_VID_R<4>
13 6 33 NOSTUFF
5%
R824 J802 & R826 CAN MOVE TO DEVELOPMENT BOM POST RAMP R828
1/16W 0
CPU_VID<5>
MF-LF
402 1
0 2 CPU_VID_R<5>
1 2 GND_SMU_AVSS_DAGND 36
13 6 33
5%
5% 1/16W
1/16W
MF-LF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF
PLL LOCK LED CHKSTOP LED MF-LF
402 CPU HEATSINK SMT NUTS
402
R832
1
R831
1
R830
1
R829
1
R827
1 1
R811
BM12B-SRSS-TB
NOSTUFF NOSTUFF NOSTUFF

1K 1K 1K 1K 1K 20K 31 8 7 6 3 =PP5V_RUN_CPU
=PP5V_RUN_CPU
SDF800 SDF801 SDF802
B
5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W
31 8 7 6 3
B
NOSTUFF
HSK-NUT-6.5MM HSK-NUT-6.5MM HSK-NUT-6.5MM

14
10
11
12
13
J803
MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF

F-ST-SM
1
2
3
4
5
6
7
8
9
2 402 2 402 2 402 2 402 2 402 2 402 TH TH TH

DEVELOPMENT
1
DEVELOPMENT
R837DEVELOPMENT R833
1 HS_SDF800 1 HS_SDF801 1 HS_SDF802 1
180
180 5%
NOTE:PULL UP CPU_VID<5>TO 5%
1/16W Q802 1/16W
MF-LF
2.2V FOR CPU VRM10. MF-LF 2N3906
SM
2
2 402
1 C880 1 C881 1 C882
2 402 0.01UF 0.01UF 0.01UF
6 Q802_B 1 6 LED801_1 20% 20% 20%
16V 16V 16V
DEVELOPMENT 2 CERM 2 CERM 2 CERM
1 402 402 402
3 LED801
Q802_E DEVELOPMENT RED-4.0MCD NOSTUFF
BACKUP SMU RESET CIRCUIT PULSAR ERROR_L LED DEVELOPMENT
6
R834
1 SM
R838
1 DEVELOPMENT 180
2 SDF803 OMIT
PP3V3_RUN 1K
1
R835 5%
1/16W
6 Q800_D HSK-NUT-6.5MM
TH
ZH804
5% 180 MF-LF 3 6P15R5P4
=PP3V3_ALL_SMU 1/16W 5%
13 7 6
MF-LF 1/16W 2 402 DEVELOPMENT HS_SDF803 1 HS_SDF804 1
NOSTUFF 2 402 MF-LF
2 402
D
Q800 SDF700 IS ALSO
2N7002
C800 1 NOSTUFF DEVELOPMENT Q803_C
LED802_1 Q800_G 1 G S
SOT23-LF 1 C883 1 C884
USED FOR HEATSINK
0.1uF
20%
1
R890
DEVELOPMENT DEVELOPMENT 6 6
0.01UF 0.01UF
MOUNTING
10V
CERM 2
2 1K R8011 1
R800 R839 3
DEVELOPMENT 1
DEVELOPMENT
2 20%
16V
20%
16V
5% 4.7K 330 180 LED802 DEVELOPMENT 2 CERM 2 CERM
402
VCC 1/16W
MF-LF
5%
1/16W
5%
1/16W
29 PLLLOCK 1 2 Q803_B 1 Q803 GREEN R836 3
402 402
2 402 MF-LF MF-LF 5% 2N3904LF 2.0X1.25A 180 DEVELOPMENT
U890 402 2 2 402
1/16W
MF-LF 2
SOT23 2 29 14 6 CHKSTOP_L 1 2 1 Q801
SM 402 5% 6 Q801_B 2N3904LF
ERROR_LED 6 1/16W SOT23
8 7 6 SMU_MANUAL_RESET_L 5 DELAY NOSTUFF RESET 1 SMU_RESET_L 6 13 MF-LF 2
402
NOSTUFF
C890 1 VOLTAGE DETECTOR 1
NOSTUFF
C891
1 DEVELOPMENT
D810 SIGNAL ALIAS
0.01UF MC33465N_30ATR 1uF RED-4.0MCD
A 10%
16V
CERM 2
GND
10%
6.3V
2 CERM 2
SM SYNC_MASTER=N/A

SYNC_DATE=N/A
A
402 402 CLOCK_ERROR_L
3 27
VESTA JTAG SHASTA JTAG PULL DOWN THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
R810 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
0 JTAG_VESTA_TRST_L =JTAG_VESTA_TRST_L 12
1 2 MAKE_BASE=TRUE 25 JTAG_SB_TRST_L I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
5% II NOT TO REPRODUCE OR COPY IT
1/16W THESE PINS HAVE INTERNAL PULLUPS
MF-LF
402
TP_JTAG_VESTA_TCK
MAKE_BASE=TRUE
=JTAG_VESTA_TCK 12 1
R840 TP_JTAG_SB_TCK JTAG_SB_TCK 25 1
R825 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
TP_JTAG_VESTA_TDI =JTAG_VESTA_TDI 12 1K MAKE_BASE=TRUE
TP_JTAG_SB_TDI JTAG_SB_TDI 10K
MAKE_BASE=TRUE 5% 25 SIZE DRAWING NUMBER REV.
TP_JTAG_VESTA_TDO =JTAG_VESTA_TDO 12 1/16W MAKE_BASE=TRUE 5%
MAKE_BASE=TRUE
TP_JTAG_VESTA_TMS =JTAG_VESTA_TMS 12
MF-LF
2 402
TP_JTAG_SB_TDO
MAKE_BASE=TRUE
TP_JTAG_SB_TMS
JTAG_SB_TDO
JTAG_SB_TMS
25 1/16W
MF-LF D 051-6772 E
MAKE_BASE=TRUE 25
2 402 APPLE COMPUTER INC.
MAKE_BASE=TRUE
SCALE SHT OF
NONE 8 102
8 5 4 3 2 1
7 6
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8 7 6 5 4 3 2 1
D D
2.5V VOLTAGE REGULATOR
PP5V_PWRON
PP5V_PWRON
D900 NOTE:
2 1 SET OUTPUT=2.588V FOR FRAMEBUFFER.
MBR0520LXXG
1
D902
1 C901 1 C911 1
C902 1
C903 1
C910 IRU3037CS VREF=1.25VDC
R900
1 SOD-123 10UF 10UF 1800UF 1800UF 1800UF VOUT=VREF*(R903+R905)/R905=2.588VDC
MBR0520LXXG 20% 20% 20% 20% 20%
4.7 SOD-123 2 6.3V
CERM 2 6.3V
CERM 2 6.3V 2 6.3V 2 6.3V
5% 2 ELEC ELEC ELEC
1/8W
MF-LF
D901 1206 1206 TH-KZJ TH-KZJ TH-KZJ PEAK CURRENT OF TOTAL RAILS
2 805
6 U900_VC_R 2 1 6 U900_VC_D 12.68A WITH DIMM TERMINATION
MBR0520LXXG
9.24A WITHOUT DIMM TERMINATION
U900_VC SOD-123
1 C904 6
1 C916
1UF
20% 1UF D 4
2 25V
CERM
2 6 20%
25V
R902 Q901 1 C917
805 VCC VC 2 CERM 0 NTD60N02R 1UF PP2V5_PWRON
805
1 2 6 Q901_GATE 1
CASE369 20%
U900 5%
G 10V
2 CERM
IRU3037CS 1/8W
MF-LF
S3
603 CRITICAL
SOI
HD 5 U900_GATE_H
805 L901
6
1.53UH
6 U900_SS 8 SS MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM6 Q902_DRAIN 1 2
C 6 U900_COMP 7 COMP
LD 3 6 U900_GATE_L
NOSTUFF TH
VOLTAGE=2.5V
C
FB 1 U900_FEEDBACK
1
R904 NOSTUFF
R903
1
6
1.1K 1 C907 10.7K
PP12V_RUN
R901
1
GND
5%
1/4W 3300PF 1%
27.4K D 4 MF-LF 10% 1/16W
2 50V
1%
1/16W
4
Q902 2 1206 CERM
603
MF-LF
2 402
MF-LF
2 402
1 NTD60N02R R904_P2 1
C908 1
C909 R940
1
1 C915 1 C913 1 C906 G
CASE369
6
NOSTUFF 1500UF 1500UF 470K

5%
0.47UF R901_P2 56PF 220PF S3 20% 20% 1/16W 5 6 7 8
20%
10V
2 CERM
5%
50V
2 CERM
5%
25V
2 CERM
1 C905 1 C912 2 4V
ELEC
2 4V
ELEC
MF-LF
C914 2200PF 1UF 2 402 Q903
603
1
3900PF
402 402 5%
50V
20%
25V
R905
1 TH-KZV TH-KZV
5% 2 CERM 2 CERM 10K HIGH TO ENABLE IRF7413

1% SO-8
2 50V
CERM
603 1206 1/16W 4
603 MF-LF Q903_GATE
2 402
NOSTUFF
1 C940 1 2 3
PP2V5_RUN
0.001UF
U900_FEEDBACK 20%
2 50V
CERM
402
DEVELOPMENT
1
R950
240
5%
1/16W
MF-LF
2 402
3
LED_PP2V5_RUN
D
Q940
2N7002
1 SOT23-LF DEVELOPMENT
59 50 46 22 11 10 8 6 SYS_SLEEP G S 1
LED900
B 2 GREEN
2.0X1.25A
B
2
2.5V VREG
A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
D 051-6772 E
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NONE 9 102
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PP1V2_ALL VOLTAGE REGULATOR

PP5V_ALL
PP5V_ALL
D1000 NOTE:
SET OUTPUT=1.2V
D
2 1
1 IRU3037ACS VREF=0.8VDC D
MBR0520LXXG D1002 C1001 C1002 C1003 VOUT=VREF*(R1003+R1005)/R1005=1.206VDC
1
R1002 SOD-123
MBR0520LXXG
10UF 10UF
1
10UF
1 1
4.7 SOD-123
5%
1/8W D1001 2 20% 20% 20%
2 6.3V 2 6.3V 2 6.3V
PEAK CURRENT OF TOTAL RAILS
MF-LF
U1000_VC_R 2 1 U1000_VC_D
CERM
1206
CERM
1206
CERM
1206 ~3A <-- NEED TO VERIFY
2 805
U1000_VC
MBR0520LXXG
SOD-123
1 C1004 1 C1000
1UF 1UF D 4
20%
2 25V
CERM
2 6 20%
25V
R1000
0 Q1001 1 C1017
805 VCC VC 2 CERM
805 1 2 Q1001_GATE 1 NTD60N02R 1UF
U1000 5% G
CASE369 20%
2 10V
IRU3037ACS 1/8W
MF-LF
S3 CERM
603 PP1V2_ALL 7 10
SOI
HD 5 U1000_GATE_H
805 L1001
1.53UH
VOLTAGE=1.2V
8 MIN_NECK_WIDTH=0.25MM
U1000_SS SS MIN_NECK_WIDTH=0.2MM
LD 3 U1000_GATE_L
NOSTUFF TH
U1000_COMP 7 COMP 1
R1004 NOSTUFF 1
C1009 1
C1010 1 C1020 1 C1021
C1007 R1003
FB 1 U1000_FEEDBACK 1
6
1.1K 1 1800UF 1800UF 10UF 10UF
1
R1001 GND
5%
1/4W 3300PF5.62K
1%
20%
2 6.3V
20%
2 6.3V
20%
2 6.3V
20%
2 6.3V
27.4K D 4 MF-LF 10% 1/16W ELEC ELEC CERM CERM
2 50V TH-KZJ TH-KZJ 805 805
1%
1/16W 4 Q1002 2 1206 CERM
603
MF-LF
2 402
MF-LF 1 NTD60N02R R1004_P2
1 C1015 2 402 1 C1013 1 C1006 G
CASE369
0.1UF R1001_P2 68PF 220PF S3 NOSTUFF
20%
2 16V
5%
2 50V
5%
2 25V
1 C1005 1 C1012
CERM
603
1 C1014 CERM
603
CERM
402
2200PF
5%
1UF
20%
1
R1005
3900PF
5% 2 50V
CERM 2 25V
CERM 10K
1%
2 50V 603 1206
C CERM
603
1/16W
MF-LF
2 402
C
U1000_FEEDBACK
PP1V2_PWRON FET SWITCH PP1V2_RUN FET SWITCH

PEAK CURRENT ??A PEAK CURRENT ??A
PP5V_RUN 6 7 11 18
PP3V3_RUN
10 7 PP1V2_ALL PP1V2_RUN 6 7 10 11 18 22 34 50
DEVELOPMENT
PP1V2_ALL PP1V2_PWRON 1
R1050
10 7
Q1003 DEVELOPMENT
330
PP5V_ALL SI3446DV 50 34 22 18 11 10 7 6 PP3V3_RUN 1 C1050 5%
TSOP 1 0.1UF
20%
1/16W
MF-LF
1
2
5
6
2 DEVELOPMENT 2 10V 2 402

CERM
R1008 5
R1051 1 402 LED_PP1V2_RUN_P
Q1006 100K
2 1 Q1003_G 3 6 100K
B PP3V3_ALL PP5V_ALL SI3446DV
TSOP
RDSON=0.06 OHM
@ VGS=2.5 V
5%
1/16W 4 DEVELOPMENT
5%
1/16W
MF-LF 1
DEVELOPMENT B
MF-LF 402 2 LED1000
402 R1053 3
DEVELOPMENT GREEN
0 1 2 PP1V2_RUN_FOR_LED 4 LM339A
2.0X1.25A
3
2
SOI
R1009
100K
5%
1/16W
MF-LF U1001
V+
2 LED_PP1V2_RUN_N
RDSON=?? OHM
2 1 Q1006_G 402 GND
R10141 5%
@ VGS=?? V 50 34 22 1V1_REF 5
PLACE LED1000 NEAR VREG
100K 1/16W
MF-LF 3 12
5% DEVELOPMENT
1/16W 402
MF-LF
402 2 R1012
D
Q1005
2N7002
R1052 1
0 SOT23-LF
47K
5%
3 TURN_ON_PP1V2_PWRON_L 1 2 Q1005_G 1 G S 1/16W
MF-LF
5%
1/16W 2 Q1004 3 6
Q1004 402 2
MF-LF
402
2N7002DW D D 2N7002DW
NOSTUFF SOT-363 SOT-363
R1013 5 G S S G 2 SYS_SLEEP 6
33 13 11 7 6 SYS_POWERUP_L 1
0 2
8 9 11 22 46 50 59
4 1
5%
1/16W
MF
402-1
1.2V VREG
A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
D 051-6772 E
APPLE COMPUTER INC.
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NONE 10 102
SHT OF
8 5 4 3 2 1
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8 7 6 5 4 3 2 1
12 11 7 6 PP5V_ALL
D D
CRITICAL
Q1100
SI4467DY
SM-1 PP5V_PWRON 6 18
18 10 7 6 PP5V_RUN 8 VOLTAGE=5V
3 PP5V_PWRON MIN_LINE_WIDTH=0.6MM
D S 2
6
1
5
G
1
R1107 1R1101 50 34 22 18 10 7 6 PP3V3_RUN
R1100 FET ON IN RUN 1K 1K Q1102
59 11 7 PP3V3_ALL
1
100K 2 4 1% 1% SI4467DY
1/16W 1/16W
MF-LF MF-LF SM-1 PP3V3_PWRON 6 18 27 58
R1104 5%
1/16W
3 CRITICAL
LM339A
2 402 2 402 8 VOLTAGE=3.3V
SYS_POWERUP_L 1
100K 2 MF-LF
402
10
7
SOI
33 13 10 7 6
V+
13 6
D S 2
5%
1/16W R1103 U1100 RAIL_RUN_FET
MIN_LINE_WIDTH=0.5MM 1
MF-LF
1
100K 2 11 GND MIN_NECK_WIDTH=0.2MM 5
SYS_SLEEP 402
59 50 46 22 10 9 8 6
RUN -> LOW G
5% 12 SLEEP -> FLOAT FET ON IN RUN
1/16W SHUTDOWN -> FLOAT
MF-LF 4
402
RAIL_CTL_POS CRITICAL
4
3
LM339A
Q1103
SI3443DV
V+ SOI TSOP 1
2
3 RAIL_CTL_NEG U1100 RAIL_SLEEP_FET
5 GND MIN_NECK_WIDTH=0.2MM 5
CRITICAL 3 6
12
R11021 Q1101
SI3443DV
C 47.0K
1%
1/10W
MF-LF
RUN -> FLOAT
SLEEP -> LOW
SHUTDOWN -> FLOAT
TSOP 1
4
C
603 2 2 FET ON IN SLEEP
5
3 6
12 11 7 6 PP5V_ALL 4
PP3V3_ALL 7 11 59
VOLTAGE=3.3V
FET ON IN SLEEP MIN_LINE_WIDTH=0.6MM
PROCESS SWING
CRITICAL 1 3.30V - 3.45V
SENSE
VR1100
CS5253
Vpwr >= Vout+0.35V 5 SM 3 Vout=Vref(1+R2/R1)+Iadj(R2)
VPWR VOUT Vref=1.250V typ
Vctrl >= Vout+1.25V 4 VCTRL VOUT 6 R1105
1 Iadj=50uA typ
TAB 124
ADJ R1 1%
1/10W
1
C1100
MF-LF 100UF
20%
2 2 603 2 10V
3_3V_ALL_ADJ ELEC
MIN_LINE_WIDTH=0.5MM SM
1
C1102 1 C1101 R1106
1
47UF 0.1UF 210

N20P80% R2 1%
20% 1/10W
16V
2 16V 2 CERM MF-LF
ELEC
SM 603 2 603
B B
5V & 3.3V VREGS

A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
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Page Notes
Power aliases required by this page:
Signal aliases required by this page:

(NONE)
BOM options provided by this page:
- VESTA1V2_BURST / VESTA1V2_PULSE
Controls operating mode of Vesta 1.2V
D regulator. If both options are off the
regulator will be in continuous mode.
D
Ethernet LowPwr
ETHERNET PORTION IN LOW POWER MODE
WHEN NOT IN RUN MODE.
=PP3V3_PWRON_VESTA
PP3V3_VESTA 7 12
2.5V LDO
7
NOSTUFF 1
R1262
10K PP2V5_VESTA 12
CRITICAL VOLTAGE=2.5V
7 =PP5V_PWRON_VESTA 1
R1260
2.0K
5%
1/16W U1280 MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
5%
MF-LF
2 402
MM1572FN MAKE_BASE=TRUE
R1263
4.7K
1 1/16W
MF-LF
VESTA_ENET_LOWPWR
12 7 PP3V3_VESTA
SOT-25A
=PP2V5_ENETFW 86 89
5% 2 402 86
1 VIN VOUT 5
1/16W
MF-LF
402 2 3 CONT NOISE 4 VESTA2V5_NOISE
Vout = 2.5V @ 150 mA
3
1 C1260 MIN_LINE_WIDTH=0.2 mm
10UF
20% C1280 1 2
GND
C1281 1 1 C1282
VESTA_ENET_HIGHPWR 1 Q1260
2N3904LF
2 6.3V
CERM
805
1uF 10%
6.3V 2
0.01uF 20%
16V
10UF
10%
NOSTUFF CERM 2 2 6.3V
1
R1261
1K
1 C1261 2
SOT23 CERM
402 402
X5R
805
5% 20%
0.1UF
1/16W
MF-LF 2 10V
CERM
2 402 402
C PP5V_ALL 6 7 11 C
12 7 PP3V3_VESTA
1
R1265
330
5%
1
R1264 1/10W
MF-LF 3
100K 2 603
5%
1/16W 12 Q1271_B 1 Q1271
2
MF-LF
402 3
2N3904LF
SOT23
2
D
Q1270
2N7002
1 SOT23-LF
Q1270_G G S
2
1 C1270
1UF
10%
2 6.3V
CERM
402
PP2V5_VESTA 12
L1200
FERR-EMI-600-OHM
PP1V2_VESTA_AVDDL
PP1V2_VESTA
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.5 mm C1220 1 C1221 1 C1222 1 C1223 1 C1224 1 C1225 1
B 1
SM
2 MIN_NECK_WIDTH=0.25 mm 0.1uF 0.1uF
20%
10V
0.1uF 0.1uF
20%
10V
0.1uF 0.1uF 20%
10V
20%
10V
20%
10V
20%
10V
B
CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2
1 C1208
10UF
C1200
0.1uF
C1201
1
0.1uF
C1202
0.1uF
C1203
0.1uF
1 1 1 402 402 402 402 402 402
10% 20% 20% 20% 20%

2 6.3V
X5R 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
805 402 402 402 402
L6/M6 L9/M9 N5/N6 N9/N10
C1230
0.1uF
1 C1231 1
0.1uF
20% 20%
10V 10V
CERM 2 CERM 2
B15
C15
N10
P10
P11
R12
A15
402 402
C1210 1 C1211 1 C1212 1 C1213
B1
J1
L6
L9
M6
M9
N5
N6
N9
P4
P5
R3
N4
1
0.1uF
20%
0.1uF 0.1uF
20%
0.1uF 20% 20% DVDD AVDDL AVDD PVDD
PP3V3_VESTA 7 12
2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
402 402 402 402
A1 C1240
0.1uF
1 C1241 1 C1242 1 C1243 1
0.1uF 0.1uF 0.1uF
A7 20% 20% 20% 20%
OVDD
10V 10V 10V 10V
F15 CERM 2 CERM 2 CERM 2 CERM 2
12 7 PP3V3_VESTA VESTA_RESET_L
Schmitt trigger
H4 RESET* VESTA MISC K1
402 402 402 402
NO STUFF
PP3V3_VESTA
R1251
82K
1 12 7
8 =JTAG_VESTA_TDI
=JTAG_VESTA_TDO
D7
E10
TDI
TDO
OMIT
5%
1/16W R1252
4.7K
1 8
8 =JTAG_VESTA_TCK E7 TCK U8600 2.5V_EN M3 TP_VESTA_2_5V_EN

MF-LF
402 2 5% =JTAG_VESTA_TMS E8 TMS BCM5462
R1253 1/16W
8
FBGA-200
MF-LF =JTAG_VESTA_TRST_L D8 TRST* 1 OF 3
REGSUP1 E1
8
0 402 2 TP_VESTA_REGSUP1
12 Q1271_B 1
402
2
B9 DNC
REGSEN1 F1 TP_VESTA_REGSEN1 Vesta Core / Misc
NO STUFF TP_VESTA_DNC_B9 REGCTL1 G5 TP_VESTA_REGCTL1
A
3 R1252 to enable wirespeed feature SYNC_MASTER=N/A SYNC_DATE=N/A
NO STUFF VESTA_RESET_H 1 Q1250

1 C1250
20%
10UF
TP_VESTA_DNC_C9
TP_VESTA_DNC_E9
C9 DNC
E9 DNC NOTICE OF PROPRIETARY PROPERTY
A
R1254 2N3904LF 2 6.3V
CERM REGSUP2 E2 TP_VESTA_REGSUP2
0 SOT23 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
25 ENETFW_RESET 1 2 2
805 NC C3 NC REGSEN2 F2 TP_VESTA_REGSEN2 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
402 NCM13 NC REGCTL2 G4 TP_VESTA_REGCTL2
To keep Vesta from being held
AGND GND III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
in reset when system is off
H11
H12
J11
J12
L7
L8
M7
M8
N7
N8
P6
P7
P8
P9
A2
B2
B7
C14
F14
J2
K2
NOTE: Reset GPIO is active HIGH SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.

D 051-6772 E
SCALE
NONE
SHT
12 102 OF
8 5 4 3 2 1
7 6
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ELECTRICAL_CONSTRAINT_SET NET_SPACING_TYPE DIFFERENTIAL_PAIR
SMU_CLK10M_XTAL P25MM SMU_CLK10M_XIN 13

Real Time Clock
P25MM SMU_CLK10M_XOUT 13
P25MM SMU_CLK10M_XOUT_R 13 7 =PP3V3_ALL_RTC

13 8 7 6 =PP3V3_ALL_SMU
RTC_CLK32K_XTAL P25MM RTC_CLK32K_X1 13
RTC_CLK32K_X2
P25MM 13
System Management Unit C1308 1 8
Page Notes 13 8 7 6 =PP3V3_ALL_SMU R1315

1
4.7 2
PP3V3_ALL_SMU_AVCC 8
VOLTAGE=3.3V
0.1uF
20%
10V
CERM 2
402
U1301
DS1338
VCC RTC_CLK32K_X1
CRITICAL
13
D Power aliases required by this page:

- _PP3V3_ALL_SMU
5%
1/16W
18 I2C_RTC_SDA 5 SDA X1
MSOP 1
1
Y1301
32.768K
D
- _PP3V3_ALL_RTC
C1300 1 C1301 1 C1302 1 MF-LF
402
1 C1303 I2C_RTC_SCL 6 SCL
X2 2
SM-1
10uF 0.1uF 0.1uF 1uF 18
4
- _PP3V3_PWRON_SMU 20% 20% 20% 10% 3
6.3V
CERM 2
10V
CERM 2
10V
CERM 2
6.3V
2 CERM NC 7 SQW/ VBAT
- _PPVREF_SMU (SMU AVCC or 2.5V reference) 805 402 402 402 OUT GND RTC_CLK32K_X2 13
GND_SMU_AVSS 8 13 33 36 4
Signal aliases required by this page: 1 C1309
Entry Desktop
Entry Desktop
(NONE) 0.1uF
20%
BOM options provided by this page: SMU_BOOT_BUSY 8 2 10V
CERM
Portable
Consumer
Portable
Consumer
Y = Primary function 13 78
Desktop
Desktop
(NONE) SMU_BOOT_SCLK 8
402
Server
Server
N = Alternate function VCC AVCC
(see aliases below) SMU_BOOT_CE 8
NOTE: CPU current/voltage monitoring
S = Spare U1300
(CPU_SENSE_I/CPU_SENSE_V) requires M30280F8
QFP-80 RTS0*/
100K/10uF RC filter at SMU pins. 33 CPU_SENSE_I Y Y Y S S 67 P0[0] AN00 CTS0* P6[0] 43 Y Y Y N N CPU_VID<0> 8 13
Caps should connect to GND_SMU_AVSS. 33 CPU_SENSE_V Y Y Y S S 66 P0[1] AN01 OMIT CLK0 P6[1] 42 Y Y Y N N CPU_VID<1> 8 13
SMU_VREF should be same signal or 36 CPU_TEMP Y Y Y S S 65 P0[2] AN02 RXD0 P6[2] 41 Y Y Y N N CPU_VID<2> 8 13
reference used by monitoring 30 CPU_BYPASS Y Y Y S S 64 P0[3] AN03 TXD0 P6[3] 40 Y Y Y S S CPU_VID<3> 8

63 RTS1*
circuit, but be aware that this will 13 FAN_RPM3 N S Y Y Y P0[4] AN04 (BUSY) P6[4] 31 Y Y Y S S CPU_VID<4> 8
affect other analog inputs such as 13 FAN_RPM4 N S Y Y Y 62 P0[5] AN05 CLK1 P6[5] 30 Y Y Y S S CPU_VID<5> 8
AC adapter ID. 13 FAN_RPM5 N S Y Y Y 61 P0[6] AN06 RXD1 P6[6] 29 Y Y Y Y Y SMU_BOOT_RXD 8
8 SMU_ONEWIRE Y Y Y Y Y 60 P0[7] AN07 TXD1 P6[7] 28 Y Y Y Y Y SMU_BOOT_TXD 8

NOTE: All analog inputs to SMU should have
a 100pF capacitor to the SMU AVSS Y Y Y Y Y 59 Y Y Y Y Y
3 SMU_PWRSEQ_P1_0 P1[0] AN20 SDA P7[0] 27 I2C_SMU_B_SDA 18
signal (GND_SMU_AVSS). None of 58
3 SMU_PWRSEQ_P1_1 Y Y Y Y Y P1[1] AN21 SCL P7[1] 26 Y Y Y Y Y I2C_SMU_B_SCL 18
those capacitors are provided on Y Y Y Y Y 57 Y Y Y N N
3 SMU_PWRSEQ_P1_2 P1[2] AN22 TA1out P7[2] 25 I2C_SMU_CPU_SDA_IN 13 18
this page.
NOTE: Some primary and alternate functions
8
3
SMU_PWRSEQ_P1_3
SMU_PWRSEQ_P1_4
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
56
55
P1[3]
P1[4]
AN23 TA1in
TA2out
P7[3] 24
P7[4] 23
Y
Y
Y
Y
Y
Y
Y
N
Y
N
FAN_RPM0
I2C_SMU_CPU_SCL_IN
16
13 18
SMU Pull-ups / pull-down
C reuire pull-ups that are not.
provided on this page. Please.
13 8 6
13 8
SYS_POWERFAIL_L
SYS_DRIVE_BAY_INT_L
N
N
Y
S
Y
S
Y
S
Y
Y
54
53
P1[5]
P1[6]
INT3*
INT4*
TA2in
TA3out
P7[5] 22
P7[6] 21
Y
N
Y
S
Y
S
Y
Y
Y
Y
FAN_RPM1
FAN_PWM8
16
8 13
=PP3V3_ALL_SMU 6 7 8 13 C
N S Y Y Y 52 P7[7] 20 Y Y Y Y Y
review the latest SMU specification 13 8 SYS_DOOR_AJAR_L P1[7] INT5* TA3in FAN_RPM2 17
R1300
to ensure missing pull-ups are 10K
1 2 SYS_POWERUP_L 6 7 10 11 13 33
provided on another page. 18 I2C_SMU_E_SDA Y Y Y Y Y 51 P2[0] SDAmm TA4out P8[0] 19 Y Y Y Y Y SYS_LED 21
5%
Y Y Y Y Y 50 P8[1] 18 Y Y Y Y Y
NOTE: Pinout matches SMU pinout v1.51.
18 I2C_SMU_E_SCL
Y Y Y Y Y 49
P2[1] SCLmm TA4in
Y Y Y Y Y
SYS_COLD_RESET_L 8 13 24
R1302 1/16W
MF-LF
16 FAN_TACH0 P2[2] IOC2 INT0* P8[2] 17 SYS_PME_L 13 25 77
1
10K 2
402
SYS_POWER_BUTTON_L 6 7 13
16 FAN_TACH1 Y Y Y Y Y 48 P2[3] IOC3 INT1* P8[3] 16 S S S S S SMU_QREQ 28
5%
17 FAN_TACH2 Y Y Y Y Y 47 P2[4] IOC4 INT2* P8[4] 15 Y Y Y Y Y SYS_SLEWING_L 13 25 27 33 1/16W
13 FAN_TACH3 S N Y Y Y 46 P2[5] IOC5 NMI* P8[5] 14 Y Y Y S S I2C_SMU_CPU_SDA_OUT_L 18
MF-LF
402 R1303
S N Y Y Y 45 Y Y Y Y Y 10K
13 FAN_TACH4 P2[6] IOC6 CE* P8[6] 8 SYS_POWERUP_L
MAKE_BASE=TRUE
6 7 10 11 13 33 1 2 SYS_RESET_BUTTON_L 7 13
13 FAN_TACH5 S N Y Y Y 44 P2[7] IOC7 P8[7] 7 Y Y Y Y Y SMU_SLEEP 8 13 5%

1/16W
MF-LF
402
18 I2C_SMU_A_SDA_IN Y Y Y Y Y 39 P3[0] CLK3 TB0in P9[0] 5 Y Y Y Y Y CLOCK_RESET_L 27
18 14 6 I2C_SMU_A_SDA_OUT_L Y Y Y Y Y 38 P3[1] Sin3 TB1in P9[1] 4 Y Y Y S S CPU_HRESET 30

NO_SMU_I2C_D 37
18 I2C_SMU_A_SCL_IN Y Y Y Y Y P3[2] Sout3 TB2in P9[2] 3 Y Y Y Y Y SB_TO_SMU_INT_L 25
PP3V3_PWRON
R1399 18 14 6 I2C_SMU_A_SCL_OUT_L Y Y Y Y Y 36 P3[3] AN24 P9[3] 2 Y Y Y Y Y SB_STOPXTALS_L 25
R1304
0 Y Y Y Y Y 35 Y Y Y Y Y
25 SMU_TO_SB_INT_L 1 2 18 I2C_SMU_D_SDA P3[4] AN25 P9[5] 1 SMU_PWRSEQ_P9_5 3 10K
2 1 SYS_PME_L 13 25 77
5% 18 I2C_SMU_D_SCL Y Y Y Y Y 34 P3[5] AN26 P9[6] 80 Y Y Y Y Y SMU_PWRSEQ_P9_6 3
13 8 7 6 =PP3V3_ALL_SMU 1/16W 5%
MF-LF 13 SMU_CHARGE_BATT Y S S S S 33 P3[6] AN27 P9[7] 79 S S Y Y S SYS_SLOT_PWR 8 1/16W
402 MF-LF
27 25 SYS_OVERTEMP_L Y S S S S 32 P3[7] 402
PP3V3_RUN
3 R1322
1
AN0 P10[0] 76 S S S S S TP_SMU_SPARE_P10_0 R1312
150K 2.0K 2
D1310
MMBD914XXG
5%
1/16W 8 =PPVREF_SMU
AN1 P10[1] 74 Y Y Y Y Y SMU_WARM_RESET_L 8 1 SYS_SLEWING_L 13 25 27 33
SOT23 MF-LF AN2 P10[2] 73 Y Y Y Y Y NB_SUSPENDACK_L 8 5%

1 1/16W
2 402 8 SMU_BOOT_CNVSS 6 PCNVSS AN3 P10[3] 72 Y Y Y Y Y SB_SUSPENDACK_L 25 MF-LF
402
SMU_RESET_L 9 RESET* KI0* P10[4] 71 Y Y Y Y Y SMU_SUSPENDREQ_L NO STUFF
B B
8 6 13 24 25 28
PP2V5_PWRON
10 KI1* P10[5] 70 Y Y Y Y Y
13 SMU_CLK10M_XOUT_R XOUT SYS_POWER_BUTTON_L 6 7 13
R1311
C1310 1 13 SMU_CLK10M_XIN 12 XIN KI2* P10[6] 69 Y Y Y Y Y SYS_RESET_BUTTON_L 7 13
1
2.0K 2
SMU_SUSPENDREQ_L
0.22uF 77 VREF KI3* P10[7] 68 Y Y Y S S I2C_SMU_CPU_SCL_OUT_L 18
13 24 25 28
20% 5%
6.3V 2
CERM
402
NO STUFF R1313 1/16W
MF-LF
R1316 R13251 R1327
1 100K 2 402
10M 10K
1 C1325 VSS
11
AVSS
75 10K
1 SYS_COLD_RESET_L 8 13 24
1 2 5% 1uF 5% 5%
1/16W 10% 1/16W 1/16W
5% 6.3V MF-LF
1/16W
MF-LF
402 2
2 CERM
402 XW1300 MF-LF
2 402
402
R13171 MF-LF
402
SM
0 1 2
R1310
5%
1/16W CRITICAL 100K 2
1 SMU_SLEEP
MF-LF
402 2 Y1300 GND_SMU_AVSS 8 13 33 36
VOLTAGE=0V 5%
8 13
10.000M
1 2 MIN_LINE_WIDTH=0.25MM 1/16W
MIN_NECK_WIDTH=0.2MM MF-LF
SMU_CLK10M_XOUT
Keep crystal subcircuit close to SMU. 402
13
SM
C1304 1 C1305 1
18pF 18pF
5% 5%
50V 50V
CERM 2 CERM 2
402 402
System Management Unit

A Alternate Functions SYNC_MASTER=N/A SYNC_DATE=N/A
A
Portable Consumer Tower & Server THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
Port Port Port PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
13 FAN_RPM3 0.4 ALS0_OUT 8 13 FAN_TACH3 2.5 SYS_LED_RED 21 13 8 CPU_VID<0> 6.0 FAN_TACH6
13 FAN_RPM4 0.5 ALS1_OUT 8 13 FAN_TACH4 2.6 SYS_LED_GREEN 21 13 8 CPU_VID<1> 6.1 FAN_TACH7
13 FAN_RPM5 0.6 ALS_GAIN_BOOST 8 13 FAN_TACH5 2.7 SYS_LED_BLUE 21 13 8 CPU_VID<2> 6.2 FAN_TACH8
13 8 6 SYS_POWERFAIL_L 1.5 SMU_ACIN 13 SMU_CHARGE_BATT 3.6 DIAG_LED 8 18 13 I2C_SMU_CPU_SDA_IN 7.2 FAN_PWM6
13 8 SYS_DRIVE_BAY_INT_L 1.6 SMU_BATT_DET_L 18 13 I2C_SMU_CPU_SCL_IN 7.4 FAN_PWM7 SIZE DRAWING NUMBER REV.
13 8
13 8
SYS_DOOR_AJAR_L
FAN_PWM8
1.7
7.6
SYS_LID_OPEN
SYS_KBDLED APPLE COMPUTER INC.
D 051-6772 E
SCALE SHT OF
NONE 13 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
DEVELOPMENT
R1400
0
27 EI_CPU1_CLK_P_R 1 2 EI_CPU1_CLK_P 6 14 27
5% 1/16W
MF-LF 402
DEVELOPMENT
R1401
0
27 EI_CPU1_CLK_N_R 1 2 EI_CPU1_CLK_N 6 14 27
5% 1/16W
MF-LF 402
D DEVELOPMENT
D
0 R1402
27 6 CPU1_HTBEN_R 1 2 CPU1_HTBEN 6 14
5% 402
DEVELOPMENT
0 R1403
27 6 EI_CPU1_SYNC_R 1 2 EI_CPU1_SYNC 6 14 27
5% 402
=PP1V2_EI_CPU 7 18 29 30 31
28 18 14 7 =PP1V2_EI_NB
NOSTUFF
=PP1V2_EI_NB 7 14 18 28
J1400
YFS-30-03-H-08-SB
F-ST-BGA
27 14 6 EI_CPU1_SYNC H1 H1 G1 G1 EI_CPU1_CLK_P 6 14 27 14 6
27
EI_CPU1_CLK_N F1 F1 E1 E1 30 29 25 6 CPU_INT_L D1 D1 C1 C1 B1 B1 A1 A1 CPU_HRESET_L 6 29 30
29 8 6 CHKSTOP_L H2 H2 G2 G2 F2 F2 E2 E2 D2 D2 C2 C2 B2 B2 A2 A2 CPU1_HTBEN 6 14
H3 H3 G3 G3 NC F3 F3 E3 E3 D3 D3 C3 C3 B3 B3 A3 A3 EI_CPU_TO_NB_AD<0> 6 28 29
H4 H4 G4 G4 EI_CPU_TO_NB_AD<3> 6 28 29 F4 F4 E4 E4 D4 D4 C4 C4 B4 B4 A4 A4 EI_CPU_TO_NB_AD<2> 6 28 29
H5 H5 G5 G5 EI_CPU_TO_NB_AD<4> 6 28 29 F5 F5 E5 E5 D5 D5 C5 C5 B5 B5 A5 A5
H6 H6 G6 G6 EI_CPU_TO_NB_AD<7> 6 28 29 F6 F6 E6 E6 EI_CPU_TO_NB_AD<8> 6 28 29 D6 D6 C6 C6 EI_CPU_TO_NB_AD<6> 6 28 29 B6 B6 A6 A6 EI_CPU_TO_NB_AD<1> 6 28 29
H8 H8 G8 G8 EI_CPU_TO_NB_CLK_N 6 28 29 F8 F8 E8 E8 NC D8 D8 C8 C8 EI_CPU_TO_NB_AD<20> 6 28 29 B8 B8 A8 A8 EI_CPU_TO_NB_AD<10> 6 28 29
H9 H9 G9 G9 EI_CPU_TO_NB_CLK_P 6 28 29 F9 F9 E9 E9 EI_CPU_TO_NB_AD<12> 6 28 29 D9 D9 C9 C9 EI_CPU_TO_NB_AD<25> 6 28 29 B9 B9 A9 A9 EI_CPU_TO_NB_AD<22> 6 28 29
H10 H10 G10 G10 EI_CPU_TO_NB_SR_N<1> 6 28 29 F10 F10 E10 E10 EI_CPU_TO_NB_AD<5> 6 28 29 D10 D10 C10 C10 EI_CPU_TO_NB_AD<26> 6 28 29 B10 B10 A10 A10 EI_CPU_TO_NB_AD<31> 6 28 29
H11 H11 G11 G11 EI_CPU_TO_NB_SR_P<1> 6 28 29 F11 F11 E11 E11 EI_CPU_TO_NB_AD<36> 6 28 29 D11 D11 C11 C11 EI_CPU_TO_NB_SR_P<0> 6 28 29 B11 B11 A11 A11 EI_CPU_TO_NB_AD<37> 6 28 29
C H12
H13
H12
H13
G12 G12 NC
G13 G13 EI_CPU_TO_NB_AD<17> 6 28 29
F12
F13
F12
F13
E12 E12
E13 E13
EI_CPU_TO_NB_AD<35> 6 28 29
D12
D13
D12
D13
C12 C12
C13 C13
EI_CPU_TO_NB_SR_N<0> 6 28 29
B12
B13
B12
B13
A12 A12
A13 A13
EI_CPU_TO_NB_AD<30>
EI_CPU_TO_NB_AD<34>
6 28 29
6 28 29
C
29 28 6 EI_NB_TO_CPU_AD<13> H17 H17 G17 G17 EI_NB_TO_CPU_AD<14> 6 28 29 28 6

29
EI_NB_TO_CPU_AD<5> F17 F17 E17 E17 EI_CPU_TO_NB_AD<40> 6 28 29 28 6
29
EI_CPU_TO_NB_AD<15> D17 D17 C17 C17 EI_CPU_TO_NB_AD<19> 6 28 29 28 6
29
EI_NB_TO_CPU_AD<4> B17 B17 A17 A17 EI_CPU_TO_NB_AD<29> 6 28 29
29 28 6 EI_NB_TO_CPU_AD<15> H18 H18 G18 G18 EI_NB_TO_CPU_AD<12> 6 28 29 F18 F18 E18 E18 EI_NB_TO_CPU_AD<9> 6 28 29 D18 D18 C18 C18 29 28 6 EI_NB_TO_CPU_AD<3> B18 B18 A18 A18
29 28 6 EI_NB_TO_CPU_AD<21> H20 H20 G20 G20 EI_NB_TO_CPU_AD<19> 6 28 29 F20 F20 E20 E20 EI_NB_TO_CPU_AD<0> 6 28 29 D20 D20 C20 C20 B20 B20 A20 A20
29 28 6 EI_NB_TO_CPU_AD<25> H22 H22 G22 G22 EI_NB_TO_CPU_AD<26> 6 28 29 F22 F22 E22 E22 D22 D22 C22 C22 B22 B22 A22 A22
29 28 6 EI_NB_TO_CPU_AD<10> H26 H26 G26 G26 F26 F26 E26 E26 EI_NB_TO_CPU_AD<2> 6 28 29
29
28 6 EI_NB_TO_CPU_AD<8> D26 D26 C26 C26 29 28 6 EI_NB_TO_CPU_AD<23> B26 B26 A26 A26
29 28 6 EI_NB_TO_CPU_AD<39> H27 H27 G27 G27 F27 F27 E27 E27 EI_NB_TO_CPU_AD<38> 6 28 29
29
28 6 EI_NB_TO_CPU_AD<24> D27 D27 C27 C27 29 28 6 EI_NB_TO_CPU_CLK_N B27 B27 A27 A27
29 28 6 EI_NB_TO_CPU_AD<36> H28 H28 G28 G28 EI_NB_TO_CPU_SR_N<0> 6 28 29
29
28 6 EI_NB_TO_CPU_AD<37> F28 F28 E28 E28 SYNCENABLE 6 29 30 28 6 EI_NB_TO_CPU_AD<7>
29
D28 D28 C28 C28 29 28 6 EI_NB_TO_CPU_CLK_P B28 B28 A28 A28
30 29 6 RI_L H29 H29 G29 G29 EI_NB_TO_CPU_SR_P<0> 6 28 29
29
28 6 EI_NB_TO_CPU_SR_N<1> F29 F29 E29 E29 TP_PROC_TRIGGER_OUT 6 29 29 28 6 EI_NB_TO_CPU_AD<6> D29 D29 C29 C29 EI_SE 6 28 29
30
29 6 MCP_L B29 B29 A29 A29
30 29 28 6 EI_QREQ_L H30 H30 G30 G30 I2C_SMU_A_SCL_OUT_L 6 13 18 28 6
29
EI_NB_TO_CPU_SR_P<1> F30 F30 E30 E30 29 28 6 EI_QACK_L D30 D30 C30 C30 18 13 6 I2C_SMU_A_SDA_OUT_L B30 B30 A30 A30
B B
CPU LOGIC ANALYZER

A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
D 051-6772 E
APPLE COMPUTER INC.
SCALE SHT OF
NONE 14 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
PP12V_RUN
FAN 0
NOSTUFF
1
R1605 R16071 1 C1602
R1602
1 1.5K 1.5K 0.1UF
5% 5%
1.0K 1/4W 1/8W 20%
5% MF-LF MF-LF 2 25V
CERM 5
1/8W 2 1206 805 2
D MF-LF
2 805 R1606
603
D
F0_VOLTAGE8R5
3.9K F0_GATESLOWDN
F0_DRV 4 1206A-03
5% NTHS5443T1
1/8W
MF-LF Q1603
805
3
R1601
D
Q1601
2N7002 1 C1604
1
2
3
6
7
8
1
0 2 FAN_0_CNTL 1 G S
SOT23-LF 0.47UF CRITICAL
5% 3
10%
2 16V
X7R NOSTUFF J1600
1/8W 2 NOSTUFF
D1603 HF28040-B
SMU_FAN_RPM0 MF-LF
805 R1603
D Q1602 805
R1608 SM
MIN_LINE_WIDTH=0.5MM M-ST-TH
0 2N7002
SOT23-LF F0_RCFEEDBK 1
0 2 FAN_0_OUT 1 2 FAN_0_PWR 1
1 MOTOR CONTROL
13 FAN_RPM0 1 2 G S
NOSTUFF 5% 2 TACH
5% 1/8W MBRS130LT3
1/8W
MF-LF
2 R1615
1 MF-LF
805 3
3 GND
PP3V3_RUN 805 1K
5% D1602 R1616 1
C1603 4 12V DC
1/10W MMBD914XXG 01 2
120UF
FF 20%
2 805 1 SOT23 2 16V 17" SYSTEM FAN 603-5518
5% ELEC
1/8W 6.3X11-TH 20" SYSTEM FAN 603-5521
1
R1610
10K
MF-LF
805
1%
SMU_FAN_TACH0 1/16W
R1609
0
MF-LF
2 402
13 FAN_TACH0 1 2 FAN_0_TACH
5%
1/16W
MF-LF
402
C C
PP12V_RUN
FAN 1
R1660 MIN_LINE_WIDTH=0.5MM
VOLTAGE=12V R1661
1
0 2 PP12V_RUN_FAN_1_LC 1
0 2
5% 5%
1/10W 1/10W
R1652
1 MF-LF
603 1 C1660 MF-LF
603
1.0K 1
R1655 NOSTUFF 0.01UF
5%
1/8W 1.5K R16571 1 C1652 20%
2 16V
MF-LF
2 805
5%
1/4W 1.5K 0.1UF
20%
CERM
402
MF-LF 5% 25V
2 1206 1/8W
MF-LF
2 CERM
805 2 603 5
F1_DRV
R1656
3.9K
F1_VOLTAGE8R5 F1_GATESLOWDN 4 1206A-03
5% NTHS5443T1
3 1/8W
MF-LF Q1653 PP12V_RUN_FAN_1_LCL
D
Q1651 805 VOLTAGE=12V
B R1651
0 1
2N7002
SOT23-LF
1 C1654
0.47UF
CRITICAL
J1601
MIN_NECK_WIDTH=0.25MM B
1 2 FAN_1_CNTL G S NOSTUFF 10-89-7062
10%
1
2
3
6
7
8
5% 3 2 16V M-ST-TH
1/8W 2 NOSTUFF X7R
R1658 D1653 MIN_LINE_WIDTH=0.5MM R1662
SMU_FAN_RPM1 MF-LF
805 R1653
D
Q1652 805
0 SM MIN_NECK_WIDTH=0.25MM
0 MOTOR CONTROL 1 17" CPU FAN 603-5519
20" HD FAN 603-5487
2N7002 F1_RCFEEDBK 1 2 FAN_1_OUT 1 2 FAN_1_PWR 1 2 FAN_1_PWR_FILT 4
FAN_RPM1 1
0 2 1 G S
SOT23-LF
5% 5%
MIN_LINE_WIDTH=0.5MM 6 5
13 NOSTUFF MIN_NECK_WIDTH=0.25MM
1/8W MBRS130LT3 1/10W
5%
1/8W 2 R1665
1 MF-LF
805
MF-LF
603
TACH GND
1K
C1653 R1663
MF-LF 3
805 5%
1/10W D1652 R1666
0
1
120UF 0
PP3V3_RUN FF MMBD914XXG 1 2 20%
1 2 FAN_1_TACH_FILT
2 805 1 SOT23 2 16V 5%
5% ELEC 1/10W FAN_1_GND_FILT
1/8W 6.3X11-TH MF-LF VOLTAGE=0V
MF-LF 603 MIN_LINE_WIDTH=0.5MM
805 R1664 MIN_NECK_WIDTH=0.25MM
1
R1659
10K
1
0 2
1% 5%
SMU_FAN_TACH1 1/16W 1/10W
R1650
0
MF-LF
2 402
MF-LF
603
13 FAN_TACH1 1 2 FAN_1_TACH
5%
1/16W
MF-LF
402
FAN 0, 1 & SYSTEM TEMP

A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
APPLE COMPUTER INC.

D 051-6772 E
SCALE SHT OF
NONE 16 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
FAN 2
PP12V_RUN
D D
R1702
1
R1705
1
R17071
NOSTUFF
1.0K
5% 1.5K 1.5K
1 C1702
1/8W 5% 5% 0.1UF
MF-LF 1/4W 1/8W 20%
25V
2 805 MF-LF MF-LF 2 CERM
2 1206 805 2 603 5
F2_DRV
R1706
F2_VOLTAGE8R5
3.9K F2_GATESLOWDN
3 4 1206A-03
5% NTHS5443T1
D Q1701 1/8W Q1703
R1701 2N7002
MF-LF
805
1
0 2 FAN_2_CNTL 1 G S
SOT23-LF CRITICAL
5%
1 C1704 J1700
0.47UF NOSTUFF 10-89-7062
1
2
3
6
7
8
1/8W 2 3
MF-LF NOSTUFF 10% M-ST-TH
SMU_FAN_RPM2 805 D Q1702 16V
2 X7R R1708 D1703 MIN_LINE_WIDTH=0.5MM +12V DC
R1703 2N7002 805 0
SM MIN_NECK_WIDTH=0.25MM MOTOR CONTROL 1
0 1
SOT23-LF F2_RCFEEDBK 1 2 FAN_2_OUT 1 2 FAN_2_PWR 4
13 FAN_RPM2 1 2 G S GND
NOSTUFF 5% 6 5
5% 1/8W MBRS130LT3 TACH
1/8W
MF-LF
2 1
R1715 MF-LF
805
3
1
C1703
PP3V3_RUN 805 1K D1702 120UF 17" HD FAN 603-5520
5%
1/10W
MMBD914XXG
SOT23 R1716 20% 20" CPU FAN 603-5459
FF 1
1
0 2
2 16V
ELEC
2 805 6.3X11-TH
5%
1
R1709 1/8W
MF-LF
10K 805
1%
SMU_FAN_TACH2 1/16W
C R1700 MF-LF
2 402 C
FAN_TACH2 1
0 2 FAN_2_TACH
13
5%
1/16W
MF-LF
402
REMOTE HARD DRIVE TEMP SENSOR
B CRITICAL B
J1701
53261-0498
PP3V3_PWRON M-RT-SM
5
18 6 I2C_HD_TEMP_SDA 2
18 6 I2C_HD_TEMP_SCL 3
4
I2C ADDR:92(1001001)
6
518S0193
FAN 2 & HD TEMP

A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
D 051-6772 E
APPLE COMPUTER INC.
SCALE SHT OF
NONE 17 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
11 6 PP5V_PWRON R1832 PP3V3_PWRON
0
PP5V_U1800
I2C B BUS
1 2
603 MIN_LINE_WIDTH=0.25MM
NOSTUFF MIN_NECK_WIDTH=0.2MM
R1833
I2C A BUS 11 10 7 6 PP5V_RUN
1
0 2
=PP1V2_EI_NB 7 14 28
603
C1800 NOSTUFF R18031 R1802
1
C1802 R1808 R1810

50 34 22 11 10 7 6 PP3V3_RUN 58 27 18 11 6 PP3V3_PWRON 1 1 1
0.1UF R18091 1
R1828 1 2.0K 2.0K
0.1UF 200 200 5% 5%
NOSTUFF NOSTUFF 20%
10V 4.7K 4.7K 20% 5% 5% SMU 1/16W 1/16W
CERM 2 5% 5% 10V 1/16W 1/16W MF-LF MF-LF
R1830 1 1
R1831 R1800 1
R1801
1
402 1/16W
MF-LF
1/16W
MF-LF
2 CERM
402
MF-LF
402 2
MF-LF
2 402
MASTER 402 2 2 402
2.0K 2.0K 2.0K 2.0K 402 2 2 402 U1300
SMU 5% 5% 5% 5%
D MASTER
U1300
1/16W
MF-LF
402 2
1/16W
MF-LF
2 402
1/16W
MF-LF
402 2
1/16W
MF-LF
2 402
LM339A
SOI
3
V+
8 13 I2C_SMU_B_SDA
MAKE_BASE=TRUE
NET_SPACING_TYPE=I2C
D
13 I2C_SMU_A_SDA_IN
MAKE_BASE=TRUE
NET_SPACING_TYPE=I2C 14
U1800 U3LITE 13 I2C_SMU_B_SCL
MAKE_BASE=TRUE
GND 6 U3
14 13 6 I2C_SMU_A_SDA_OUT_L NET_SPACING_TYPE=I2C 9 PINS 26, 27
MAKE_BASE=TRUE
12
D
Q1800
13 I2C_SMU_A_SCL_IN NET_SPACING_TYPE=I2C 2N7002DW I2C_NB_A_SDA 24
MAKE_BASE=TRUE 2
SOT-363
G S I2C_NB_A_SCL 24
14 13 6 I2C_SMU_A_SCL_OUT_L NET_SPACING_TYPE=I2C
MAKE_BASE=TRUE
PINS 36-39
1 PULSAR
U2600
3 PINS A20, B20
LM339A 6
SOI V+
1 I2C_CLOCK_SDA
U1800 3 NOSTUFF NOSTUFF
27
I2C_CLOCK_SCL
GND 27
7 D Q1800 R18201 1
R1821
12 2N7002DW 0 0
5 G
SOT-363 5% 5% PINS C1, B1
S 1/16W 1/16W
MF-LF MF-LF
402 2 2 402
58 27 18 11 6 PP3V3_PWRON 4
=PP1V2_EI_CPU 7 14 29 30 31
R18191 R1818
1
OPTICAL TEMP SENSOR
2.0K 2.0K
5% 5% U1602
1/16W 1/16W 3
MF-LF
402 2
MF-LF
2 402
LM339A 10 R1816 1 1
R1817 NOTE: REMOVED FOR PVT
SOI 200 200 I2C_OPTICAL_SDA
SMU 13
V+ 5% 5%
I2C_OPTICAL_SCL
MASTER U1800 1/16W
MF-LF
1/16W
MF-LF
GND
U1300 RP1800 11 402 2 2 402 CPU PINS 1, 2
13 I2C_SMU_CPU_SCL_IN I2C 0 12 U2900 I2C ADDR:90
MAKE_BASE=TRUE 5%
C 13 I2C_SMU_CPU_SCL_OUT_L
MAKE_BASE=TRUE
I2C 1
2
8
7
SMU_CPU_JTAG_OR_I2C
I2C_CPU_A_SCL
I2C_CPU_A_SCL 29
C
13 I2C_SMU_CPU_SDA_IN I2C 3 6 NET_SPACING_TYPE=I2C
MAKE_BASE=TRUE I2C_CPU_A_SDA_TO_SMU I2C_CPU_A_SDA 29
I2C_SMU_CPU_SDA_OUT_L 4 5 I2C_CPU_A_SDA_TO_CPU
AMBIENT LIGHT SENSOR
13 I2C 3
MAKE_BASE=TRUE LM339A 4 J2100
1/16W
PINS 14,25,23,68 SM-LF SOI V+ PINS AA20, Y21
2 I2C_ALS_SDA
6 U1800 21
I2C_ALS_SCL
GND 21
D
Q1801 5
2N7002DW 12 PINS 2, 3
2 SOT-363 3
G S I2C ADDR:94??
1
D
Q1801 J2100 CAN BE USED AS A SECOND TEMP SENSOR
2N7002DW
SOT-363
5 G S
I2C_CPU_SCL_LS
I2C_0V6_REF
HD TEMP SENSOR
4
U1702
NOSTUFF
RP1801 C1801 1 R18111 I2C_HD_TEMP_SDA
0 CPU JTAG 0.1UF 4.7K
17 6
20% 5% I2C_HD_TEMP_SCL
5% 10V 17 6
1 8 JTAG_CPU_TDO CERM 2 1/16W
29 30 402 MF-LF USE 576 OHM FOR R1811 IF 5V RAIL IS USED FOR REFERENCE
2 7 402 2 PINS 2, 3
JTAG_CPU_TDI 29 30
3 6 JTAG_CPU_TMS
I2C ADDR:92
29 30
4 5 JTAG_CPU_TCK 29 30
PP2V5_PWRON
I2C D & E BUS
1/16W
SM-LF
GPU TEMP SENSOR
I2C C BUS PP2V5_PWRON
I2C SB BUS PP3V3_RUN
U5890
B PP3V3_ALL
58 I2C_GPU_DIODE_SDA B
58 I2C_GPU_DIODE_SCL
R18051 1
R1804 U3LITE SHASTA R18151 R1814
1
2.0K 2.0K R18121 1

R1813 1K 1K PINS 7, 8
5% 5% MASTER 5% 5%
1/16W
MF-LF
1/16W
MF-LF
MASTER 2.0K
5%
2.0K
5%
R18071 R1806
1
U2300
1/16W
MF-LF
1/16W
MF-LF
I2C ADDR:98
402 2 2 402 U3 1/16W 1/16W 2.0K 2.0K 402 2 2 402
NET_SPACING_TYPE=I2C MF-LF MF-LF 5% 5%
I2C_NB_C_SDA
MAKE_BASE=TRUE
24
U3LITE ’B’ 402 2 2 402 1/16W
MF-LF
1/16W
MF-LF
RTC 25 6 I2C_SB_SDA
402 2 2 402 MAKE_BASE=TRUE
NET_SPACING_TYPE=I2C U3 U1301 NET_SPACING_TYPE=I2C
I2C_NB_C_SCL 24 25 6 I2C_SB_SCL
PINS C21, E21 PINS Y9, AB7
24 I2C_NB_B_SDA I2C I2C I2C_RTC_SDA 13
24 I2C_NB_B_SCL I2C I2C I2C_RTC_SCL 13
DIMMS PINS C20, B21

PINS 5, 6 AUDIO
J4000 = A0
J4001 = A2 U9500 / AU300
NOSTUFF NOSTUFF
I2C_DIMM_SDA 40 95 I2C_AUDIO_SDA
I2C_DIMM_SCL 40
R18221 1
R1823 95 I2C_AUDIO_SCL
0 0
PINS 91, 92 5% 5%
1/16W 1/16W PINS 18, 19
OF EACH DIMM MF-LF MF-LF
402 2 2 402 NOSTUFF
R1824 R1826
2
0 1 2
0 1
SMU OLD ’E’ 5% 5%
SMU NEW ’E’ I2C CONNECTIONS
MASTER 1/16W 1/16W MASTER
MF-LF MF-LF
A U1300
NOSTUFF
402 402 U1300 SYNC_MASTER=N/A

SYNC_DATE=N/A
A
13 I2C_SMU_E_SDA I2C R1825 R1827 I2C I2C_SMU_D_SDA 13
0 0 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

13 I2C_SMU_E_SCL I2C 2 1 2 1 I2C I2C_SMU_D_SCL 13 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
5% 5%
PINS 50, 51 1/16W 1/16W PINS 34, 35 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
MF-LF MF-LF
402 402 II NOT TO REPRODUCE OR COPY IT
D 051-6772 E
APPLE COMPUTER INC.
SCALE SHT OF
NONE 18 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
TOTAL CURRENT EXCLUDING LEDS CURRENT < 170 MICRO AMPS
RGB_LED
C2105
220PF
RGB_LED AMBIENT LIGHT SENSOR
1 2 GND_CHASSIS_LED
LED2100 PP5V_PWRON
7 21 LATBG66B
AMB-GRN-BLUE CRITICAL
5% RGB_LED
PLACE THESE PARTS CLOSE TO SMU IC PP5V_PWRON 25V
PLCC
L2104 J2100
CERM
402 400-OHM-EMI 53261-0498
PP3V3_PWRON M-RT-SM
G_DRV_K 1 6 RGB_LED_A 1 2 5
MIN_LINE_WIDTH=0.6MM AMB MIN_LINE_WIDTH=0.6MM SM-1
RGB_LED MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM
D R21091
953K
1
3 2 18 I2C_ALS_SDA
1
2
D
RGB_LED 1% RGB_LED GRN
R2101 1/16W
MF-LF L2100 18 I2C_ALS_SCL 3
0 402 2 RGB_LED 400-OHM-EMI 4
SYS_LED_GREEN 2 1 G_PWM_IN_H RGB_LED
13
MAKE_BASE=TRUE
5%
U2100 SM-1 4 5
1 C2107
4 BLUE 6
PWM INPUT FROM SMU 1/16W RGB_LED LP324 220PF
MF-LF
402 R21041 12 + 14 G_BASE_DRV 2 5%
G_PWM_DC
953K 13 25V
- 2 CERM
1% G_DRV 402
1/16W 11TSSOP MIN_LINE_WIDTH=0.6MM 518S0193
MF-LF MIN_NECK_WIDTH=0.2MM
402 2 RGB_LED 3 RGB_LED
C2104 RGB_LED C2108 GND_CHASSIS_LED 7 21 J2100 CAN BE USED AS A SECOND TEMP SENSOR
220PF
0.022UF 1 Q2102 2 1
2 1 2N3904LF
SOT23
RGB_LED 2 5%
RGB_LED 20% 25V
C2106 1 R21051 16V
CERM RGB_LED G_DRV_FB
CERM
402
0.47UF 200K 402
20%
10V 1% R2112 MIN_LINE_WIDTH=0.6MM
CERM 2 1/16W 1K RGB_LED
603 MF-LF
402 2
G_IN_OFFSET 2 1 RGB_LED C2109
5MV INPUT OFFSET 1%
1/16W R2100
1
<-- 17 INCH
220PF
MF-LF 25.5 2 1
402 1%
1/16W 5%
MF-LF 25V
2 402 CERM
402
CHANGE R2100 VALUE PP3V3_PWRON
100% DUTY CYCLE OF 3V-PP PWM = 0.5V TO SET LED CURRENT
MAX LED CURRENT = 0.5 / R
PP5V_PWRON
RGB_LED RGB_LED
C PLACE THESE PARTS CLOSE TO SMU IC
C2103
0.1UF
1 U2100
4 SYS_DRV_A
C
20% 10 + LP324 MIN_LINE_WIDTH=0.6MM
PP5V_PWRON R_DRV_K 10V 8
CERM 2 MIN_NECK_WIDTH=0.2MM
MIN_NECK_WIDTH=0.2MM 402
9
- LED2101
1 11TSSOP
2 1
RGB_LED RGB_LED PP5V_PWRON
L2101
R21021 400-OHM-EMI
WHITE
SM6 WHITE_LED
953K
1%
1/16W
SM-1
R2120
RGB_LED MF-LF 6 U2100_UNUSED
1
0 2
402 2
R2115 RGB_LED
2
5%
SYS_DRV_K
0 1/10W
13 SYS_LED_RED
MAKE_BASE=TRUE
2 1 R_PWM_IN_H U2100 R_DRV
MF-LF
WHITE_LED 603
5% RGB_LED 4
LP324 MIN_LINE_WIDTH=0.6MM
PWM INPUT FROM SMU 1/16W
MF-LF R21101 5 + 7 R_BASE_DRV
MIN_NECK_WIDTH=0.2MM 1 C2111
220PF
R_PWM_DC
402 953K 6
-
3
5%
1% RGB_LED WHITE_LED 25V
1/16W 11TSSOP C2110 2 CERM
MF-LF
402 2
RGB_LED 1 Q2108 220PF 402
2N3904LF
C2101 SOT23 2 1 GND_CHASSIS_LED 7 21
0.022UF 2
2 1 PLACE THESE PARTS CLOSE TO SMU IC 5%
RGB_LED 1 R_DRV_FB 25V
RGB_LED R2111 20% MIN_LINE_WIDTH=0.6MM
CERM
402
C2112 1 200K 16V
CERM RGB_LED
0.47UF 1%
1/16W 402 R2114 NOSTUFF WHITE_LED
20%
10V MF-LF 1K RGB_LED Q2100
CERM 2
603
402 2 R_IN_OFFSET 2 1
R2113
1
FDV302P
1
R2121
1% 0
1/16W 25.5 <-- 17 INCH PP3V3_PWRON SOT-23 WHITE_LED 5%
MF-LF
402
1%
1/16W R2106 1/10W
MF-LF
MF-LF 1K 2 603
D
SYS_LED_H SYS_GATE
3
2 1
B 2 402
R2119
NOSTUFF 5%
1/16W
SYS_LED_DRV_K
B
WHITE_LED MF-LF MIN_NECK_WIDTH=0.2MM
G
953K 1 402
2
R2129 1
117_INCH_LCD
1% 4.7K R2103
1
1/16W 5%
MF-LF
402
1/16W 56.2
PLACE THESE PARTS CLOSE TO SMU IC MF-LF 1%
402 2 1/16W
MF-LF
PP5V_PWRON NOSTUFF 2 402
B_DRV_K
MIN_LINE_WIDTH=0.6MM R2132
MIN_NECK_WIDTH=0.2MM 1K SYS_LED_DRV_C
13 SYS_LED 2 1 SYS_LED_IN MIN_LINE_WIDTH=0.6MM
PWM INPUT FROM SMU 5%
1/16W 3
RGB_LED RGB_LED MF-LF WHITE_LED WHITE_LED
R21181 L2102 402
R2107 Q2101
953K 400-OHM-EMI 2
0 1
FDV301N
1% 1 SM
RGB_LED 1/16W SM-1
R2130 MF-LF
402 2 RGB_LED
5%
1/16W
0 MF-LF 2
13 SYS_LED_BLUE
MAKE_BASE=TRUE
2 1 B_PWM_IN_H U2100 2 402
(STUFF WHEN SYS_LED_L = ACTIVE HIGH)
PWM INPUT FROM SMU 5% RGB_LED 4
LP324 (AND NO STUFF R2132, R2119 & Q2100)
1/16W
MF-LF R21161 3 + 1 B_BASE_DRV
B_DRV
B_PWM_DC
402 953K 2
- MIN_NECK_WIDTH=0.2MM
1%
1/16W 11TSSOP 3
MF-LF
402 2 RGB_LED
RGB_LED
C2102 1 Q2114
0.022UF 2N3904LF TABLE_5_HEAD
SOT23 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION

1 2 2
INDICATOR LED
TABLE_5_ITEM
RGB_LED RGB_LED 114S3921 1 RES, 39.2 OHM, 1%, 402 R2103 20_INCH_LCD
C2118 1 R21171 20%
16V
B_DRV_FB
MIN_LINE_WIDTH=0.6MM TABLE_5_ITEM
0.47UF 200K CERM MIN_NECK_WIDTH=0.2MM 20 INCH --> 114S1821 3 RES, 18.2 OHM, 1%, 402 R2100,R2113,R2126 NOSTUFF
A
402 SYNC_MASTER=N/A SYNC_DATE=N/A
20%
10V
CERM 2
603
1%
1/16W
MF-LF
402 2
RGB_LED
R2127
RGB_LED
R2126
1 NOTICE OF PROPRIETARY PROPERTY
A
1K 25.5 <-- 17 INCH
B_IN_OFFSET 2 1 1% THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1/16W PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
1% MF-LF AGREES TO THE FOLLOWING
1/16W
MF-LF 2 402 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
402
APPLE COMPUTER INC.

D 051-6772 E
SCALE SHT OF
NONE 21 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
22 7 =PPVCORE_NB
1 C2222 1 C2223 1 C2225 1 C2227 1 C2228 1 C2229 1 C2230 1 C2231 1 C2232 1 C2233 1 C2234 1 C2235 1 C2236 1 C2237 1 C2238 1 C2239 1 C2240 1 C2242 1 C2243 1 C2244 1 C2245 1 C2246 1 C2247
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
D D
NOTE:
SET OUTPUT=1.5VDC FOR U3LITE CORE
IRU3037CS VREF=1.25VDC
VOUT=VREF*(R2203+R2205)/R2205=1.53VDC
7.73A OF PEAK CURRENT DRAW ON PCORE_NB
PP5V_PWRON PP5V_PWRON
PPVCORE_NB 6
PP5V_PWRON VOLTAGE=1.5V
D2200 MAKE_BASE=TRUE
2 1
=PPVCORE_NB
MBR0520LXXG
R2200
1 1
W14
W17
V12
V15
U10
U13
U18
T11
T16
R14
R17
P12
P15
N13
N18
M11
M16
L14
L17
K12
K15
SOD-123
4.7 D2202
5% MBR0520LXXG AG7 VDD R18
SOD-123
1/8W
MF-LF
D2201 2 1 C2201 1 C2210 1 C2202 1 C2203 AG13 P11
2 805 10UF 10UF 1800UF 1800UF OMIT
6 U2200_VC_R 2 1 6 U2200_VC_D 20% 20% 20% 20% AG16 P16
6 U2200_VC
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
ELEC 2 6.3V
ELEC AG22 U3 P19
MBR0520LXXG
SOD-123
1206 1206 TH-KZJ TH-KZJ
AE4 U3LITE N4
1 C2204 1 C2216 AE10
V1.0-300MM
PBGA N8
1UF 1UF D AE19 N9
R2202
(SYM 6 OF 7)
20% 2 6 20%
2 25V
CERM VCC VC 2 25V
CERM 0
Q2201 1 C2217 AE25 N14
805
U2200 805 1 2 6 Q2201_GATE NTD60N02R
CASE369
1UF
20% AC7 N17
G
IRU3037CS 5% 2 25V
CERM AC13 N23
C SOI
HD 5 6 U2200_GATE_H
1/8W
MF-LF
805
S
805 L2201
1.53UH AC16 N27 C
6 U2200_SS 8 SS AC22 M12
LD 3 6 U2200_GATE_L MIN_NECK_WIDTH=0.2MM AB2 M15
TH
6 U2200_COMP 7 COMP NOSTUFF AB6 M20
NOSTUFF
FB 1 6 U2200_FEEDBACK 1
R2204 1 C2207 R2203
1 AB23 L10
R2201
1 D 4 1.1K 1UF 2.21K AB27 L13
27.4K GND Q2202 1%
1/16W 20%
2 10V
0.5%
1/16W AA10 L18
1%
1/16W 4 1 NTD60N02R MF-LF
402 CERM MF-LF
2 603
AA19 K2
MF-LF G
CASE369 2 603 1
C2208 1
C2209 Y12 K6
1 C2214 2 402 1 C2213 1 C2206 S3 6 R2204_P2 1800UF
20%
1800UF
20% Y15 K11
0.1UF R2201_P2 68PF 220PF 6.3V 6.3V
20%
2 16V
5%
50V
5%
25V
1 C2205 1
NOSTUFF
C2212
2 ELEC
TH-KZJ
2 ELEC
TH-KZJ
Y20 GND K16
CERM
603
1 C2215 2 CERM
603
2 CERM
402 5%
2200PF 1UF R2205
1 W4 GND K21
3900PF 50V
2 CERM 20% 10K W8 K25
5% 2 25V 0.5% W13 J9
2 50V
CERM
603 CERM
1206 1/16W
603 MF-LF W18 J14
2 603
W21 H10
W25 H19
V11 G4
V16 G23
U2200_FEEDBACK V19 G27
U9 F13
U14 F16
U17 F22
CHECK FETS T2 D2
T6 D7
T12 D10
B T15
T20
D19
D25
B
T23 B4
1.5V RUN FET PP3V3_RUN

DEVELOPMENT
6 7 10 11 18 34 50
T27
R10
B13
B16
IS D2250 NEEDED?
1
R2260 R13 B22
330
5%
1/16W
PP1V5_RUN MF-LF
51 50 7 PPVCORE_GPU 2 402
NOSTUFF LED_PP1V5_RUN_P
D2250
2
10BQ040PBF 1 DEVELOPMENT
DEVELOPMENT
SMB LED2200
R2261 3
DEVELOPMENT GREEN
1
0 6 LM339A
2.0X1.25A
22 7 =PPVCORE_NB Q2250 1
5%
2 PP1V5_RUN_FOR_LED
V+ SOI
2
IRF7413 1 LED_PP1V5_RUN_N
SO-8 1/16W
MF-LF
402
U1001
7 GND
5 6 7 8
50 34 10 1V1_REF
1 2 3

12
PP5V_PWRON RDSON=0.012 OHM
@ VGS=3.5 V
NOSTUFF
4
C2250
R2250
100K 1
0.1UF
1 2
U3LITE CORE POWER
2 Q5006G
A 5%
1/16W
MF-LF
20%
10V
SYNC_MASTER=N/A

SYNC_DATE=N/A
A
402 3 CERM
402
Q2251 D THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
2N7002 AGREES TO THE FOLLOWING
SOT23-LF 1
S G SYS_SLEEP 6 8 9 10 11 46 50 59 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
2
D 051-6772 E
APPLE COMPUTER INC.
SCALE
NONE 22 102
SHT OF
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
Page Notes
- _PPPCI64_PWRON_SB (to 5V or 3.3V)
- _PPPCI32_PWRON_SB (to 5V or 3.3V)
- _PP3V3_PWRON_SB
- _PP2V5_PWRON_SB
- _PPVCORE_PWRON_SB (1.2V)
NOTE: PCI pads use the VIO supply to meet
different drive timing
characteristics required by the PCI
D spec for 5V vs. 3.3V operation.

Connect _PPPCI32_PWRON_SB to
D
appropriate PCI bus voltage and
_PPPCI64_PWRON_SB to same if 64-bit
PCI, otherwise 3.3V.
(NONE)
(NONE)
Power Sequencing:
Must power Shasta VCore rail before any
other Shasta supplies. =PP2V5_PWRON_SB 7 23 25 74 88
7 6 3 =PPVCORE_PWRON_SB
1 C2350 1 C2351
0.1uF 0.1uF
20% 20%
H15
J12
J15
L15
M15
P15
R10
R12
T10
T15
1 C2300 1 C2301 1 C2302 1 C2303 1 C2304 10V 10V
H8
K8
L8
N8
R9
2 CERM 2 CERM
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 402 402
20% 20% 20% 20% 20% VDDC
2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM AA1 D19
402 402 402 402 402
AA2 VDDO25 G15
AA3 U2300
AB10
SHASTA =PPPCI64_PWRON_SB 7
V1.0 H18
1 C2305 1 C2306 1 C2307 1 C2308 1 C2309 AB2 BGA
H17
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF AB6 (1 OF 8) VIO1
20% 20% 20% 20% 20% K21 1 C2355 1 C2356 1 C2357
C 2 10V
CERM
402
2 10V
CERM
402
2 10V
CERM
402
2 10V
CERM
402
2 10V
CERM
402
B1
B2
POWER
0.1uF
20%
2 10V
0.1uF
20%
2 10V
0.1uF
20%
2 10V
C
B5 L21 CERM CERM CERM
VDDO33
402 402 402
D1 OMIT W22
VIO2
F4 Y19 For PCI_AD<63..32>
1 C2310 1 C2311 1 C2312 1 C2313 1 C2314 F8
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
20% 20% 20% 20% 20% H1
2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM L7 VDDP_KL V8 =PPPCI32_PWRON_SB 7
402 402 402 402 402
M1
R2
U12
1 C2360 1 C2361 1 C2362
Shasta max (est 06/30/03) current: 0.1uF 0.1uF 0.1uF
U9 20% 20% 20%
10V 10V 10V
V7 2 CERM 2 CERM 2 CERM
74 25 7 =PP3V3_PWRON_SB DIGITAL - 1.2V - 950 mA (1175 mW) 402 402 402
W4 ANALOG12 - 1.2V - 600 mA ( 760 mW)
VDDPs - 2.5V - 100 mA ( 250 mW) For PCI_AD<31..0>
1 C2320 1 C2321 1 C2322 1 C2323 1 C2324 A1 I/O 2.5 - 2.5V - 20 mA ( 60 mW) W5
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF A2 I/O 3.3 - 3.3V - 220 mA ( 770 mW) W19
20% 20% 20% 20% 20% =PP2V5_PWRON_SB 7 23 25 74 88
10V 10V 10V 10V 10V A22 U22
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 A5 Total: 3015 mW U13
AA10 U10
AA6 T12
1 C2365
0.1uF
AB1 R19 20%
1 C2325 1 C2326 1 C2327 1 C2328 1 C2329 AB22 P9
10V
2 CERM
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 402
20% 20% 20% 20% 20% C19 P4
10V
2 CERM 10V
2 CERM 10V
2 CERM 10V
2 CERM 10V
2 CERM D2 GND GND P14
402 402 402 402 402
E22 P13
F3 P12
B F7 P10 B
1 C2330 1 C2331 1 C2332 1 C2333 1 C2334 H2 N9
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF H9 N22
20% 20% 20% 20% 20%
2 10V 2 10V 2 10V 2 10V 2 10V J10 N13
CERM CERM CERM CERM CERM
402 402 402 402 402 J11 N12
J13 N11
J14 N10
J16 M2
1 C2335 1 C2336 1 C2337 1 C2338 1 C2339 GND
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
J22
K10
K11
K12
K13
K7
K9
L10
L11
L12
L13
L14
L16
L9
M10
M11
M12
M13
M14
20% 20% 20% 20% 20%
2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
402 402 402 402 402
Shasta Core Power

A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
APPLE COMPUTER INC.

D 051-6772 E
SCALE SHT OF
NONE 23 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
D D
60 7 =PP1V2_HT
PP3V3_PWRON PP2V5_PWRON
PP2V5_PWRON
R2400
1
100
1%
U3LITE REQUIRES ALL JTAG SIGNALS 1/16W
HIGH FOR NORMAL OPERATION
NOSTUFF MF-LF
2 402
R2420
1
R2419
1
1 C2401 NB_VSP_CLK_VREF
330
5%
330
5%
1000PF VOLTAGE=0.6V MIN_LINE_WIDTH=0.6MM 1/16W 1/16W
5% MIN_NECK_WIDTH=0.2MM MF-LF MF-LF
25V
2 CERM
C2400 R2402 R2401 2 402 2 402
R2424 R2426 R2429 R2431 R2433 R2436
1 1 1 1 1 1
603 R2403
1 1
0.1UF
1 1
PMU_SUSPEND_REQ NB_SUSPEND_REQ_L 24
10K 10K 10K 10K 10K 10K 100 20%
121 121
5% 5% 5% 5% 5% 5% 1% 1% 1% 6 3
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2 10V
CERM 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF
2 402 2 402 2 402 2 402 2 402 2 402 2 402
402
2 402 2 402
D
Q2404
2N7002DW
D
Q2404
2N7002DW
U3 28 25 13 SMU_SUSPENDREQ_L 2 G S
SOT-363 5 G S
SOT-363
U3LITE
V1.0-300MM 1 4
PBGA
(SYM 7 OF 7)
27 VSP_NB_CLK_P P4 VSP_CLKP HRESET* A21 NB_WARM_RESET_L 8

R4 VSP_CLKN OMIT E20 NOSTUFF
27 VSP_NB_CLK_N PURESET* NB_COLD_RESET_L 24
R2408
R25 CE1_LT_TCK SUSPENDACK* D20 NB_SUSPEND_ACK_L 8 0
JTAG_NB_TCK JTAG_NB_TCK D21
1 2
SUSPENDREQ* NB_SUSPEND_REQ_L 24
JTAG_NB_TDI JTAG_NB_TDI V25 CE1_A_TDI 5%
1/16W
JTAG_NB_TDO JTAG_NB_TDO AA25 CE1_B_TDO API0_ISCL A20 I2C_NB_A_SCL 18 MF-LF
402
JTAG_NB_TMS JTAG_NB_TMS M26 CE1_DI1_TMS API_ISCA B20 I2C_NB_A_SDA 18
C JTAG_NB_TRST_L JTAG_NB_TRST_L
NB_RI_PU
F20 CE1_DI2_TRST
AC2 CE1_RI
SYS_ISCL0 C20
SYS_ISCA0 B21
I2C_NB_B_SCL
I2C_NB_B_SDA
18
18
C
AH3 CEO_TEST SYS_ISCL1 C21 I2C_NB_C_SCL 18
NB_TEST_PD
AD5 CE0_MC SYS_ISCA1 E21 I2C_NB_C_SDA 18
NB_MC_PD
NB_RE_PD AD3 CE0_RE DUMMY_A AC28 TP_DUMMY_A 6
D15 PM_SLEEP0 DUMMY_B AB28 TP_DUMMY_B 6

6 TP_NB_PM_SLEEP0
R2444 1R2443 1R2442
1
IRQ0 E9 NB_INT_L 25
10K 10K 10K
5% 5% 5%
1/16W 1/16W 1/16W PMR_OBSV Y9 NB_PMR_OBSV 8
MF-LF MF-LF MF-LF
2 402 2 402 2 402 THMI J17 NB_THMI 8
THMO J18 NB_THMO 8
PP3V3_PWRON
PP2V5_PWRON
NOSTUFF NOSTUFF
B R2405 R2438
1
4.7K
1
10K
R2435
1
4.7K B
5% 5% 5%
1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF
2 402 2 402 2 402
NB_PU_RESET NB_COLD_RESET_L 24
6 NOSTUFF 3 NOSTUFF
D
Q2412
2N7002DW
D
Q2412
2N7002DW
2 SOT-363 5 SOT-363
13 8 SYS_COLD_RESET_L G S G S
1 4
R2406
1
0 2
5%
1/16W
MF-LF
402
U3LITE MISC
A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
D 051-6772 E
APPLE COMPUTER INC.
SCALE SHT OF
NONE 24 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
I2S0_TO_SB I2S0_DEV_TO_SB_DTI 25 95 74 25 23 7 =PP3V3_PWRON_SB

I2S0_TO_DEV I2S0_SB_TO_DEV_DTO
R2554
25 95
I2S0_TO_DEV AUDIO I2S0_MCLK

I2S0_BITCLK
25 102
SB_TO_SMU_INT_L 1
1K 2
I2S0_BIDIR 25 102 25 13
NO STUFF
I2S0_BIDIR I2S0_SYNC 5%
R2555
25 95
1/16W
MF-LF
I2S1_TO_SB I2S1_DEV_TO_SB_DTI 6 25 94
CPU_SRESET_L
402
1
10K 2
30 29 25
I2S1_TO_DEV I2S1_SB_TO_DEV_DTO 6 25 94
5%
I2S1_TO_DEV P25MM I2S1_MCLK
I2S1_BITCLK
6 25 94
R2560
1K
1/16W
MF-LF
402
I2S1_BIDIR 6 25 94
1 2
SYS_OVERTEMP_L
D I2S1_BIDIR I2S1_SYNC 6 25 94 PP1V2_PWRON_SB_PLL45VDD

VOLTAGE=1.2V
MIN_LINE_WIDTH=0.5MM R2520 =PP1V2_PWRON_SB
27 25 13
5%
1/16W
R2561
D
I2S2_TO_SB I2S2_DEV_TO_SB_DTI 25 102 MIN_NECK_WIDTH=0.25MM 1
3.3 2 7
MF-LF
402 10K
I2S2_TO_DEV I2S2_SB_TO_DEV_DTO 25 102 25 UDASH_RESET_L 1 2
5% NO STUFF
I2S2_MCLK 1/8W 5%
I2S2_TO_DEV P25MM
I2S2_BITCLK
25 102
C2521 1 C2520 1 MF-LF
805 R2562 1/16W
MF-LF
I2S2_BIDIR 25 102
1uF
10%
10uF
20% 1K 402
I2S2_BIDIR I2S2_SYNC 25 102 6.3V 2 6.3V 2 33 27 25 13 SYS_SLEWING_L 1 2
CERM CERM REDUNDANT - NEED TO ADDRESS THIS 5%
402 1206
SB_CLK18M_XTAL CLOCKS SB_CLK18M_XTALI
SB_CLK18M_XTALO
25 1/16W
MF-LF
402
R2563
10K
CLOCKS 25
1 2
94 25 6 MODEM_RING2SYS_L
CLOCKS SB_CLK18M_XTALO_R 25 PP2V5_PWRON_SB_XTAL18VDD
SB_CLK25M_ATA CLOCKS SB_CLK25M_ATA =PP2V5_PWRON_SB R2505 VOLTAGE=2.5V
5%
1/16W
25 27 88 74 23 7
1
3.3 2 MIN_NECK_WIDTH=0.25MM
PP1V2_PWRON_SB_PLL49VDD 10K
MF-LF
402
VOLTAGE=1.2V R2530 I2S1_RESET_L 1 2
Page Notes
94 25 6
5% MIN_LINE_WIDTH=0.5MM
1/8W 3.3 5%
MF-LF
805
1 C2500 1 C2501 MIN_NECK_WIDTH=0.25MM 1 2 1/16W
MF-LF
10uF
20%
1uF
10% 5% 402
1/8W
Power aliases required by this page: 2 6.3V 2 6.3V C2531 1 C2530 1 MF-LF
- _PP3V3_PCI
CERM
1206
CERM
402 1uF 10uF 805 R2565
10%
6.3V 2
20%
6.3V 2 10K 2
- _PP3V3_PWRON_SB CERM CERM 25 SB_SATABR_RESET_L 1
- _PP2V5_PWRON_SB 402 1206 REDUNDANT - NEED TO ADDRESS THIS 5%
- _PP1V2_PWRON_SB R2566
0
1/16W
MF-LF
402
PP2V5_PWRON_SB_XTALVDD 89 25 FW_LOWPWR 1 2
Signal aliases required by this page: R2510 VOLTAGE=2.5V
MIN_LINE_WIDTH=0.5MM 5%
(NONE) 1
3.3 2 MIN_NECK_WIDTH=0.25MM
=PP3V3_PWRON_SB
1/16W
MF-LF R2567
7 23 25 74
402 10K
BOM options provided by this page: 5%
1/8W
NOSTUFF 25 12 ENETFW_RESET 1 2
C2510 1 C2511
AA13
- PCI_64BIT MF-LF 1 5%
R2568
W14
Y13
Y12
W17
805 1/16W
Configures Shasta for 64-bit PCI 10uF
20%
1uF
10%
1 C2540 10K
MF-LF
402
NOTE: XGC required for Shasta GPIOs Re-pin within each RPAK as necessary 2 6.3V
CERM 2 6.3V
CERM
0.1uF 86 25 ENET_ENERGYDET 1 2
C - MPIC_NB/MPIC_SB
Selects whether NorthBridge or
DO NOT swap between RPAKs
R2511
0
1206 402
XTAL
VDD
XTAL_18 PLL_45 PLL_49
VDD VDD VDD
VIO
PME
20%
2 10V
CERM
402
5%
1/16W C
SouthBridge MPIC will be used for
1 2 U2300 OMIT
MF-LF
402
5% SHASTA
I2S0: Audio DAC

interrupt controller. 1/16W
MF-LF V1.0 74 25 23 7 =PP3V3_PWRON_SB
GPIO "Slot E" - AD21
402 BGA
95 25 I2S0_DEV_TO_SB_DTI (I2S0_DEV_TO_SB_DTI) W7 I2S0DTI_H
(2 OF 8) 6 PCI1REQ_3_L U17 PCI_SLOTE_REQ_L 25 RP2550
95 25 I2S0_SB_TO_DEV_DTO 4 5 I2S0_SB_TO_DEV_DTO_R Y5 I2S0DTO_H 7 PCI1GNT_3_L AA19 PCI_SLOTE_GNT_L 25
4
10K 5
RP2510 "Slot F" - AD22 SB_GPIO12
I2S0
25
I2S0_MCLK 3 33 6 I2S0_MCLK_R U8 I2S0MCLK_H
102 25
102 25 I2S0_BITCLK 1 5%
1/16W 8 I2S0_BITCLK_R AA4 I2S0BITCLK_H 8 PCI1REQ_4_L AB21 PCI_SLOTF_REQ_L
AA20 PCI_SLOTF_GNT_L
25 5%
1/16W
RP2550
10K
2 SM-LF 7 Y6 I2S0SYNC_H 9 PCI1GNT_4_L 25 56 SM-LF 2 7
NorthBridge / SouthBridge MPIC Routing I2S0_SYNC I2S0_SYNC_R PCI_SLOTB_INT_L
I2S1: Soft Modem

95 25 25
I2S1_DEV_TO_SB_DTI (I2S1_DEV_TO_SB_DTI) V10 I2S1DTI_H

10 PCI1REQ_5_L U16 SB_TO_SMU_INT_L 13 25 RP2550 5%
1/16W
PP3V3_RUN
94 25 6
2 7 AB5 11 PCI1GNT_5_L Y20 CPU_SRESET_L 25 29 30
1
10K 8 SM-LF
94 25 6 I2S1_SB_TO_DEV_DTO I2S1_SB_TO_DEV_DTO_R I2S1DTO_H 25 PCI_SLOTC_INT_L
RP2520
1 8 V9 PCI1AD_32_H D18 RP2551
(SCCA)
I2S1
94 25 6 I2S1_MCLK 33 I2S1_MCLK_R I2S1MCLK_H 12 SB_GPIO12 25 5%
4 5% 5 AA8 A20 1/16W 10K
94 25 6 I2S1_BITCLK 1/16W I2S1_BITCLK_R I2S1BITCLK_H 13 PCI1AD_33_H SYS_OVERTEMP_L 13 25 27 SM-LF
SM-LF PCI_SLOTF_INT_L 1 8
R2576 AA7 F18 25
1 I2S1_SYNC 3 6 I2S1_SYNC_R I2S1SYNC_H 14 PCI1AD_34_H UDASH_SDOWN
10K
94 25 6
I2S1_RESET_L (I2S1_RESET_L) V5 GPIO_H_0 15 PCI1AD_35_H F17 UDASH_RESET_L

94
RP2551 5%
1/16W
5%
94 25 6
G16
25
3
10K 6 SM-LF
1/16W AA5 I2S2DTI_H 16 PCI1AD_36_H AGP_INT_L 49 25 SB_GPIO23
MF-LF I2S2_DEV_TO_SB_DTI (I2S2_DEV_TO_SB_DTI)
I2S2: S/P-DIF
2 402 To SouthBridge ->

102 25
I2S2_SB_TO_DEV_DTO 4 5 I2S2_SB_TO_DEV_DTO_R Y8 I2S2DTO_H 17 PCI1AD_37_H F16 PCI_SLOTA_INT_L 6 25 76 5%

1/16W
RP2551
102 25
3 RP2530 6 Y7 I2S2MCLK_H 18 PCI1AD_38_H A21 PCI_SLOTB_INT_L 25 SM-LF 2
10K 7
I2S2
(SCCB)
NB_TO_SB_INT 25 102 25 I2S2_MCLK 33 I2S2_MCLK_R B21 25 SB_GPIO24
5% 19 PCI1AD_39_H PCI_SLOTC_INT_L
MPIC_SB 102 25 I2S2_BITCLK
2 1/16W
SM-LF
7 I2S2_BITCLK_R AB4 I2S2BITCLK_H
20 PCI1AD_40_H C20 PCI_SLOTD_INT_L
25
RP2550 5%
1/16W
R2575 3 102 25 I2S2_SYNC
1 8 I2S2_SYNC_R W9 I2S2SYNC_H
G17
25
3
10K 6 SM-LF
-> From NorthBridge MPIC_SB 21 PCI1AD_41_H PCI_SLOTE_INT_L SB_GPIO25
10K 102 I2S2_RESET_L
Y2 GPIO_H_1 25 25
24 NB_INT_L 1 2 NB_INT_L_R 1 Q2576 AUDIO GPIO - see note on right

(I2S2_RESET_L)
22 PCI1AD_42_H G18 PCI_SLOTF_INT_L 25 5%
1/16W
RP2551
MPIC_NB 5% 2N3904LF 25 SB_INT_L AB3 GPIO_H_2 23 PCI1AD_43_H E19 SB_GPIO23 25 SM-LF 4
10K 5
GPIO
1/16W SOT23 SB_GPIO30
R25791 W8 GPIO_H_3 F19 25
MF-LF 2 MODEM_RING2SYS_L 24 PCI1AD_44_H SB_GPIO24 NOSTUFF
0
402
=PP3V3_PWRON_SB
94 25 6
SB_PCI_SEL32BIT W6 PCI_SEL32BIT_H 25 PCI1AD_45_H D20 SB_GPIO25

25
R2570 RP2552 5%
1/16W
5%
74 25 23 7 25
0 10K SM-LF
B E20 1 8
B
PCI
1/16W MPIC_SB 26 PCI1AD_46_H SB_SATABR_RESET_L 1 2 FW_LOWPWR SB_GPIO45
MF-LF I2C_SB_SCL Y9 I2CCLK_H 25 25 89 25
I2C
<- To CPU
402 2 R2578 From SouthBridge <- R25001
18 6
I2C_SB_SDA AB7 I2CDATA_H 27 PCI1AD_47_H C21 PCI_SLOTG_INT_L 25 77 5%

1/16W
5%
1/16W
RP2552
10K
CPU_INT_L 1
47 2 SB_INT_L
10K 18 6
28 PCI1AD_48_H F20 FW_LOWPWR_SHASTA MF-LF
402 SB_GPIO46 SM-LF 2 7
30 29 14 6 25 5% E9 G19 25
1/16W SYS_WARM_RESET_L RESET_L 29 PCI1AD_49_H ENETFW_RESET
5% MF-LF
77 74 8
W10 C22
12 25
RP2552 5%
PWR_MGT
1/16W 402 2 SB_STOPXTALS_L 30 SB_GPIO30 1/16W
MF-LF
13 STOPXTALS_L PCI1AD_50_H 25
10K SM-LF
AUDIO GPIOS
U11 D21
NOTE: It is the responsibility of

the audio circuit to provide the
necessary pull-ups & pull-downs.
402 28 24 13 SMU_SUSPENDREQ_L SUSPENDREQ_L 31 PCI1AD_51_H ENET_ENERGYDET 25 86 25 SB_GPIO47 3 6
PCI_64BIT
13 SB_SUSPENDACK_L V11
W18
SUSPENDACK_L 32 PCI1AD_52_H G20
D22
AUDIO_LO_DET_L 6 101 5%
1/16W
RP2552
10K
PCI 32-bit select SYS_PME_L PCI1PME_L 33 PCI1AD_53_H AUDIO_LO_OPTICAL_PLUG_L SM-LF
=PP3V3_PCI 7 74 75 76 77 R25011 77 13
TP_SB_WATCHDOG V12 INTRWD_H 34 PCI1AD_54_H K18 AUDIO_LI_DET_L

101
25 SB_GPIO49 4 5
R2550
1 = 32-bit PCI & GPIOs 1K5% 35 H19 AUDIO_LI_OPTICAL_PLUG_L
101
RP2553 5%
1/16W
0 = 64-bit PCI & XGC MF-LF
1/16W JTAG_SB_TDI AA11 TDI
PCI1AD_55_H 102
10K SM-LF
10K
1 2 PCI_SLOTE_REQ_L
8
JTAG_SB_TDO W11 36 PCI1AD_56_H J17 AUDIO_HP_DET_L 102 25 SB_GPIO50 4 5

402 2 TDO
5%
25 8
8 JTAG_SB_TCK AB11 TCK

37 PCI1AD_57_H F21
G21
AUDIO_SPKR_DET_L 102 5%
1/16W
RP2553
10K
R2551 1/16W Y11 38 PCI1AD_58_H AUDIO_LO_MUTE_L 98 SM-LF 2 7
TEST
MF-LF JTAG_SB_TMS TMS SB_GPIO51
10K 402
8
39 PCI1AD_59_H H20 AUDIO_HP_MUTE_L
25
1 2 PCI_SLOTE_GNT_L 25 8 JTAG_SB_TRST_L W12 TRST_L
40 PCI1AD_60_H J19 AUDIO_SPKR_MUTE_L
102
100
RP2553
10K
5%
1/16W
5% A3 TEST_MODE_H F22 SM-LF
1/16W
MF-LF R2552 SB_TEST_MODE_PD 41 PCI1AD_61_H AUDIO_EXT_MCLK_SEL 102 25 SB_GPIO52 3 6
402 10K
1 2 PCI_SLOTF_REQ_L
6 TP_SB_PLLTEST U14 PLLTEST 42 PCI1AD_62_H G22 AUDIO_GPIO_11 102 5%
1/16W
RP2553
10K
R2580 V14 FSTEST H21
25
1 6 TP_SB_FSTEST 43 PCI1AD_63_H AUDIO_GPIO_12 101 SM-LF
5% SMU_TO_SB_INT_L 1 8
R2553 1/16W
MF-LF
4.7K SB_CLK18M_XTALI W13 XTAL_18_I J20 I2S0_RESET_L
25 13
5% 25 44 PCI1C_BE_4_L 5%
1
10K 2 402
PCI_SLOTF_GNT_L
1/16W
SB_CLK18M_XTALO_R V13 XTAL_18_O H22 SB_GPIO45
95
1/16W
XTALS
25 56 MF-LF 25 45 PCI1C_BE_5_L 25 SM-LF
402 2 K22
5% 46 PCI1C_BE_6_L SB_GPIO46
U15 XTALI 25
1/16W
MF-LF R2556 27 25 SB_CLK25M_ATA
47 PCI1C_BE_7_L K20 SB_GPIO47
402 10K 2 NC V15 XTALO
25
1 PCI_SLOTA_INT_L 6 25 76
1
R2590 48 PCI1REQ64_L K17 SYS_SLEWING_L
200 13 25 27 33
R2557
5%
1/16W
MF-LF
1%
1/16W
49 PCI1ACK64_L L17 SB_GPIO49 25 Shasta Serial / Misc
10K 2 402 MF-LF 50 PCI1PAR64_H E18 SB_GPIO50 25
A 1
5%
PCI_SLOTD_INT_L 25
Y2590
2 402
51 XGI_CLK_H Y4 SB_GPIO51
SYNC_MASTER=N/A SYNC_DATE=N/A
A
R2558
25
1/16W 18.432M SB_CLK18M_XTALO NOTICE OF PROPRIETARY PROPERTY
XGI_DTO0_H U7
25
MF-LF 52 SB_GPIO52
XGI
402 10K 1 2 25
1 2 PCI_SLOTE_INT_L 25 53 XGI_DTO1_H T9 NB_TO_SB_INT 25 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
5% 11.4X4.7X4.2-SM XGI_DTI_H W2 SMU_TO_SB_INT_L
R2559 1/16W
MF-LF
C2590 1 1 C2591 54 13 25 AGREES TO THE FOLLOWING
10K 402 22pF

5%
22pF
5%
XTAL_18
GND
PLL_45
GND
PLL_49
GND
1 2 PCI_SLOTG_INT_L 25 77 50V II NOT TO REPRODUCE OR COPY IT
CERM 2 2 50V
AB12
AB13
AA12
5% CERM III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1/16W 402 402
MF-LF
402 SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.

D 051-6772 E
25 102
SCALE SHT OF
NONE
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
L2601 26 7 =PPVCORE_PWRON_PULSAR SYM 2 OF 2

26 7 =PPVCORE_PWRON_PULSAR 180-OHM-1.5A F1 C1_VDD OMIT
C1_VSS G1
1 2 L3 C2_VDD U2600 C2_VSS M4
0603 E12 C3_VDD PULSAR C3_VSS E10
FSBGA
R2601
4.7
B9 C4_VDD C4_VSS C9
1 2 PP1V5_PSL_PLL1 D10 VDD_PLL1 VSS_PLL1 D12

VOLTAGE=1.5V D2 VDD_PLL2
5% VSS_PLL2 D1
1/16W
MF-LF
1 C2645 1 C2609 MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM L8 VDD_PLL3 VSS_PLL3 K8
402 2.2UF 0.1UF
20% M3 VDD_PLL4
20% VSS_PLL4 M2
1 C2611 2 6.3V 2 10V
D
D 0.1UF
20%
CERM1
603
CERM
402
PP3V3_PWRON
VSS_CML A6
2 10V
CERM
B2 VDD_I2C VSS_I2C C2
402 26 7 =PP1V2_PULSAR G12 VDD_NBSYNC VSS_NBSYNC F11
PLACE NEAR PIN D10 D12 M12 VDD_PCLK VSS_PCLK L12
L2603 =PP2V5_PWRON_RAM
180-OHM-1.5A 46 40 37 26 7
H3 VDD25 VSS25 L2
1 2 PP3V3_PWRON K1 VDD25 VSS25 H2
0603 PP3V3_RUN
R2609 E1 VDD33 VSS33 E2
1
4.7 2 PP1V5_PSL_PLL2
L5 VDD33_BC VSS33_BC L7
VOLTAGE=1.5V M9 VDD33_BC1 VSS33_BC1 M5
5% =PPVCORE_PULSAR
1/16W
MF-LF
26 7
A11 VDD_HCLK0 VSS_HCLK0 C10
402 2.2UF 0.1UF
20% A9 VDD_HCLK0
20% VSS_HCLK0 B11
1 C2613 6.3V
2 CERM1 2 10V
CERM A8 VDD_HCLK1 VSS_HCLK1 B7
0.1UF 603 402
20% C5 VDD_HCLK2 VSS_HCLK2 A4
2 10V
CERM B4 VDD_HCLK2
402 VSS_HCLK2 A7
26 7 =PP1V2_PULSAR K10 VDD_HSYNC
PLACE NEAR PIN D2 D1 VSS_HSYNC H10
L2605
180-OHM-1.5A
H12 VDD_HSYNC VSS_HSYNC K12
26 7 =PPVCORE_PULSAR
1 2 J11 VDD15_HSYNC
0603 M11 VDD15_PCLK
R2603
4.7
A1 VDD_VCLK VSS_VCLK A3
1 2 PP1V5_PSL_PLL3 A12 VDD_XTAL VSS_XTAL C12
VOLTAGE=1.5V
5%
1/16W
MF-LF
402 2.2UF 0.1UF
C 1 C2615
0.1UF
20%
6.3V
2 CERM1
603
20%
2 10V
CERM
402 PINS G12, M12, H3, K1, L5, M9, A11, A9
C
20%
2 10V
CERM A8, C5, B4, K10, H12 J11, M11, A1
402 CAN BE TURNED OFF IN SLEEP
L2607 PLACE NEAR PIN L8 K8
180-OHM-1.5A
1 2 PP3V3_PWRON PP3V3_RUN
0603
R2605
4.7
1 2 PP1V5_PSL_PLL4 1 C2665 1 C2667 1 C2651 1 C2671
5%
VOLTAGE=1.5V 0.1UF 0.1UF 0.1UF 0.1UF
1/16W
MF-LF
MIN_NECK_WIDTH=0.2MM 20%
2 10V
20%
2 10V
20%
2 10V
20%
2 10V
402 2.2UF
20%
0.1UF
20%
CERM
402
CERM
402
CERM
402
CERM
402
1 C2619 6.3V
2 CERM1 2 10V
CERM
0.1UF 603 402 46 40 37 26 7 =PP2V5_PWRON_RAM
20%
2 10V
CERM
402
PLACE NEAR PIN M3 M2 1 C2639 1 C2640
PP3V3_PWRON L2609
180-OHM-1.5A
0.1UF
20%
0.1UF
20%
2 10V
CERM 2 10V
CERM
1 2 402 402
0603
R2607
1
4.7 2 PP3V3_PSL_XTAL
VOLTAGE=3.3V 26 7 =PPVCORE_PULSAR
5%
1/16W
MF-LF
402 2.2UF
20%
0.1UF
20%
1 C2631 1 C2632 1 C2633 1 C2634 1 C2635 1 C2636 1 C2637 1 C2638
B 1 C2620 2 6.3V
CERM1 2 10V
CERM
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20% B
0.1UF
20%
603 402 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
2 10V
CERM
402 402 402 402 402 402 402 402
402
402 CAPS NOT NEEDED

26 7 =PPVCORE_PWRON_PULSAR
IF 603 CAN BE PLACED CLOSE TO PULSAR
1 C2627 1 C2628 1 C2629 1 C2630
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
402 402 402 402
26 7 =PP1V2_PULSAR
1 C2623 1 C2624 1 C2625 1 C2626

0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
402 402 402 402
TABLE_5_HEAD
359S0076 1 PULSAR, PBGA U2600

TABLE_5_ITEM
PULSAR POWER
A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
APPLE COMPUTER INC.

D 051-6772 E
SCALE SHT OF
NONE 26 102
8 5 4 3 2 1
7 6
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8 7 6 5 4 3 2 1
ELECTRICAL_CONSTRAINT_SET NET_PHYSICAL_TYPE NET_SPACING_TYPE DIFFERENTIAL_PAIR
29 27
29 27
EI_CPU_CLK_P
EI_CPU_CLK_N
EI_CPU_CLK
EI_CPU_CLK
CLOCKS
CLOCKS
CLOCKS
CLOCKS
EI_CPU_CLK
EI_CPU_CLK
I86 R2701
0 5%
I87 1 2 PCI_CLK_GP0 8
14 6 EI_CPU1_CLK_P EI_CPU1_CLK CLOCKS CLOCKS EI_CPU1_CLK I116 3.3V 33MHZ
14 6 EI_CPU1_CLK_N EI_CPU1_CLK CLOCKS CLOCKS EI_CPU1_CLK I117
R2761
28 27 EI_NB_CLK_P EI_NB_CLK CLOCKS CLOCKS EI_NB_CLK I96 0
1 2 PCI_CLK_GP1 8
28 27 EI_NB_CLK_N EI_NB_CLK CLOCKS CLOCKS EI_NB_CLK I97 3.3V 33MHZ
5% 402
29 27 EI_CPU_SYNC EI_SYNC CLOCKS CLOCKS I98
EI_NB_SYNC CLOCKS CLOCKS
C2708
28 27 I99
D 14 6 EI_CPU1_SYNC EI_CPU1_SYNC CLOCKS CLOCKS I118

0.001UF
50V 1 2CERM
D
27 24 VSP_NB_CLK_P VSP_NB_CLK CLOCKS CLOCKS VSP_NB_CLK I94
27 24 VSP_NB_CLK_N VSP_NB_CLK CLOCKS CLOCKS VSP_NB_CLK 10% 402
I95 VSP_NB_CLK_P 24 27
C2710 VSP_NB_CLK_N 24 27
48 27 AGP_CLK66M_NB AGP_NB_CLK CLOCKS CLOCKS I100 0.001UF
49 27 AGP_CLK66M_GPU AGP_GPU_CLK CLOCKS CLOCKS 50V 1 2CERM
I101
10% 402
60 27 HT_CLK66M_NB HT_NB_CLK CLOCKS CLOCKS
62 27 HT_CLK66M_SB HT_SB_CLK CLOCKS CLOCKS
I102
C2713
I103
0.001UF
50V 1 2CERM
74 27 PCI_CLK66M_SB_INT CLOCKS_PCI CLOCKS CLOCKS I90 10% 402
74 8 PCI_CLK33M_SB_EXT CLOCKS_PCI CLOCKS CLOCKS I91 EI_CPU_CLK_P
C2715
27 29
EI_CPU_CLK_N 27 29
27 PLS_EXTCLK PLS_XTAL CLOCKS CLOCKS I119 0.001UF
50V 1 2CERM
30 29 27 CPU_HTBEN CLOCKS CLOCKS I120 10% 402
DIFFERENTIAL SIGNALS SHOULD HAVE 5 MIL SPACING TO EACH OTHER NET

ALL SPACING GROUPS SHOULD HAVE 15 MIL SPACING TO SIGNALS NOT IN THEIR GROUP SPACING
TYPE
EI_NB_SYNC IS PART OF EI_CPU_SYNC TOPOLOGY SYM 1 OF 2
GPCLK33_0 L4 PCI_CLK_GP0_R CLOCKS

GPCLK33_1 K4 PCI_CLK_GP1_R CLOCKS
OMIT
VCLKN A2 VSP_NB_CLK_N_C CLOCKS
U2600 VCLKP B3 C2700
C PULSAR HCLKN_0 B10
VSP_NB_CLK_P_C
EI_CPU_CLK_N_C
CLOCKS
CLOCKS
0.001UF C
50V 1 2CERM
FSBGA HCLKN_1 C8 EI_CPU1_CLK_N_R CLOCKS 14
10% 402
18 I2C_CLOCK_SCL C1 SCLK HCLKN_2 C4 EI_NB_CLK_N_C CLOCKS EI_NB_CLK_P 27 28
B1 SDATA HCLKP_0 A10 EI_CPU_CLK_P_C CLOCKS C2702 EI_NB_CLK_N 27 28
R2704
18 I2C_CLOCK_SDA
HCLKP_1 B8 EI_CPU1_CLK_P_R CLOCKS 14
0.001UF
0 50V 1 2CERM
13 CLOCK_RESET_L 1 2 PLS_RESET_L D3 RESET* HCLKP_2 B5 EI_NB_CLK_P_C CLOCKS
NOSTUFF 10% 402
5% 402 0 R2775
C11 XIN GPCLK25_0 J3 6 PLS_CLK_66M_0_R CLOCKS 1 2 NOSTUFF 2.5V 66MHZ TP_PLS_CLK_66M_0 6
PLS_X_IN 0 R2776
GPCLK25_1 J1 6 PLS_CLK_66M_1_R CLOCKS 5% 402 1 2 2.5V 66MHZ TP_PLS_CLK_66M_1 6
PLS_X_OUT B12 XOUT 5% 402 20 R2703

NOSTUFF PCLK25_0 K2 6 HT_CLK66M_NB_R CLOCKS 1 2 2.5V 66MHZ HT_CLK66M_NB 27 60
R2738 20 R2709
0=IIC ADDR D2/D3 1K E3 ADDRSEL PCLK25_1 L1 6 RAM_CLK66M_NB_R CLOCKS 1 2 5% 402 2.5V 66MHZ RAM_CLK66M_NB 37
1 2 PLS_X_ADDRSEL
5% 402 0 R2705
1=IIC ADDR D4/D5 5% 402 PCLK33_0 K5 6 PCI_CLK66M_SB_INT_R CLOCKS 1 2 3.3V 66MHZ PCI_CLK66M_SB_INT 27 74
K3 TEST1 0 R2711
6 TP_PLS_TEST1 PCLK33_1 L6 PCI_CLK_P1_R CLOCKS 5% 402 1 2 3.3V 33MHZ PCI_CLK_P1 8
E11 TEST2 0 R2707
6 TP_PLS_TEST2 PCLK33_2 M7 6 AGP_CLK66M_GPU_R CLOCKS 1 2 5% 402 3.3V 66MHZ AGP_CLK66M_GPU 27 49
D11 TEST3 0 R2702
6 TP_PLS_TEST3 PCLK33_3 L9 6 PCI_CLK_P3_R CLOCKS 5% 402 1 2 3.3V 33MHZ PCI_CLK_P3 8
0 R2779
PCLK33_4 M10 6 PCI_CLK_P4_R CLOCKS 5% 402 1 2 PCI_CLK_P4 8
R2706 249 1 2 402 1% PLS_SCAN_MODE M1 SCAN_MODE 0 R2715 5% 402
HTBEN_0 K11 6 CPU_HTBEN_R CLOCKS 1 2 1.2V 33MHZ CPU_HTBEN 27 29 30
58 18 11 6 PP3V3_PWRON R2744 681 1 2 402 1% PLS_REF15 G11 REF15 HTBEN_1 J12 CPU1_HTBEN_R CLOCKS 6 14 5% 402
J2 REF25 NOSTUFF
R2740 1K 1 2 402 1% PLS_REF25 0 R2768
NBSYNC F12 6 EI_NB_SYNC_R CLOCKS NOSTUFF 1 2 1.2V EI_NB_SYNC
R2722 M6 REF33 27 28
1 R2746 1K 1 2 402 1% PLS_REF33
0 R2772 5% 402
1K TP_PLS_REF_CML A5 REF_CML HSYNC_0 J10 6 EI_CPU_SYNC_R CLOCKS 1 2 1.2V EI_CPU_SYNC 27 29
5%
HSYNC_1 H11
6
1/16W EI_CPU1_SYNC_R CLOCKS 6 14 5% 402
MF-LF B6 PRES_CML
NOSTUFF 2 402 R2742 806 1 2 402 1% PLS_PRES_CML 20 R2770
R2748 REFCLK_0 G2 6 SB_CLK25M_ATA_R CLOCKS NOSTUFF 1 2 2.5V 25MHZ SB_CLK25M_ATA 25
22 R2700
0 REFCLK_1 H1 SATA_CLK25M_R CLOCKS 1 2 5% 402 2.5V 25MHZ TP_SATA_CLK25M
B B
6
25 13 SYS_OVERTEMP_L 1 2 PLS_FORCE_P0_L_R F2 FORCESPO* 6
K9 0 R2720 5% 402
5% SLEWING* SLEWING_L_R CLOCKS 1 2 SYS_SLEWING_L
1/16W C3 PD 13 25 33
MF-LF ERROR* M8 CLOCK_ERROR_L 8 5% 402

402
0 R2717
PCLK12 L11 6 HT_CLK66M_SB_R CLOCKS 1 2 1.2V 66MHZ HT_CLK66M_SB 27 62
0 R2719
PCLK15 L10 6 AGP_CLK66M_NB_R CLOCKS 5% 402 1 2 1.5V 66MHZ AGP_CLK66M_NB 27 48
5% 402
3 =PULSAR_POWER_DOWN R2750 47 1 2 402 5% PULSAR_POWER_DOWN_R
NO STUFF
R2752
0 R2724 1K 1
NOSTUFF
2 402 5%
NOSTUFF 27 PLS_EXTCLK 1 2
NOSTUFF
J2700 R2762
1
5%
1/16W R2754
0
U.FL-R_SMT
F-ST-SM 24 MF-LF
402 1 2
3 5%
1/16W NO STUFF 5%
MF-LF
2 402
R2758
330K
1/16W
MF-LF
402
1 PLS_INTERM 1 2
NOSTUFF 5%
1/16W R2756
2
R2764
1
24
MF-LF
402
0 1 2
5% 5%
1/16W 1/16W
MF-LF CRITICAL MF-LF
402
2 402 Y2701
25.0000M
1 2
PLS_X_OUT_B
PLS_X_IN_B 8X4.5MM-SM
PULSAR CLOCKS
A C2707 1 1 C2705
SYNC_MASTER=N/A

SYNC_DATE=N/A
A
33PF 5% 5%
33PF
50V 50V THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
CERM 2 2 CERM PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
402 402
D 051-6772 E
APPLE COMPUTER INC.
SCALE
NONE 27 102
SHT OF
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
=PP1V2_EI_NB 7 14 18 28
29 28 14 6 EI_CPU_TO_NB_CLK_P EI_CPU_TO_NB_CLK EI_CLK EI_CPU_TO_NB_CLK EI_CPU_TO_NB_CLK I212

1 C28001 C2801
1 C2802
1 C2803
1 C2804
1 C2805
1 C2806
1 C2807
1 C2808
1 C2809
1 C2810
1 C2811
1 C2812
1 C2813
1 C2814
1 C2815
1 C2816
1 C2817
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
29 28 14 6
29 28 14 6
EI_CPU_TO_NB_CLK_N
EI_NB_TO_CPU_CLK_P
EI_CPU_TO_NB_CLK
EI_NB_TO_CPU_CLK
EI_CLK
EI_CLK
EI_CPU_TO_NB_CLK
EI_NB_TO_CPU_CLK
EI_CPU_TO_NB_CLK
EI_NB_TO_CPU_CLK
I213
I214
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% EI_NB_TO_CPU_CLK_N EI_NB_TO_CPU_CLK EI_CLK EI_NB_TO_CPU_CLK EI_NB_TO_CPU_CLK
2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V
29 28 14 6 I215
CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 EI_CPU_TO_NB_AD<0..43> EI_CPU_TO_NB_CAD EI_CAD EI_CPU_TO_NB_AD
29 28 14 6 I216
29 28 14 6 EI_NB_TO_CPU_AD<0..43> EI_NB_TO_CPU_CAD EI_CAD EI_NB_TO_CPU_AD I217
29 28 14 6 EI_CPU_TO_NB_SR_P<0> EI_CPU_TO_NB_CAD EI_SR EI_SR EI_CPU_TO_NB_SR0 I218

29 28 14 6 EI_CPU_TO_NB_SR_N<0> EI_CPU_TO_NB_CAD EI_SR EI_SR EI_CPU_TO_NB_SR0 I219
=PP1V5_PWRON_NB_AVDD
R2800 EI_CPU_TO_NB_SR_P<1> EI_CPU_TO_NB_CAD EI_SR EI_SR EI_CPU_TO_NB_SR1
D
60 48 37 7
1
2.2 2 PP1V5_PWRON_EI_NB_AVDD MIN_LINE_WIDTH=0.6MM
29 28 14 6
29 28 14 6 EI_CPU_TO_NB_SR_N<1> EI_CPU_TO_NB_CAD EI_SR EI_SR EI_CPU_TO_NB_SR1

I220
I221 D
VOLTAGE=1.5V MIN_NECK_WIDTH=0.2MM
5% 29 28 14 6 EI_NB_TO_CPU_SR_P<0> EI_NB_TO_CPU_CAD EI_SR EI_SR EI_NB_TO_CPU_SR0 I222
1/10W
MF-LF
603
1 C2818
1UF
1 C2819
0.1UF
=PP1V2_EI_NB 7 14 18 28 29 28 14 6 EI_NB_TO_CPU_SR_N<0> EI_NB_TO_CPU_CAD EI_SR EI_SR EI_NB_TO_CPU_SR0 I223
10% 20% 29 28 14 6 EI_NB_TO_CPU_SR_P<1> EI_NB_TO_CPU_CAD EI_SR EI_SR EI_NB_TO_CPU_SR1 I224
2 6.3V 2 10V EI_NB_TO_CPU_SR_N<1>
F21
J13
H13
H16
F10
D13
D16
B10
B19
CERM CERM 29 28 14 6 EI_NB_TO_CPU_CAD EI_SR EI_SR EI_NB_TO_CPU_SR1 I225
K4
K8
G2
F7
D4
B7
402 402
API VDD_API
APCLK_AVDD
U3 OMIT OMIT OMIT OMIT OMIT OMIT OMIT
U3LITE ZT2847
HOLE-VIA-20R10
ZT2857
HOLE-VIA-20R10 HOLE-VIA-20R10
ZT2867 ZT2807
HOLE-VIA-20R10
ZT2817 ZT2827
HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10
ZT2837
F15 V1.0-300MM D6
29 28 14 6 EI_NB_TO_CPU_CLK_P API0_BCLKIP PBGA API0_BCLKOP EI_CPU_TO_NB_CLK_P 6 14 28 29 1 1 1 1 1 1 1
29 28 14 6 EI_NB_TO_CPU_CLK_N E15 API0_BCLKIN

(SYM 1 OF 7)
API0_BCLKON E6 EI_CPU_TO_NB_CLK_N 6 14 28 29
OMIT OMIT OMIT OMIT OMIT OMIT OMIT
29 28 14 6 EI_NB_TO_CPU_AD<0> F11
F12
API0_ADI0
OMIT
API0_ADO0 J2
H1
EI_CPU_TO_NB_AD<0> 6 14 28 29 ZT2848
HOLE-VIA-20R10
ZT2858
ZT2868 ZT2808
HOLE-VIA-20R10
ZT2818 ZT2828
ZT2838
29 28 14 6 EI_NB_TO_CPU_AD<1> API0_ADI1 API0_ADO1 EI_CPU_TO_NB_AD<1> 6 14 28 29
1 1 1 1 1 1 1
29 28 14 6 EI_NB_TO_CPU_AD<2> G11 API0_ADI2 API0_ADO2 J1 EI_CPU_TO_NB_AD<2> 6 14 28 29
29 28 14 6 EI_NB_TO_CPU_AD<3> H11 API0_ADI3 API0_ADO3 K1 EI_CPU_TO_NB_AD<3> 6 14 28 29 OMIT OMIT OMIT OMIT OMIT OMIT OMIT
29 28 14 6 EI_NB_TO_CPU_AD<4> G12
H12
API0_ADI4 API0_ADO4 E1
F2
EI_CPU_TO_NB_AD<4> 6 14 28 29 ZT2849
HOLE-VIA-20R10
ZT2859
ZT2869 ZT2809
HOLE-VIA-20R10
ZT2819 ZT2829
ZT2839
29 28 14 6 EI_NB_TO_CPU_AD<5> API0_ADI5 APPLE PI API0_ADO5 EI_CPU_TO_NB_AD<5> 6 14 28 29
1 1 1 1 1 1 1
29 28 14 6 EI_NB_TO_CPU_AD<6> H14 API0_ADI6 INTERFACE API0_ADO6 J4 EI_CPU_TO_NB_AD<6> 6 14 28 29
29 28 14 6 EI_NB_TO_CPU_AD<7> G14 API0_ADI7 API0_ADO7 H4 EI_CPU_TO_NB_AD<7> 6 14 28 29 OMIT OMIT OMIT OMIT OMIT OMIT OMIT
29 28 14 6 EI_NB_TO_CPU_AD<8> D9 API0_ADI8 API0_ADO8 G1 EI_CPU_TO_NB_AD<8> 6 14 28 29 ZT2850
HOLE-VIA-20R10
ZT2860
ZT2800 ZT2810
HOLE-VIA-20R10
ZT2820 ZT2830
ZT2840
29 28 14 6 EI_NB_TO_CPU_AD<9> C9 API0_ADI9 API0_ADO9 H2 EI_CPU_TO_NB_AD<9> 6 14 28 29
1 1 1 1 1 1 1
29 28 14 6 EI_NB_TO_CPU_AD<10> D11 API0_ADI10 API0_ADO10 F1 EI_CPU_TO_NB_AD<10> 6 14 28 29
29 28 14 6 EI_NB_TO_CPU_AD<11> E11 API0_ADI11 API0_ADO11 H5 EI_CPU_TO_NB_AD<11> 6 14 28 29 OMIT OMIT OMIT OMIT OMIT OMIT OMIT
29 28 14 6 EI_NB_TO_CPU_AD<12> A10
A9
API0_ADI12 API0_ADO12 H3
J3
EI_CPU_TO_NB_AD<12> 6 14 28 29 ZT2851
HOLE-VIA-20R10
ZT2861
ZT2801 ZT2811
HOLE-VIA-20R10
ZT2821 ZT2831
ZT2841
C 29 28 14 6
29 28 14 6
EI_NB_TO_CPU_AD<13>
EI_NB_TO_CPU_AD<14> A8
API0_ADI13
API0_ADI14
API0_ADO13
API0_ADO14 J5
EI_CPU_TO_NB_AD<13>
EI_CPU_TO_NB_AD<14>
6 14 28 29
6 14 28 29
1 1 1 1 1 1 1 C
29 28 14 6 EI_NB_TO_CPU_AD<15> B9 API0_ADI15 API0_ADO15 J6 EI_CPU_TO_NB_AD<15> 6 14 28 29 OMIT OMIT OMIT OMIT OMIT OMIT OMIT
29 28 14 6 EI_NB_TO_CPU_AD<16> C11
B11
API0_ADI16 API0_ADO16 E3
F4
EI_CPU_TO_NB_AD<16> 6 14 28 29 ZT2852
HOLE-VIA-20R10
ZT2862
ZT2802 ZT2812
HOLE-VIA-20R10
ZT2822 ZT2832
ZT2842
1 1 1 1 1 1 1
29 28 14 6 EI_NB_TO_CPU_AD<18> A11 API0_ADI18 API0_ADO18 E2 EI_CPU_TO_NB_AD<18> 6 14 28 29
29 28 14 6 EI_NB_TO_CPU_AD<19> A12 API0_ADI19 API0_ADO19 F5 EI_CPU_TO_NB_AD<19> 6 14 28 29 OMIT OMIT OMIT OMIT OMIT OMIT OMIT
29 28 14 6 EI_NB_TO_CPU_AD<20> B12
C12
API0_ADI20 API0_ADO20 H6
J7
EI_CPU_TO_NB_AD<20> 6 14 28 29 ZT2853
HOLE-VIA-20R10
ZT2863
ZT2803 ZT2813
HOLE-VIA-20R10
ZT2823 ZT2833
ZT2843
1 1 1 1 1 1 1
29 28 14 6 EI_NB_TO_CPU_AD<22> D12 API0_ADI22 API0_ADO22 F3 EI_CPU_TO_NB_AD<22> 6 14 28 29
29 28 14 6 EI_NB_TO_CPU_AD<23> E12 API0_ADI23 API0_ADO23 J8 EI_CPU_TO_NB_AD<23> 6 14 28 29 OMIT OMIT OMIT OMIT OMIT OMIT OMIT
29 28 14 6 EI_NB_TO_CPU_AD<24> A13
A14
API0_ADI24 API0_ADO24 F6
E5
EI_CPU_TO_NB_AD<24> 6 14 28 29 ZT2854
HOLE-VIA-20R10
ZT2864
ZT2804 ZT2814
HOLE-VIA-20R10
ZT2824 ZT2834
ZT2844
1 1 1 1 1 1 1
29 28 14 6 EI_NB_TO_CPU_AD<26> B14 API0_ADI26 API0_ADO26 D5 EI_CPU_TO_NB_AD<26> 6 14 28 29
29 28 14 6 EI_NB_TO_CPU_AD<27> C14 API0_ADI27 API0_ADO27 E4 EI_CPU_TO_NB_AD<27> 6 14 28 29 OMIT OMIT OMIT OMIT OMIT OMIT OMIT
29 28 14 6 EI_NB_TO_CPU_AD<28> A16
A15
API0_ADI28 API0_ADO28 D8
A5
EI_CPU_TO_NB_AD<28> 6 14 28 29 ZT2855
HOLE-VIA-20R10
ZT2865
ZT2805 ZT2815
HOLE-VIA-20R10
ZT2825 ZT2835
ZT2845
1 1 1 1 1 1 1
29 28 14 6 EI_NB_TO_CPU_AD<30> B15 API0_ADI30 API0_ADO30 C2 EI_CPU_TO_NB_AD<30> 6 14 28 29
29 28 14 6 EI_NB_TO_CPU_AD<31> C15 API0_ADI31 API0_ADO31 C3 EI_CPU_TO_NB_AD<31> 6 14 28 29 OMIT OMIT OMIT OMIT

29 28 14 6 EI_NB_TO_CPU_AD<32> H15
G15
API0_ADI32 API0_ADO32 C5
C6
EI_CPU_TO_NB_AD<32> 6 14 28 29 ZT2806
HOLE-VIA-20R10
ZT2816 ZT2826
ZT2836
1 1 1 1
29 28 14 6 EI_NB_TO_CPU_AD<34> F17 API0_ADI34 API0_ADO34 B2 EI_CPU_TO_NB_AD<34> 6 14 28 29
29 28 14 6 EI_NB_TO_CPU_AD<35> G17 API0_ADI35 API0_ADO35 D1 EI_CPU_TO_NB_AD<35> 6 14 28 29 OMIT OMIT OMIT

29 28 14 6 EI_NB_TO_CPU_AD<36> G18
H18
API0_ADI36 API0_ADO36 B1
C1
EI_CPU_TO_NB_AD<36> 6 14 28 29
=PP1V2_EI_NB 7 14 18 28
ZT2846
HOLE-VIA-20R10
ZT2856
ZT2866
NOSTUFF 1 1 1
EI_NB_TO_CPU_AD<38> F18 A6 EI_CPU_TO_NB_AD<38>
29 28 14 6
EI_NB_TO_CPU_AD<39> E18
API0_ADI38
API0_ADI39
API0_ADO38
API0_ADO39 C8 EI_CPU_TO_NB_AD<39>
6 14 28 29
R2802
1
B
29 28 14 6
29 28 14 6 EI_NB_TO_CPU_AD<40> A17
A18
API0_ADI40 API0_ADO40 A2
B3
EI_CPU_TO_NB_AD<40>
6 14 28 29
6 14 28 29
100
1%
1/16W
B
29 28 14 6 EI_NB_TO_CPU_AD<41> API0_ADI41 API0_ADO41 EI_CPU_TO_NB_AD<41> 6 14 28 29 NOSTUFF MF-LF
29 28 14 6 EI_NB_TO_CPU_AD<42> B17
C17
API0_ADI42 API0_ADO42 A7
B8
EI_CPU_TO_NB_AD<42> 6 14 28 29
1 C2821
0.001UF
2 402
EI_APCLK_VREF
10% VOLTAGE=0.6V
2 50V NOSTUFF
29 28 14 6 EI_NB_TO_CPU_SR_P<0> D17 API0_SRIP0 API0_SROP0 A3 EI_CPU_TO_NB_SR_P<0> 6 14 28 29
CERM
402 R2801
1
100 C2820 R2803R2804
1
1 1
29 28 14 6 EI_NB_TO_CPU_SR_N<0> A19
E17
API0_SRIN0 API0_SRON0 A4
B5
EI_CPU_TO_NB_SR_N<0> 6 14 28 29
1% 0.1UF 121 121
20% 1% 1%
29 28 14 6 EI_NB_TO_CPU_SR_P<1> API0_SRIP1 API0_SROP1 EI_CPU_TO_NB_SR_P<1> 6 14 28 29 1/16W 10V 1/16W 1/16W
PLACE R2805 AND R2806 B18 B6 MF-LF 2 CERM MF-LF MF-LF
29 28 14 6 EI_NB_TO_CPU_SR_N<1> API0_SRIN1 API0_SRON1 EI_CPU_TO_NB_SR_N<1> 6 14 28 29
2 402 402 2 402 2 402
NEAR U3LITE
29 14 6 EI_QACK_L D14 API_QACK0 API_QREQ0 E14
E8 D18 EI_NB_CLK_P
API0_APSYNC API_APCLKP EI_NB_CLK_P 27
NOSTUFF H17 C18 EI_NB_CLK_N
API0_SE API_APCLKN EI_NB_CLK_N
R2805
0 API_CSTP F14 CPU_CHKSTOP_L 29
27
27 EI_NB_SYNC 1 2 NB_APSYNC
402 MF-LF
R2806
10
29 EI_SYNC_FROM_NB 1 2 API_APCLK_AVSS
G20
402 5% 1/16W
30 29 14 6 EI_SE
QREQ_L HACK QREQ TO SMU

28 7 =PP3V3_PWRON_EI
28 7 =PP3V3_PWRON_EI
CRITICAL NOSTUFF
C2850
0.1UF
1
U2850 R2898
1 U3LITE APPLE PI
20% 74LVC1G66DBVG4 10K
A 10V
CERM 2
402
5
VCC
SOT23-5
TI
5%
1/16W
MF-LF
SYNC_MASTER=N/A

SYNC_DATE=N/A
A
2 402
30 29 14 6 EI_QREQ_L 1 2 EI_NB_QREQ_L THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
SMU_QREQ 13 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
NOSTUFF
25 24 13 SMU_SUSPENDREQ_L 4 R2899
180
3
NOSTUFF
TABLE_ALT_HEAD
GND 1 2 EI_NB_QREQ_L_R 1 Q2899 II NOT TO REPRODUCE OR COPY IT

3 5% 2N3904LF III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
PART NUMBER
NOSTUFF R2851 1 1/16W
MF-LF 2
SOT23
R2850 10K SIZE DRAWING NUMBER REV.
TABLE_ALT_ITEM
353S0920 353S0867 U2850 PERICOM ANALOG SWITCH

CRITICAL
0 1 2
5%
1/16W
MF-LF
402
D 051-6772 E
402 2 APPLE COMPUTER INC.
PLACE QREQ CIRCUITS BETWEEN CPU AND U3LITE

5%
1/16W
MF-LF
402
SCALE
NONE 28 102
SHT OF
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
PLACE NEAR PROCESSOR.
PLACE AT PROCESSOR PINS. 31 30 29 18 14 7 =PP1V2_EI_CPU

NOSTUFF
NOSTUFF
R2903 R2909
1
100 MORE PROCESSOR DECOUPLING
ON PAGES 31 & 32
D 27 EI_CPU_CLK_P
46.4
1 2 1%
1/16W
MF-LF
36 32 31 7 =PPVCORE_CPU
D
1% 2 402
1/16W
MF-LF
402 SYSCLK_TERM 1 C2953 1 C2947 1 C2945 1 C2939 1 C2937 1 C2928 1 C2924 1 C2920 1 C2914 1 C2912
NOSTUFF NOSTUFF VOLTAGE=0.6V
NOSTUFF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
R2901 1 C2901 R2907
1 10%
2 6.3V
10%
2 6.3V
10%
2 6.3V
10%
2 6.3V
10%
2 6.3V
10%
2 6.3V
10%
2 6.3V
10%
2 6.3V
10%
2 6.3V
10%
2 6.3V
EI_CPU_CLK_N
46.4
1 2 0.22UF 100 CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
27
20% 1%
1/16W
1% 2 6.3V
X5R MF-LF
1/16W 402 2 402
MF-LF
402 1 C2954 1 C2948 1 C2946 1 C2940 1 C2938 1 C2929 1 C2925 1 C2921 1 C2915 1 C2913
1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
T22
R22 402 402 402 402 402 402 402 402 402 402
SYSCLK* SYSCLK
28 14 6 EI_NB_TO_CPU_CLK_P EI_CPU_TO_NB_CLK_P
28 14 6 EI_NB_TO_CPU_CLK_N
E24 EI_CLKI
D24 EI_CLKI* OMIT
EI_CLKO
EI_CLKO*
D3
E3 EI_CPU_TO_NB_CLK_N
6 14 28
6 14 28
1 C2955 1 C2951 1 C2949 1 C2943 1 C2941 1 C2930 1 C2926 1 C2922 1 C2918 1 C2916
6 EI_NB_TO_CPU_AD<0> H21 CRITICAL EI_ADO0 N3 EI_CPU_TO_NB_AD<0> 6 14 28 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
U2900
28 14 EI_ADI0
28 14 6 EI_NB_TO_CPU_AD<1> J21 EI_ADO1 H2 EI_CPU_TO_NB_AD<1> 6 14 28 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
EI_ADI1
28 14 6 EI_NB_TO_CPU_AD<2> H22
EI_ADI2 EI_ADO2 K3 EI_CPU_TO_NB_AD<2> 6 14 28 CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM
28 14 6 EI_NB_TO_CPU_AD<3> J22 EI_ADI3 EI_ADO3 L1 EI_CPU_TO_NB_AD<3> 6 14 28 402 402 402 402 402 402 402 402 402 402
28
28
28
14
14
14
6 EI_NB_TO_CPU_AD<4>
C13
A13
K22
EI_ADI4
EI_ADI5
EI_ADI6
CBGA
(1 OF 3)
EI_ADO4
EI_ADO5
EI_ADO6
M3
K4
K2
28 14 6 EI_NB_TO_CPU_AD<7> H23
EI_ADI7 EI_ADO7 H3 EI_CPU_TO_NB_AD<7> 6 14 28
NEO-10S-REV2
1.8GHZ-76C
6 EI_NB_TO_CPU_AD<8> EI_CPU_TO_NB_AD<8> 6 14 28
28
28
14
14 6 EI_NB_TO_CPU_AD<9>
J24
G20
EI_ADI8
EI_ADI9
EI_ADO8
EI_ADO9
H1
G4 EI_CPU_TO_NB_AD<9> 6 14 28
1 C2956 1 C2952 1 C2950 1 C2944 1 C2942 1 C2931 1 C2927 1 C2923 1 C2919 1 C2917
28
28
14
F23
G21
EI_ADI10
EI_ADI11
EI_ADO10
EI_ADO11
F2
F4 EI_CPU_TO_NB_AD<11> 6 14 28 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
6 EI_NB_TO_CPU_AD<12> D22 E2 EI_CPU_TO_NB_AD<12> 6 14 28 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
28
28
14
14 6 EI_NB_TO_CPU_AD<13> G24
EI_ADI12 EI_ADO12
EI_ADO13 G3 EI_CPU_TO_NB_AD<13> 6 14 28 6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM
EI_ADI13
28 14 6 EI_NB_TO_CPU_AD<14> G19 EI_ADI14 EI_ADO14 B8 EI_CPU_TO_NB_AD<14> 6 14 28 402 402 402 402 402 402 402 402 402 402
28 14 6 EI_NB_TO_CPU_AD<15> B15 EI_ADI15 EI_ADO15 D11 EI_CPU_TO_NB_AD<15> 6 14 28
28 14 6 EI_NB_TO_CPU_AD<16> A14 EI_ADI16 EI_ADO16 E12 EI_CPU_TO_NB_AD<16> 6 14 28
28 14 6 EI_NB_TO_CPU_AD<17> C15 EI_ADI17 EI_ADO17 A11 EI_CPU_TO_NB_AD<17> 6 14 28
28 14 6 EI_NB_TO_CPU_AD<18> D15 EI_ADI18 EI_ADO18 B10 EI_CPU_TO_NB_AD<18> 6 14 28
28
28
14
A16
C22
EI_ADI19
EI_ADI20
EI_ADO19
EI_ADO20
C11
C1 EI_CPU_TO_NB_AD<20> 6 14 28
1 C2900 1 C2960 1 C2959 1 C2958 1 C2957 1 C2936 1 C2935 1 C2934 1 C2933 1 C2932
28
28
14
E20
E21
EI_ADI21 EI_ADO21
EI_ADO22
C5
B2 EI_CPU_TO_NB_AD<22> 6 14 28 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
C
EI_ADI22 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
C 28
28
28
28
14
14
14
14
B23
B24
F21
B17
EI_ADI23
EI_ADI24
EI_ADI25
EI_ADI26
EI_ADO23
EI_ADO24
EI_ADO25
EI_ADO26
D6
A5
A2
D2
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
28 14 6 EI_NB_TO_CPU_AD<27> B19 EI_ADI27 EI_ADO27 D8 EI_CPU_TO_NB_AD<27> 6 14 28
28 14 6 EI_NB_TO_CPU_AD<28> C14 EI_ADI28 EI_ADO28 C12 EI_CPU_TO_NB_AD<28> 6 14 28
28 14 6 EI_NB_TO_CPU_AD<29> C17
EI_ADI29 EI_ADO29 A12 EI_CPU_TO_NB_AD<29> 6 14 28
28
28
14
D18
B21
EI_ADI30
EI_ADI31
EI_ADO30
EI_ADO31
B6
B4 EI_CPU_TO_NB_AD<31> 6 14 28
1 C2911 1 C2910 1 C2909 1 C2908 1 C2907 1 C2906 1 C2905 1 C2904 1 C2903 1C2902
28
28
14
D20
A22
EI_ADI32
EI_ADI33
EI_ADO32
EI_ADO33
C4
C7 EI_CPU_TO_NB_AD<33> 6 14 28 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
6 EI_NB_TO_CPU_AD<34> C19 A7 EI_CPU_TO_NB_AD<34> 6 14 28 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
28 14 EI_ADI34 EI_ADO34
28 14 6 EI_NB_TO_CPU_AD<35> C18 EI_ADI35 EI_ADO35 C8 EI_CPU_TO_NB_AD<35> 6 14 28
CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM
28 14 6 EI_NB_TO_CPU_AD<36> A21 EI_ADI36 EI_ADO36 C6 EI_CPU_TO_NB_AD<36> 6 14 28 402 402 402 402 402 402 402 402 402 402
28 14 6 EI_NB_TO_CPU_AD<37> A23 EI_ADI37 EI_ADO37 A4 EI_CPU_TO_NB_AD<37> 6 14 28
28 14 6 EI_NB_TO_CPU_AD<38> A20 EI_ADI38 EI_ADO38 A9 EI_CPU_TO_NB_AD<38> 6 14 28
28 14 6 EI_NB_TO_CPU_AD<39> A18 EI_ADI39 EI_ADO39 C9 EI_CPU_TO_NB_AD<39> 6 14 28
28 14 6 EI_NB_TO_CPU_AD<40> A15 EI_ADI40 EI_ADO40 A10 EI_CPU_TO_NB_AD<40> 6 14 28 NOSTUFF
28 14 6 EI_NB_TO_CPU_AD<41> A17 EI_ADI41 EI_ADO41 C10 EI_CPU_TO_NB_AD<41> 6 14 28
28
28
14
14
C16
A19
EI_ADI42
EI_ADI43
EI_ADO42
EI_ADO43
A8
A6
EI_CPU_TO_NB_AD<43> 6 14 28 R2910
1
0 2
28 14 6 EI_NB_TO_CPU_SR_P<0> L24 EI_SRI0 EI_SRO0 L3 EI_CPU_TO_NB_SR_P<0> 6 14 28 EI_CPU_SYNC 27
28 14 6 EI_NB_TO_CPU_SR_N<0> K24 EI_SRI0* EI_SRO0* L2 EI_CPU_TO_NB_SR_N<0> 6 14 28
28 14 6 EI_NB_TO_CPU_SR_P<1> L21
EI_SRI1 EI_SRO1 G1 EI_CPU_TO_NB_SR_P<1> 6 14 28 5%
28 14 6 EI_NB_TO_CPU_SR_N<1> L22
EI_SRI1* EI_SRO1* F1 EI_CPU_TO_NB_SR_N<1> 6 14 28 1/16W
MF-LF
28 14 6 EI_QACK_L V21 QACK* QREQ* AB12 EI_QREQ_L 6 14 28 30 402
29 14 8 6 CHKSTOP_L R20 CHKSTOP* INT* AB19 CPU_INT_L 6 14 25 30
30 29 27 CPU_HTBEN AD17
TBEN
R2911
MATCH TO SYSCLK 1
0 2
6 TP_PSYNCOUT AD14 APSYNCOUT APSYNCIN AA10 CPU_APSYNC EI_SYNC_FROM_NB 28
5%
30 14 6 CPU_HRESET_L V20 HRESET* IIC_SCL AA20 I2C_CPU_A_SCL 18 1/16W
IIC_SDA Y21 I2C_CPU_A_SDA 18 MF-LF
30 25 CPU_SRESET_L AB4 SRESET* 402
I2CGO N22 I2CGO 30
30 PROC_THERM_INT_L V22 THERM_INT*
CKTERMDIS AA14 CKTERMDIS_L 30
30 PROCID0 L19 PROCID0
30 PROCID1 M19 PROCID1 EI_DISABLE P20 EI_DISABLE 30
30 PROCID2 M18 PROCID2
BUSCFG0 AA19 BUSCFG0 30
30 28 14 6 EI_SE N21 TRIGGER_IN BUSCFG1 AC19 BUSCFG1 30
14 6 TP_PROC_TRIGGER_OUT N19
TRIGGER_OUT BUSCFG2 AB16 BUSCFG2 30
TP_AFN AA12 AFN ATTENTION AD12 TP_ATTENTION 6

30 AVPRESET_L W23
AVPRESET* GPUL_DBG AA22 GPUL_DBG 30
30 BIMODE_L AC24 BIMODE* JTAGMODE W4 JTAGMODE_SPARE2 30
C1UNDGLOBAL
B B
30 AC16 C1UNDGLOBAL
30 C2UNDGLOBAL AC15
C2UNDGLOBAL TCK AD21 JTAG_CPU_TCK 18 30
30 DI2_L U24 DI2* TDI AB21 JTAG_CPU_TDI 18 30
TDO AD13 JTAG_CPU_TDO 18 30
30 LSSDMODE AB5 LSSDMODE TMS AD22 JTAG_CPU_TMS 18 30
30 LSSDSCANENABLE U19
LSSDSCANENABLE TRST* W20 JTAG_CPU_TRST_L 30
30 LSSDSTOPC2ENABLE AD8 LSSDSTOPC2ENABLE
30 LSSDSTOPC2STARENABLE AD7 LSSDSTOPC2STARENABLE BYPASS* V24 CPU_BYPASS_L 30
30 LSSDSTOPENABLE AD11 PLLLOCK T20 PLLLOCK 8
29 14 6 MCP_L AD18
LSSDSTOPENABLE
MCP* PLLMULT AA8 PLLMULT 30
PROCESSOR IIC ADDRESS:
PLLRANGE0 AB7 PLLRANGE0 30
6 TP_PSRO1 V23
PSRO1 PLLRANGE1 AA9 PLLRANGE1 30 80,84
TP_PSRO2 V5
PSRO2 PLLTEST W22 PLLTEST 30
30 PULSESEL0 AC9 PULSESEL0 PLLTESTOUT T19 PLLTESTOUT 30
30 PULSESEL1 AB11
PULSESEL1
30 PULSESEL2 AC10
PULSESEL2 SPARE AA13 CPU_SPARE 30
30 RAMSTOPENABLE AB6
RAMSTOPENABLE
30 14 6 RI_L AA5
RI*
30 14 6 SYNCENABLE AB24 SYNCENABLE*
31 30 29 18 14 7 =PP1V2_EI_CPU
1 1
NOSTUFF R2906 R2908
1K 1K
R2905
49.9
5%
1/16W
5%
1/16W
CPU_HTBEN 1 2 MF-LF MF-LF
30 29 27
R2902 2 402 2 402
1%
1/16W
MF-LF 1
0 2 CHKSTOP_L 6 8 14 29
NEO APPLE PI
402
A PLACE BY PROCESSOR PIN. 28 CPU_CHKSTOP_L
5%
1/16W
MF-LF
402
SYNC_MASTER=N/A

SYNC_DATE=N/A
A
NOSTUFF
R2904 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
1
0 2 MCP_L 6 14 29 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
5% II NOT TO REPRODUCE OR COPY IT
1/16W
MF-LF III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
402
D 051-6772 E
PROCESSOR LOGIC I/O APPLE COMPUTER INC.
SCALE
NONE
SHT
29
OF
102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
SELECT PROCESSOR CLOCK MULTIPLIER. PROCESSOR CLOCK(MHZ)= SYSTCLOCK * PLLMULT.
TABLE_5_HEAD
*
TABLE_5_ITEM
114S1103 1 RES,1K OHM,1/16W,5%,0402 R3034 EI_3TO1 SYSCLK * 12

TABLE_5_ITEM
114S1103 1 RES,1K OHM,1/16W,5%,0402 R3018 EI_2TO1 SYSCLK * 8
=PP1V2_EI_CPU 7 14 18 29 30 31 SELECT EI BUS DIVIDER. BUS DATA RATE(BPS)= (PROCESSOR CLOCK) / BUSCFG.
R3039 TABLE_5_HEAD
1
0 2
31 30 29 18 14 7 =PP1V2_EI_CPU PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
29 JTAGMODE_SPARE2
TABLE_5_ITEM
5% NOSTUFF 114S1103 3 RES,1K OHM,1/16W,5%,0402 R3024,R3026,R3028 EI_2TO1 PROC / 2

1/16W
R3009 MF-LF
402
R3000 R3001 *
TABLE_5_ITEM
PROC / 3
C1UNDGLOBAL 0 0 114S1103 3 RES,1K OHM,1/16W,5%,0402 R3024,R3026,R3012 EI_3TO1
D
29
NOSTUFF
R3077 R3043
29 JTAG_CPU_TRST_L 2
1K
5%
1 R3045
1K
1
5%
1/16W
2 1
5%
1/16W
2
114S1103 3 RES,1K OHM,1/16W,5%,0402 R3024,R3010,R3028 NOSTUFF
TABLE_5_ITEM
PROC / 4 D
LSSDMODE 1 2
JTAG_SEL
29
TABLE_5_ITEM
1K 1K 1/16W MF-LF MF-LF

1 2 1 2 MF-LF 402 402 114S1103 3 RES,1K OHM,1/16W,5%,0402 R3024,R3010,R3012 NOSTUFF PROC / 6
402 5%
1/16W TABLE_5_ITEM
5% 5% MF-LF 114S1103 3 RES,1K OHM,1/16W,5%,0402 R3008,R3026,R3028 NOSTUFF PROC / 8

1/16W 1/16W 402
MF-LF MF-LF R3093 R3095 TABLE_5_ITEM
29 C2UNDGLOBAL
402 402
JTAG_CPU_TDO 1
1K 2
R3041 29 18 JTAG_CPU_TCK 1
10K 2
114S1103 3 RES,1K OHM,1/16W,5%,0402 R3008,R3026,R3012 NOSTUFF PROC / 12
29 18
LSSDSCANENABLE 1
1K 2
TABLE_5_ITEM
NOSTUFF 5% 29 5% 114S1103 3 RES,1K OHM,1/16W,5%,0402 R3008,R3010,R3028 NOSTUFF PROC / 16

R3079 R3069 1/16W
MF-LF 5% 1/16W
MF-LF
TABLE_5_ITEM
1
1K 2 1
1K 2 402 1/16W 402 114S1103 3 RES,1K OHM,1/16W,5%,0402 R3008,R3010,R3012 NOSTUFF
MF-LF
402
5% 5%
R3031 R3097
1/16W
MF-LF
1/16W
MF-LF 1K R3047 29 18 JTAG_CPU_TDI 1
10K 2 SELECT ELASTIC MODE OR BYPASS.
402 402 29 BIMODE_L 1 2
1
1K 2
29 LSSDSTOPC2ENABLE 5%
TABLE_5_HEAD
29 PLLTEST 5% 1/16W PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION

1/16W 5% MF-LF
MF-LF 1/16W
NOSTUFF
*
TABLE_5_ITEM
402
R3063 R3061 402 MF-LF
402
114S1103 1 RES,1K OHM,1/16W,5%,0402 R3036
1K 1K R3033 R3099 TABLE_5_ITEM
1 2 1 2
1K R3049 29 18 JTAG_CPU_TMS 1
10K 2
114S1103 1 RES,1K OHM,1/16W,5%,0402 R3020 NOSTUFF BYPASS MODE
5% 5% 29 DI2_L 1 2 1K
1/16W
MF-LF
1/16W
MF-LF 5%
29 LSSDSTOPC2STARENABLE 1 2 5% SELECT PLL FREQUENCY RANGE.
402 402 1/16W 5% 1/16W TABLE_5_HEAD
CKTERMDIS_L MF-LF 1/16W MF-LF

29 402 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
402 MF-LF
NOSTUFF 402 TABLE_5_ITEM
R3075 R3073 R3035 R3051

114S1103 2 RES,1K OHM,1/16W,5%,0402 R3030,R3032 CPU_PLL_LOW
1K 1K 1K TABLE_5_ITEM
1 2 1 2 29 14 6 RI_L 1 2
29 LSSDSTOPENABLE 1
1K 2
NOSTUFF >= 1.8 GHZ * 114S1103 2 RES,1K OHM,1/16W,5%,0402 R3030,R3016 CPU_PLL_HIGH
5%
1/16W
5%
1/16W
5%
1/16W 5% R3071 <= 1.6 GHZ * 114S1103 2 RES,1K OHM,1/16W,5%,0402 R3014,R3032 CPU_PLL_MEDIUM
TABLE_5_ITEM
MF-LF
402
MF-LF
402
MF-LF
402
1/16W
MF-LF PLLTESTOUT 1
1K 2
29
TABLE_5_ITEM
29 GPUL_DBG 402 114S1103 2 RES,1K OHM,1/16W,5%,0402 R3014,R3016 NOSTUFF RESERVED

NOSTUFF R3091 R3053
5%
1/16W
R3040 R3042 1K MF-LF
29 25 14 6 CPU_INT_L 1 2 10K 402
C 1
5%
1K 2 1
1K
5%
2 5%
1/16W
MF-LF
29 28 14 6 EI_QREQ_L 1
5%
1/16W
2
TABLE_5_HEAD
TABLE_5_ITEM
C
1/16W 1/16W 402 MF-LF 114S1103 1 RES,1K OHM,1/16W,5%,0402 R3022 AVPRESET OFF
MF-LF MF-LF 402
402 402
R3065
TABLE_5_ITEM
1K
R3037 114S1103 1 RES,1K OHM,1/16W,5%,0402 R3038 NOSTUFF AVPRESET ON
29 PROC_THERM_INT_L 1 2 1
1K 2
29 14 6 SYNCENABLE
5% 5%
1/16W
MF-LF 1/16W
MF-LF
* STUFF THESE ON Q45.
402 402
R3085 R3055
CPU_SRESET_L 1
1K 2 29 RAMSTOPENABLE 1
1K 2
SYSTEM CONFIGURATION
29 25
5% 5%
1/16W 1/16W =PP1V2_EI_CPU 7 14 18 29 30 31
MF-LF MF-LF
402 402 31 30 29 18 14 7 =PP1V2_EI_CPU
NOSTUFF
R3067
1
R3068
R3087 10K
1K 5%
1K 29 CPU_SPARE 1 2 1/16W
I2CGO 1 2 MF-LF
29
5% 1 OMIT 1 OMIT 1 OMIT 1 OMIT 1 OMIT 1 OMIT 1 OMIT 1 OMIT
5% 1/16W 2 402 R3008 R3010 R3012 R3014 R3016 R3018 R3020 R3022
1/16W MF-LF 1K 1K 1K 1K 1K 1K 1K 1K
MF-LF 402 5% 5% 5% 5% 5% 5% 5% 5%
402 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W
R3081 MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF
R3089 EI_SE 1
1K 2 BUSCFG0
2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402
1
1K 2
29 28 14 6 29
29 27 CPU_HTBEN 5% BUSCFG1
29
5% 1/16W
1/16W MF-LF 29 BUSCFG2
MF-LF 402
402 29 PLLRANGE0
R3003 29 PLLRANGE1
PULSESEL0 1
1K 2 29 PLLMULT
29
EI_DISABLE
B =PP1V2_EI_CPU
2
7 14 18 29 30 31
5%
1/16W
MF-LF
402
29
29 AVPRESET_L B
R3083
1K 1 OMIT 1 OMIT 1 OMIT 1 OMIT 1 OMIT 1 OMIT 1 OMIT 1 OMIT
5%
1/16W R3005 R3024
1K
R3026
1K
R3028
1K
R3030
1K
R3032
1K
R3034
1K
R3036
1K
R3038
1K
MF-LF 1K
1 402 29 PULSESEL1 1 2 5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W
5% MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF
CPU_HRESET_L 6 14 29
1/16W 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402
MF-LF
402
6
D
Q3000 R3007
2N7002DW 1
1K 2
29 PULSESEL2
2 SOT-363
13 CPU_HRESET G S 5%
1/16W
MF-LF
1 402
R3002
1
1K 2
29 PROCID0
5%
1/16W
MF-LF
402
=PP1V2_EI_CPU 7 14 18 29 30 31
R3004
1
1K 2
29 PROCID1
1
R3059
1K
5%
1/16W
5%
1/16W
MF-LF
402
CPU STRAPS
MF-LF
A 2 402
CPU_BYPASS_L
R3006
SYNC_MASTER=N/A

SYNC_DATE=N/A
A
29
1
1K 2
29 PROCID2
3 5% THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

NOSTUFF 1/16W PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
D
Q3000
2N7002DW
1
R3057 MF-LF
402
1K
5 SOT-363 5% II NOT TO REPRODUCE OR COPY IT
13 CPU_BYPASS G S 1/16W
MF-LF III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
4 2 402
APPLE COMPUTER INC.

D 051-6772 E
SCALE SHT OF
NONE 30 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
36 32 31 29 7 =PPVCORE_CPU =PP1V2_EI_CPU 7 14 18 29 30
VOLTAGE=1.2V
7 =PP2V5_RUN_CPU
NOSTUFF
L3101 NET_SPACING_TYPE=PROC_DIFF 1 C3117 1 C3116 1 C3115 1 C3114 1 C3111 1 C3106 1 C3105 1 C3103
R3132 60-OHM-EMI DIFFERENTIAL_PAIR=P_TDD
10UF 10UF 10UF 10UF 1UF 1UF 1UF 1UF
1
2.2 2 1 2
20% 20% 20% 20% 10% 10% 10% 10%
35 PP2V5_RUN_CPU_AVDD_R PP2V5_RUN_CPU_AVDD_R_L TDIODE_POS 36 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
VOLTAGE=2.5V SM VOLTAGE=2.5V MIN_NECK_WIDTH=0.2MM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
5% MIN_LINE_WIDTH=0.6MM MIN_LINE_WIDTH=0.6MM
1/10W MIN_NECK_WIDTH=0.2MM 0805 MIN_NECK_WIDTH=0.2MM 805 805 805 805 402 402 402 402
MF-LF
OMIT 603 P24 R2
D
Y1
=PP5V_RUN_CPU
D 8 7 6 3
VR3100
MM1572JN
R3101
2.2
1 C3199
1UF A1
AVDD KPVDD1 KPVDD2
A3 OMIT
1 C3112
1UF
1 C3109
1UF
1 C3107
1UF
1 C3104
1UF
SOT-25A PP2V5_RUN_CPU_AVDD 1 2 A24 OMIT B1 CRITICAL
10% 10% 10% 10% 10%
U2900
B11 B12
1 5 MIN_NECK_WIDTH=0.2MM
VOLTAGE=2.5V
5%
1/10W
1 C3100 2 6.3V
CERM
B13
B16
CRITICAL B14
B18
P1
P11
P18
P2 GND_Z_OUT
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
VIN VOUT
C3102 0.22UF 402 31 402 402 402 402
3 CPU_AVDD_EN 3 CONT NOISE 4 CPU_AVDD_NOISE

MF-LF
603
1
10UF
20%
20%
6.3V
2 X5R
B20
B3
B7
U2900 B22
B5
B9
P13
P15
P17
CBGA
(3 OF 3)
P22
P4
P6
2 6.3V 402
C2
C20 CBGA C21
C23
P19
P21
P8
GND_Z_SENSE
1.8GHZ-76C
R1
C3113 C3110 C3108
NEO-10S-REV2
CERM 31
GND C24 C3 P23 R11 1 1 1
805 D13 (2 OF 3) D1 P3 R13
2
C3150 1UF 1UF 1UF
1.8GHZ-76C
CPU_AVDD_2V6&CPU_AVDD_2V7&CPU_AVDD_2V8 1
NEO-10S-REV2
D17 D10 P5 R15
CPU_AVDD_2V6&CPU_AVDD_2V7&CPU_AVDD_2V8 D19 D12 P7 R17 10% 10% 10%
1 C3148 10UF 6.3V 6.3V 6.3V
1 C3149 20%
D21
D23
D14
D16
P9
R10
R19
R21
2 CERM 2 CERM 2 CERM
1UF 0.01UF 2 6.3V
CERM
D5 D4 R12 R23 402 402 402
20%
20% D7 E11 R14 R3
16V 805 D9 E13 R16 R5
2 10V
CERM CERM 2 E1 E15 R18 R7
603 402 E10 E17 R4 R9
E14 E19 R6 T10 1 C3126 1 C3120 1 C3118
E16
E18
E23
E5
R8
T1
T12
T14 1UF 1UF 1UF
E22 E7 T11 T16 10% 10% 10%
E4 E9 T13 T18 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
E6 F10 T15 T24
E8 F12 T17 T4 402 402 402
F11 F14 T21 T6
TABLE_5_HEAD
F13 F16 T23 T8

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION F15 F18 T3 U1
F17 F20 T5 U11
CRITICAL 353S0806 1 VREG MM1572 2.6V VR3100 CPU_AVDD_2V6

TABLE_5_ITEM
F19
F3
F22
F24
T7
T9
U13
U15
1 C3127 1 C3121 1 C3119
F5 F6 U10 U17 1UF 1UF 1UF
TABLE_5_ITEM
F7 F8 U12 U21 10% 10% 10%
6.3V 6.3V 6.3V
CRITICAL 353S0886 1 VREG MM1572 2.7V VR3100 CPU_AVDD_2V7 F9 G11 U14 U23 2 CERM 2 CERM 2 CERM
G10 G13 U16 U3
TABLE_5_ITEM
G12 G15 U18 U5 402 402 402
CRITICAL 353S0807 1 VREG MM1572 2.8V VR3100 CPU_AVDD_2V8 G14 G17 U2 U7
G16 G2 U20 U9
G18 G23 U22 V10
G22 G5 U4 V12
G6 G7 U6 V14 1 C3128 1 C3124 1 C3122
G8
H11
G9
H10
U8
V1
V16
V18 1UF 1UF 1UF
H13 H12 V11 V2 10% 10% 10%
H15 H14 V13 V4 2 6.3V
CERM 2 6.3V
CERM
6.3V
2 CERM
H17 H16 V15 V6
H19 H18 V17 V8 402 402 402
C H24
H5
H7
H9 VCORE GND
H20
H4
H6
H8
V19
V3
V7
V9
VCORE
X100
GND
X99
W1
W11
W13
W15
C
J1
J10
X105 X105 J11
J13
W10
W12
W17
W19
1 C3129 1 C3125 1 C3123
J12 J15 W14 W21 1UF 1UF 1UF
J14 J17 W16 W3 10% 10% 10%
J16 J19 W18 W5 6.3V 6.3V 6.3V
J18 J23 W2 W7
J2 J3 W24 W9 402 402 402
J20 J5 W6 Y10
J4 J7 W8 Y12
J6 J9 Y11 Y14
J8 K1 Y13 Y16
K11 K10 Y15 Y18 1 C3136 1 C3131 1 C3130
K13
K15
K12
K14
Y17
Y19
Y2
Y20 1UF 1UF 1UF
K17 K16 Y22 Y24 10% 10% 10%
K19 K18 Y23 Y4 2 6.3V
CERM 2 6.3V
CERM
6.3V
2 CERM
K21 K20 Y3 Y6
K23 K6 Y5 Y8 402 402 402
K5 K8 Y7 AA11
K7 L11 Y9 AA15
K9 L13 AA16 AA17
L10 L15 AA18 AA21
L12
L14
L17
L23
AA2
AA24
AA23
AA3
1 C3137 1 C3134 1 C3132
L16 L5 AA4 AA7 1UF 1UF 1UF
L18 L7 AA6 AB10 10% 10% 10%
L20 L9 AB1 AB14 6.3V 6.3V 6.3V
L4 M10 AB13 AB18
L6 M12 AB15 AB2 402 402 402
L8 M14 AB17 AB20
M1 M16 AB23 AB22
M11 M2 AB3 AB8
M13 M20 AB9 AC1
M15 M22 AC12 AC11 1 C3138 1 C3135 1 C3133
M17
M21
M24
M4
AC14
AC18
AC13
AC17 1UF 1UF 1UF
M23 M6 AC2 AC21 10% 10% 10%
M5 M8 AC20 AC23 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
M7 N1 GND_SPARE_GND 31 AC22 AC3
402 402 402
M9 N11 AC4 AC5
N10 N13 AC6 AC7
N12 N15 AC8 AD10
N14 N17 AD1 AD16
N16 N23 AD15 AD2
N18
N2
N5
N7
AD19
AD23
AD20
AD24
1 C3145 1 C3141 1 C3139
N20 N9 AD3 AD4 1UF 1UF 1UF
N24 P10 AD5 AD6 10% 10% 10%
6.3V 6.3V 6.3V
B
N4 P12 AD9
B
N6 P14
N8 P16 402 402 402
AGND KPGND1 KPGND2

R24 AA1 T2
1 C3146 1 C3142 1 C3140
1UF 1UF 1UF
10% 10% 10%
GND_CPU_AVDD 2 6.3V 2 6.3V 2 6.3V
R3127 CERM
402
CERM
402
CERM
402
TDIODE_NEG 6 36 1
0 2
31 GND_Z_OUT
2 OMIT DIFFERENTIAL_PAIR=P_TDD
MIN_LINE_WIDTH=0.25MM 5%
XW3100
SM
MIN_NECK_WIDTH=0.2MM 1/16W
MF-LF R3129 1 C3147 1 C3144 1 C3143
NET_SPACING_TYPE=PROC_DIFF 402 0 1UF 1UF 1UF
31 GND_Z_SENSE 1 2 10% 10% 10%
1 6.3V 6.3V 6.3V
5% 2 CERM 2 CERM 2 CERM
R3131 1/16W
MF-LF
402 402 402
0 402
31 GND_SPARE_GND1 2
5%
1/16W
MF-LF
402
CPU POWER AND BYPASS

NOSTUFF
A 36 32 31 29 7 =PPVCORE_CPU
R3103
1
0 2 KPVDD2 6 33 36
SYNC_MASTER=N/A

SYNC_DATE=N/A
A
NOSTUFF MIN_LINE_WIDTH=0.25MM
5% MIN_NECK_WIDTH=0.2MM
1/16W
MF-LF
1 C3101 DIFFERENTIAL_PAIR=P_KP2
NET_SPACING_TYPE=PROC_DIFF
402 0.22UF AGREES TO THE FOLLOWING
NOSTUFF 20%
6.3V
R3105 2 X5R
402
1
0 2
KPGND2 6 33 36
MIN_LINE_WIDTH=0.25MM III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1/16W DIFFERENTIAL_PAIR=P_KP2
MF-LF NET_SPACING_TYPE=PROC_DIFF SIZE DRAWING NUMBER REV.
402
PLACE ALL THESE PARTS VERY CLOSE TO U2900
APPLE COMPUTER INC.
D 051-6772 E
SCALE SHT OF
NONE 31 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
D D
1 C3222 1 C3221 1 C3220 1 C3219 1 C3218 1 C3217 1 C3216 1 C3215 1 C3212 1 C3200
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402 402 402 402 402
1 C3293 1 C3268 1 C3261 1 C3259 1 C3235 1 C3232 1 C3226 1 C3224 1 C3245 1 C3223
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
402 402 402 402 402 402 402 402 402 402
1 C3294 1 C3269 1 C3264 1 C3260 1 C3236 1 C3233 1 C3227 1 C3225 1 C3256 1 C3234
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
402 402 402 402 402 402 402 402 402 402
1 C3295 1 C3271 1 C3265 1 C3262 1 C3239 1 C3237 1 C3230 1 C3228 1 C3289 1 C3267
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
C 2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402 C
1 C3296 1 C3270 1 C3266 1 C3263 1 C3240 1 C3238 1 C3231 1 C3229 1 C3201 1 C3278
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
402 402 402 402 402 402 402 402 402 402
1 C3297 1 C3282 1 C3276 1 C3272 1 C3252 1 C3250 1 C3243 1 C3241 1 C3206 1 C3204
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
402 402 402 402 402 402 402 402 402 402
1 C3298 1 C3281 1 C3277 1 C3273 1 C3253 1 C3251 1 C3244 1 C3242 1 C3207 1 C3205
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
402 402 402 402 402 402 402 402 402 402
1 C3299 1 C3284 1 C3279 1 C3274 1 C3257 1 C3254 1 C3248 1 C3246 1 C3210 1 C3208
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
402 402 402 402 402 402 402 402 402 402
1 C3202 1 C3283 1 C3280 1 C3275 1 C3258 1 C3255 1 C3249 1 C3247 1 C3211 1 C3209
B 1UF
10%
6.3V
2 CERM
1UF
10%
6.3V
2 CERM
1UF
10%
6.3V
2 CERM
1UF
10%
6.3V
2 CERM
1UF
10%
6.3V
2 CERM
1UF
10%
6.3V
2 CERM
1UF
10%
6.3V
2 CERM
1UF
10%
6.3V
2 CERM
1UF
10%
6.3V
2 CERM
1UF
10%
6.3V
2 CERM
B
402 402 402 402 402 402 402 402 402 402
1 C3203 1 C3292 1 C3291 1 C3290 1 C3288 1 C3287 1 C3286 1 C3285 1 C3214 1 C3213
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
402 402 402 402 402 402 402 402 402 402
PROC DECOUPLING
A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
D 051-6772 E
APPLE COMPUTER INC.
SCALE SHT OF
NONE 32 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
33 7 =PP12V_RUN_CPU
C3310 34 33 6 PP12V_CPU
R3329
1 1UF
10 SC2643_VCC 33 U3310_BST_R 1 2
5% CRITICAL CRITICAL
1/16W
MF-LF 20%
16V
1
C3311 1 C3312
2 402 CERM 1000UF 10UF
1206
R3330 6 U3310_DRN 2
20%
16V 2 CERM
10%
16V
0 ELEC
1 2 SYS_SLEWING_L 13 25 27 TH-KZJ 1210
1 C3319 R33901 5%
1/16W
34 33 6 PP12V_CPU U3310
1UF
9
0 MF-LF
6 VIN
SC1211
20%
16V 5% 402 SOIC BG 8
D 33 SC2643_AGND
2 CERM
1206
VCC
U3300
1/16W
MF-LF
402 2 33 OUT1 4 CO VREG 7
D 4 CRITICAL
Q3310 D
14 VID0 OUT1 19 OUT1 1 DRN TG 2 U3310_TG NTD60N02R
CPU_VID_R<0>
C3329 R3307
8 6 TSSOP 33 1
1 G CASE369
8 6 CPU_VID_R<1> 13 VID1 OUT2 20 OUT2 33
1UF 2.2 1 2 U3310_BST 3 BST VPN 5 S3 CRITICAL
SC2643VX
CPU_VID_R<2> 12 VID2 OUT3 21 OUT3 20% 1
8 6
11 VID3 OUT4 22 OUT4
34
2 16V
CERM
5% THMPAD R3350 L3310
8 6 CPU_VID_R<3>
R3300 1206 1/10W
MF-LF 9
10K
5%
0.6UH-24A
8 6 CPU_VID_R<4> 10 VID4
U3300_BGOUT
1.5K 2 VRM_EN
603 1/16W
PN1 1 2 PPVCORE_CPU
15 VID5 BGOUT 4 1 3
R3310 MF-LF 33 6 6 7 33 34 35
CPU_VID_R<5> MIN_NECK_WIDTH=0.25MM
8 6
PGOOD 16 SC2643_PGOOD
5%
1/16W 3 Q3312 D3310
BAS16 1
1 2
2 402 MIN_LINE_WIDTH=0.6MM TH1 CRITICAL
SC2643_OS1 3 OS1 MF-LF 2N7002 SOT23 1
C3318 1
C3317 1
C3332
402 D SOT23-LF 1 5%
SC2643_OS2 2 OS2 ERROUT 5 1/16W 4 1800UF 1800UF 1800UF
1 OS3
U3310_VREG MF-LF 20% 20% 20%
SC2643_OS3 402 2 6.3V 2 6.3V 2 6.3V
24 OS4 DACSTEP 8 SC2643_DACSTEP S G 1 SYS_POWERUP_L 6 7 10 11 13 VPN1 D
ELEC ELEC ELEC
SC2643_OS4 CRITICAL TH-KZJ TH-KZJ TH-KZJ
1 C3301 Q3311
23 OUTSEN FB 7 1UF 2 1
R3312 NTD70N03R
1
R3311
GSENSE 6
1 C3300 10%
2 6.3V 100
U3310_BG 1 G 1
SC2643_OSCREF
CASE369 5%
0.1UF CERM S
1
R3391 17 OSCREF
20% 402 5%
1/16W
1/8W
MF-LF
0 2 10V MF-LF 2 805
5%
1/16W AGND
CERM
402 SC2643_AGND
1 C3313 2 402 NOSTUFF 3
MF-LF
33
1UF C3316_1
2 402
18 NOSTUFF 20%
16V AUX1
1 C3315
R3328
1
R3303
2 CERM
1206
33
0.0022UF 1 C3316
332K 10%
50V 0.0047UF
1% 2.7M 2 2 CERM
1/16W SC2643_ERROUT 1 SC2643_VCC 10%
MF-LF
5%
33
1 C3314 402 2 25V
CERM
2 402 0.001UF 402
1
R3301 1/10W
MF-LF 20%
50V VOLTAGE SENSE
30K 603 2 CERM
SC2643_AGND 33 5% 402 PLACE NEXT TO SMU
1/16W
MF-LF NOSTUFF 34 33 6 PP12V_CPU
2 402 33 6 PN1
AUX1 33 AUX2 33 AUX3 34
1
R3302 R3360
1
C3302_1 0
C 1
R3313
20.5K
1
R3316
20.5K
1
R3317
20.5K
1 C3302
330PF
5%
1/16W
MF-LF NOSTUFF
10K
1%
1/16W
C
10% 2 402 MF-LF
1%
1/16W
1%
1/16W
1%
1/16W
50V
2 CERM 35 34 33 7 6 PPVCORE_CPU R3308 2 402
MF-LF MF-LF MF-LF 402 100K 2
2 402 2 402 2 402
1 CPU_SENSE_V 13
5%
NOSTUFF NOSTUFF NOSTUFF C3320 PP12V_CPU
1/16W
MF-LF
1
R3361 1 C3303
1UF
34 33 6
402 2.0K 10UF
C3304 R3314 SC2643_AGND
C3305 R3315 C3306 R3318
1 1 1 1 33 1% 20%
0.0082UF
1 1 U3320_BST_R 1 2 1/16W
6.3V
2 CERM
10%
20.5K 20.5K
0.0082UF 1% 20.5K
0.0082UF MF-LF 805
1% 1% 2 402
2
25V
X7R 1/16W
MF-LF
10%
25V
2 X7R
1/16W
MF-LF
10%
25V
2 X7R
1/16W
MF-LF
20%
16V
1
C3321 1 C3322 GND_SMU_AVSS 8 13 33 36
402 CERM 1000UF 10UF
2 402 402 2 402 402 2 402 1206 20% 10%
6 U3320_DRN 2 16V 16V
2 CERM
VCORE_SENSE_GND 6 33 ELEC
1210
TH-KZJ
R3305 R3304 DIFFERENTIAL PAIR

PP12V_CPU U3320 SCALE COUNT
SC2643_VCC
4.99K2
SC2643_OS_HUB
261 34 33 6
6 VIN
SC1211 6 V/V .01464 V/COUNT
33 1 1 2 FOR REMOTE SENSE SOIC BG 8
1% 1% D 4 CRITICAL
1/16W 1/16W OUT2 4 CO VREG 7 ADC IS 10BIT 0 TO 1023
MF-LF
402 C3308 MF-LF
402
VCORE_SENSE_VOUT 6 33
33
Q3320 0 TO 2.5V
0.068UF U3320_TG NTD60N02R
R3306 1 DRN TG 2 1
G
CASE369
1 2 2.2 U3320_BST 3 BST
1 2 VPN 5 1
S 3
10% 1 C3330 THMPAD R3351 L3320
10V R3326 1UF
5%
1/10W 10K 0.6UH-24A
OMIT CERM
402 1
301 2 20%
MF-LF 9 5%
603
XW3300
SM 1%
NOSTUFF 16V
2 CERM 3
R3320
1/16W
MF-LF
33 6 PN2 1 2 PPVCORE_CPU 6 7 33 34 35
1/16W 1206
D3320 1 2 402 MIN_NECK_WIDTH=0.25MM TH1
33 SC2643_AGND 1 2 MF-LF
402 R3324
1
BAS16
SOT23
1 2 1
C3328 1
C3333
330 1 5% 1800UF 1800UF
NOSTUFF 5% 1/16W 4 20% 20%
1/16W U3320_VREG MF-LF 2 6.3V 2 6.3V
R3325 MF-LF
VPN2
402 ELEC
TH-KZJ
ELEC
TH-KZJ
B 1
1K 2 R3325_2
2 402 D CRITICAL
Q3321 1
R3321
B
5%
1/16W R3322
1
U3320_BG 1 G NTD70N03R 1
MF-LF 100 S
CASE369 5%
402 5% 1/8W
PLACE R3325 CLOSE TO INDUCTOR OUTPUT LEAD. 1/16W MF-LF
NOSTUFF MF-LF 2 805
1 C3323 2 402 NOSTUFF 3
C3309 1UF
20%
1 C3325 C3326_1
0.015UF AUX2 0.0022UF
2 16V
SC2643_OUTSEN 1 2
OMIT
CERM
1206
33
10%
50V
2 CERM
1 C3326
0.0047UF
R3327 10% 16V
X7R 402
XW3302
SM 1 C3324
402 10%
25V
2 CERM
1.5K 2 0.001UF
1 SC2643_OUTSEN_R 1 2 PPVCORE_CPU 6 7 33 34 35
20%
402
1% CONNECT BETWEEN THE INDUCTOR & BULK CAPS. 50V
2 CERM
1/16W 402
MF-LF
402
33 6 PN2
PLACE REGULATOR SENSE POINTS AT DESIGNATED LOCATIONS.
R3335 CRITICAL
0
35 34 33 7 6 PPVCORE_CPU MIN_LINE_WIDTH=0.25MM 1 2 VCORE_SENSE_VOUT 6 33 L3300 PP12V_CPU 6 33 34
R3336 5%
DIFFERENTIAL_PAIR=P_SENSE_CORE
33 7 =PP12V_RUN_CPU 1UH-20A-4.5MOHM R3343 VOLTAGE=12V
1/16W MIN_NECK_WIDTH=0.2MM 0.0252 MIN_NECK_WIDTH=0.25MM
UNDER PROCESSOR
1
0 2
MF-LF
402
NET_SPACING_TYPE=PROC_DIFF 1 2 PP12V_CPU_R 1 CURRENT SENSE
TH-VERT 1%
5% NOSTUFF 1W KEEP SHORTS NEXT TO U3301
1/16W
R3337 VCORE_SENSE_GND 6 33 MF
MF-LF 2512 PLACE R3344 AND C3331 BY SMU
402
1
0 2
DIFFERENTIAL_PAIR=P_SENSE_CORE
NOSTUFF MIN_NECK_WIDTH=0.2MM OMIT

5% NET_SPACING_TYPE=PROC_DIFF =PP3V3_RUN_CPU
NEAR SIDE R3338 1/16W
MF-LF
XW3304
SM
7
1
0 2
402 3
VIN+ VIN-
4
INA138_OUT 1 2 CORE_ISNS_P 6 36 3 NOSTUFF
SCALE COUNT
CPU VREG
5% NOSTUFF OMIT D3300
A 1/16W
R3339 U3301 BAS16 2.73224 A/V .00675 A/COUNT SYNC_MASTER=N/A SYNC_DATE=N/A
MF-LF
402
1
0 2
5
INA138
SOT23-5 1
XW3303
SM R3344
100K 2
1
SOT23
A
NOSTUFF 5%
V+ OUT 1 2 CPU_SENSE_I_R 1 CPU_SENSE_I 13 ADC IS 10BIT 0 TO 1023
FAR SIDE R3340 1/16W
MF-LF
5%
1/16W
0 TO 2.5V THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
0 402 MF-LF AGREES TO THE FOLLOWING
1 2
R3345
1 402 1 C3331 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
5% NOSTUFF GND 73.2K 10UF
20%
1/16W
MF-LF R3341 2 1%
1/16W 2 6.3V
CERM
402
1
0 2
MF-LF 805 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
KPVDD2
36 31 6
2 402
NOSTUFF 5% OMIT SIZE DRAWING NUMBER REV.
CPU SENSE SIDE R3342 1/16W
XW3301 GND_SMU_AVSS 8 13 33 36
051-6772 E
36 31 6 KPGND2 1
0 2
MF-LF
402 SM
APPLE COMPUTER INC.
D
1 2 CORE_ISNS_M 6 36
5% SCALE SHT OF
1/16W
MF-LF
402
NONE 33 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
PP12V_CPU 6 33 34
C3410 35 34 33 7 6 PPVCORE_CPU
1
C3411 1
C3412 1
C3422 1 C3468
1UF 1000UF 1000UF 1000UF 10UF
U3410_BST_R 1 2 20% 20% 20% 10%
16V
2 16V
ELEC
2 16V
ELEC
2 16V
ELEC
2 CERM EXTRA_C EXTRA_C EXTRA_C EXTRA_C
20%
16V
TH-KZJ TH-KZJ TH-KZJ 1210 1 C3433 1 C3431 1 C3429 1 C3461 1 C3459
CERM 10UF 10UF 10UF 10UF 10UF
1206 20% 20% 20% 20% 20%
6 U3410_DRN 2 6.3V
CERM
6.3V
2 CERM 2 6.3V
CERM
6.3V
2 CERM 2 6.3V
CERM
1206 1206 1206 1206 1206
U3410 EXTRA_C EXTRA_C EXTRA_C

D 34 33 6 PP12V_CPU 6 VIN
SC1211
SOIC BG 8 1 C3434
10UF
1 C3432
10UF
1 C3430
10UF
1 C3462
10UF
1 C3460
10UF
D
D 4 CRITICAL
OUT3 4 CO VREG 7 20% 20% 20% 20% 20%
33
Q3410 6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
1 DRN TG 2 U3410_TG NTD60N02R 1206 1206 1206 1206 1206
R3423 1
G CASE369
2.2
1 2 U3410_BST 3 BST VPN 5 1
S3 EXTRA_C EXTRA_C EXTRA_C
1 C3470 5%
1/10W
THMPAD R3450
10K
L3410 1 C3443 1 C3437 1 C3435 1 C3465 1 C3463
1UF MF-LF 9 5%
0.6UH-24A PPVCORE_CPU 6 7 33 34 35
10UF 10UF 10UF 10UF 10UF
20% 603 1/16W
20% 20% 20% 20% 20%
2 16V
CERM 3
R3410 MF-LF 34 6 PN3 1 2 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
1206 D3410 1 2 402 MIN_NECK_WIDTH=0.25MM TH1 1206 1206 1206 1206 1206
BAS16
SOT23
1 2 1
C3417 1
C3418 1
C3472 1
C3473 1
C3427 1
C3474 1
C3475
1 5% 1800UF 1800UF 1800UF 1800UF 1800UF 1800UF 1800UF EXTRA_C EXTRA_C EXTRA_C
1/16W 4 20% 20% 20% 20% 20% 20% 20%
U3410_VREG MF-LF
402
2 6.3V
ELEC
2 6.3V
ELEC
2 6.3V
ELEC
2 6.3V
ELEC
2 6.3V
ELEC
2 6.3V
ELEC
2 6.3V
ELEC
1 C3444 1 C3438 1 C3436 1 C3466 1 C3464
VPN3 TH-KZJ TH-KZJ TH-KZJ TH-KZJ TH-KZJ TH-KZJ TH-KZJ 10UF 10UF 10UF 10UF 10UF
D CRITICAL 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V
Q3411 1
R3411
2 CERM
1206
2 CERM
1206
2 CERM
1206
2 CERM
1206
2 CERM
1206
1
R3412 U3410_BG 1 G NTD70N03R 1
100 S
CASE369 5%
5% 1/8W PP3V3_RUN 6 7 10 11 18 22 50 EXTRA_C EXTRA_C EXTRA_C EXTRA_C
1/16W MF-LF
1 C3413 MF-LF NOSTUFF 2 805 DEVELOPMENT 1 C3445 1 C3441 1 C3439 1 C3401 1 C3467
2 402 C3415 3 10UF 10UF 10UF 10UF 10UF
1UF
1
0.0022UF C3416_1
1
R3490 20% 20% 20% 20% 20%
20%
16V 330 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
2 CERM AUX3 10% 5%
CERM CERM CERM CERM CERM
1206
33
2 50V
CERM
1 C3416 1/16W
MF-LF
1206 1206 1206 1206 1206
402 0.0047UF
10% 2 402 EXTRA_C EXTRA_C EXTRA_C
1 C3414 2 25V
CERM LED_CPU_CORE_P 1 C3446 1 C3442 1 C3440 1 C3402 1 C3400
0.001UF 402
20% 10UF 10UF 10UF 10UF 10UF
50V 20% 20% 20% 20% 20%
2 CERM 6.3V 6.3V 6.3V 6.3V 6.3V
402 1
DEVELOPMENT 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
DEVELOPMENT 1206 1206 1206 1206 1206
PN3 LED3400
34 6
R3491 DEVELOPMENT
C 1
0 2 CPU_CORE_FOR_LED 8
3
LM339A
SOI
2
GREEN
2.0X1.25A
1
EXTRA_C
C3455 1
EXTRA_C
C3449 1 C3447 1
EXTRA_C
C3405 1
EXTRA_C
C3403
C
5% V+
14 LED_CPU_CORE_N 10UF 10UF 10UF 10UF 10UF
1/16W
MF-LF U1001 20% 20% 20% 20% 20%
402
9 GND 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
50 22 10 1V1_REF 1206 1206 1206 1206 1206
12
EXTRA_C EXTRA_C EXTRA_C
1 C3456 1 C3450 1 C3448 1 C3406 1 C3404
20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V
1206 1206 1206 1206 1206
EXTRA_C EXTRA_C EXTRA_C EXTRA_C

1 C3457 1 C3453 1 C3451 1 C3409 1 C3407
20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
1206 1206 1206 1206 1206
EXTRA_C
1 C3458 1 C3454 1 C3452 1 C3419 1 C3408
20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V
1206 1206 1206 1206 1206
B B
CPU VREG
A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
D 051-6772 E
APPLE COMPUTER INC.
SCALE SHT OF
NONE 34 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
D D
35 34 33 7 6 PPVCORE_CPU
CRITICAL
EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C
1 C3500 1 C3512 1 C3523 1 C3534 1 C3545 1 C3501 1 C3589 1 C3578 1 C3567 1 C3556
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
1206 1206 1206 1206 1206 1206 1206 1206 1206 1206

1 C3513 1 C3511 1 C3510 1 C3509 1 C3508 1 C3507 1 C3506 1 C3505 1 C3504 1 C3503
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
1206 1206 1206 1206 1206 1206 1206 1206 1206 1206
35 34 33 7 6 PPVCORE_CPU DS3502
SMB
PP2V5_RUN_CPU_AVDD_R 31
1 2 EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C

1 C3524 1 C3522 1 C3521 1 C3520 1 C3519 1 C3518 1 C3517 1 C3516 1 C3515 1 C3514
10BQ040PBF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
1206 1206 1206 1206 1206 1206 1206 1206 1206 1206

1 C3535 1 C3533 1 C3532 1 C3531 1 C3530 1 C3529 1 C3528 1 C3527 1 C3526 1 C3525
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
1206 1206 1206 1206 1206 1206 1206 1206 1206 1206
EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C

C 1 C3546
10UF
1 C3544
10UF
1 C3543
10UF
1 C3542
10UF
1 C3541
10UF
1 C3540
10UF
1 C3539
10UF
1 C3538
10UF
1 C3537
10UF
1 C3536
10UF
C
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
1206 1206 1206 1206 1206 1206 1206 1206 1206 1206
EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C

1 C3557 1 C3555 1 C3554 1 C3553 1 C3552 1 C3551 1 C3550 1 C3549 1 C3548 1 C3547
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
1206 1206 1206 1206 1206 1206 1206 1206 1206 1206
EXTRA_C EXTRA_C EXTRA_C EXTRA_C

1 C3568 1 C3566 1 C3565 1 C3564 1 C3563 1 C3562 1 C3561 1 C3560 1 C3559 1 C3558
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
1206 1206 1206 1206 1206 1206 1206 1206 1206 1206
EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C

1 C3579 1 C3577 1 C3576 1 C3575 1 C3574 1 C3573 1 C3572 1 C3571 1 C3570 1 C3569
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
1206 1206 1206 1206 1206 1206 1206 1206 1206 1206
EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C

1 C3590 1 C3588 1 C3587 1 C3586 1 C3585 1 C3584 1 C3583 1 C3582 1 C3581 1 C3580
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
1206 1206 1206 1206 1206 1206 1206 1206 1206 1206
B EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C B

1 C3502 1 C3599 1 C3598 1 C3597 1 C3596 1 C3595 1 C3594 1 C3593 1 C3592 1 C3591
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
1206 1206 1206 1206 1206 1206 1206 1206 1206 1206
CPU VREG OUTPUT CAPS

A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
D 051-6772 E
APPLE COMPUTER INC.
SCALE SHT OF
NONE 35 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
NOSTUFF
7 =PP5V_PWRON_CPU
DS3602
SOD-123
1 2
B0530WXF
7 =PP5V_ALL_CPU
D R3602
1
2 2 MIN_LINE_WIDTH=0.25MM DAVDD 36
D
1/10W
MF-LF
1 C3603 1 C3604 1 C3605 1 C3600
603 2.2UF 2.2UF 2.2UF 2.2UF
XW3601
SM
20%
10V
2 CERM
20%
10V
2 CERM
20%
10V
2 CERM
20%
10V
2 CERM
805 805 805 805
1 2 DAGND 36
OMIT MIN_NECK_WIDTH=0.2MM
XW3600, R3602, AND DS3602 MUST BE PLACED CLOSE TO SMU
100UA CURRENT SOURCE
R3606 R3603
DAGND 1
10.0K2 TD11
10.0K2 TD_CURRENT
36
0.1% 0.1%
1/16W 1/16W
MF-LF MF-LF
THESE SIGNALS HAVE A MIN_LINE_WIDTH=0.25MM 603 603
AND MIN_NECK_WIDTH=0.2MM 36 DAVDD
MIN_NECK_WIDTH=0.2MM U3601
5 LMV2011
4 BUFFER
SOT23-5
1
R3604
20.0K2
36 ADC_REF 1 TD23 36 DAVDD
0.1%
1/16W
2
DAGND
1
R3608 U3602
MF-LF
36 12.7K 4 5 LMV2011
C 603
1%
1/10W
MF-LF
2 603
SOT23-5
1 C
3
R3607 R3605 DAGND

2
36
20.0K2 10.0K2
36 DAGND 1 1 TD_BUFFERED
POWER MONITOR
0.1%
1/16W
0.1%
1/16W
MIN_NECK_WIDTH=0.2MM C3607
MF-LF MF-LF 10UF
603 603 1 2
20% =PP3V3_ALL_CPU 7 =PP3V3_PWRON_CPU 7

6.3V
R3609 R3611 CERM
10.0K2 100K 2 805 R3650
1
1 NOSTUFF
1 TD3
0.25MM
1
5%
0 DS3650
SOD-123
0.1% 0.1%
1/16W 0.2MM 1/16W 1/10W
B0530WXF
MF-LF MF-LF MF-LF
603 603 2 603 2
CPU0_DIODE_POS NEED TO CONNECT TO P65 OF 80PIN SMU OR PIN 49 OF 64PIN SMU

R3612 PP3V3_CPU_DIODE
DAGND 1
40.2K2 36 DAVDD MIN_LINE_WIDTH=0.6MM
36 31 TDIODE_POS 36
0.1%
U3603
5 LMV2011 R3601
1NOSTUFF 4
R3628
1 C3610 1 C3606 R3616 1/16W
MF-LF
SOT23-5
100K 2
200 1 C3601
0.0022UF 0.0022UF 1K 603 1 CPU_TEMP_R 1 CPU_TEMP
1%
1/10W
10% 10% 1% 13 36
MIN_LINE_WIDTH=0.25MM MF-LF 2.2UF
1/16W 5% 20%
2 50V
CERM 2 50V
CERM MF-LF R3610 3 1/16W MIN_NECK_WIDTH=0.2MM 2 603 10V
2 CERM
402 402 2 402 10.0K2 MF-LF 1 C3613 36 ADC_REF 805
TDIODE_NEG 1 2 402 MIN_LINE_WIDTH=0.25MM
36 31 6 DAGND 36 10UF
0.1% 20% MIN_NECK_WIDTH=0.2MM
CPU0_DIODE_NEG R3615
1 1/16W
MF-LF
2 6.3V
CERM R3690 6
0 603 805
PPVREF_SMU_ADC_REF 1
0 2
5% GND_SMU_AVSS 8 13 33
8 VREF
1/16W
R3613 R3614 5%
B MF-LF
2 402
36 ADC_REF 1
40.2K2
TD4 1 2
100K
ADC_REF 36
1/16W
MF-LF
402
U3650
NCV1009D
ADJ 5 NC
B
0.25MM SO-8 1
0.1% 0.1% NC1
1/16W
MF-LF
0.2MM 1/16W
MF-LF
C3608 NC2 2
603 603 10UF
NC3 3 NOSTUFF
1
1 2
NC4 7 D3600
20%
6.3V NC5 8 2.5V 1 C3602
CERM SSOT-23 0.47UF
805 GND 20%
10V
NOSTUFF 2 CERM
4
R3691
2
3
603
0
8 GND_SMU_AVSS_DAGND 1 2 DAGND 36
PLACE CLOSE 5%
1/16W NEEDED FOR FMAX
TO U2900 MF-LF
402
OMIT
XW3611
SM
NOSTUFF KPVDD2_FMAX 1 2 KPVDD2 NOSTUFF
J3600
6
DIFFERENTIAL_PAIR=KP2_FMAX
MIN_LINE_WIDTH=0.25MM OMIT
6 31 33
R3620
51
BM12B-SRSS-TB MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PROC_DIFF XW3612 36 13 CPU_TEMP 1 2 FMAXT_P
F-ST-SM
14 SM 5% DIFFERENTIAL_PAIR=P_FMAXT NOSTUFF
6 KPGND2_FMAX
DIFFERENTIAL_PAIR=KP2_FMAX
1 2 KPGND2 6 31 33
1/16W
MF-LF NET_SPACING_TYPE=PROC_DIFF R3619
1
MIN_LINE_WIDTH=0.25MM OMIT 402 0

1 MIN_NECK_WIDTH=0.2MM 5%
2 NET_SPACING_TYPE=PROC_DIFF XW3613
SM
NOSTUFF
R3621
1/8W
MF-LF
3 51 2 805
6 TDIODE_POS_FMAX 1 2 TDIODE_POS 31 36
36 DAGND 1 2 FMAXT_M
DIFFERENTIAL_PAIR=TDIODE
4
5
OMIT
XW3614
5%
1/16W
MF-LF
DIFFERENTIAL_PAIR=P_FMAXT
NET_SPACING_TYPE=PROC_DIFF CPU DIODE CONDITIONER
SM 402
A
6 SYNC_MASTER=N/A SYNC_DATE=N/A
7
8
6 TDIODE_NEG_FMAX
DIFFERENTIAL_PAIR=TDIODE
1 2 TDIODE_NEG 6 31 36
PLACE AT BOARD EDGE
A
9 NET_SPACING_TYPE=PROC_DIFF
10 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
CORE_ISNS_M 6 33 AGREES TO THE FOLLOWING
11 DIFFERENTIAL_PAIR=CORE_ISNS
MIN_LINE_WIDTH=0.25MM I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NET_SPACING_TYPE=PROC_DIFF II NOT TO REPRODUCE OR COPY IT
13
CORE_ISNS_P 6 33
DIFFERENTIAL_PAIR=CORE_ISNS
MIN_LINE_WIDTH=0.25MM SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6772 E
SCALE SHT OF
NONE 36 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
U3TWINS DO NOT HAVE MASKS
46 40 37 26 7 =PP2V5_PWRON_RAM
60 48 28 7 =PP1V5_PWRON_NB_AVDD R3702
2.2
1 2 PP1V5_PWRON_RAM_NB_AVDD
AG19
AG25
AE13
AE16
AE22
AE27
AC19
AB25
AA13
AA16
Y16
Y19
W23
W27
V20
VOLTAGE=1.5V MIN_LINE_WIDTH=0.6MM
5% MIN_NECK_WIDTH=0.25MM =PP2V5_PWRON_RAM 7 26 37 40 46
1/10W
VDD_DDR
MF-LF
603
1 C3745 1 C3744
1UF 0.1UF
U3 10% 20%
2 6.3V 2 10V
AB21
U3LITE CERM CERM
T19
T21
T25
P20
N21
N25
M19
K19
K23
K27
G25
F19
D22
D27
B25
V1.0-300MM 402 402
D 38 RAM_DQ_R<0> AF20 DDR_DQ0

AH22 DDR_DQ1
PBGA
(SYM 2 OF 7) DDR_DQ64 AG27 RAM_DQ_R<64> 38 DDR VDD_DDR
D
38 RAM_DQ_R<1> DDR_DQ65 AF24 RAM_DQ_R<65> 38 CLK_AVDD
38 RAM_DQ_R<2> AH21 DDR_DQ2 OMIT
DDR_DQ66 AE24 RAM_DQ_R<66> 38 U3
AG21 DDR_DQ3 U3LITE
38 RAM_DQ_R<3> DDR_DQ67 AG26 RAM_DQ_R<67> 38 27 RAM_CLK66M_NB AC20 DDR_CLKP
V1.0-300MM DDR_RAS AE21 RAM_RAS_L_R 38
38 RAM_DQ_R<4> AB20 DDR_DQ4 DDR_DQ68 AF26 RAM_DQ_R<68> 38 PBGA

38 RAM_CLK_A_P_R AA12 DDR_CK_A (SYM 3 OF 7) DDR_CAS AD20 RAM_CAS_L_R 38
38 RAM_DQ_R<5> AC21 DDR_DQ5 DDR_DQ69 AD24 RAM_DQ_R<69> 38
38 RAM_CLK_A_N_R AB12 DDR_CK_AN OMIT
RAM_DQ_R<6> AD23 DDR_DQ6 DDR_DQ70 AD25 RAM_DQ_R<70> DDR_WE AC23 RAM_WE_L_R
38
MEMORY 38
38 RAM_CLK_B_P_R AB14 DDR_CK_B 38
RAM_DQ_R<7> AD21 DDR_DQ7 DDR_DQ71 AG28 RAM_DQ_R<71>

38
DATA 38
38 RAM_CLK_B_N_R AA14 DDR_CK_BN
RAM_DQ_R<8> AH26 DDR_DQ8 DDR_DQ72 AF28 RAM_DQ_R<72> DDR_BA0 AF21 RAM_BA_R<0>
38
INTERFACE 38
38 RAM_CLK_C_P_R AE15 DDR_CK_C 38
38 RAM_DQ_R<9> AH25 DDR_DQ9 DDR_DQ73 AE28 RAM_DQ_R<73> 38 DDR_BA1 AE20 RAM_BA_R<1> 38

38 RAM_CLK_C_N_R AE14 DDR_CK_CN
38 RAM_DQ_R<10> AH24 DDR_DQ10 DDR_DQ74 AD26 RAM_DQ_R<74> 38
38 RAM_CLK_D_P_R AC14 DDR_CK_D
38 RAM_DQ_R<11> AH23 DDR_DQ11 DDR_DQ75 AF27 RAM_DQ_R<75> 38 DDR_MUXEN0 AH16 RAM_MUXEN0 8
38 RAM_CLK_D_N_R AD14 DDR_CK_DN
38 RAM_DQ_R<12> AH27 DDR_DQ12 DDR_DQ76 AC26 RAM_DQ_R<76> 38 DDR_MUXEN4 AH18 RAM_MUXEN4 8
38 RAM_CLK_E_P_R AD15 DDR_CK_E
38 RAM_DQ_R<13> AG24 DDR_DQ13 DDR_DQ77 AC25 RAM_DQ_R<77> 38
38 RAM_CLK_E_N_R AC15 DDR_CK_EN
38 RAM_DQ_R<14> AF23 DDR_DQ14 DDR_DQ78 AC27 RAM_DQ_R<78> 38 MEMORY DDR_MAD0 AG12 RAM_A_R<0> 38
38 RAM_CLK_F_P_R AA15 DDR_CK_F
38 RAM_DQ_R<15> AH28 DDR_DQ15 DDR_DQ79 AD27 RAM_DQ_R<79> 38 CONTROL DDR_MAD1 AH13 RAM_A_R<1> 38
38 RAM_CLK_F_N_R AB15 DDR_CK_FN
38 RAM_DQ_R<16> U25 DDR_DQ16 DDR_DQ80 AA27 RAM_DQ_R<80> 38 INTERFACE DDR_MAD2 AH14 RAM_A_R<2> 38
38 RAM_DQ_R<17> AA23 DDR_DQ17 DDR_DQ81 AA26 RAM_DQ_R<81> 38 DDR_MAD3 AH15 RAM_A_R<3> 38

38 RAM_CKE_R<0> AC17 DDR_CKE0
38 RAM_DQ_R<18> Y22 DDR_DQ18 DDR_DQ82 AA24 RAM_DQ_R<82> 38 DDR_MAD4 AF12 RAM_A_R<4> 38
38 RAM_CKE_R<1> AD17 DDR_CKE1
38 RAM_DQ_R<19> AA22 DDR_DQ19 DDR_DQ83 AA28 RAM_DQ_R<83> 38 DDR_MAD5 AE12 RAM_A_R<5> 38
8 RAM_CKE_R<2> AE17 DDR_CKE2
38 RAM_DQ_R<20> U24 DDR_DQ20 DDR_DQ84 Y26 RAM_DQ_R<84> 38 DDR_MAD6 AD12 RAM_A_R<6> 38
8 RAM_CKE_R<3> AF17 DDR_CKE3
38 RAM_DQ_R<21> V23 DDR_DQ21 DDR_DQ85 Y25 RAM_DQ_R<85> 38 DDR_MAD7 AC12 RAM_A_R<7> 38
38 RAM_CKE_R<4> AB17 DDR_CKE4
38 RAM_DQ_R<22> V22 DDR_DQ22 DDR_DQ86 Y28 RAM_DQ_R<86> 38 DDR_MAD8 AG15 RAM_A_R<8> 38
38 RAM_CKE_R<5> AA17 DDR_CKE5
38 RAM_DQ_R<23> U22 DDR_DQ23 DDR_DQ87 Y24 RAM_DQ_R<87> 38 DDR_MAD9 AF15 RAM_A_R<9> 38
8 RAM_CKE_R<6> AB18 DDR_CKE6
38 RAM_DQ_R<24> P25 DDR_DQ24 DDR_DQ88 V26 RAM_DQ_R<88> 38 DDR_MAD10 AF14 RAM_A_R<10> 38
8 RAM_CKE_R<7> AA18 DDR_CKE7
38 RAM_DQ_R<25> R22 DDR_DQ25 DDR_DQ89 V27 RAM_DQ_R<89> 38 DDR_MAD11 AG14 RAM_A_R<11> 38
C 38
38
RAM_DQ_R<26>
RAM_DQ_R<27>
R21 DDR_DQ26
U23 DDR_DQ27
DDR_DQ90 V24
DDR_DQ91 W28
RAM_DQ_R<90>
RAM_DQ_R<91>
38
38
Y21 DDR_VREF0
U21 DDR_VREF1
DDR_MAD12 AH17
DDR_MAD13 AG17
RAM_A_R<12>
RAM_A_R<13>
38
38
C
38 RAM_DQ_R<28> P26 DDR_DQ28 DDR_DQ92 U27 RAM_DQ_R<92> 38
R24 DDR_DQ29
=PP2V5_PWRON_RAM 7 26 37 40 46
L21 DDR_VREF2
38 RAM_DQ_R<29> DDR_DQ93 V28 RAM_DQ_R<93> 38
H20 DDR_VREF3 DDR_CS0 AF18 RAM_CS_L_R<0> 38
38 RAM_DQ_R<30> P24 DDR_DQ30 DDR_DQ94 T28 RAM_DQ_R<94> 38 DDR_CS1 AE18 RAM_CS_L_R<1> 38

AA21 DDR_VREF4
38 RAM_DQ_R<31> P23 DDR_DQ31 DDR_DQ95 U26 RAM_DQ_R<95> 38
R37001 DDR_CS2 AG20 RAM_CS_L_R<2> 8
M25 DDR_DQ32 1K M21 DDR_VREF5
38 RAM_DQ_R<32> DDR_DQ96 R27 RAM_DQ_R<96> 38 1% V21 DDR_VREF6 DDR_CS3 AH20 RAM_CS_L_R<3> 8
M23 DDR_DQ33 1/16W MIN_LINE_WIDTH=0.6MM
38 RAM_DQ_R<33> DDR_DQ97 R26 RAM_DQ_R<97> 38 MF-LF MIN_NECK_WIDTH=0.25MM J20 DDR_VREF7 DDR_CS8 AC18 RAM_CS_L_R<8> 38
P21 DDR_DQ34 402 2
38 RAM_DQ_R<34> DDR_DQ98 R28 RAM_DQ_R<98> 38 DDR_CS9 AD18 RAM_CS_L_R<9> 38
P22 DDR_DQ35
PP1V25_PWRON_RAM_VREF_NB
38 RAM_DQ_R<35> DDR_DQ99 P27 RAM_DQ_R<99> 38 VOLTAGE=1.25V DDR_CS10 AG18 RAM_CS_L_R<10> 8
M24 DDR_DQ36 DDR_DQ100 M28 DDR_CS11 AH19
38 RAM_DQ_R<36>
L22 DDR_DQ37
RAM_DQ_R<100> 38 R37011 1 C3730 1 C3746 1 C3747 1 C3748 RAM_CS_L_R<11> 8
38 RAM_DQ_R<37> DDR_DQ101 N28 RAM_DQ_R<101> 38 1K 0.1UF 0.1UF 0.1UF 0.1UF

L23 DDR_DQ38 1%
38 RAM_DQ_R<38> DDR_DQ102 L28 RAM_DQ_R<102> 38 1/16W 20% 20% 20% 20% DDR_DQSP0 AC24 RAM_DQS_R<0> 38
J23 DDR_DQ39 MF-LF 2 10V 2 10V 2 10V 2 10V
38 RAM_DQ_R<39> DDR_DQ103 P28 RAM_DQ_R<103> 38 402 2
CERM
402
CERM
402
CERM
402
CERM
402 DDR_DQSP1 AG23 RAM_DQS_R<1> 38
38 RAM_DQ_R<40> D23 DDR_DQ40 DDR_DQ104 L25 RAM_DQ_R<104> 38 DDR_DQSP2 Y23 RAM_DQS_R<2> 38
38 RAM_DQ_R<41> D24 DDR_DQ41 DDR_DQ105 L26 RAM_DQ_R<105> 38 DDR_DQSP3 R23 RAM_DQS_R<3> 38
38 RAM_DQ_R<42> C26 DDR_DQ42 DDR_DQ106 L27 RAM_DQ_R<106> 38 DDR_DQSP4 M22 RAM_DQS_R<4> 38
38 RAM_DQ_R<43> C27 DDR_DQ43 DDR_DQ107 K28 RAM_DQ_R<107> 38 DDR_DQSP5 B26 RAM_DQS_R<5> 38
38 RAM_DQ_R<44> A22 DDR_DQ44 DDR_DQ108 H27 RAM_DQ_R<108> 38 DDR_DQSP6 B27 RAM_DQS_R<6> 38
38 RAM_DQ_R<45> A25 DDR_DQ45 DDR_DQ109 H28 RAM_DQ_R<109> 38 DDR_DQSP7 F23 RAM_DQS_R<7> 38
38 RAM_DQ_R<46> C24 DDR_DQ46 DDR_DQ110 J27 RAM_DQ_R<110> 38 DDR_DQSP8 AE23 RAM_DQS_R<8> 38
38 RAM_DQ_R<47> C23 DDR_DQ47 DDR_DQ111 L24 RAM_DQ_R<111> 38 DDR_DQSP9 AD28 RAM_DQS_R<9> 38
38 RAM_DQ_R<48> B24 DDR_DQ48 DDR_DQ112 J25 RAM_DQ_R<112> 38 DDR_DQSP10 Y27 RAM_DQS_R<10> 38
38 RAM_DQ_R<49> B23 DDR_DQ49 DDR_DQ113 J24 RAM_DQ_R<113> 38 DDR_DQSP11 U28 RAM_DQS_R<11> 38
38 RAM_DQ_R<50> A23 DDR_DQ50 DDR_DQ114 J26 RAM_DQ_R<114> 38 DDR_DQSP12 M27 RAM_DQS_R<12> 38
38 RAM_DQ_R<51> A24 DDR_DQ51 DDR_DQ115 G28 RAM_DQ_R<115> 38 DDR_DQSP13 J28 RAM_DQS_R<13> 38
RAM_DQ_R<52> A27 DDR_DQ52 DDR_DQ116 H25 RAM_DQ_R<116> DDR_DQSP14 F28 RAM_DQS_R<14>

B
38
38 RAM_DQ_R<53> A28 DDR_DQ53

B28 DDR_DQ54
DDR_DQ117 H24 RAM_DQ_R<117>
38
38 DDR_DQSP15 F25 RAM_DQS_R<15>

38
38 B
38 RAM_DQ_R<54> DDR_DQ118 F27 RAM_DQ_R<118> 38
DDR_CLK_AVSS
RAM_DQ_R<55> A26 DDR_DQ55 DDR_DQ119 H26 RAM_DQ_R<119>
AA20
38 38
38 RAM_DQ_R<56> F24 DDR_DQ56 DDR_DQ120 E28 RAM_DQ_R<120> 38
38 RAM_DQ_R<57> J22 DDR_DQ57 DDR_DQ121 E27 RAM_DQ_R<121> 38
38 RAM_DQ_R<58> E23 DDR_DQ58 DDR_DQ122 F26 RAM_DQ_R<122> 38
38 RAM_DQ_R<59> H23 DDR_DQ59 DDR_DQ123 E26 RAM_DQ_R<123> 38
38 RAM_DQ_R<60> J21 DDR_DQ60 DDR_DQ124 D28 RAM_DQ_R<124> 38
38 RAM_DQ_R<61> H21 DDR_DQ61 DDR_DQ125 C28 RAM_DQ_R<125> 38
38 RAM_DQ_R<62> G21 DDR_DQ62 DDR_DQ126 E25 RAM_DQ_R<126> 38
38 RAM_DQ_R<63> H22 DDR_DQ63 DDR_DQ127 E24 RAM_DQ_R<127> 38
=PP2V5_PWRON_RAM 7 26 37 40 46
1 C3700 1 C3701 1 C3702 1 C3703 1 C3704 1 C3705 1 C3706 1 C3707 1 C3708 1 C3709 1 C3710 1 C3711 1 C3712 1 C3713 1 C3714 1 C3731 1 C3732 1 C3733 1 C3734 1 C3735 1 C3736 1 C3737
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402 U3LITE MEMORY
A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
1 C3715 1 C3716 1 C3717 1 C3718 1 C3719 1 C3720 1 C3721 1 C3722 1 C3724 1 C3725 1 C3726 1 C3727 1 C3728 1 C3729 1 C3743 1 C3742 1 C3740 1 C3739 1 C3738 II NOT TO REPRODUCE OR COPY IT
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 SIZE DRAWING NUMBER REV.
D 051-6772 E
APPLE COMPUTER INC.
SCALE SHT OF
NONE 37 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
ALL R PACKS ARE 1/16W 5% ELECTRICAL_CONSTRAINT_SET NET_PHYSICAL_TYPE NET_SPACING_TYPE DIFFERENTIAL_PAIR
RP3836 RP3818 RAM_CLK_A_P_R RAM_CLK RAM_CLK RAM_CLK_A_R

38 37 RAM_DQ_R<7> 4 5 22 RAM_DQ<7> 38 40 44 38 37 RAM_DQ_R<68> 2 7 22 RAM_DQ<68> 38 40 45
38 37 I206
RP3836 RP3805 RAM_CLK_A_N_R RAM_CLK RAM_CLK RAM_CLK_A_R

38 37 I207
RP3836 RP3818 RAM_CLK_B_P_R RAM_CLK RAM_CLK RAM_CLK_B_R
38 37 I208
RP3836 RP3805 RAM_CLK_B_N_R RAM_CLK RAM_CLK RAM_CLK_B_R
38 37 I209
RP3816 RP3818 RAM_CLK_C_P_R RAM_CLK RAM_CLK RAM_CLK_C_R
38 37 I210
RP3816 RP3805 RAM_CLK_C_N_R RAM_CLK RAM_CLK RAM_CLK_C_R
38 37 I211
RP3816 RP3805 RAM_CLK_D_P_R RAM_CLK RAM_CLK RAM_CLK_D_R
38 37 I212
RP3816 RP3818 RAM_CLK_D_N_R RAM_CLK RAM_CLK RAM_CLK_D_R
38 37 I213
RP3835 RP3817 RAM_CLK_E_P_R RAM_CLK RAM_CLK RAM_CLK_E_R
38 37 I214
RP3801 RP3802 RAM_CLK_E_N_R RAM_CLK RAM_CLK RAM_CLK_E_R
RAM_DQ_R<10> 1 8 22 RAM_DQ<10> RAM_DQ_R<73> 4 5 22 RAM_DQ<73>
38 37 I215
D
38 37
38 37 RAM_DQ_R<11> RP3801
RP3801
3
4
6
5
22
22
RAM_DQ<11>
38 40 44
38 40 44
38 37
38 37 RAM_DQ_R<72> RP3817
RP3817
2
4
7
5
22
22
RAM_DQ<72>
38 40 45
38 40 45
38 37
38 37
RAM_CLK_F_P_R
RAM_CLK_F_N_R
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK_F_R
RAM_CLK_F_R
I216
I217
D
38 37 RAM_DQ_R<14> RAM_DQ<14> 38 40 44 38 37 RAM_DQ_R<75> RAM_DQ<75> 38 40 45
RP3835 RP3802 RAM_CLK_A_P RAM_CLK0 RAM_CLK RAM_CLK RAM_CLK_A
40 38 I218
RP3801 RP3817 RAM_CLK_A_N RAM_CLK0 RAM_CLK RAM_CLK RAM_CLK_A
40 38 I219
RP3835 RP3802 RAM_CLK_B_P RAM_CLK0 RAM_CLK RAM_CLK RAM_CLK_B
40 38 I220
RP3835 RP3802 RAM_CLK_B_N RAM_CLK0 RAM_CLK RAM_CLK RAM_CLK_B
40 38 I221
RP3822 RP3806 RAM_CLK_C_P RAM_CLK0 RAM_CLK RAM_CLK RAM_CLK_C
40 38 I222
RP3822 RP3821 RAM_CLK_C_N RAM_CLK0 RAM_CLK RAM_CLK RAM_CLK_C

40 38 I223
RP3822 RP3821 RAM_CLK_D_P RAM_CLK1 RAM_CLK RAM_CLK RAM_CLK_D
40 38 I224
RP3822 RP3821 RAM_CLK_D_N RAM_CLK1 RAM_CLK RAM_CLK RAM_CLK_D
40 38 I225
RP3823 RP3806 RAM_CLK_E_P RAM_CLK1 RAM_CLK RAM_CLK RAM_CLK_E
40 38 I226
RP3823 RP3806 RAM_CLK_E_N RAM_CLK1 RAM_CLK RAM_CLK RAM_CLK_E
40 38 I227
RP3823 RP3821 RAM_CLK_F_P RAM_CLK1 RAM_CLK RAM_CLK RAM_CLK_F
40 38 I228
RP3823 RP3806 RAM_CLK_F_N RAM_CLK1 RAM_CLK RAM_CLK RAM_CLK_F
40 38 I229
RAM_DQ_R<30> RP3808 3 6 22 RAM_DQ<30> RAM_DQ_R<91> RP3819 3 6 22 RAM_DQ<91>

38 37 38 40 44 38 37 38 40 45
RP3824 RP3819 RAM_CKE_R<1..0> RAM_CAD RAM_CAD
38 37 I230
RP3808 RP3803 RAM_CKE_R<5..4> RAM_CAD RAM_CAD
38 37 I232
RP3824 RP3819 RAM_CKE<0> RAM_CKECS0 RAM_CAD RAM_CAD
44 40 38 I234

44 40 38 I236
45 40 38 I235
45 40 38 I237
RP3824 RP3803 RAM_CS_L_R<1..0> RAM_CAD RAM_CAD
38 37 I238
RP3826 RP3820 RAM_CS_L_R<9..8> RAM_CAD RAM_CAD
38 37 I241
RP3807 RP3820 RAM_CS_L<0> RAM_CKECS0 RAM_CAD RAM_CAD
44 40 38 I243

44 40 38 I242
45 40 38 I245
22 22 45 40 38
C
I244
C 38 37 RAM_DQ_R<39> 3 6 RAM_DQ<39> 38 40 44 38 37 RAM_DQ_R<100> 2 7 RAM_DQ<100> 38 40 45
RAM_DQ_R<33> RP3807 3 6 22 RAM_DQ<33> RAM_DQ_R<99> RP3825 3 6 22 RAM_DQ<99> RAM_DQS_R<15..0>

38 37 38 40 44 38 37 38 40 45 38 37 RAM_CAD RAM_CAD I305
RAM_DQ_R<34> RP3807 1 8 22 RAM_DQ<34> RAM_DQ_R<102> RP3825 1 8 22 RAM_DQ<102> RAM_DQ_R<127..0>
38 37 38 40 44 38 37 38 40 45 38 37 RAM_CAD RAM_CAD I294
38 37 RAM_DQ_R<36> RP3826 1 8 22 RAM_DQ<36> 38 40 44 38 37 RAM_DQ_R<101> RP3825 4 5 22 RAM_DQ<101> 38 40 45 45 44 40 38 RAM_DQ<127..0> RAM_CAD RAM_CAD I293
RAM_DQ_R<47> RP3811 2 7 22 RAM_DQ<47> RAM_DQ_R<111> RP3809 1 8 22 RAM_DQ<111> RAM_DQS<0>
38 37 38 40 44 38 37 38 40 45 44 40 38 RAM_DQS0 RAM_CAD RAM_CAD I246
RAM_DQ_R<46> RP3811 1 8 22 RAM_DQ<46> RAM_DQ_R<106> RP3809 3 6 22 RAM_DQ<106> RAM_DQ<7..0>
38 37 RAM_DQ_R<45> RP3811 4 5 22 RAM_DQ<45> 38 40 44 38 37 RAM_DQ_R<107> RP3829 4 5 22 RAM_DQ<107> 38 40 45 44 40 38 RAM_DQS<2> RAM_DQS2 RAM_CAD RAM_CAD I253
38 37 RAM_DQ_R<42> RP3814 3 6 22 RAM_DQ<42> 38 40 44 38 37 RAM_DQ_R<110> RP3829 3 6 22 RAM_DQ<110> 38 40 45 44 40 38 RAM_DQ<23..16> RAM_DQS2 RAM_CAD RAM_CAD I254
RAM_DQ_R<58> RP3813 3 6 22 RAM_DQ<58> RAM_DQ_R<126> RP3810 1 8 22 RAM_DQ<126> RAM_DQS<11> RAM_DQS11 RAM_CAD RAM_CAD
B
38 37
38 37 RAM_DQ_R<62> RP3813 4 5 22 RAM_DQ<62>

38 40 44
38 40 44
38 37
38 37 RAM_DQ_R<127> RP3810 3 6 22 RAM_DQ<127>

38 40 45
38 40 45
45 40 38
45 40 38 RAM_DQ<95..88> RAM_DQS11 RAM_CAD RAM_CAD

I272
I271
B
45 40 38 RAM_DQS<12> RAM_DQS12 RAM_CAD RAM_CAD I273
THE FOLLOWING IS A SWAPPABLE GROUP
RP3841 3 RAM_DQ<103..96> RAM_DQS12 RAM_CAD RAM_CAD
38 37 RAM_CKE_R<4> 6 15 RAM_CKE<4> 38 40 45
45 40 38 I275
RP3841 4 THE FOLLOWING ARE 0402 5% RESISTORS RAM_DQS<13> RAM_DQS13 RAM_CAD RAM_CAD
38 37 RAM_CKE_R<5> 5 15 RAM_CKE<5> 38 40 45
45 40 38 I274
RP3841 RAM_DQ<111..104> RAM_DQS13 RAM_CAD RAM_CAD
38 37 RAM_CKE_R<0> 2 7 15 RAM_CKE<0> 38 40 44
R3816
45 40 38 I277
RP3841 1 8 15 38 37 RAM_CLK_A_P_R 1 2 15 RAM_CLK_A_P 38 40 45 40 38 RAM_DQS<14> RAM_DQS14 RAM_CAD RAM_CAD I276
38 37 RAM_CKE_R<1> RAM_CKE<1> 38 40 44
R3817
38 37 RAM_CLK_A_N_R 1 2 15 RAM_CLK_A_N 38 40 45 40 38 RAM_DQ<119..112> RAM_DQS14 RAM_CAD RAM_CAD I278
RAM_CS_L_R<8> RP3842 1 8 15 RAM_CS_L<8> RAM_CLK_B_P_R R3818 1 2 15 RAM_CLK_B_P RAM_DQS<15>
38 37 38 40 45 38 37 38 40 45 40 38 RAM_DQS15 RAM_CAD RAM_CAD I280
38 37 RAM_CS_L_R<9> RP3842 2 7 15 RAM_CS_L<9> 38 40 45 38 37 RAM_CLK_B_N_R R3819 1 2 15 RAM_CLK_B_N 38 40 45 40 38 RAM_DQ<127..120> RAM_DQS15 RAM_CAD RAM_CAD I279
38 37 RAM_CS_L_R<1> RP3842 3 6 15 RAM_CS_L<1> 38 40 44 38 37 RAM_CLK_C_P_R R3820 1 2 15 RAM_CLK_C_P 38 40
RAM_CS_L_R<0> RP3842 4 5 15 RAM_CS_L<0> RAM_CLK_C_N_R R3821 1 2 15 RAM_CLK_C_N RAM_A_R<13..0>

38 37 38 40 44 38 37 38 40 38 37 RAM_CAD RAM_CAD I295
38 37 RAM_CLK_D_P_R R3822 1 2 15 RAM_CLK_D_P 38 40 38 37 RAM_BA_R<1..0> RAM_CAD RAM_CAD I296
THE FOLLOWING IS A SWAPPABLE GROUP 38 37 RAM_CLK_D_N_R R3823 1 2 15 RAM_CLK_D_N 38 40 38 37 RAM_RAS_L_R RAM_CAD RAM_CAD I297
RAM_A_R<11> RP3832 3 6 15 RAM_A<11> RAM_CLK_E_P_R R3824 1 2 15 RAM_CLK_E_P RAM_CAS_L_R
38 37 38 40 44 38 37 38 40 38 37 RAM_CAD RAM_CAD I298
38 37 RAM_A_R<1> RP3832 4 5 15 RAM_A<1> 38 40 44 38 37 RAM_CLK_E_N_R R3825 1 2 15 RAM_CLK_E_N 38 40 38 37 RAM_WE_L_R RAM_CAD RAM_CAD I299
38 37 RAM_A_R<10> RP3832 2 7 15 RAM_A<10> 38 40 45 38 37 RAM_CLK_F_P_R R3826 1 2 15 RAM_CLK_F_P 38 40 45 44 40 38 RAM_A<13..0> RAM_A_CTL RAM_CAD RAM_CAD I300
38 37 RAM_WE_L_R RP3800 4 5 15 RAM_WE_L 38 40 45 38 37 RAM_CLK_F_N_R R3827 1 2 15 RAM_CLK_F_N 38 40 45 40 38 RAM_BA<1..0> RAM_A_CTL RAM_CAD RAM_CAD I304
38 37 RAM_A_R<4> RP3833 3 6 15 RAM_A<4> 38 40 44 45 40 38 RAM_RAS_L RAM_A_CTL RAM_CAD RAM_CAD I303
RAM_A_R<6> RP3833 2 7 15 RAM_A<6> RAM_CAS_L
38 37 38 40 44 45 40 38 RAM_A_CTL RAM_CAD RAM_CAD I302
38 37 RAM_A_R<7> RP3833 1 8 15 RAM_A<7> 38 40 44 38 37 RAM_DQS_R<0> R3800 1 2 15 RAM_DQS<0> 38 40 44 45 40 38 RAM_WE_L RAM_A_CTL RAM_CAD RAM_CAD I301
RP3834 1 8 15 38 37 RAM_DQS_R<1> R3801 1 2 15 RAM_DQS<1> 38 40 44
RAM_A_R<12> RP3800 3 6 15 RAM_A<12> RAM_DQS_R<2> R3802 1 2 15 RAM_DQS<2>

38 37 38 40 44 38 37 38 40 44
38 37 RAM_A_R<2> RP3834 2 7 15 RAM_A<2> 38 40 44 38 37 RAM_DQS_R<3> R3803 1 2 15 RAM_DQS<3> 38 40 44

RP3833 15 R3804
38 37
38 37
RAM_A_R<0>
RAM_A_R<5> RP3832
4
1
5
8 15
RAM_A<0>
RAM_A<5>
38 40 44
38 40 44
38 37
38 37
RAM_DQS_R<4>
RAM_DQS_R<5> R3805
1
1
2
2
15
15
RAM_DQS<4>
RAM_DQS<5>
38 40 44
38 40 44
RAM_CLK PRIMARY SPACING SET BASED ON DIFF IMPEDANCE
RAM_CLK LINE-LINE SPACING SET TO 15MIL
SERIES TERM
RP3800 15 R3806 15
A RAM_A_R<13> 2 7 RAM_A<13> RAM_DQS_R<6> 1 2 RAM_DQS<6> TOTAL LENGTH TOLERENCE = 20PS = 2.82MM SYNC_MASTER=N/A SYNC_DATE=N/A
38 37
38 37 RAM_A_R<3> RP3800 1 8 15 RAM_A<3>

38 40 44
38 40 44
38 37
38 37 RAM_DQS_R<7> R3807
R3808
1 2 15 RAM_DQS<7>
38 40 44
38 40 44
RAM_CAD SPACING IS 10MIL NOTICE OF PROPRIETARY PROPERTY
A
38 37 RAM_DQS_R<8> 1 2 15 RAM_DQS<8> 38 40 45
38 37 RAM_CAS_L_R RP3804 1 8 15 RAM_CAS_L 38 40 45 38 37 RAM_DQS_R<9> R3809 1 2 15 RAM_DQS<9> 38 40 45 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
RAM_BA_R<0> RP3804 4 5 15 RAM_BA<0> RAM_DQS_R<10> R3810 1 2 15 RAM_DQS<10>
38 37 38 40 45 38 37 38 40 45 AGREES TO THE FOLLOWING
38 37 RAM_DQS_R<11> R3811 1 2 15 RAM_DQS<11> 38 40 45 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
38 37 RAM_BA_R<1> RP3804 2 7 15 RAM_BA<1> 38 40 45 38 37 RAM_DQS_R<12> R3812 1 2 15 RAM_DQS<12> 38 40 45 II NOT TO REPRODUCE OR COPY IT
RAM_RAS_L_R RP3804 3 6 15 RAM_RAS_L RAM_DQS_R<13> R3813 1 2 15 RAM_DQS<13>
38 37 38 40 45 38 37 38 40 45 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
38 37 RAM_A_R<9> RP3834 3 6 15 RAM_A<9> 38 40 44 38 37 RAM_DQS_R<14> R3814 1 2 15 RAM_DQS<14> 38 40 45
RAM_A_R<8> RP3834 4 5 15 RAM_A<8> RAM_DQS_R<15> R3815 1 2 15 RAM_DQS<15>

051-6772 E
38 37 38 40 44 38 37 38 40 45
APPLE COMPUTER INC.

D
SCALE SHT OF
NONE 38 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
PIN 82:
46 40 37 26 7 =PP2V5_PWRON_RAM J4001 =PP2V5_PWRON_RAM 7 26 37 40 46
46 40 37 26 7 =PP2V5_PWRON_RAM J4000 =PP2V5_PWRON_RAM 7 26 37 40 46 NC: VDD & VDDQ ARE THE SAME =PP2V5_PWRON_RAM 7 26 37 40 46
DDR-DIMM-STD GND: VDD & VDDQ ARE DIFFERENT

DDR-DIMM-STD
516-0086 F-28DEG-TH
F-28DEG-TH 1
BOT SIDE TOP SIDE 40 PP1V25_RAM_VREF_DIMM 1 BOT SIDE TOP SIDE
93 R4008
PP1V25_RAM_VREF_DIMM 1 93 VREF OMIT VSS 150
40 VREF OMIT VSS 45 38 RAM_DQ<75> 2 94 RAM_DQ<74> 38 45 1%
44 38 RAM_DQ<14> 2 94 RAM_DQ<11> 38 44
DQ0 DQ4 1/16W
DQ0 DQ4 3 95 RAM_DQ<72> MF-LF
3 95 RAM_DQ<13> VSS DQ5 38 45
VSS DQ5 38 44
45 38 RAM_DQ<79> 4 96 2 402
RAM_DQ<10> 4 96 DQ1 VDDQ PP1V25_RAM_VREF_DIMM 40
44 38 DQ1 VDDQ 45 38 RAM_DQS<9> 5 97 MIN_LINE_WIDTH=0.6MM
44 38 RAM_DQS<1> 5 97 DQS0 DM0/DQS9 MIN_NECK_WIDTH=0.25MM
DQS0 DM0/DQS9 45 38 RAM_DQ<73> 6 98 RAM_DQ<76> 38 45
44 38 RAM_DQ<9> 6 98 RAM_DQ<8> 38 44
DQ2 DQ6 1 C4035 R40101
DQ2 DQ6 7 99 RAM_DQ<78>
7 99 RAM_DQ<12> 38 44
VDD DQ7 38 45
1UF 150
VDD DQ7 RAM_DQ<77> 8 100 10% 1%
RAM_DQ<15> 8 100 45 38 DQ3 VSS 6.3V
D
44 38
NC 9
10
DQ3
NC
VSS
NC
101 NC
102 NC 6 TP_J4001_SJRESET_L
NC 9
10
NC
NC
NC
NC
101 NC
102 NC
2 CERM
603
1/16W
MF-LF
2 402
D
6 TP_J4000_SJRESET_L NC NC 11 103 NC FETEN
11 103 NC FETEN VSS A13
VSS A13 45 38 RAM_DQ<66> 12 104
RAM_DQ<2> 12 104 DQ8 VDDQ
44 38 DQ8 VDDQ 45 38 RAM_DQ<67> 13 105 RAM_DQ<65> 38 45
44 38 RAM_DQ<0> 13 105 RAM_DQ<3> 38 44
DQ9 DQ12
DQ9 DQ12 RAM_DQS<8> 14 106 RAM_DQ<64>
44 38 RAM_DQS<0> 14 106 RAM_DQ<7> 38 44
45 38 DQS1 DQ13 38 45
DQS1 DQ13 15 107
15 107 VDDQ DM1/DQS10
VDDQ DM1/DQS10 38 RAM_CLK_F_P 16 108
38 RAM_CLK_A_P 16 108 CK1 VDD
CK1 VDD 38 RAM_CLK_F_N 17 109 RAM_DQ<69> 38 45
38 RAM_CLK_A_N 17 109 RAM_DQ<1> 38 44
CK1* DQ14
CK1* DQ14 18 110 RAM_DQ<68> 38 45
18 110 RAM_DQ<4> 38 44
VSS DQ15
VSS DQ15 RAM_DQ<71> 19 111 RAM_CKE<5>
44 38 RAM_DQ<6> 19 111 RAM_CKE<1> 38 44
45 38 DQ10 CKE1 38 45
DQ10 CKE1 45 38 RAM_DQ<70> 20 112
RAM_DQ<5> 20 112 =PP2V5_PWRON_RAM DQ11 VDDQ =PP2V5_PWRON_RAM
44 38 DQ11 VDDQ 7 26 37 40 46
45 38 RAM_CKE<4> 21 113 NC 7 26 37 40 46
44 38 RAM_CKE<0> 21 113 NC CKE0 BA2

CKE0 BA2 22 114 RAM_DQ<81>
22 114 RAM_DQ<17> VDDQ DQ20 38 45
RAM_DQ<19> 23
VDDQ DQ20
115 RAM_A<12>
38 44
1 C4036 1 C4006 45 38 RAM_DQ<83> 23
DQ16 A12
115 RAM_A<12> 38 40 44
1 C4008 1 C4007
44 38 DQ16 A12 38 40 44
10UF 10UF 45 38 RAM_DQ<80> 24 116 10UF 10UF
44 38 RAM_DQ<18> 24 116 20% 20% DQ17 VSS 20% 20%
DQ17 VSS 6.3V
2 CERM
6.3V
2 CERM RAM_DQS<10> 25 117 RAM_DQ<86> 6.3V
2 CERM
6.3V
2 CERM
44 38 RAM_DQS<2> 25 117 RAM_DQ<22> 38 44
45 38 DQS2 DQ21 38 45
DQS2 DQ21 1206 1206 26 118 RAM_A<11> 38 40 44
1206 1206
26 118 RAM_A<11> VSS A11
VSS A11 38 40 44
44 40 38 RAM_A<9> 27 119
RAM_A<9> 27 119 A9 DM2/DQS11
44 40 38
RAM_DQ<23> 28
A9 DM2/DQS11
120
1 C4039 1 C4037 1 C4023 45 38 RAM_DQ<82> 28
DQ18 VDD
120 1 C4011 1 C4010 1 C4009
44 38 DQ18 VDD 0.1UF 0.1UF 0.1UF 44 40 38 RAM_A<7> 29 121 RAM_DQ<85> 38 45
0.1UF 0.1UF 0.1UF
44 40 38 RAM_A<7> 29 121 RAM_DQ<21> 38 44
20% 20% 20% A7 DQ22 20% 20% 20%
30
A7 DQ22
122 2 10V
CERM 2 10V
CERM 2 10V
CERM
30
VDDQ A8
122 RAM_A<8> 38 40 44
10V
2 CERM
10V
2 CERM
10V
2 CERM
VDDQ A8 RAM_A<8> 38 40 44
402 402 402 31 123 402 402 402
45 38 RAM_DQ<87> DQ19 DQ23 RAM_DQ<84> 38 45
RAM_DQ<16> 31 123 RAM_DQ<20>
44 38 DQ19 DQ23 38 44
44 40 38 RAM_A<5> 32 124
RAM_A<5> 32 124 A5 VSS
44 40 38
RAM_DQ<27> 33
A5 VSS
125 RAM_A<6>
1 C4040 1 C4038 1 C4024 45 38 RAM_DQ<90> 33
DQ24 A6
125 RAM_A<6> 38 40 44
1 C4014 1 C4012 1 C4033
44 38 DQ24 A6 38 40 44
0.1UF 0.1UF 0.1UF 34 126 RAM_DQ<91> 38 45
0.1UF 0.1UF 0.1UF
34 126 RAM_DQ<26> 20% 20% 20% VSS DQ28 20% 20% 20%
VSS DQ28 2 10V 2 10V 2 10V 10V 10V 10V
38 44
RAM_DQ<89> 35 127 RAM_DQ<93> 2 CERM 2 CERM 2 CERM
CERM CERM CERM 45 38 38 45
C 44 38
44 38
RAM_DQ<29>
RAM_DQS<3>
35
36
DQ25
DQS3
DQ29
VDDQ
127
128
RAM_DQ<25> 38 44 402 402 402 45 38
44 40 38
RAM_DQS<11>
RAM_A<4>
36
37
DQ25
DQS3
DQ29
VDDQ
128
129
402 402 402
C
RAM_A<4> 37 129 A4 DM3/DQS12
44 40 38
38
A4 DM3/DQS12
130 RAM_A<3>
1 C4044 1 C4041 1 C4025 38
VDD A3
130 RAM_A<3> 38 40 44
1 C4000 1 C4013 1 C4042
VDD A3 38 40 44
0.1UF 0.1UF 0.1UF 45 38 RAM_DQ<88> 39 131 RAM_DQ<92> 38 45
0.1UF 0.1UF 0.1UF
44 38 RAM_DQ<31> 39 131 RAM_DQ<24> 38 44
20% 20% 20% DQ26 DQ30 20% 20% 20%
40
DQ26 DQ30
132 2 10V
CERM 2 10V
CERM 2 10V
CERM 45 38 RAM_DQ<94> 40
DQ27 VSS
132 2 10V
CERM 2 10V
CERM 2 10V
CERM
44 38 RAM_DQ<28> DQ27 VSS 402 402 402 41 133 402 402 402
41 133 44 40 38 RAM_A<2> A2 DQ31 RAM_DQ<95> 38 45
44 40 38 RAM_A<2> A2 DQ31 RAM_DQ<30> 38 44
42 134 NC
42 134 NC VSS NC
RAM_A<1> 43
VSS NC
135 NC
1 C4045 1 C4043 1 C4026 44 40 38 RAM_A<1> 43
A1 NC
135 NC 1 C4020 1 C4015 1 C4001
44 40 38
A1 NC 0.1UF 0.1UF 0.1UF NC 44 136 0.1UF 0.1UF 0.1UF
NC 44 136 20% 20% 20% NC VDDQ 20% 20% 20%
NC VDDQ 2 10V
CERM
10V
2 CERM 10V
2 CERM NC 45 NC CK0
137 RAM_CLK_D_P 38
10V
2 CERM 2 10V
CERM 2 10V
CERM
NC 45 NC CK0
137 RAM_CLK_C_P 38 402 402 402 46 138 402 402 402
46 138 VDD CKO* RAM_CLK_D_N 38
VDD CKO* RAM_CLK_C_N 38
47 139
NC NC VSS
NC 47 139
RAM_A<0> 48
NC VSS
140 NC
1 C4048 1 C4046 1 C4029 44 40 38 RAM_A<0> 48
A0 NC
140 NC 1 C4017 1 C4016 1 C4027
44 40 38 A0 NC 0.1UF 0.1UF 0.1UF NC 49 141 RAM_A<10> 38 40 45
0.1UF 0.1UF 0.1UF
NC 49 141 RAM_A<10> 38 40 45
20% 20% 20% NC A10 20% 20% 20%
50
NC A10
142 NC 2 10V
CERM 2 10V
CERM 2 10V
CERM
50
VSS NC
142 NC 2 10V
CERM 2 10V
CERM 2 10V
CERM
VSS NC 402 402 402 NC 51 143 402 402 402
NC 51 143 NC VDDQ
NC VDDQ RAM_BA<1> 52 144 NC
RAM_BA<1> 52 144 NC 45 40 38 BA1 NC
45 40 38 BA1 NC 1 C4031 1 C4047 1 C4030 RAM_DQ<98> 53 145
1 C4019 1 C4051 1 C4004
44 38 RAM_DQ<34> 53 145 0.1UF 0.1UF 0.1UF 45 38 DQ32 VSS 0.1UF 0.1UF 0.1UF
DQ32 VSS 20% 20% 20% 54 146 RAM_DQ<96> 20% 20% 20%
54 146 RAM_DQ<35> 2 CERM
10V 10V
2 CERM
10V
2 CERM
VDDQ DQ36 38 45 10V
2 CERM
10V
2 CERM
10V
2 CERM
VDDQ DQ36 38 44
RAM_DQ<103> 55 147 RAM_DQ<97>
44 38 RAM_DQ<37> 55 147 RAM_DQ<33> 38 44
402 402 402 45 38 DQ33 DQ37 38 45 402 402 402
DQ33 DQ37 RAM_DQS<12> 56 148
44 38 RAM_DQS<4> 56 148 45 38 DQS4 VDD
DQS4 VDD RAM_DQ<101> 57 149
44 38 RAM_DQ<38> 57
DQ34 DM4/DQS13
149 1 C4050 1 C4049 1 C4032 45 38
58
DQ34 DM4/DQS13
150 RAM_DQ<99>
1 C4021 1 C4018 1 C4005
58 150 RAM_DQ<36> 38 44
0.1UF 0.1UF 0.1UF VSS DQ38 38 45
0.1UF 0.1UF 0.1UF
VSS DQ38 20% 20% 20% RAM_BA<0> 59 151 RAM_DQ<100> 20% 20% 20%
2 10V 10V 10V BA0 DQ39 10V 10V 10V
45 40 38 38 45
45 40 38 RAM_BA<0> 59 151 RAM_DQ<39> 38 44 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
BA0 DQ39 CERM RAM_DQ<102> 60 152
44 38 RAM_DQ<32> 60 152 402 402 402 45 38 DQ35 VSS 402 402 402
DQ35 VSS RAM_DQ<106> 61 153 RAM_DQ<104>
B 44 38 RAM_DQ<61> 61
62
DQ40
VDDQ
DQ44
RAS*
153
154
RAM_DQ<60>
RAM_RAS_L
38 44
38 40 45
1 C4028 1 C4022
45 38
62
63
DQ40
VDDQ
DQ44
RAS*
154
155
RAM_RAS_L
38 45
38 40 45
1 C4052 1 C4002 1 C4003
B
63 155 0.1UF 0.1UF 45 40 38 RAM_WE_L WE* DQ45 RAM_DQ<105> 38 45
0.1UF 0.1UF 0.1UF
45 40 38 RAM_WE_L WE* DQ45 RAM_DQ<63> 38 44
20% 20% 64 156 20% 20% 20%
RAM_DQ<111>
2 10V 2 10V DQ41 VDDQ 10V 10V 10V
45 38
44 38 RAM_DQ<57> 64 156 2 CERM 2 CERM 2 CERM
DQ41 VDDQ CERM CERM RAM_CAS_L 65 157 RAM_CS_L<8>
RAM_CAS_L 65 157 RAM_CS_L<0> 402 402 45 40 38 CAS* S0* 38 45 402 402 402
45 40 38 CAS* S0* 38 44
66 158 RAM_CS_L<9> 38 45
66 158 RAM_CS_L<1> 38 44
VSS S1*
VSS S1* RAM_DQS<13> 67 159
44 38 RAM_DQS<7> 67 159 45 38 DQS5 DM5/DQS14
DQS5 DM5/DQS14 45 38 RAM_DQ<107> 68 160
RAM_DQ<59> 68 160 DQ42 VSS
44 38 DQ42 VSS 45 38 RAM_DQ<110> 69 161 RAM_DQ<108> 38 45
44 38 RAM_DQ<56> 69 161 RAM_DQ<62> 38 44
DQ43 DQ46
DQ43 DQ46 70 162 RAM_DQ<109>
70 162 RAM_DQ<58> 38 44
VDD DQ47 38 45
VDD DQ47 NC 71 163 NC
NC 71 163 NC NC,S2* NC,S3*
NC,S2* NC,S3* 45 38 RAM_DQ<114> 72 164
44 38 RAM_DQ<43> 72 164 DQ48 VDDQ
DQ48 VDDQ 45 38 RAM_DQ<113> 73 165 RAM_DQ<112> 38 45
RAM_DQ<41> 73 165 RAM_DQ<40> DQ49 DQ52
44 38 DQ49 DQ52 38 44
74 166 RAM_DQ<117> 38 45
74 166 RAM_DQ<42> 38 44
VSS DQ53
VSS DQ53 RAM_CLK_E_N 75 167 RAM_A<13>
38 RAM_CLK_B_N 75 167 RAM_A<13> 38 40 44
38 CK2* NC,FETEN 38 40 44
CK2* NC,FETEN 38 RAM_CLK_E_P 76 168
RAM_CLK_B_P 76 168 CK2 VDD
38 CK2 VDD 77 169
77 169 VDDQ DM6/DQS15
VDDQ DM6/DQS15 RAM_DQS<14> 78 170 RAM_DQ<119>
44 38 RAM_DQS<5> 78 170 RAM_DQ<46> 38 44
45 38 DQS6 DQ54 38 45
DQS6 DQ54 45 38 RAM_DQ<115> 79 171 RAM_DQ<116> 38 45
RAM_DQ<47> 79 171 RAM_DQ<45> DQ50 DQ55
44 38 DQ50 DQ55 38 44
45 38 RAM_DQ<118> 80 172
44 38 RAM_DQ<44> 80 172 DQ51 VDDQ
DQ51 VDDQ 81 173 NC
81 173 NC VSS NC
VSS NC NC 82 174 RAM_DQ<120> 38 45
NC 82 174 RAM_DQ<49> 38 44
VDDID DQ60
VDDID DQ60 45 38 RAM_DQ<124> 83 175 RAM_DQ<121> 38 45
44 38 RAM_DQ<50> 83 175 RAM_DQ<48> 38 44
DQ56 DQ61
DQ56 DQ61 45 38 RAM_DQ<125> 84 176
RAM_DQ<51> 84 176 DQ57 VSS
44 38 DQ57 VSS
85
86
VDD DM7/DQS16
177
178 45 38 RAM_DQS<15>
85
86
VDD
DQS7
DM7/DQS16
DQ62
177
178 RAM_DQ<122> 38 45
DIMMS
44 38 RAM_DQS<6> DQS7 DQ62 RAM_DQ<54> 38 44
87 179
A 44 38
44 38
RAM_DQ<53>
RAM_DQ<52>
87
88
DQ58 DQ63
179
180
RAM_DQ<55> 38 44
45 38
45 38
RAM_DQ<127>
RAM_DQ<126> 88
DQ58
DQ59
DQ63
VDDQ
180
RAM_DQ<123> 38 45 SYNC_MASTER=N/A

SYNC_DATE=N/A
A
DQ59 VDDQ 89 181 SA0
89 181 SD_A_SA0 VSS SA0
VSS SA0 NC 90 182 SA1 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
NC 90 182 SA1 WP SA1 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
WP SA1 40 18 I2C_DIMM_SDA 91 183 SA2 SD_B_SA2 AGREES TO THE FOLLOWING
I2C_DIMM_SDA 91 183 SDA SA2
40 18
92
SDA SA2
184
SA2 R4014 40 18 I2C_DIMM_SCL 92
SCL VVDDSPD
184 R4006 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
40 18 I2C_DIMM_SCL SCL VVDDSPD 1
10K 2 1
10K 2
5% 5% III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1/16W TABLE_5_HEAD
1/16W
MF-LF PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION MF-LF
ADDR=0(A0/A1) 402 402 SIZE DRAWING NUMBER REV.
ADDR=1(A2/A3)
051-6772 E
TABLE_5_ITEM
516-0086 2 CONN,DDR DIMM 30 DEG J4000,J4001 17_INCH_LCD

TABLE_5_ITEM
CRITICAL
V
V R’S ADJACENT TO V’S OR G’S APPLE COMPUTER INC.
D
516-0087 2 CONN,DDR DIMM REVERSE 30 DEG J4000,J4001 20_INCH_LCD CRITICAL R V’S ADJACENT TO G’S FORBIDDEN
R SCALE SHT OF
V
NONE 40 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
46 45 44 PP1V25_RAM_VTT
46 45 44 PP1V25_RAM_VTT 46 45 44 PP1V25_RAM_VTT
8 RAM_VTT RAM_VTT RAM_VTT RAM_VTT RAM_VTT RAM_VTT RAM_VTT RAM_VTT RAM_VTT RAM_VTT
RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5 RAM_VTT RAM_VTT RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT RAM_VTT RAM_VTT
RP4400 RP4400 RP4400 RP4400 RP4401 RP4401 RP4401 RP4401 1 C4400 1 C4412 RP4416 RP4416 RP4416 RP4416 RP4417 RP4417 RP4417 RP4417 1 C4407 1 C4414
1
R4400 1R4401 1R4402 1R4403 1R4404 1R4405 1R4406 1R4407 1 C4408 1 C4420
120 120 120 120 120 120 120 120 0.1UF 0.1UF
82 82 82 82 82 82 82 82 0.1UF 0.1UF 82 82 82 82 82 82 82 82 0.1UF 0.1UF 5% 5% 5% 5% 5% 5% 5% 5% 20% 20%
5% 5% 5% 5% 5% 5% 5% 5% 20%
10V
20%
10V
5% 5% 5% 5% 5% 5% 5% 5% 20%
10V
20%
10V 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2 10V
CERM 2 10V
CERM
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2 CERM 2 CERM 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2 CERM 2 CERM MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF
SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF 402 402
1 2 3 4 1 2 3 4 402 402 1 2 3 4 1 2 3 4 402 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402
40 38 RAM_DQS<0>
40 38 RAM_DQ<7> 40 38 RAM_DQ<33>
40 38 RAM_DQS<1>
40 38 RAM_DQ<0> 40 38 RAM_DQ<37>
40 38 RAM_DQS<2>
RAM_DQ<3> RAM_DQ<35>
D
40 38
40 38 RAM_DQ<2>
40 38
40 38 RAM_DQ<34>
40 38
40 38
RAM_DQS<3>
RAM_DQS<4>
D
40 38 RAM_DQ<5> 40 38 RAM_DQ<32>
40 38 RAM_DQS<5>
40 38 RAM_DQ<4> 40 38 RAM_DQ<39>
40 38 RAM_DQS<6>
40 38 RAM_DQ<1> 40 38 RAM_DQ<36>
40 38 RAM_DQS<7>
40 38 RAM_DQ<6> 40 38 RAM_DQ<38>
PP1V25_RAM_VTT 45 44 7 =PP2V5_RUN_RAM
46 45 44 PP1V25_RAM_VTT 46 45 44
8 7 6 5 8 7 6 5
8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6
RAM_VTT 5RAM_VTT RAM_VTT RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT RAM_VTT RAM_VTT
RP4404 RP4404 RP4404 RP4404 RP4405 RP4405 RP4405 RP4405 1 C4401 1 C4413 RP4420 RP4420 RP4420 RP4420 RP4421 RP4421 RP4421 RP4421 1 C4406 1 C4415 RP4437 RP4437 RP4437 RP4437 RP4436 RP4436 RP4436 RP4436 1 C4409 1 C4421
150 150 150 150 150 150 150 150 0.1UF 0.1UF
82 82 82 82 82 82 82 82 0.1UF 0.1UF 82 82 82 82 82 82 82 82 0.1UF 0.1UF 5% 5% 5% 5% 5% 5% 5% 5% 20% 20%
5% 5% 5% 5% 5% 5% 5% 5% 20% 20% 5% 5% 5% 5% 5% 5% 5% 5% 20% 20% 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2 10V 2 10V
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2 10V
CERM 2 10V
CERM
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2 10V
CERM 2 10V
CERM
SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF CERM
402
CERM
402
SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF 1 2 3 4 1 2 3 4
402 402 402 402
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
40 38 RAM_A<0>
40 38 RAM_DQ<10> 40 38 RAM_DQ<43>
40 38 RAM_A<1>
40 38 RAM_DQ<13> 40 38 RAM_DQ<42>
40 38 RAM_A<2>
40 38 RAM_DQ<11> 40 38 RAM_DQ<40>
40 38 RAM_A<3>
40 38 RAM_DQ<14> 40 38 RAM_DQ<41>
40 38 RAM_A<4>
C 40 38
40 38
RAM_DQ<15>
RAM_DQ<12>
40 38
40 38
RAM_DQ<44>
RAM_DQ<45>
40 38
40 38
RAM_A<6>
RAM_A<5>
C
40 38 RAM_DQ<8> 40 38 RAM_DQ<47>
40 38 RAM_A<7>
40 38 RAM_DQ<9> 40 38 RAM_DQ<46>
8 7 6 5 8 7 6 5
RP4438 RP4438 RP4438 RP4438 RP4439 RP4439 RP4439 RP4439

150 150 150 150 150 150 150 150
5% 5% 5% 5% 5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W
SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF
1 2 3 4 1 2 3 4
45 44 7 =PP2V5_RUN_RAM
8 7 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5

RAM_VTT RAM_VTT RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT RAM_VTT RAM_VTT
RAM_VTT RAM_VTT 8 7 6 5
RP4408 RP4408 RP4408 RP4408 RP4409 RP4409 RP4409 RP4409 1 C4402 1 C4416 RP4424 RP4424 RP4424 RP4424 RP4425 RP4425 RP4425 RP4425 1 C4405 1 C4419 RP4441 RP4441 RP4441 RP4441 R4416
1 1
R4417 1 C4410 1 C4422
82 82 82 82 82 82 82 82 0.1UF 0.1UF 82 82 82 82 82 82 82 82 0.1UF 0.1UF 150 150
5% 5% 5% 5% 5% 5% 5% 5% 20% 20% 5% 5% 5% 5% 5% 5% 5% 5% 20% 20% 150 150 150 150 5% 5%
0.1UF 0.1UF
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2 10V
CERM 2 10V
CERM
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2 10V
CERM 2 10V
CERM
5% 5% 5% 5% 1/16W 1/16W
20%
10V
20%
10V
SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF 1/16W 1/16W 1/16W 1/16W MF-LF MF-LF 2 CERM 2 CERM
402 402 402 402 SM-LF SM-LF SM-LF SM-LF
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 2 402 2 402 402 402
1 2 3 4
40 38 RAM_DQ<22> 40 38 RAM_DQ<51>
RP4441_NC
40 38 RAM_DQ<18> 40 38 RAM_DQ<48>
40 38 RAM_A<8>
40 38 RAM_DQ<19> 40 38 RAM_DQ<50>
40 38 RAM_A<9>
40 38 RAM_DQ<17> 40 38 RAM_DQ<49>
40 38 RAM_A<11>
40 38 RAM_DQ<20> 40 38 RAM_DQ<52>
40 38 RAM_A<12>
RAM_DQ<16> RAM_DQ<55>
B
40 38
40 38 RAM_DQ<21>
40 38
40 38 RAM_DQ<53>
40 38 RAM_A<13>
B
40 38 RAM_DQ<23> 40 38 RAM_DQ<54>
8 7 6 5 1 1
R4420 R4421
RP4442 RP4442 RP4442 RP4442 150 150
150 150 150 150 5% 5%
1/16W 1/16W
5% 5% 5% 5% MF-LF MF-LF
1/16W 1/16W 1/16W 1/16W
SM-LF SM-LF SM-LF SM-LF 2 402 2 402
1 2 3 4
46 45 44 PP1V25_RAM_VTT 46 45 44 PP1V25_RAM_VTT 46 45 44 PP1V25_RAM_VTT

=PP2V5_RUN_RAM 7 44 45
8RAM_VTT 7RAM_VTT 6RAM_VTT RAM_VTT

5RAM_VTT 8 7RAM_VTT 6
RAM_VTT 5 RAM_VTT RAM_VTT RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT RAM_VTT RAM_VTT 1 1 1 1
RP4412 RP4412 RP4412 RP4412 RP4413 RP4413 RP4413 RP4413 1 C4403 1 C4417 RP4428 RP4428 RP4428 RP4428 RP4429 RP4429 RP4429 RP4429 1 C4404 1 C4418 R4408
120
R4409
120
R4410
150
R4411
150
1 C4411
82 82 82 82 82 82 82 82 0.1UF 0.1UF 82 82 82 82 82 82 82 82 0.1UF 0.1UF 5% 5% 5% 5% 0.1UF
5% 5% 5% 5% 5% 5% 5% 5% 20% 20% 5% 5% 5% 5% 5% 5% 5% 5% 20% 20% 1/16W 1/16W 1/16W 1/16W
20%
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 10V 10V 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 10V 10V 10V
2 CERM 2 CERM 2 CERM 2 CERM MF-LF MF-LF MF-LF MF-LF 2 CERM
SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF
1 2 3 4 1 2 3 4
402 402
1 2 3 4 1 2 3 4
402 402 2 402 2 402 2 402 2 402 402
40 38 RAM_DQ<30> 40 38 RAM_DQ<58> 40 38 RAM_CKE<0>

40 38 RAM_DQ<28> 40 38 RAM_DQ<62> 40 38 RAM_CKE<1>
40 38 RAM_DQ<31> 40 38 RAM_DQ<56> 40 38 RAM_CS_L<0>
40 38
40 38
RAM_DQ<24>
RAM_DQ<29>
40 38
40 38
RAM_DQ<59>
RAM_DQ<57>
40 38 RAM_CS_L<1>
PARALLEL TERM
A 40 38
40 38
RAM_DQ<25>
RAM_DQ<26>
40 38
40 38
RAM_DQ<63>
RAM_DQ<60>
1
R4412
4.7K
1
R4413
4.7K
1
R4414
150
1
R4415
150
SYNC_MASTER=N/A

SYNC_DATE=N/A
A
40 38 RAM_DQ<27> 40 38 RAM_DQ<61> 5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
2 402 2 402 2 402 2 402 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
D 051-6772 E
APPLE COMPUTER INC.
SCALE SHT OF
NONE 44 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
46 45 44 PP1V25_RAM_VTT
8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT RAM_VTT RAM_VTT RAM_VTT RAM_VTT RAM_VTT RAM_VTT RAM_VTT RAM_VTT RAM_VTT RAM_VTT RAM_VTT RAM_VTT
8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT RAM_VTT RAM_VTT
1
R4500 1R4501 1R4502 1R4503 1R4504 1R4505 1R4506 1R4507 1 C4508 1 C4518
82 82 82 82 82 82 82 82 0.1UF 0.1UF 120 120 120 120 120 120 120 120 0.1UF 0.1UF
5% 5% 5% 5% 5% 5% 5% 5% 20% 20% 82 82 82 82 82 82 82 82 0.1UF 0.1UF 5% 5% 5% 5% 5% 5% 5% 5% 20% 20%
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 10V 10V 5% 5% 5% 5% 5% 5% 5% 5% 20% 20% 10V 10V
2 CERM 2 CERM 10V 10V 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2 CERM 2 CERM
SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2 CERM 2 CERM MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF
1 2 3 4 1 2 3 4 402 402 SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF 402 402
1 2 3 4 1 2 3 4 402 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402
40 38 RAM_DQ<64> 40 38 RAM_DQS<8>
40 38 RAM_DQ<97>
40 38 RAM_DQ<67> 40 38 RAM_DQS<9>
40 38 RAM_DQ<103>
RAM_DQ<65> RAM_DQS<10>
D
40 38
40 38 RAM_DQ<66>
40 38
40 38
RAM_DQ<96>
RAM_DQ<98>
40 38
40 38 RAM_DQS<11> D
40 38 RAM_DQ<70> 40 38 RAM_DQS<12>
40 38 RAM_DQ<102>
40 38 RAM_DQ<71> 40 38 RAM_DQS<13>
40 38 RAM_DQ<100>
40 38 RAM_DQ<68> 40 38 RAM_DQS<14>
40 38 RAM_DQ<99>
40 38 RAM_DQ<69> 40 38 RAM_DQS<15>
40 38 RAM_DQ<101>
46 45 44 PP1V25_RAM_VTT
46 45 44 PP1V25_RAM_VTT
8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT RAM_VTT RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT RAM_VTT RAM_VTT
82 82 82 82 82 82 82 82 0.1UF 0.1UF
5% 5% 5% 5% 5% 5% 5% 5% 20% 20% 82 82 82 82 82 82 82 82 0.1UF 0.1UF
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2 10V
CERM 2 10V
CERM
5% 5% 5% 5% 5% 5% 5% 5% 20%
10V
20%
10V
SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2 CERM 2 CERM
402 402 SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF
1 2 3 4 1 2 3 4 402 402
1 2 3 4 1 2 3 4
40 38 RAM_DQ<79>
40 38 RAM_DQ<111>
40 38 RAM_DQ<72>
40 38 RAM_DQ<105>
40 38 RAM_DQ<74>
40 38 RAM_DQ<106>
40 38 RAM_DQ<75>
40 38 RAM_DQ<104>
C 40 38
40 38
RAM_DQ<77>
RAM_DQ<78>
40 38
40 38
RAM_DQ<109>
RAM_DQ<108>
C
40 38 RAM_DQ<76>
40 38 RAM_DQ<110>
40 38 RAM_DQ<73>
40 38 RAM_DQ<107>
1 C4509 1 C4519
0.1UF 0.1UF
20% 20%
10V 10V
2 CERM 2 CERM
402 402
46 45 44 PP1V25_RAM_VTT
46 45 44 PP1V25_RAM_VTT
46 45 44 PP1V25_RAM_VTT
44 7 =PP2V5_RUN_RAM
8 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT RAM_VTT RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT RAM_VTT RAM_VTT
RP4508 RP4508 RP4508 RP4508 RP4509 RP4509 RP4509 RP4509 1 C4502 1 C4514 RP4524 RP4524 RP4524 RP4524 RP4525 RP4525 RP4525 RP4525 1 C4505 1 C4516 RAM_VTT RAM_VTT
82 82 82 82 82 82 82 82 0.1UF 0.1UF 7 6 7 6 7 6 7 6
5% 5% 5% 5% 5% 5% 5% 5% 20% 20% 82 82 82 82 82 82 82 82 0.1UF 0.1UF 1
R4508 1
R4509
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2 10V
CERM 2 10V
CERM
5% 5% 5% 5% 5% 5% 5% 5% 20%
10V
20%
10V RP4530 RP4530 RP4531 RP4531 RP4532 RP4532 RP4533 RP4533
402 402
1/16W
SM-LF
1/16W
SM-LF
1/16W
SM-LF
1/16W
SM-LF
1/16W
SM-LF
1/16W
SM-LF
1/16W
SM-LF
1/16W
SM-LF
2 CERM 2 CERM 150 150 150 150 150 150 150 150 120 120
1 2 3 4 1 2 3 4 402 402 5% 5%
1 2 3 4 1 2 3 4 5% 5% 5% 5% 5% 5% 5% 5% 1/16W 1/16W
40 38 RAM_DQ<84> 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W MF-LF MF-LF
RAM_DQ<117> SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF
40 38 RAM_DQ<87>
40 38
2 3 2 3 2 3 2 3 2 402 2 402
40 38 RAM_DQ<112>
40 38 RAM_DQ<85>
40 38 RAM_DQ<113> 40 38 RAM_RAS_L
40 38 RAM_DQ<82>
40 38 RAM_DQ<114> 40 38 RAM_BA<0>
40 38 RAM_DQ<86>
40 38 RAM_DQ<118> 40 38 RAM_CAS_L
RAM_DQ<80>
B
40 38
40 38 RAM_DQ<83>
40 38
40 38
RAM_DQ<116>
RAM_DQ<115>
40 38
40 38
RAM_WE_L
RAM_CS_L<9>
B
40 38 RAM_DQ<81>
40 38 RAM_DQ<119> 40 38 RAM_CS_L<8>
40 38 RAM_BA<1>
40 38 RAM_A<10>
40 38 RAM_CKE<4>
40 38 RAM_CKE<5>
1 4 1 4 1 4 1 4
RP4530
150
RP4530
150
RP4531
150
RP4531
150
RP4532
150
RP4532
150
RP4533
150
RP4533
150
1
R4510 1R4511
5% 5% 5% 5% 5% 5% 5% 5% 4.7K 4.7K
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 5% 5%
SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF 1/16W 1/16W
MF-LF MF-LF
8 5 8 5 8 5 8 5 2 402 2 402
46 45 44 PP1V25_RAM_VTT
46 45 44 PP1V25_RAM_VTT
8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT RAM_VTT RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT RAM_VTT RAM_VTT
82 82 82 82 82 82 82 82 0.1UF 0.1UF
5% 5% 5% 5% 5% 5% 5% 5% 20% 20% 82 82 82 82 82 82 82 82 0.1UF 0.1UF
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 10V 10V 5% 5% 5% 5% 5% 5% 5% 5% 20% 20%
2 CERM 2 CERM
402 402
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2 10V
CERM 2 10V
CERM
1 2 3 4 1 2 3 4 SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF
402 402
1 2 3 4 1 2 3 4
40 38 RAM_DQ<95>
40 38 RAM_DQ<126>
40 38 RAM_DQ<94>
40 38 RAM_DQ<123>
40 38 RAM_DQ<92>
40 38 RAM_DQ<127>
40 38
40 38
RAM_DQ<88>
RAM_DQ<93>
40 38 RAM_DQ<122> PARALLEL TERM
40 38 RAM_DQ<125>
A 40 38
40 38
RAM_DQ<89>
RAM_DQ<91>
40 38
40 38
RAM_DQ<124>
RAM_DQ<121>
SYNC_MASTER=N/A

SYNC_DATE=N/A
A
40 38 RAM_DQ<90>
40 38 RAM_DQ<120>
D 051-6772 E
APPLE COMPUTER INC.
SCALE SHT OF
NONE 45 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
ONLY STUFF ONE VTT VREG
40 37 26 7 =PP2V5_PWRON_RAM
NOSTUFF
1
C4610
10UF
1
R4660
20%
6.3V
20.5K
2 CERM 1%
1206 1/16W
MF-LF
2 402
D 1
NOSTUFF
R4661
D
20.5K
1%
1/16W
MF-LF
2 402
NOSTUFF
RT9173A
1 U4660 5
VIN VOUT
TO-252
NOSTUFF
REFEN 4
1
C4611 NOSTUFF
10UF
20%
6.3V GND
VCNTRL
(TAB)
1 C4660
2 CERM 1UF
1206 2 3 6 10%
2 6.3V
CERM
7 =PP3V3_PWRON_RAM 402
NOSTUFF
1
C4661
10UF
20%
6.3V
PP1V25_RAM_VTT 44 45
2 CERM MIN_LINE_WIDTH=0.6MM
VOLTAGE=1.25V
C C
NOSTUFF NOSTUFF
1
1
C4601 R4603
PHILIPS 0.1UF 10K
5%
10%
353S0603 1/16W
2
16V
2 X7R MF-LF
402
VDD 603 2
U4600_REFOUT 5 REFOUT VTT 1

RAM_VTT
1
C4606 SHTDWN 4 VR4600_SHTDWN 1
C4609 1
C4608 1
C4600 1
C4602
0.1UF
10%
220UF 10UF
20%
10UF
20%
10UF
20%
16V
20% 6.3V 6.3V 6.3V
2 2 2V 2 2 2
X7R
603
VSS VSS TANT CERM
1206
CERM
1206
CERM
1206
7343
3
U4600
NE57811
SPAK-5
RAM_VTT
PLACE 10UF CAPS NEAR DIMMS
NOTE: U4700 PIN 4 IS LOW ACTIVE.
NOSTUFF
R4610
0
3 TURN_ON_VTT 1 2
5%
1/16W
MF-LF
B 402
3 B
D
Q4600
2N7002
1 SOT23-LF
59 50 22 11 10 9 8 6 SYS_SLEEP G S
MEM TERM VREGS

A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
D 051-6772 E
APPLE COMPUTER INC.
SCALE SHT OF
NONE 46 102
8 5 4 3 2 1
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AGP_CBE<1..0> AGP_AD_0 AGP_DATA AGP_DATA

60 37 28 7 =PP1V5_PWRON_NB_AVDD R4800
49 48
AGP_CBE<3..2>
I46
AGP_AD_1 AGP_DATA AGP_DATA
1
2.2 2 PP1V5_PWRON_AGP_NB_AVDD
=PP1V5_AGP 7 48 49 50
49 48 I48
VOLTAGE=1.5V MIN_LINE_WIDTH=0.6MM
5% MIN_NECK_WIDTH=0.25MM 49 48 AGP_SB_STBF AGP_SB_STBS AGP_STROBE AGP_STROBE AGP_SB_STB I49
1/10W
MF-LF 1C4811 C4816 1 49 48 AGP_SB_STBS AGP_SB_STBS AGP_STROBE AGP_STROBE AGP_SB_STB
AG10
AC10
603 I50
1UF 0.1UF
AE6
AG4
AE2
AE7
AB4
Y11
W10
10% 20% 49 48 AGP_AD_STBF<0> AGP_AD_STB_0 AGP_STROBE AGP_STROBE AGP_AD_STB0 I51
W2
W6
V9
2 6.3V
CERM
10V
2 CERM 49 48 AGP_AD_STBS<0> AGP_AD_STB_0 AGP_STROBE AGP_STROBE AGP_AD_STB0 I52
402 402 AGP VDD_AGP 49 48 AGP_AD_STBF<1> AGP_AD_STB_1 AGP_STROBE AGP_STROBE AGP_AD_STB1
REFCLK_AVDD I53
OMIT
49 48 AGP_AD_STBS<1> AGP_AD_STB_1 AGP_STROBE AGP_STROBE AGP_AD_STB1 I54
U3 D
D 49 48 AGP_CBE<0> AG8 AGP_CBE0
AF8 AGP_CBE1
U3LITE
V1.0-300MM
AGP_AD0 AB11
AGP_AD1 AA11
AGP_AD<0>
AGP_AD<1>
48 49
48 49
49 48 AGP_DBI_LO AGP_AD_1 AGP_DATA AGP_DATA I55
AGP_CBE<1> PBGA AGP_DBI_HI AGP_AD_1 AGP_DATA AGP_DATA
AGP_AD2 AG11
49 48 49 48 I56
(SYM 4 OF 7)
AGP_AD<2> 48 49
49 48 AGP_DBI_LO AA6 AGP_DBI_LO AGP_AD3 AH12 AGP_AD<3> 48 49

AGP_AD<15..0> AGP_AD_0 AGP_DATA AGP_DATA
AGP_AD4 AC11
49 48 I57
AGP_AD<4>
AGP_AD_STBF<0> AE8 AGP_AD_STBF0 48 49
AGP_AD<31..16> AGP_AD_1 AGP_DATA AGP_DATA
49 48
AGP_AD5 AD11 AGP_AD<5>
49 48 I58
AGP_AD_STBS<0> AD8 AGP_AD_STBS0 48 49
49 48
AGP_AD6 AE11 AGP_AD<6> 48 49
AF11 49 48 AGP_SBA_L<7..0> AGP_SBA AGP_DATA AGP_DATA I59
AGP_AD7 AGP_AD<7> 48 49
AGP_AD8 AH8 AGP_AD<8> 48 49
AGP_AD9 AH9 AGP_AD<9> 48 49
DBIHI AND DBILO AGP AGP_AD10 AH10 AGP_AD<10> 48 49 DBI_HI IS NOT A STROBE BUT SHARES THE SAME TOPOLOGY AS A STROBE
GROUPS WITH STROBE1 INTERFACE AGP_AD11 AH11 AGP_AD<11> 48 49
FOR CONSTRAINTS AGP_AD12 AG9 AGP_AD<12> 48 49
AGP_AD13 AF9 AGP_AD<13> 48 49
AGP_AD14 AE9 AGP_AD<14> 48 49
AGP_AD15 AD9 AGP_AD<15> 48 49
Y8 AGP_CBE2 AGP_AD16 Y4 AGP_AD<16> 48 49

AGP_CBE<2>
49 48
AGP_CBE<3> AA5 AGP_CBE3 AGP_AD17 Y3 AGP_AD<17> 48 49 LEVEL SHIFTER FOR U3LITE

AGP_AD18 Y6
49 48
AGP_AD<18> 48 49
AA4 AGP_DBI_HI Y5 AGP BUSY AND STOP ARE NOT USED IN ALL DESIGNS
49 48 AGP_DBI_HI AGP_AD19 AGP_AD<19> 48 49
AGP_AD20 AA1 AGP_AD<20>

AGP_AD_STBF<1> AA3 AGP_AD_STBF1 48 49
49 48
AGP_AD21 Y2 AGP_AD<21> 48 49 59 56 50 48 7 =PP3V3_AGP
AGP_AD_STBS<1> AA2 AGP_AD_STBS1
49 48
AGP_AD22 Y1 AGP_AD<22> 48 49 50 49 48 7 =PP1V5_AGP
AGP_AD23 Y7 AGP_AD<23> 48 49
AGP_AD24 V5 AGP_AD<24> 48 49
AGP_AD25 V6 AGP_AD<25> 48 49 AGP_BUSYSTOP

C AGP_AD26
AGP_AD27
V4
V3
AGP_AD<26>
AGP_AD<27>
48 49
48 49
R4811
1
10K
1
R4807
10K
C
AGP_AD28 V8 AGP_AD<28> 48 49
1
R4812 5%
1/16W
5%
1/16W
V7 10K MF-LF MF-LF
AGP_AD29 AGP_AD<29> 48 49 5% 2 402 2 402
W1 1/16W
AGP_AD30 AGP_AD<30> 48 49 MF-LF NB_AGP_BUSY_L 48
AA7 2 402
AGP_BUSY_L_F
AGP_AD31 AGP_AD<31> 48 49
6 3
AGP_BUSYSTOP AGP_BUSYSTOP
AD1 AGP_SB_STBF AGP_SBA0 AG2 AGP_SBA_L<0> 48 49 D
Q4801 D
Q4801
AGP_SB_STBF
AGP_SBA1 AF3
49 48
AE1 AGP_SB_STBS AGP_SBA_L<1> 48 49 2N7002DW 2N7002DW
AGP_SB_STBS SOT-363 SOT-363
AGP_SBA2 AH1
49 48
AGP_SBA_L<2> 48 49 AGP_BUSY_L 2 G S 5 G S
AGP_SBA3 AG3 AGP_SBA_L<3> 48 49
AD2 1 4
AGP_SBA4 AGP_SBA_L<4> 48 49
AGP_SBA5 AF2 AGP_SBA_L<5> 48 49
AGP_SBA6 AG1 AGP_SBA_L<6> 48 49
AGP_SBA7 AF1 AGP_SBA_L<7> 48 49
49 AGP_PAR AH7 AGP_PAR

AC4 AGP_ST0 AGP_REFCLK AH2 AGP_CLK66M_NB 27
49 AGP_ST<0> 59 56 50 48 7 =PP3V3_AGP
49 AGP_ST<1> AC1 AGP_ST1
49 AGP_ST<2> AB1 AGP_ST2 AGP_BUSY* AC8 NB_AGP_BUSY_L 48 59 56 50 48 7 =PP3V3_AGP
AGP_STP_AGP* AD4 NB_STOP_AGP_L
49 AGP_RBF AC6 AGP_RBF
48
49 AGP_WBF AD6 AGP_WBF

50 49 48 7 =PP1V5_AGP AGP_BUSYSTOP R4810
1
AGP_TRDY AH5 R4808

1 10K
49 AGP_TRDY 5%
AG6 PVTREF RESISTOR 1
R4809 10K 1/16W
AGP_IRDY AGP_IRDY 5% MF-LF
R4801
49
AGP_GNT AC3 10K 1/16W 2 402

AGP_GNT 5% MF-LF
49
AGP_FRAME AH6 1
182 2 1/16W 2 402 STOP_AGP_L
AGP_FRAME
B
49
49 AGP_DEVSEL AF6 AGP_DEVSEL 1%

1/16W
MF-LF
2 402
STOP_AGP_L_F
3 AGP_BUSYSTOP
B
AGP_PVTREF1 AG5 AGP_PVTREF1 MF-LF AGP_BUSYSTOP
AGP_PVTREF2 AF5 AGP_PVTREF2
402 R4813 3
AGP_BUSYSTOP
D Q4803
1K 2N7002
49 AGP_REQ AB9 AGP_REQ 48 NB_STOP_AGP_L 1 2 STOP_AGP_L_R 1 Q4802 1 G S
SOT23-LF
49 AGP_STOP AH4 AGP_STOP AGP_VREFCG AC5 TP_VREF_CG 6 5% 2N3904LF
1/16W SOT23
AGP_VREFGC AA9 AGP_VREF_GC 49 MF-LF 2 2
402
AGP_TYPEDET_L AC9 AGP_TYPEDET
AGP_MB_AGP8X_DET AA8
49
AB8 AGP_GC_AGP8X_DET TP_AGP_MB_AGP8X_DET_L 6
49 NB_AGP_GCDET_L
AGP_REFCLK_AVSS
C4817
AE5
1
0.01UF
20%
2 16V
CERM
402
=PP1V5_AGP 7 48 49 50
U3LITE AGP
A 1 C4800 1 C4801 1 C4802 1 C4803 1 C4804 1 C4805 1 C4806 1 C4807 1 C4808 1 C4810 1 C4812 1 C4813 1 C4814 1 C4815
SYNC_MASTER=N/A

SYNC_DATE=N/A
A
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
10V THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
2 CERM 2 10V
CERM
10V
2 CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
10V
2 CERM 2 10V
CERM
10V
2 CERM 2 10V
CERM
10V
2 CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
402 402 402 402 402 402 402 402 402 402 402 402 402 402 AGREES TO THE FOLLOWING
D 051-6772 E
APPLE COMPUTER INC.
SCALE
NONE 48 102
SHT OF
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TABLE_5_HEAD
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION 50 49 48 7 =PP1V5_AGP

TABLE_5_ITEM
338S0231 1 IC,RV351LE, GRAPHICS CTLR U4900

1 C4900 1 C4901 1 C4902 1 C4903 1 C4904 1 C4905
1UF 1UF 0.01UF 0.01UF 0.01UF 0.01UF
10% 10% 20% 20% 20% 20%
6.3V 6.3V 16V 16V 16V 16V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402
U3LITE AGP I/O REFERENCE
(PLACE CLOSE TO GPU AGP BALL)
AB30
AC23
AC27
AF27
AA23
AE30
AA24
=PP1V5_AGP
D
U27
V23
V24
W30
Y27
M23
M24
N30
P23
T23
50 49 48 7
P27
T24
T30
J30
GPU_AGP_VREF 49
R4914
1
VDDP
1%
3.32K 1 C4910
1/16W 0.01UF
MF-LF 20%
16V
2 402 OMIT 2 CERM
402
AGP_VREF_GC 48
27 AGP_CLK66M_GPU AG30 PCICLK U4900 AGPREF M26 PLACE C4910 CLOSE TO BALL M26
VOLTAGE=0.35V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM AGP_AD<0> H29 AD0
RV351 CBE0* N29 AGP_CBE<0>
R4940 1 C4940 48 48
1
AGP_AD<1> H28 AD1 BGA CBE1* U28 AGP_CBE<1>
1.02K 0.01UF
48
J29 (1 OF 5)
48
1% 20% 48 AGP_AD<2> AD2

1/16W
MF-LF 2 16V
CERM 48 AGP_AD<3> J28 AD3 DBI_LO AB26 AGP_DBI_LO 48
2 402 402
48 AGP_AD<4> K29 AD4
48 AGP_AD<5> K28 AD5 AD_STBF_0 M28 AGP_AD_STBF<0> 48
48 AGP_AD<6> L29 AD6 AD_STBS_0* M29 AGP_AD_STBS<0> 48
48 AGP_AD<7> L28 AD7

48 AGP_AD<8>
AGP_AD<9>
N28
P29
AD8 AGP
48 AD9
48 AGP_AD<10> P28 AD10
48 AGP_AD<11> R29 AD11
48 AGP_AD<12> R28 AD12
48 AGP_AD<13> T29 AD13
48 AGP_AD<14> T28 AD14
AGP_AD<15> U29 AD15
GPU AGP I/O REFERENCE 48
(PLACE CLOSE TO GPU AGP BALLS) 48 AGP_AD<16> N25 AD16 CBE2* P26 AGP_CBE<2> 48
C 48 AGP_AD<17>
AGP_AD<18>
R26
P25
AD17 CBE3* U26 AGP_CBE<3> 48 C
50 49 48 7 =PP1V5_AGP
48 AD18
48 AGP_AD<19> R27 AD19 DBI_HI AB25 AGP_DBI_HI 48
AGP 3.0 R25
48 AGP_AD<20> AD20
0.233 * VDDP
R4906
1
0.35V
48 AGP_AD<21> T25 AD21 AD_STBF_1 V25 AGP_AD_STBF<1> 48
3.32K 48 AGP_AD<22> T26 AD22 AD_STBS_1* V26 AGP_AD_STBS<1> 48

1% U25
1/16W 48 AGP_AD<23> AD23
MF-LF V27
2 402 48 AGP_AD<24> AD24
48 AGP_AD<25> W26 AD25
AGP_AD<26> W25 AD26
GPU_AGP_VREF 49
48
VOLTAGE=0.35V 48 AGP_AD<27> Y26 AD27

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM AGP_AD<28> Y25 AD28
R4907 1 C4957
48
1
AGP_AD<29> AA26 AD29
1.02K 0.01UF
48
AGP_AD<30> AA25
1%
1/16W 20% 48 AD30
MF-LF 2 16V
CERM 48 AGP_AD<31> AA27 AD31
2 402 402
48 AGP_SBA_L<0> AD28 SBA0 SB_STBF AB29 AGP_SB_STBF 48
48 AGP_SBA_L<1> AD29 SBA1 SB_STBS* AB28 AGP_SB_STBS 48
48 AGP_SBA_L<2> AC28 SBA2

48 AGP_SBA_L<3> AC29 SBA3 PP3V3_GPU 50 56 58 59
48 AGP_SBA_L<4> AA28 SBA4
SERIES R NEEDED TO PREVENT GPU GLITCH 48 AGP_SBA_L<5> AA29 SBA5
WE CAN LOWER OR REMOVE THIS IF WE MEET GPU
POWER SEQUENCING REQUIREMENTS 48 AGP_SBA_L<6> Y28 SBA6 R4908
1
Y29
10K
R4912 48 AGP_SBA_L<7> SBA7 5%
1/16W
330 MF-LF
8 GPU_RESET_L 1 2 ATI_PCIRST_L AG28 RST* PAR M25 AGP_PAR 48
2 402
5%
B 1/16W
MF-LF
402
48
48
AGP_ST<0>
AGP_ST<1>
AF29
AD27
ST0
ST1
INTA* AE26
R4910
AGP_INT_L 25
B
AE28 M27
47
48 AGP_ST<2> ST2 AGPTEST* GPU_AGPTEST_L 1 2 =PP1V5_AGP 7 48 49 50
1%
48 AGP_REQ AF28 REQ* AGP8X_DET* AC25 1/16W
MF-LF
48 AGP_GNT AD26 GNT* 402
N26 AGP VERSION SELECT
48 AGP_STOP STOP*
V29 (LOW = AGP V3.X)
48 AGP_DEVSEL DEVSEL*
V28 (HIGH = AGP V2.X)
48 AGP_TRDY TRDY*
48 AGP_IRDY W29 IRDY*
48 AGP_FRAME W28 FRAME*
48 AGP_WBF AC26 WBF*
48 AGP_RBF AE29 RBF*
U3LITE SIGNALS
48 NB_AGP_GCDET_L
48 AGP_TYPEDET_L
1
R4913 1R4909 GPU AGP
0 10K
5% 5%
A 1/16W
MF-LF
2 402
1/16W
MF-LF
2 402
SYNC_MASTER=N/A

SYNC_DATE=N/A
A
APPLE COMPUTER INC.

D 051-6772 E
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GPU VCORE VREG NOTE:

SET OUTPUT = 1.20V +/- 5% FOR RV351LE
IRU3037ACS VREF = 0.8 VDC
VOUT=VREF*(R5003+R5005)/R5005 = 1.199 VDC
59 7 =PP12V_AGP 59 56 50 48 7 =PP3V3_AGP PEAK CURRENT OF TOTAL RAILS
5A WITH RV351LE
=PP5V_AGP
59 7
1
R5000 1 C5016
D 5%
4.7 1UF
20%
1 C5001 1 C5010
10UF 10UF
1
C5002 1
C5003 D
1/8W 2 25V 1800UF 1800UF
C5004 1 MF-LF
CERM
805
20%
6.3V
20%
6.3V 20%
2 6.3V
20%
2 6.3V =PP3V3_AGP
1UF 2 805 2 CERM 2 CERM
ELEC ELEC
7 48 50 56 59
20% 1206 1206 TH-KZJ TH-KZJ PP3V3_RUN
25V 6 7 10 11 18 22 34
CERM 2
6 U5000_VC 2
D 4 DEVELOPMENT
805
R5002 Q5001 D5000
SMB
1
R5019
2 6 0 NTD60N02R
VCC VC
1 2 6 Q5001_GATE 1
CASE369
10BQ040PBF 330
G 1 5%
U5000 5%
1/8W S3
1/16W
MF-LF
IRU3037ACS MF-LF PPVCORE_GPU
SOI 805 L5001 VOLTAGE=1.2V
7 22 51
2 402
HD 5 6 U5000_GATE_H 1.53UH MIN_NECK_WIDTH=0.25MM LED_GPU_CORE_P

8 1 2
6 U5000_SS SS 6 Q5002_DRAIN
LD 3 6 U5000_GATE_L TH
1
DEVELOPMENT
NOSTUFF
6 U5000_COMP 7 COMP 1
R5004 1 C5007 R5003
1
R5020 DEVELOPMENT
LED5000
FB 1 6 U5000_FEEDBACK 0.51 3300PF 4.99K 3 GREEN
3 5% 1% 0 LM339A
2.0X1.25A
D
Q5000
1
R5001 GND D 4
1/4W
FF
10%
2 50V
CERM
1/16W
MF-LF
1 2 GPU_CORE_FOR_LED 10
V+ SOI
2
61.9K 5%
2N7002 1% 4 Q5002 2 1206 603 2 402
C5008 1/16W
U1001 13 LED_GPU_CORE_N
46 22 11 10 9 8 6 SYS_SLEEP
1 G S
SOT23-LF 1/16W
MF-LF 1 NTD60N02R R5004_P2
1 1
C5009 MF-LF
402 GND
59 50 1 C5014 1 C5013 1 C5006 CASE369 10UF 1800UF 1V1_REF 11
2 402 G 20% 20%
34 22 10
2 0.1UF R5001_2 20PF 220PF S3 2 6.3V 2 6.3V 12
20%
2 16V
5%
2 50V
5%
2 25V 1 C5005
1 C5012 1
R5005 CERM
805
ELEC
TH-KZJ
CERM CERM CERM 0.1UF 10K
603 1 C5023 603 402 2200PF 20%
50V 1%
5% 2 CERM 1/16W
0.0018UF 2 50V MF-LF
10% CERM 1206
50V
2 CERM
603 2 402
402
C U5000_FEEDBACK
C
GPU 1.8V VREG
GPU 2.5V A2VDD GPU 3.3V I/O
CRITICAL
59 56 50 48 7 =PP3V3_AGP
PP1V8_GPU =PP1V8_GPU PP12V_RUN
U5080 VOLTAGE=1.8V
51 52 58
MIC39102 MIN_LINE_WIDTH=0.6MM
59 56 50 48 7 =PP3V3_AGP SOP-8
MAKE_BASE=TRUE
2
IN OUT 3 U5070
MM1572FN
1
R5050
Q5051
1
EN ADJ 4 U5080_ADJ 1 SOT-25A
PP2V5_GPU_A2VDD 51 58 SI3446DV
R5081 VOLTAGE=2.5V 3.3K TSOP
1 C5080 1
R5080 GND 453
1
C5083 59 56 50 48 7 =PP3V3_AGP MIN_LINE_WIDTH=0.5MM
5%
1
10UF 3.3K 5 6 7 8 1% 330UF 1 VIN VOUT 5 1/16W
MF-LF
2
20%
2 6.3V
CERM
5%
1/16W
1/16W
MF-LF
20%
2 6.3V 2 402
R5051 5
ELEC 3 4 U5070_NOISE 470
1206
2
MF-LF
402
2
402
SM-1 1 C5070 1R5070 CONT NOISE
Q5050_D 1 2 Q5051_G 3 6
1UF 10K GND C5071 1 1 C5072 5%
20% 5% 2 1/16W 4
10V
2 CERM 1/16W 0.01UF 10UF 3 MF-LF NOSTUFF
1
R5082 805 MF-LF
2 402
20%
16V
CERM 2
20%
6.3V
2 CERM D Q5050
402
1 C5050 1
R5052
U5080_EN 1K 402 805 2N7002 0.1UF
1% 20% 47K
1/16W SOT23-LF 10V 5%
3 MF-LF U5070_CONT 59 50 46 22 11 10 9 8 6 SYS_SLEEP 1 G S 2 CERM 1/16W
2 402 402 MF-LF
D Q5080 2 2 402 PP3V3_GPU 49 56 58 59
2N7002 3 VOLTAGE=3.3V
SOT23-LF MIN_LINE_WIDTH=0.5MM
59 50 46 22 11 10 9 8 6 SYS_SLEEP 1 G S D
Q5070 MIN_NECK_WIDTH=0.25MM
2N7002
SOT23-LF
B
2
59 50 46 22 11 10 9 8 6 SYS_SLEEP 1 G S NOSTUFF
R5053
1
B
2
0
5%
1/8W
MF-LF
GPU 1.80V TPVDD 2 805

=PP3V3_AGP 7
GPU 1.50V VDDC_CT

48 50 56 59
THIS RAIL SHOULD BE THE LAST UP AND THE FIRST DOWN =PP3V3_AGP 7 48 50 56 59 PP1V8_GPU_TPVDD 58
VOLTAGE=1.8V
59 56 50 48 7 =PP3V3_AGP MIN_NECK_WIDTH=0.25MM
D5090
SMB
10BQ040PBF
NOSTUFF R50621 C5060 1 CRITICAL
=PP1V5_AGP R5092 1
3.3K 4.7UF R5060
1
49 48 7
1
0 2
PP1V5_GPU_VDDC_CT 51 5% 20%
6.3V
U5060 1 C5061 100K
VOLTAGE=1.5V 1/16W CERM 2 FAN2558 0.001UF 1%
59 56 50 48 7 =PP3V3_AGP MIN_LINE_WIDTH=0.5MM MF-LF 805 SOT23-6 10% 1/16W
5% MIN_NECK_WIDTH=0.25MM 402 2 MF-LF
1/8W 1 VIN VOUT 6 2 50V
CERM 2 402
MF-LF
805 4 PG 402 1 C5062
C5090 1 1uF
1
R5097 4.7UF
CRITICAL 1
R5090
U5060_EN 3 EN ADJ 5 U5060_ADJ 10%
3.3K 2 6.3V
5% 20%
6.3V U5090 1 C5091 100K 3
GND
R5061
1 CERM
402
1/16W CERM 2 FAN2558 0.001UF 1%
MF-LF 805 1/16W 2 48.7K
2 402 1 VIN
SOT23-6
VOUT 6
10%
50V
2 CERM
MF-LF
2 402
D Q5060 1%
1/16W
2N7002 MF-LF
4 PG 402 1 C5092 SYS_SLEEP 1 G S
SOT23-LF
2 402
1uF 59 50 46 22 11 10 9 8 6
U5090_EN 3 EN
GND
ADJ 5 FAN2558_ADJ 10%
6.3V
2 CERM 2
GRAPHICS VREGS
1
R5091 402
A 3 2 56.2K
1%
VOUT = 0.59V * [1 + R5060 / R5061]
SYNC_MASTER=N/A SYNC_DATE=N/A
A
D
Q5090 1/16W
MF-LF
VOUT = 1.80V NOTICE OF PROPRIETARY PROPERTY
2N7002 2 402
1 SOT23-LF THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
59 50 46 22 11 10 9 8 6 SYS_SLEEP G S PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
2 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
VOUT = 0.59V * [1 + R5090 / R5091] POWER SEQUENCING FOR RV351: =PP3V3_AGP > PP2V5_GPU > PPVCORE_GPU > VDDC_CT II NOT TO REPRODUCE OR COPY IT
VOUT = 1.50V PP2V5_GPU_A2VDD > PP1V8_GPU III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
HOWEVER IDEALLY ALL POWER RAILS SHOULD RAMP TOGETHER
POWER DOWN SEQUENCE SHOULD BE IN REVERSE ORDER APPLE COMPUTER INC.

D 051-6772 E
SCALE SHT OF
NONE 50 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
51 50 22 7 PPVCORE_GPU
AD15
AC13
AC15
AC17
AD13
NOSTUFF
V19
W18
M12
M14
N12
N17
N18
P14
U14
U17
U12
W14
W17
M13
M18
M19
N14
P12
P13
P17
P19
U18
V14
N13
W19
M17
N19
P18
U13
W12
W13
U19
V12
V13
V17
V18
1 C5100
10UF
20%
VDDC 6.3V
2 CERM
AJ1 805
OMIT
AG9
U4900 AG5
RV351 AG27
AG22 1 C5101 1 C5102 1 C5103 1 C5104
D BGA
(2 OF 5)
AG18 1UF
10%
1UF
10%
1UF
10%
1UF
10%
D
AG15 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
AG11 402 402 402 402
AF20
AF15
AE19
AE16
CORE POWER AD30
1 C5105 1 C5106 1 C5107 1 C5108 1 C5109 1 C5110 1 C5111 1 C5112
0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF
AD25 20% 20% 20% 20% 20% 20% 20% 20%
2 16V
CERM 2 16V
CERM 2 16V
CERM 2 16V
CERM 2 16V
CERM 2 16V
CERM 2 16V
CERM 2 16V
CERM
AD16
402 402 402 402 402 402 402 402
AD12
AC4
AC18
AC16
AC14 1 C5113 1 C5114 1 C5115 1 C5116 1 C5117 1 C5118 1 C5119 1 C5120
AB8 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF
20% 20% 20% 20% 20% 20% 20% 20%
AB7 16V 16V 16V 16V 16V 16V 16V 16V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
AB4 402 402 402 402 402 402 402 402
AB27
AB24
L5130 AB23
58 52 50 =PP1V8_GPU 1.8UH AB1
1 2 PP1V8_GPU_PVDD AA30
0805
VOLTAGE=1.8V NOSTUFF A29
MIN_NECK_WIDTH=0.25MM C5130 1 C5131 A22
10UF 1UF
XW5130 20%
6.3V
10%
6.3V AK28
AD18
SM 2 CERM 2 CERM PVDD 25MA MAX
C 1 2 GND_GPU_PVSS
VOLTAGE=0V
805 402 AJ28 PVSS
Y4
W8 C
MIN_NECK_WIDTH=0.25MM W7
W27
AC11 W24
50 PP1V5_GPU_VDDC_CT
AC20 W23
H11 W15
1 C5140 1 C5141 1 C5142 1 C5143 H20 V30
1UF 1UF 1UF 1UF L23 VDD15 V16
10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V P8 U8
2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 Y23 U4
Y8 U23
U16
VSS U15
T27
58 PP1V8_GPU_TXVDDR AE15
T19
AF21 VDDL0 T18
AJ20
T17
L5150 T16
58 50 PP2V5_GPU_A2VDD FERR-220-OHM T14
1 2 PP2V5_GPU_VDDL1 AE17 T13
0805
VOLTAGE=2.5V AE20 VDDL1 T1
MIN_NECK_WIDTH=0.25MM R8
R7
R30
51 50 22 7 PPVCORE_GPU M15 R24
R19 R23
B T12
W16
VDDCI
R18
R17
B
R15
R14
R13
R12
P4
P16
P15
N27
N24
N23
N15
M8
M7
M30
M16
L4
K8
K7
K30
K27
K23
K1
H9 GPU CORE POWER
A H8
H4
SYNC_MASTER=N/A

SYNC_DATE=N/A
A
H27
H23 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
H21 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
H18 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
VSS II NOT TO REPRODUCE OR COPY IT

A10
A16
C3
D6
H14
K24
N16
R16
T15
V15
A2
AC12
AE27
AJ19
AJ30
AK2
AK25
AK29
C1
C28
C30
D10
D12
D15
D18
D21
D24
D25
D27
D4
D9
E4
F27
G12
G16
G18
G21
G24
G9
H12
H16
APPLE COMPUTER INC.

D 051-6772 E
SCALE SHT OF
NONE 51 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
55 54 52 7 PP2V5_GPU
1 C5200 1 C5201 1 C5202 1 C5203 1 C5204 1 C5205 1 C5206 1 C5207 1 C5208 1 C5209 1 C5210 1 C5211 1 C5212
10UF 10UF 1UF 1UF 1UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF
20% 20% 10% 10% 10% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 16V 16V 16V 16V 16V 16V 16V 16V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
805 805 402 402 402 402 402 402 402 402 402 402 402
L5230
=PP1V8_GPU 1.8UH
D
58 52 51 50
1 2
10MA MAX
PP1V8_GPU_MPVDD D
G13
E27
G10
G15
G19
G22
G27
H10
H13
H19
J24
L27
H15
H22
J23
VOLTAGE=1.8V NOSTUFF
A15
A21
D11
H17
A28
AA1
AA4
AA7
AA8
AD4
B30
D13
D14
D17
D19
D20
D23
D26
F18
G7
L8
N8
C5231
D8
J1
J4
J8
N4
N7
R1
R4
T4
T7
J7
1 C5230 1
F4
M4
T8
V4
V7
V8
A3
A9
B1
D5
N6
10UF 1UF
L25 XW5230 20%
6.3V
10%
6.3V A7 MPVDD VDDR1 MAB0 N5 FBBA<0> 53 55
VDDRH0
VDDRH1
FBD<40> DQA0 SM 2 CERM 2 CERM
53
VDDR1 MAB1 M1 FBBA<1>
FBD<41> L26 DQA1 1 2 GND_GPU_MPVSS 805 402 A6 MPVSS 53 55
53
MAB2 M3 FBBA<2>
FBD<43> K25 DQA2
VOLTAGE=0V 53 55
53
MAA0 E22 FBA<0>
FBD<104> D7 DQB0 MAB3 L3 FBBA<3>
FBD<42> K26 DQA3
53 54 MIN_NECK_WIDTH=0.25MM 53
OMIT
53 55
53
B22 F7 DQB1 L2
U4900
J26 MAA1 FBA<1> 53 54 53 FBD<107> MAB4 FBBA<4> 53 55
FBD<44> DQA4 OMIT
U4900
53
MAA2 B23 FBA<2> FBD<106> E7 DQB2 MAB5 M2 FBBA<5>
FBD<46> H25 DQA5
53 54 53 53 55
53
MAA3 B24 G6 DQB3 MAB6 M5
RV351
FBA<3> FBD<111> FBBA<6>
FBD<45> H26 DQA6
53 54 53 53 55
RV351 C23 G5 DQB4 P6

53
G26 MAA4 FBA<4> 53 54 53 FBD<109> MAB7 FBBA<7> 53 55
FBD<47> DQA7
53
53 FBD<35> G30 DQA8 BGA

MAA5 C22
F22
FBA<5> 53 54 53 FBD<110> F5 DQB5
E5 DQB6
BGA MAB8 N3
K2
FBBA<8> 53 55
D29 MAA6 FBA<6> 53 54 53 FBD<108>

(4 OF 5) MAB9 FBBA<9> 53 55
53 FBD<38> DQA9 F21 C4 DQB7 K3
FBD<39> D28 (3 OF 5) MAA7 FBA<7> 53 54 53 FBD<105> MAB10 FBBA<10> 53 55
53 DQA10 C21 B5 DQB8 J2
FBD<37> E28 MAA8 FBA<8> 53 54 53 FBD<96> MAB11 FBBA<11> 53 55
DQA11 A24 C5 DQB9 P5
MEMORY INTERFACE B
53
E29 MAA9 FBA<9> 53 54 53 FBD<97> MAB12 FBBA<12> 53 55
53 FBD<36> DQA12 C24 A4 DQB10 P3
FBD<32> G29 MAA10 FBA<10> 53 54 53 FBD<98> MAB13 FBBA<13> 53 55
53 DQA13 A25 B4 DQB11 P2
MAA11 FBA<11> FBD<99> MAB14 TP_FBBA<14>
MEMORY INTERFACE A
FBD<33> G28 DQA14
53 54 53
53
MAA12 E21 FBA<12> FBD<100> C2 DQB12
FBD<34> F28 DQA15
53 54 53
53
MAA13 B20 FBA<13> FBD<101> D3 DQB13 DQMB0* E6 FBDQM<13>
FBD<59> G25 DQA16
53 54 53 53 55
53
MAA14 C19 TP_FBA<14> FBD<102> D1 DQB14 DQMB1* B2 FBDQM<12>
FBD<56> F26 DQA17
53 53 55
53
FBD<103> D2 DQB15 DQMB2* J5 FBDQM<15>
FBD<57> E26 DQA18 DQMA0* J25 FBDQM<5>
53 53 55
53 53 54
FBD<120> G4 DQB16 DQMB3* G3 FBDQM<14>
FBD<58> F25 DQA19 DQMA1* F29 FBDQM<4>
53 53 55
53 53 54
FBD<121> H6 DQB17 DQMB4* W6 FBDQM<8>
FBD<60> E24 DQA20 DQMA2* E25 FBDQM<7>
53 53 55
53 53 54
FBD<123> H5 DQB18 DQMB5* W2 FBDQM<9>
FBD<62> F23 DQA21 DQMA3* A27 FBDQM<6>
53 53 55
53 53 54
FBD<122> J6 DQB19 DQMB6* AC6 FBDQM<10>
FBD<61> E23 DQA22 DQMA4* F15 FBDQM<0>
53 53 55
53 53 54
K5 DQB20 AD2
C 53 FBD<63>
FBD<49>
D22
B29
DQA23 DQMA5*
DQMA6*
C15
C11
FBDQM<1>
FBDQM<3>
53 54
53
53
FBD<124>
FBD<126> K4 DQB21
DQMB7* FBDQM<11> 53 55
C
53 DQA24 53 54
FBD<125> L6 DQB22 QSB0 F6 FBDQS<13>
FBD<48> C29 DQA25 DQMA7* E11 FBDQM<2>
53 53
53 53 54
FBD<127> L5 DQB23 QSB1 B3 FBDQS<12>
FBD<54> C25 DQA26
53 53
53
FBD<116> G2 DQB24 QSB2 K6 FBDQS<15>
FBD<50> C27 DQA27 QSA0 J27 FBDQS<5>
53 53
53 53
FBD<113> F3 DQB25 QSB3 G1 FBDQS<14>
FBD<51> B28 DQA28 QSA1 F30 FBDQS<4>
53 53
53 53
FBD<118> H2 DQB26 QSB4 V5 FBDQS<8>
FBD<55> B25 DQA29 QSA2 F24 FBDQS<7>
53 53
53 53
FBD<112> E2 DQB27 QSB5 W1 FBDQS<9>
FBD<52> C26 DQA30 QSA3 B27 FBDQS<6>
53 53
53 53
FBD<114> F2 DQB28 QSB6 AC5 FBDQS<10>
FBD<53> B26 DQA31 QSA4 E16 FBDQS<0>
53 53
53 53
FBD<119> J3 DQB29 QSB7 AD1 FBDQS<11>
FBD<0> F17 DQA32 QSA5 B16 FBDQS<1>
53 53
53 53
FBD<115> F1 DQB30
FBD<1> E17 DQA33 QSA6 B11 FBDQS<3>
53
53 53
FBD<117> H3 DQB31
FBD<2> D16 DQA34 QSA7 F10 FBDQS<2>
53
RASB* R2 FBBRAS_L
53 53
FBD<64> U6 DQB32 55
FBD<3> F16 DQA35

53
53
FBD<65> U5 DQB33 CASB* T5 FBBCAS_L
FBD<5> E15 DQA36
53 55
53
FBD<66> U3 DQB34
FBD<6> F14 DQA37 RASA* A19 FBARAS_L
53
WEB* T6 FBBWE_L
53 54
FBD<67> V6 DQB35 55
FBD<4> E14 DQA38

53
CASA* E18 W5 DQB36 CSB0* R5

53
FBACAS_L FBD<68> FBBCS0_L
FBD<7> F13 DQA39
54 53 55
53
FBD<70> W4 DQB37
FBD<9> C17 DQA40 WEA* E19 FBAWE_L
53
CSB1* R6 TP_FBBCS1_L
53 54
FBD<69> Y6 DQB38 6
FBD<8> B18 DQA41

53
CSA0* E20 Y5 DQB39 CKEB R3

53
FBACS0_L FBD<71> FBBCKE
FBD<11> B17 DQA42
54 53 55
53
FBD<72> U2 DQB40
FBD<12> B15 DQA43 CSA1* F20 TP_FBACS1_L
53
1
R5201
53
FBD<73> V2 DQB41
FBD<15> C13 DQA44
53
CLKB0 N1 FBBCLK0 10K
CKEA B19 V1 DQB42
53 53 55
FBACKE FBD<75> 5%
FBD<14> B14 DQA45
54 53
CLKB0* N2 FBBCLK0_L 1/16W
53
FBD<74> V3 DQB43 53 55
MF-LF
FBD<13> C14 DQA46 1
R5200
53
2 402
CLKA0 B21 W3 DQB44 CLKB1 T2
53
FBACLK0 FBD<76> FBBCLK1
FBD<10> C16 DQA47
53 54
10K 53 53 55
CLKA0* C20 Y2 DQB45 CLKB1* T3

53
FBACLK0_L 5% FBD<77> FBBCLK1_L
FBD<24> A13 DQA48
53 54
1/16W
53 53 55
53
FBD<78> Y3 DQB46
B 53
53
FBD<26>
FBD<25>
A12
C12
DQA49
DQA50
CLKA1 C18
CLKA1* A18
FBACLK1
FBACLK1_L
53 54
53 54
MF-LF
2 402
53
53 FBD<79> AA2 DQB47

AA6 DQB48
ROMCS* AF5 TP_GPU_ROMCS_L
58 52 51 50 =PP1V8_GPU B
FBD<80> MEMVMODE 01 NOSTUFF
FBD<27> B12 DQA51
53
53
FBD<81> AA5 DQB49 MEMVMODE0 C6 GPU_MEMVMODE0 R5224 1 1
R5226
FBD<29> C10 DQA52
53
1.8V 01
53
MVREFD B7 GPU_MVREFD PP2V5_GPU FBD<82> AB6 DQB50 4.7K 4.7K
FBD<31> C9 DQA53 MIN_LINE_WIDTH=0.5MM
7 52 54 55 53
2.5V 10 5% 5%
53
MIN_NECK_WIDTH=0.25MM FBD<83> AB5 DQB51 1/16W 1/16W
FBD<30> B9 DQA54
53
2.8V 11 MEMVMODE1 C7 GPU_MEMVMODE1 MF-LF MF-LF
53
MVREFS B8 GPU_MVREFS 1
R5220 FBD<84> AD6 DQB52 402 2
FBD<28> B10 DQA55 MIN_LINE_WIDTH=0.5MM
53
2 402
53
MIN_NECK_WIDTH=0.25MM 100 FBD<85> AD5 DQB53
FBD<17> E13 DQA56 1%
53
53
1/16W FBD<86> AE5 DQB54 MEMTEST C8 GPU_MEMTEST
FBD<16> E12 DQA57 MF-LF
53
NOSTUFF
53
2 402 FBD<87> AE4 DQB55 MIN_LINE_WIDTH=0.5MM
FBD<20> E10 DQA58
1
R5228 R52251 1
R5227
53
FBD<88> AB2 DQB56
FBD<18> F12 DQA59 DIMA_0 D30 TP_GPU_DIMA_0
53
DIMB_0 E3 TP_GPU_DIMB_0 47 4.7K 4.7K
53
FBD<89> AB3 DQB57 1% 5% 5%
FBD<19> F11 DQA60 DIMA_1 B13 TP_GPU_DIMA_1 1
R5221
53
DIMB_1 AA3 TP_GPU_DIMB_1
53
FBD<21> E9 DQA61
C5221 1 100 53 FBD<90> AC2 DQB58 1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
53
0.1UF 1% FBD<91> AC3 DQB59 2 402 402 2 2 402
FBD<22> F9 DQA62 20% 1/16W
53
53
10V
2 MF-LF FBD<92> AD3 DQB60
FBD<23> F8 DQA63 CERM
2 402
53
53
VSSRH0 VSSRH1 402
53 FBD<93> AE1 DQB61
F19
M6

PP2V5_GPU 7 52 54 55
1
R5222
47
1%
1/16W
MF-LF
2 402
GPU FRAME BUFFER
A
1
R5223 SYNC_MASTER=N/A SYNC_DATE=N/A
C5223
0.1UF
20%
1
1%
51.1
A
10V 1/16W
CERM 2 MF-LF
402 2 402 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
APPLE COMPUTER INC.

D 051-6772 E
SCALE SHT OF
NONE 52 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
PLACE R’S CLOSE TO MEMORY

FRAME BUFFER A TERMINATION PLACE CLOCK TERMINATION AFTER MEMORY
GPU -> MEMORY -> TERMINATION
FBD<31> 22 1 8 RP5320 RFBD<31> FBD<32> 22 3 6 RP5328 RFBD<32>

53 52 53 54 53 52 6 53 54

53 52 6 53 54 53 52 6 53 54

53 52 6 53 54 53 52 53 54
4 5 RP5320 2 7 RP5328 54 53 52 FBACLK0
53 52 FBD<28> 22 RFBD<28> 6 53 54 53 52 FBD<35> 22 RFBD<35> 6 53 54
1 8 RP5321 4 5 RP5316 53 52 FBDQS<0> RFBDQS<0> 54
53 52 FBD<27> 22 RFBD<27> 53 54 53 52 FBD<36> 22 RFBD<36> 6 53 54 MAKE_BASE=TRUE
FBD<26> 22 2 7 RP5321 RFBD<26> FBD<37> 22 3 6 RP5316 RFBD<37> R53201
D
53 52
53 52 FBD<25> 22
22
3
4
6
5
RP5321
RP5321
RFBD<25>
6 53 54
6 53 54
53 52
53 52 FBD<38> 22
22
2
1
7
8
RP5316
RP5316
RFBD<38>
6 53 54
6 53 54 53 52 FBDQS<1>
MAKE_BASE=TRUE
RFBDQS<1> 54
56.2
1%
1/16W
D
53 52 FBD<24> RFBD<24> 6 53 54 53 52 FBD<39> RFBD<39> 53 54 MF-LF
22 1 8 RP5322 22 2 7 RP5329 402 2
53 52 FBD<0> RFBD<0> 53 54 53 52 FBD<40> RFBD<40> 6 53 54
2 7 RP5322 1 8 RP5329 FBACLK0_TERM
53 52 FBD<1> 22 RFBD<1> 6 53 54 53 52 FBD<41> 22 RFBD<41> 53 54 53 52 FBDQS<2> RFBDQS<2> 54 MIN_LINE_WIDTH=0.5MM
3 6 RP5322 3 6 RP5329 MAKE_BASE=TRUE MIN_NECK_WIDTH=0.25MM
53 52 FBD<2> 22
4 5 RP5322
RFBD<2> 6 53 54 53 52 FBD<42> 22
4 5 RP5329
RFBD<42> 6 53 54
R53211 C5321 1
53 52 FBD<3> 22 RFBD<3> 6 53 54 53 52 FBD<43> 22 RFBD<43> 6 53 54 56.2 0.01UF
1 8 RP5323 1 8 RP5330 53 52 FBDQS<3> RFBDQS<3> 54 1%
53 52 FBD<17> 22 RFBD<17> 53 54 53 52 FBD<44> 22 RFBD<44> 53 54 MAKE_BASE=TRUE 1/16W 20%
16V
22 2 7 RP5323 22 2 7 RP5330 MF-LF CERM 2
53 52 FBD<16> RFBD<16> 6 53 54 53 52 FBD<45> RFBD<45> 6 53 54 402 2 402
53 52 6 53 54 53 52 6 53 54
RP5323 RP5330 53 52 FBDQS<4> RFBDQS<4> 54
53 52 FBD<19> 22 4 5 RFBD<19> 6 53 54 53 52 FBD<47> 22 3 6 RFBD<47> 6 53 54 MAKE_BASE=TRUE 54 53 52 FBACLK0_L
53 52 53 54 53 52 6 53 54
FBD<14> 22 2 7 RP5324 RFBD<14> FBD<49> 22 3 6 RP5331 RFBD<49> FBDQS<5> RFBDQS<5>

53 52 6 53 54 53 52 6 53 54 53 52 54
22 3 6 RP5324 22 1 8 RP5331 MAKE_BASE=TRUE
53 52 FBD<13> RFBD<13> 6 53 54 53 52 FBD<50> RFBD<50> 53 54
4 5 RP5324 2 7 RP5331 54 53 52 FBACLK1
53 52 FBD<12> 22 RFBD<12> 6 53 54 53 52 FBD<51> 22 RFBD<51> 53 54
FBD<10> 22 1 8 RP5325 RFBD<10> FBD<52> 22 4 5 RP5300 RFBD<52> FBDQS<6> RFBDQS<6>

53 52 53 54 53 52 53 54 53 52 54
53 52 FBD<11> 22 2 7 RP5325 RFBD<11> 6 53 54 53 52 FBD<53> 22 3 6 RP5300 RFBD<53> 53 54

MAKE_BASE=TRUE R53221
22 3 6 RP5325 22 2 7 RP5300 56.2
53 52 FBD<9> RFBD<9> 6 53 54 53 52 FBD<54> RFBD<54> 53 54 1%
RP5325 RP5300 53 52 FBDQS<7> RFBDQS<7> 54 1/16W
53 52 FBD<8> 22 4 5 RFBD<8> 6 53 54 53 52 FBD<55> 22 1 8 RFBD<55> 53 54 MAKE_BASE=TRUE MF-LF
22 1 8 RP5326 22 1 8 RP5301 402 2
53 52 FBD<5> RFBD<5> 53 54 53 52 FBD<56> RFBD<56> 53 54
2 7 RP5326 2 7 RP5301 FBACLK1_TERM
53 52 FBD<6> 22 RFBD<6> 6 53 54 53 52 FBD<57> 22 RFBD<57> 53 54 MIN_LINE_WIDTH=0.5MM
3 6 RP5326 4 5 RP5301 MIN_NECK_WIDTH=0.25MM
53 52 FBD<4> 22 RFBD<4> 6 53 54 53 52 FBD<58> 22 RFBD<58> 53 54 R53231
53 52 FBD<7> 22 4 5 RP5326
RP5327
RFBD<7> 6 53 54 53 52 FBD<59> 22 3 6 RP5301
RP5302
RFBD<59> 53 54 56.2
1%
C5323 1
53 52 FBD<20> 22 1 8 RFBD<20> 53 54 53 52 FBD<60> 22 1 8 RFBD<60> 53 54 1/16W 0.01UF
MF-LF 20%
FBD<21> 22 2 7 RP5327 RFBD<21> FBD<61> 22 3 6 RP5302 RFBD<61> 16V
53 52 6 53 54 53 52 53 54 402 2 CERM 2
FBD<22> 22 3 6 RP5327 RFBD<22> FBD<62> 22 2 7 RP5302 RFBD<62> 402
53 52 6 53 54 53 52 53 54
FBD<23> 22 4 5 RP5327 RFBD<23> FBD<63> 22 4 5 RP5302 RFBD<63> FBACLK1_L

53 52 6 53 54 53 52 53 54 54 53 52
C C
FRAME BUFFER B TERMINATION

GPU128BIT
1 8 RP5310 GPU128BIT
4 5 RP5315 55 53 52 FBBCLK0
53 52 FBD<64> 22 RFBD<64> 53 55 53 52 FBD<96> 22 RFBD<96> 53 55
FBD<65>
GPU128BIT
22 2 7 RP5310 RFBD<65> FBD<97>
GPU128BIT
22 3 6 RP5315 RFBD<97>
53 52 53 55 53 52 53 55
53 52 FBD<66>
GPU128BIT
22 3 6 RP5310 RFBD<66> 53 55 53 52 FBD<98>
GPU128BIT
22 2 7 RP5315 RFBD<98> 53 55
R53241
GPU128BIT
22 4 5 RP5310 GPU128BIT
22 1 8 RP5315 56.2
53 52 FBD<67> RFBD<67> 53 55 53 52 FBD<99> RFBD<99> 53 55 1%
GPU128BIT
4 5 RP5314 53 52 FBDQS<8> RFBDQS<8> 55 1/16W
53 52 FBD<84> 22 RFBD<84> 53 55 53 52 FBD<100> 22 RFBD<100> 53 55 MAKE_BASE=TRUE MF-LF
GPU128BIT
22 2 7 RP5309 GPU128BIT
22 3 6 RP5314 402 2
53 52 FBD<85> RFBD<85> 53 55 53 52 FBD<101> RFBD<101> 53 55
GPU128BIT RP5309 GPU128BIT RP5314 FBBCLK0_TERM
53 52 FBD<86> 22 3 6 RFBD<86> 53 55 53 52 FBD<102> 22 2 7 RFBD<102> 53 55 53 52 FBDQS<9> RFBDQS<9> 55 MIN_LINE_WIDTH=0.5MM
GPU128BIT
1 8 RP5314 MAKE_BASE=TRUE MIN_NECK_WIDTH=0.25MM
53 52 FBD<87> 22 RFBD<87> 53 55 53 52 FBD<103> 22 RFBD<103> 53 55
R5325 1
53 52 FBD<72>
GPU128BIT
22 4 5 RP5319
RP5319
RFBD<72> 53 55 53 52 FBD<104>
GPU128BIT
22 1 8 RP5312
RP5312
RFBD<104> 53 55 56.2
1%
C5325 1
53 52 FBD<73>
GPU128BIT
22 3 6 RFBD<73> 53 55 53 52 FBD<105>
GPU128BIT
22 2 7 RFBD<105> 53 55 53 52 FBDQS<10> RFBDQS<10> 55 1/16W 0.01UF
MAKE_BASE=TRUE MF-LF 20%
FBD<75>
GPU128BIT
22 2 7 RP5319 RFBD<75> FBD<106>
GPU128BIT
22 3 6 RP5312 RFBD<106> 16V
53 52 53 55 53 52 53 55 402 2 CERM 2
FBD<74>
GPU128BIT
22 1 8 RP5319 RFBD<74> FBD<107>
GPU128BIT
22 4 5 RP5312 RFBD<107> 402
53 52 53 55 53 52 53 55
GPU128BIT RP5308 GPU128BIT RP5313 53 52 FBDQS<11> RFBDQS<11> 55
53 52 FBD<68> 22 1 8 RFBD<68> 53 55 53 52 FBD<108> 22 1 8 RFBD<108> 53 55 MAKE_BASE=TRUE 55 53 52 FBBCLK0_L
FBD<70>
GPU128BIT
22 2 7 RP5308 RFBD<70> FBD<109>
GPU128BIT
22 2 7 RP5313 RFBD<109>
53 52 53 55 53 52 53 55
FBD<69>
GPU128BIT
22 3 6 RP5308 RFBD<69> FBD<110>
GPU128BIT
22 3 6 RP5313 RFBD<110>
53 52 53 55 53 52 53 55
GPU128BIT
4 5 RP5313 53 52 FBDQS<12> RFBDQS<12> 55
53 52 FBD<71> 22 RFBD<71> 53 55 53 52 FBD<111> 22 RFBD<111> 53 55 MAKE_BASE=TRUE
GPU128BIT
4 5 RP5311 55 53 52 FBBCLK1
53 52 FBD<80> 22 RFBD<80> 53 55 53 52 FBD<112> 22 RFBD<112> 53 55
FBD<81>
GPU128BIT
22 2 7 RP5307 RFBD<81> FBD<113>
GPU128BIT
22 3 6 RP5311 RFBD<113> FBDQS<13> RFBDQS<13>
B
53 52
53 52 FBD<82>
GPU128BIT
GPU128BIT
22
22
3
4
6
5
RP5307
RP5307
RFBD<82>
53 55
53 55
53 52
53 52 FBD<114>
GPU128BIT
GPU128BIT
22
22
2
1
7
8
RP5311
RP5311
RFBD<114>
53 55
53 55
53 52
MAKE_BASE=TRUE
55
R53261
56.2
B
53 52 FBD<83> RFBD<83> 53 55 53 52 FBD<115> RFBD<115> 53 55 1%
GPU128BIT
4 5 RP5306 1/16W
53 52 FBD<76> 22 RFBD<76> 53 55 53 52 FBD<116> 22 RFBD<116> 53 55 53 52 FBDQS<14> RFBDQS<14> 55 MF-LF
GPU128BIT
22 3 6 RP5317 GPU128BIT
22 3 6 RP5306 MAKE_BASE=TRUE 402 2
53 52 FBD<77> RFBD<77> 53 55 53 52 FBD<117> RFBD<117> 53 55
GPU128BIT
2 7 RP5306 FBBCLK1_TERM
53 52 FBD<78> 22 RFBD<78> 53 55 53 52 FBD<118> 22 RFBD<118> 53 55 MIN_LINE_WIDTH=0.5MM
GPU128BIT
1 8 RP5306 53 52 FBDQS<15> RFBDQS<15> 55 MIN_NECK_WIDTH=0.25MM
53 52 FBD<79> 22 RFBD<79> 53 55 53 52 FBD<119> 22 RFBD<119> 53 55 MAKE_BASE=TRUE R53271
53 52 FBD<91>
GPU128BIT
22 1 8 RP5318
RP5318
RFBD<91> 53 55 53 52 FBD<120>
GPU128BIT
22 1 8 RP5304
RP5304
RFBD<120> 53 55 56.2
1%
C5327 1
53 52 FBD<90>
GPU128BIT
22 2 7 RFBD<90> 53 55 53 52 FBD<121>
GPU128BIT
22 2 7 RFBD<121> 53 55 1/16W 0.01UF
MF-LF 20%
FBD<89>
GPU128BIT
22 3 6 RP5318 RFBD<89> FBD<122>
GPU128BIT
22 4 5 RP5304 RFBD<122> 16V
53 52 53 55 53 52 53 55 402 2 CERM 2
FBD<88>
GPU128BIT
22 4 5 RP5318 RFBD<88> FBD<123>
GPU128BIT
22 3 6 RP5304 RFBD<123> 402
53 52 53 55 53 52 53 55
FBD<95>
GPU128BIT
22 1 8 RP5303 RFBD<95> FBD<124>
GPU128BIT
22 1 8 RP5305 RFBD<124> FBBCLK1_L
53 52 53 55 53 52 53 55 55 53 52
FBD<94>
GPU128BIT
22 2 7 RP5303 RFBD<94> FBD<125>
GPU128BIT
22 3 6 RP5305 RFBD<125>
53 52 53 55 53 52 53 55
FBD<93>
GPU128BIT
22 3 6 RP5303 RFBD<93> FBD<126>
GPU128BIT
22 2 7 RP5305 RFBD<126>
53 52 53 55 53 52 53 55
FBD<92>
GPU128BIT
22 4 5 RP5303 RFBD<92> FBD<127>
GPU128BIT
22 4 5 RP5305 RFBD<127>
53 52 53 55 53 52 53 55
53 52 FBD<127..0> GPU_FB GPU_FB

55 54 53 6 RFBD<127..0> GPU_FB GPU_FB
I421
I425 FB TERMINATION
54 52 FBA<13..0> GPU_FB GPU_FB I426
A 55 52
55 54 52
FBBA<13..0>
FBDQM<15..0>
GPU_FB
GPU_FB
GPU_FB
GPU_FB
I427
SYNC_MASTER=N/A

SYNC_DATE=N/A
A
I428
53 52 FBDQS<15..0> GPU_FB GPU_FB I429
54 53 52 FBACLK0 GPU_FBCLK GPU_FBCLK FBACLK0 I423 AGREES TO THE FOLLOWING
54 53 52 FBACLK0_L GPU_FBCLK GPU_FBCLK FBACLK0 I430 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
54 53 52 FBACLK1 GPU_FBCLK GPU_FBCLK FBACLK1 I431 II NOT TO REPRODUCE OR COPY IT
54 53 52 FBACLK1_L GPU_FBCLK GPU_FBCLK FBACLK1 I432 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
55 53 52 FBBCLK0 GPU_FBCLK GPU_FBCLK FBBCLK0 I433
55 53 52 FBBCLK0_L GPU_FBCLK GPU_FBCLK FBBCLK0 I435
55 53 52 FBBCLK1 GPU_FBCLK GPU_FBCLK FBBCLK1 I434
APPLE COMPUTER INC.
D 051-6772 E
55 53 52 FBBCLK1_L GPU_FBCLK GPU_FBCLK FBBCLK1 I436
SCALE SHT OF
NONE 53 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
55 54 52 7 PP2V5_GPU 55 54 52 7 PP2V5_GPU
55 54 52 7 PP2V5_GPU
PLACE NEAR VDD PINS PLACE NEAR VDD PINS
C5415 C5414 C5401 C5400

1 C5424 1 C5425 1 C5426 1 C5422 1 C5427 1 C5428 1 C5429 1 C5423 1 10UF 1 10UF 1 10UF 1 10UF
0.1UF 0.1UF 0.1UF 0.001UF 0.1UF 0.1UF 0.1UF 0.001UF 20% 20% 20% 20%
20% 20% 20% 10% 20% 20% 20% 10% 6.3V 6.3V 6.3V 6.3V
10V 10V 10V 50V 10V 10V 10V 50V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402 402 402
805 805 805 805
D D
55 54 52 7 PP2V5_GPU
55 54 52 7 PP2V5_GPU
OMIT
OMIT
U5401
U5400 SDRAM_DDR_4MX32
SDRAM_DDR_4MX32 BGA
BGA D7 (2 OF 2)
E5
(2 OF 2)
D7 E5
D8 E7
D8 E7 OMIT
E4 E8 OMIT
E4 E8 U5400
SDRAM_DDR_4MX32 E11 E10 U5401
E11 E10 SDRAM_DDR_4MX32
FBA<0> N5 A0 BGA
L4 VDD K6
L4 VDD K6 54 53 52 (1 OF 2)
VSS 54 53 52 FBA<0> N5 A0
BGA
(1 OF 2)
VSS 54 53 52 FBA<1> N6 A1 DQ0 B7 RFBD<7> 6 53
L7 K7
L7 K7 54 53 52 FBA<1> N6 A1 DQ0 B7 RFBD<48> 6 53
54 53 52 FBA<2> M6 A2 DQ1 C6 RFBD<5> 53 L8 K8
L8 K8 54 53 52 FBA<2> M6 A2 DQ1 C6 RFBD<49> 6 53
54 53 52 FBA<3> N7 A3 DQ2 B6 RFBD<6> 6 53 L11 K9
L11 K9 54 53 52 FBA<3> N7 A3 DQ2 B6 RFBD<50> 53
L5 54 53 52 FBA<4> N8 A4 DQ3 B5 RFBD<4> 6 53
C3
L5
N8 B5
54 53 52 FBA<4> A4 DQ3 RFBD<51> 53
C3 54 53 52 FBA<5> M9 A5 DQ4 C2 RFBD<2> 6 53 L10
C5
L10
N9 D3
C5 54 53 52 FBA<5> M9 A5 DQ4 C2 RFBD<53> 53
54 53 52 FBA<6> A6 DQ5 RFBD<3> 6 53
C7 F6 54 53 52 FBA<6> N9 A6 DQ5 D3 RFBD<52> 53
C7 F6 54 53 52 FBA<7> N10 A7 DQ6 D2 RFBD<1> 6 53
C8 F7 N10 D2
54 53 52 FBA<7> A7 DQ6 RFBD<54> 53
C8 F7 54 53 52 FBA<8> N11 A8 DQ7 E2 RFBD<0> 53
C10 F8 M8 K13
C10 F8 54 53 52 FBA<8> N11 A8 DQ7 E2 RFBD<55> 53
54 53 52 FBA<9> A9 DQ8 RFBD<31> 53
C12 F9 54 53 52 FBA<9> M8 A9 DQ8 K13 RFBD<32> 6 53
C12 F9 54 53 52 FBA<10> L6 A10 DQ9 K12 RFBD<30> 6 53
E3 G6 L6 K12
54 53 52 FBA<10> A10 DQ9 RFBD<33> 6 53
E3 G6 54 53 52 FBA<11> M7 A11 DQ10 J13 RFBD<29> 6 53
E12 G7 J12
E12 G7 54 53 52 FBA<11> M7 A11 DQ10 J13 RFBD<35> 6 53
DQ11 RFBD<28> 6 53 VDDQ
VDDQ 53 RFBDQS<0> B2 DQS0 F4 G8 DQ11 J12 RFBD<34> 53
F4 G8 DQ12 G13 RFBD<27> 53 53 RFBDQS<6> B2 DQS0
53 RFBDQS<3> H13 DQS1 F11 VSS_THERM G9 DQ12 G13 RFBD<37> 6 53
F11 VSS_THERM G9 DQ13 G12 RFBD<26> 6 53 53 RFBDQS<4> H13 DQS1
53 RFBDQS<1> H2 DQS2 G4 H6 DQ13 G12 RFBD<36> 6 53
G4 H6
B13 DQ14 F13 RFBD<25> 6 53
G11 H7 53 RFBDQS<7> H2 DQS2 F13
53 RFBDQS<2> DQS3 DQ14 RFBD<38> 6 53
C G11
J4
H7
H8 53 52 FBDQM<0> B3 DM0
DQ15
DQ16
F12
F3
RFBD<24>
RFBD<15>
6 53
53
J4
J11
H8
H9
53
53 52
RFBDQS<5>
FBDQM<6>
B13
B3
DQS3
DM0
DQ15
DQ16
F12
F3
RFBD<39>
RFBD<57>
53
53
C
J11 H9 53 52 FBDQM<3> H12 DM1 DQ17 F2 RFBD<14> 6 53
K4 J6 H12 F2
53 52 FBDQM<4> DM1 DQ17 RFBD<56> 53
K4 J6 53 52 FBDQM<1> H3 DM2 DQ18 G3 RFBD<13> 6 53
K11 J7 B12 G2
K11 J7 53 52 FBDQM<7> H3 DM2 DQ18 G3 RFBD<58> 53
53 52 FBDQM<2> DM3 DQ19 RFBD<12> 6 53
J8 53 52 FBDQM<5> B12 DM3 DQ19 G2 RFBD<59> 53
N13
J8
N4 DQ20 J3 RFBD<10> 53 54 SGRAVREF N13 VREF J9 J3
54 SGRAVREF VREF 54 53 52 FBA<12> BA0 DQ20 RFBD<62> 53
J9 DQ21 J2 RFBD<11> 6 53 54 53 52 FBA<12> N4 BA0
54 53 52 FBA<13> M5 BA1 K2 B4 M5
DQ21 J2 RFBD<60> 53
DQ22 RFBD<8> 6 53 54 53 52 FBA<13> BA1
B4 1 C5435 DQ22 K2 RFBD<61> 53
1 C5434 53 52 FBACLK0 M11 CK DQ23 K3 RFBD<9> 6 53
0.1UF
B11
0.1UF
B11 53 52 FBACLK1 M11 CK DQ23 K3 RFBD<63> 53
53 52 FBACLK0_L M12 CK DQ24 E13 RFBD<23> 6 53
20% D4
20% D4 2 10V
53 52 FBACLK1_L M12 CK DQ24 E13 RFBD<41> 53
2
10V
D5 54 52 FBACKE N12 CKE DQ25 D13 RFBD<22> 6 53
CERM D5
N12 D13
CERM 402
54 52 FBACKE CKE DQ25 RFBD<40> 6 53
402
54 52 FBACS0_L N2 CS DQ26 D12 RFBD<21> 6 53 D6
D6
M2 C13 D9 54 52 FBACS0_L N2 CS DQ26 D12 RFBD<42> 6 53
54 52 FBARAS_L RAS DQ27 RFBD<20> 53
D9 54 52 FBARAS_L M2 RAS DQ27 C13 RFBD<43> 6 53
D10 54 52 FBACAS_L L2 CAS DQ28 B10 RFBD<19> 6 53 D10
L2 B10
54 52 FBACAS_L CAS DQ28 RFBD<44> 53
54 52 FBAWE_L L3 WE DQ29 B9 RFBD<16> 6 53 D11
D11
C9 E6 54 52 FBAWE_L L3 WE DQ29 B9 RFBD<47> 6 53
DQ30 RFBD<18> 6 53
E6 C4 VSSQ DQ30 C9 RFBD<45> 6 53
VSSQ E9 C11
DQ31 B8 RFBD<17> 53 E9 C4
B8
F5 C11 DQ31 RFBD<46> 6 53
F5 H4 MCL M13
F10 H4 M13
F10 H11
MCL
RFU1 L9 TP_U5400_RFU1 NO_TEST G5 H11
G5 L12
NC RFU1 L9 TP_U5401_RFU1 NO_TEST
RFU2 M10 TP_U5400_RFU2 NO_TEST G10 L12
NC
G10 L13
H5 L13
RFU2 M10 TP_U5401_RFU2 NO_TEST
H5 M3
H10 M3
H10 M4
J5 M4
J5 N3
J10 N3
J10
K5
K5
K10
B K10
B
55 54 52 7 PP2V5_GPU
55 54 52 7 PP2V5_GPU
1 C5418 1 C5408 1 C5409 1 C5419 1 C5410 1 C5411 1 C5420 1 C5412 1 C5413 1 C5421 1 C5433 1 C5402 1 C5403 1 C5430 1 C5404 1 C5405 1 C5431 1 C5406 1 C5407 1 C5432
0.001UF 0.1UF 0.1UF 0.001UF 0.1UF 0.1UF 0.001UF 0.1UF 0.1UF 0.001UF 0.001UF 0.1UF 0.1UF 0.001UF 0.1UF 0.1UF 0.001UF 0.1UF 0.1UF 0.001UF
10% 20% 20% 10% 20% 20% 10% 20% 20% 10% 10% 20% 20% 10% 20% 20% 10% 20% 20% 10%
50V 10V 10V 50V 10V 10V 50V 10V 10V 50V 50V 10V 10V 50V 10V 10V 50V 10V 10V 50V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
EVENLY PLACE 0.1UF CAP & 0.01UF CAPS
DDR SDRAM A VREF
SGRAM0 & SGRAM1 MEMORY SUPPORT

PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 55 54 52 7 PP2V5_GPU
333S0251 2 SDRAM,4MX32,DDR,300MHZ U5400,U5401 CRITICAL SAMSUNG64 1

R5400 GPU DDR SDRAM A
333S0252 2 SDRAM,4MX32,DDR,300MHZ U5400,U5401 CRITICAL HYNIX64 1K
A 333S0341 2 SDRAM,8MX32,DDR,300MHZ U5400,U5401 CRITICAL HYNIX128
1%
1/16W
MF-LF
402
SYNC_MASTER=N/A

SYNC_DATE=N/A
A
2
SGRAVREF 54
VOLTAGE=1.25V THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1 MIN_LINE_WIDTH=0.5MM PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
TABLE_ALT_HEAD
R5401 1 C5417 MIN_NECK_WIDTH=0.25MM AGREES TO THE FOLLOWING
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: 1K 0.1UF I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
PART NUMBER 1%
20%
1/16W 10V II NOT TO REPRODUCE OR COPY IT
TABLE_ALT_ITEM
MF-LF 2 CERM
333S0290 333S0251 SAMSUNG64 U5400,U5401,U5500,U5501 HYN4M G-DIE 2 402 402 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
TABLE_ALT_ITEM
333S0292 333S0252 HYNIX64 U5400,U5401,U5500,U5501 SAM4M B-DIE SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.

D 051-6772 E
SCALE SHT OF
NONE 54 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
55 54 52 7 PP2V5_GPU 55 54 52 7 PP2V5_GPU
55 54 52 7 PP2V5_GPU
PLACE NEAR VDD PINS PLACE NEAR VDD PINS
GPU128BIT GPU128BIT GPU128BIT GPU128BIT
GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT

C5515 C5514 C5501 C5500
1 C5518 1 C5519 1 C5520 1 C5521 1 C5522 1 C5523 1 C5524 1 C5525 1 10UF 1 10UF 1 10UF 1 10UF
0.1UF 0.1UF 0.1UF 0.001UF 0.1UF 0.1UF 0.1UF 0.001UF 20% 20% 20% 20%
20% 20% 20% 10% 20% 20% 20% 10% 6.3V 6.3V 6.3V 6.3V
10V 10V 10V 50V 10V 10V 10V 50V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402 402 402
805 805 805 805
D 55 54 52 7 PP2V5_GPU
D
55 54 52 7 PP2V5_GPU
U5501
U5500 SDRAM_DDR_4MX32
SDRAM_DDR_4MX32 BGA
BGA D7 (2 OF 2)
E5
(2 OF 2)
D7 E5
D8 OMIT E7
D8 OMIT E7
E4 E8
E4 E8 U5500
SDRAM_DDR_4MX32 E11 E10 U5501
E11 E10 SDRAM_DDR_4MX32
FBBA<0> N5 A0 BGA
L4 VDD K6
L4 VDD K6 55 53 52 (1 OF 2)
VSS 55 53 52 FBBA<0> N5 A0
BGA
(1 OF 2)
VSS 55 53 52 FBBA<1> N6 A1 DQ0 B7 RFBD<71> 53 L7 K7
L7 K7 OMIT 55 53 52 FBBA<1> N6 A1 OMIT DQ0 B7 RFBD<113> 53
55 53 52 FBBA<2> M6 A2 DQ1 C6 RFBD<69> 53 L8 K8
L8 K8 55 53 52 FBBA<2> M6 A2 DQ1 C6 RFBD<114> 53
55 53 52 FBBA<3> N7 A3 DQ2 B6 RFBD<70> 53 L11 K9
L11 K9 55 53 52 FBBA<3> N7 A3 DQ2 B6 RFBD<112> 53
L5 55 53 52 FBBA<4> N8 A4 DQ3 B5 RFBD<68> 53
C3
L5
N8 B5
55 53 52 FBBA<4> A4 DQ3 RFBD<115> 53
C3 55 53 52 FBBA<5> M9 A5 DQ4 C2 RFBD<65> 53 L10
C5
L10
N9 D3
C5 55 53 52 FBBA<5> M9 A5 DQ4 C2 RFBD<117> 53
55 53 52 FBBA<6> A6 DQ5 RFBD<67> 53
C7 F6 55 53 52 FBBA<6> N9 A6 DQ5 D3 RFBD<116> 53
C7 F6 55 53 52 FBBA<7> N10 A7 DQ6 D2 RFBD<66> 53
C8 F7 N10 D2
55 53 52 FBBA<7> A7 DQ6 RFBD<118> 53
C8 F7 55 53 52 FBBA<8> N11 A8 DQ7 E2 RFBD<64> 53
C10 F8 M8 K13
C10 F8 55 53 52 FBBA<8> N11 A8 DQ7 E2 RFBD<119> 53
55 53 52 FBBA<9> A9 DQ8 RFBD<95> 53
C12 F9 55 53 52 FBBA<9> M8 A9 DQ8 K13 RFBD<97> 53
C12 F9 55 53 52 FBBA<10> L6 A10 DQ9 K12 RFBD<94> 53
E3 G6 L6 K12
55 53 52 FBBA<10> A10 DQ9 RFBD<96> 53
E3 G6 55 53 52 FBBA<11> M7 A11 DQ10 J13 RFBD<93> 53
E12 G7 J12
E12 G7 55 53 52 FBBA<11> M7 A11 DQ10 J13 RFBD<99> 53
DQ11 RFBD<92> 53 VDDQ
VDDQ 53 RFBDQS<8> B2 DQS0 F4 G8 DQ11 J12 RFBD<98> 53
F4 G8 DQ12 G13 RFBD<91> 53 53 RFBDQS<14> B2 DQS0
53 RFBDQS<11> H13 DQS1 F11 VSS_THERM G9 DQ12 G13 RFBD<100> 53
F11 VSS_THERM G9 DQ13 G12 RFBD<90> 53 53 RFBDQS<12> H13 DQS1
53 RFBDQS<9> H2 DQS2 G4 H6 DQ13 G12 RFBD<101> 53
G4 H6
B13 DQ14 F13 RFBD<89> 53
G11 H7 53 RFBDQS<15> H2 DQS2 F13
53 RFBDQS<10> DQS3 DQ14 RFBD<102> 53
C G11
J4
H7
H8 53 52 FBDQM<8> B3 DM0
DQ15
DQ16
F12
F3
RFBD<88>
RFBD<79>
53
53
J4
J11
H8
H9
53
53 52
RFBDQS<13>
FBDQM<14>
B13
B3
DQS3
DM0
DQ15
DQ16
F12
F3
RFBD<103>
RFBD<121>
53
53
C
J11 H9 53 52 FBDQM<11> H12 DM1 DQ17 F2 RFBD<78> 53
K4 J6 H12 F2
53 52 FBDQM<12> DM1 DQ17 RFBD<120> 53
K11 J7 B12 G2
53 52 FBDQM<10> DM3 DQ19 RFBD<76> 53
J8 53 52 FBDQM<13> B12 DM3 DQ19 G2 RFBD<123> 53
N13
J8
N4 DQ20 J3 RFBD<74> 53 55 SGRBVREF N13 VREF J9 J3
55 SGRBVREF VREF 55 53 52 FBBA<12> BA0 DQ20 RFBD<126> 53
J9 DQ21 J2 RFBD<75> 53 55 53 52 FBBA<12> N4 BA0
55 53 52 FBBA<13> M5 BA1 K2 B4 M5
DQ21 J2 RFBD<124> 53
DQ22 RFBD<72> 53 GPU128BIT 55 53 52 FBBA<13> BA1
GPU128BIT B4 DQ22 K2 RFBD<125> 53
53 52 FBBCLK0 M11 CK DQ23 K3 RFBD<73> 53
1 C5535 B11
1 C5534 B11
0.1UF 53 52 FBBCLK1 M11 CK DQ23 K3 RFBD<127> 53
0.1UF 53 52 FBBCLK0_L M12 CK DQ24 E13 RFBD<87> 53 D4
D4 20%
53 52 FBBCLK1_L M12 CK DQ24 E13 RFBD<104> 53
20%
D5 55 52 FBBCKE N12 CKE DQ25 D13 RFBD<86> 53 2
10V D5
N12 D13
2
10V CERM
55 52 FBBCKE CKE DQ25 RFBD<105> 53
CERM
55 52 FBBCS0_L N2 CS DQ26 D12 RFBD<85> 53
402 D6
402 D6
M2 C13 D9 55 52 FBBCS0_L N2 CS DQ26 D12 RFBD<106> 53
55 52 FBBRAS_L RAS DQ27 RFBD<84> 53
D9 55 52 FBBRAS_L M2 RAS DQ27 C13 RFBD<107> 53
D10 55 52 FBBCAS_L L2 CAS DQ28 B10 RFBD<83> 53 D10
L2 B10
55 52 FBBCAS_L CAS DQ28 RFBD<108> 53
55 52 FBBWE_L L3 WE DQ29 B9 RFBD<81> 53 D11
D11
C9 E6 55 52 FBBWE_L L3 WE DQ29 B9 RFBD<110> 53
DQ30 RFBD<82> 53
E6 C4 VSSQ DQ30 C9 RFBD<109> 53
VSSQ E9 C11
DQ31 B8 RFBD<80> 53 E9 C4
B8
F5 C11 DQ31 RFBD<111> 53
F5 H4 MCL M13
F10 H4 M13
F10 H11
MCL
RFU1 L9 TP_U5500_RFU1 NO_TEST G5 H11
G5 L12
NC RFU1 L9 TP_U5501_RFU1 NO_TEST
RFU2 M10 TP_U5500_RFU2 NO_TEST G10 L12
NC
G10 L13
H5 L13
RFU2 M10 TP_U5501_RFU2 NO_TEST
H5 M3
H10 M3
H10 M4
J5 M4
J5 N3
J10 N3
J10
K5
K5
K10
B K10
B
55 54 52 7 PP2V5_GPU
55 54 52 7 PP2V5_GPU
GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT
1 C5526 1 C5508 1 C5509 1 C5527 1 C5510 1 C5511 1 C5528 1 C5512 1 C5513 1 C5529 1 C5530 1 C5502 1 C5503 1 C5531 1 C5504 1 C5505 1 C5532 1 C5506 1 C5507 1 C5533
0.001UF 0.1UF 0.1UF 0.001UF 0.1UF 0.1UF 0.001UF 0.1UF 0.1UF 0.001UF 0.001UF 0.1UF 0.1UF 0.001UF 0.1UF 0.1UF 0.001UF 0.1UF 0.1UF 0.001UF
10% 20% 20% 10% 20% 20% 10% 20% 20% 10% 10% 20% 20% 10% 20% 20% 10% 20% 20% 10%
50V 10V 10V 50V 10V 10V 50V 10V 10V 50V 50V 10V 10V 50V 10V 10V 50V 10V 10V 50V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
DDR SDRAM B VREF EVENLY PLACE 0.1UF CAP & 0.01 UF CAPS
55 54 52 7 PP2V5_GPU
1GPU128BIT
R5500
1K
1%
1/16W
MF-LF
GPU DDR SDRAM B
2 402
A GPU128BIT
GPU128BIT
SGRBVREF
VOLTAGE=1.25V
55
SYNC_MASTER=N/A

SYNC_DATE=N/A
A
R5501 1 C5517 MIN_NECK_WIDTH=0.25MM
1K 0.1UF THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1%
20%
1/16W 10V AGREES TO THE FOLLOWING
MF-LF 2
SGRAM0 & SGRAM1 MEMORY SUPPORT 2 402
CERM
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
333S0251 2 SDRAM,4MX32,DDR,300MHZ U5500,U5501 CRITICAL SAMSUNG64
333S0252 2 SDRAM,4MX32,DDR,300MHZ U5500,U5501 CRITICAL HYNIX64
APPLE COMPUTER INC.
D 051-6772 E
333S0341 2 SDRAM,8MX32,DDR,300MHZ U5500,U5501 CRITICAL HYNIX128
SCALE SHT OF
NONE 55 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
PP3V3_GPU 49 50 56 58 59
APPLE GPIO ATI STRAP PIN DESCRIPTION DEFAULT

1
R56001R5602
10K 10K GPU_GPIO<9>
5% 5% 58
1/16W 1/16W
MF-LF MF-LF 58 GPU_GPIO<13> AGPFBSKEW(1:0) GPIO(1:0) AGP 1X CLOCK FEEDBACK PHASE ADJUSTMENT WRT REFCLK (CPUCLK) 00
2 402 2 402 GPU_GPIO<12> 00 - REFCLK SLIGHTLY EARLIER THEN FEEDBACK
58 GPU_GPIO<0>
58
58 GPU_GPIO<11> 58 GPU_GPIO<8> 01 - REFCLK 1 TAP EARLIER THEN FEEDBACK

INTERNAL
58 GPU_GPIO<1>
NOSTUFF NOSTUFF NOSTUFF 10 - REFCLK 1 TAP LATER THEN FEEDBACK PULL-DOWN
1
R56011R5603 R56041R56051R56061R5607
1
R56231 11 - REFCLK 2 TAPS EARLIER THEN FEEDBACK CLOCK (ATI RECOMMENDED)
10K 10K 10K 10K 10K 10K 10K
D 5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF
1%
1/16W
MF-LF
D
2 402 2 402 2 402 2 402 2 402 2 402 402 2 X1CLK_SKWE(1:0) GPIO(3:2) CLOCK PHASE ADJUSTMENT BETWEEN X1 CLK AND X2CLK 00
00 - 0 TAP DELAY INTERNAL
PULL-DOWN
ROMIDCFG(3:0) GPIO(9,13:11) IF NO ROM ATTACHED, CONTROLS CHIP IDS. IF ROM- IDENTIFIES TYPE
0X0X - NO ROM, CHG_ID=0
59 56 50 48 7 =PP3V3_AGP 59 56 50 48 7 =PP3V3_AGP ID_DISABLE GPIO(8) STRAP 0

59 56 FPD_PWR_ON 0 - NORMAL OPERATION INTERNAL PULL-DOWN
1 C5600 NOSTUFF NOSTUFF
1 - SHUTS THE CHIP DOWN BY NOT RESPONDING TO ANY CONFIG CYCLES
0.1UF R5625 1
R5626
1
20% 0 0
2 10V
CERM 5% 5%
402 1/16W 1/16W
MF-LF MF-LF
402 2 2 402
PCI_RESET_L 1
5
R5611 BUSCFG(2:0) GPIO(6:4) AGP8X_DETB BUSCFG[2:0] AGPMODE SIGNALING IDSEL 000
74 56 8 6
4 47
U5600 LCD_PWM_U5600 1 2 LCD_PWM 59 0 000 AGP8X 0.8V AD16 INTERNAL
58 ATI_PWM 2 5% PULL-DOWN
1/16W
NOSTUFF MC74VHC1G08
3 SOT23-5 R5610 1 MF-LF
402
R5624
1 10K
1%
MULTIFUNC(1:0) LCDDATA(17:16) MULTI-FUNCTION DEVICE SELECT 00
10K 1/16W 00 - SINGLE FUNCTION DEVICE.
1% MF-LF
1/16W 402 2 01 - TWO FUNCTION DEVICE. NO AGP IN EITHER FUNCTION
MF-LF NOSTUFF
2 402 10 - TWO FUNCTION DEVICE. AGP ONLY IN FUNCTION 0
R5609 11 - TWO FUNCTION DEVICE. AGP IN BOTH FUNCTIONS
1
0 2 IF BUSCFG PIN BASED STRAPS ARE SET TO PCI, THEN AGP WILL NOT BE
C 5%
1/16W
MF-LF
ENABLED IN ANY FUNCTION. C
402
MEMSTRAP(1:0) GPU_GPIO<15,10> 00 - SAMSUNG 4MX32
NOSTUFF 01 - UNDEFINED
R5629 10 - HYNIX 4MX32
PCI_SLOTF_GNT_L 1
0 2
11 - HYNIX 8MX32
25
5%
1/16W
MF-LF
402
INV_CUR_HI GPIO<7> OUTPUT: GPU READS PANEL ID AND SETS THIS BIT ACCORDINGLY
FOR REFERENCE ONLY, ACTIONS COME FROM BOOTROM
SYSTEM PANEL ID INV_CUR_HI

Q45 A 0X9C27 1
PP3V3_GPU 49 50 56 58 59 PP3V3_GPU 49 50 56 58 59 0X9C38 0
NOSTUFF NOSTUFF HYNIX128&HYNIX64 HYNIX128
Q45 B 0X9C3A 1
R5612 R5614
1 1
R5618
1
R5616
1
10K 10K 10K 10K 0X9C39 0
5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF
2 402 2 402 2 402 2 402 Q45 C TBD 1
58 GPU_LCDDATA<16> 58 GPU_GPIO<15>
58 GPU_LCDDATA<17> 58 GPU_GPIO<10>
SAMSUNG64 SAMSUNG64&HYNIX64
TBD 0
R56131R5615
1
R5619
1
R5617
1
Q45 D 0X9C3A 1
10K 10K 10K 10K
5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W
2 402 2 402 2 402 2 402 Q45 A/B SUPPORT IS FOR DEVELOPMENT
B B
FPD_PWR_ON GPIO<16> OUTPUT: PANEL POWER SEQUENCING
TMDS_EN GPIO<14> INPUT: PANEL POWER SEQUENCING

R5620
GPU_GPIO<7> 1
47 2 INV_CUR_HI
58 59
5%
1/16W
MF-LF
402
59 56 50 48 7 =PP3V3_AGP
PP3V3_GPU 49
1 C5601 50 56 58 59
0.1UF NOSTUFF
20%
2 10V
CERM
1
R5627
402 10K
5%
1/16W
5 MF-LF
2 402
74 56 8 6 PCI_RESET_L 1
4 FPD_PWR_ON
58 GPU_GPIO<14> R5622
47
2
U5601 56 59
1 2 TMDS_EN 59
58 GPU_GPIO<16> NOSTUFF
5%
3 MC74VHC1G08
SOT23-5
1
R5628 1/16W
MF-LF
10K
5%
1/16W
402
GPU STRAPS
MF-LF
A NOSTUFF 2 402 SYNC_MASTER=N/A SYNC_DATE=N/A
A
R5621
0
1 2 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
5% AGREES TO THE FOLLOWING
1/16W
MF-LF I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
402
APPLE COMPUTER INC.

D 051-6772 E
SCALE SHT OF
NONE 56 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
DIFFERENTIAL IMPEDANCE SHOULD BE 100 OHM
59 58 56 50 49 PP3V3_GPU
ELECTRICAL_CONSTRAINT_SET NET_PHYSICAL_TYPE NET_SPACING_TYPE DIFFERENTIAL_PAIR NOSTUFF
AD19
AD21
AD22
AC21
AC22
AC19
AC10
AD10
C5800 C5801 C5802 C5803
AD7
AC8
AC9
AD9
AG7
1 1 1 1
59 58 TMDS_CKP TMDS GPU_TMDS GPU_TMDS TMDS_CK I572

10UF 1UF 1UF 1UF
20% 10% 10% 10%
59 58 6 TMDS_CKM GPU_TMDS GPU_TMDS TMDS_CK I573 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
59 58 TMDS_D0P TMDS GPU_TMDS GPU_TMDS TMDS_D0 I575
VDDR3 VDDR4 805 402 402 402
56 GPU_GPIO<0> AJ5 0 OMIT
TMDS_D0M GPU_TMDS GPU_TMDS TMDS_D0
U4900
59 58 I574
56 GPU_GPIO<1> AH5 1
59 58 TMDS_D1P TMDS GPU_TMDS GPU_TMDS TMDS_D1 I576 0 AH6 TP_GPU_LCDDATA<0>
TP_GPU_GPIO<2> AJ4 2
TMDS_D1M GPU_TMDS GPU_TMDS TMDS_D1 1 AJ6 TP_GPU_LCDDATA<1>
59 58 6
59 58 TMDS_D2P TMDS GPU_TMDS GPU_TMDS TMDS_D2

I577
I578
TP_GPU_GPIO<3>
TP_GPU_GPIO<4>
AK4
AH4
3
4
RV351 2 AK6 TP_GPU_LCDDATA<2>
TMDS_D2M GPU_TMDS GPU_TMDS TMDS_D2 BGA 3 AH7 TP_GPU_LCDDATA<3>
D
59 58
59 58 6 ANALOG_GRN GPU_VGA_37P5 GPU_VGA_37P5

I579
I589
TP_GPU_GPIO<5>
TP_GPU_GPIO<6>
AF4
AJ3
5
6
(5 OF 5) 4 AK7 TP_GPU_LCDDATA<4>
AJ7 TP_GPU_LCDDATA<5>
D
59 58 6 ANALOG_RED GPU_VGA_37P5 GPU_VGA_37P5 I590 5
AK3
GPIO
56 GPU_GPIO<7> 7
59 58 6 ANALOG_BLU GPU_VGA_37P5 GPU_VGA_37P5 I591 6 AH8 TP_GPU_LCDDATA<6>
7 AJ8 TP_GPU_LCDDATA<7>
GPU_GPIO<9> AJ2 9
EXTERNAL TMDS
56
8 AH9 TP_GPU_LCDDATA<8>
9 AJ9 TP_GPU_LCDDATA<9>
10 AK9 TP_GPU_LCDDATA<10>
LCDDATA
56 GPU_GPIO<12> AG3 12
11 AH10 TP_GPU_LCDDATA<11>
12 AE6 TP_GPU_LCDDATA<12>
13 AG6 TP_GPU_LCDDATA<13>
56 GPU_GPIO<15> AF3 15
14 AF6 TP_GPU_LCDDATA<14>
56 GPU_GPIO<16> AF2 16
1
R5814 15 AE7 TP_GPU_LCDDATA<15>
1M 16 AF7 GPU_LCDDATA<16> 56 PP3V3_GPU 49 50 56 58 59
5%
1/16W 17 AE8 GPU_LCDDATA<17> 56
Y5800 R5815
MF-LF
2 402 GPU_CLK27M_XIN AH28 XTALIN
18 AG8 TP_GPU_LCDDATA<18>
CLK
SM-3
249 19 AF8 TP_GPU_LCDDATA<19> 8 7 6 5
RP5810 RP5810 RP5810 RP5810 R5818
AJ29 1
1 3 GPU_CLK27M_XOUT_R 1 2 GPU_CLK27M_XOUT XTALOUT AE9 TP_GPU_LCDDATA<20>
20
1% GPU_TESTEN
4.7K 4.7K 10K 4.7K 4.7K
C5814 1
27.000M
1 C5815 1/16W
MF-LF
21 AF9 TP_GPU_LCDDATA<21>
5% 5% 5% 5%
5%
1/16W
22PF 22PF 402 1 AG10 TP_GPU_LCDDATA<22> 1/16W 1/16W 1/16W 1/16W
5% 5% R5830 22 SM-LF SM-LF SM-LF SM-LF
MF-LF
50V 50V 100 B6 TEST_MCLK 23 AF10 TP_GPU_LCDDATA<23> 2 402
CERM 2 2 CERM 1 2 3 4
TEST
603 603 5%
1/16W E8 TEST_YCLK
MF-LF 0 AJ10 GPU_LCDCNTL<0>
2 402 NC AE25 PLLTEST AK10
1 GPU_LCDCNTL<1>
AH27 TESTEN
59 58 56 50 49 PP3V3_GPU LCDCNTL 2 AJ11 GPU_LCDCNTL<2>
3 AH11 GPU_LCDCNTL<3>
R5816 1 58 GPU_DIODE_PLUS AF11 DPLUS
1K 58 GPU_DIODE_MINUS AE11 DMINUS DVOMODE AE10
1%
C 1/16W
MF-LF
402 2
AG29 RSTB_MSK R5819
0
C
GPU_VREFG AG4 VREFG HPD1 AF12 MON_DETECT_R 1 2 MON_DETECT 6 59
R58171 1 C5817 1/16W
MF-LF
1K 0.1UF AF17 AE12 402
1%
1/16W
MF-LF
20%
10V
2 CERM
AF18 AE18 GPU THERMAL SENSOR
402 2 56 ATI_PWM AG12 AH18
402
AG16 AH30 27 18 11 6 PP3V3_PWRON
AG17 AJ16
AG19 NC AJ17 DEVELOPMENT DEVELOPMENT DEVELOPMENT DEVELOPMENT
NC NO CONNECTS
L5835 PP1V8_GPU_TXVDDR
AG20 AJ18 1 C5890 1 C5891 1
R5891 1
R5892
FERR-220-OHM VOLTAGE=1.8V
51
AH16 AJ25 0.1UF 100PF 10K 10K
52 51 50 =PP1V8_GPU MIN_LINE_WIDTH=0.5MM 20% 5% 5% 5%
1 2 MIN_NECK_WIDTH=0.25MM AH17 AK16 2 10V
CERM 2 50V
CERM 1/16W 1/16W
AH19 AK19 402 402 MF-LF MF-LF
0805 NOSTUFF 2 402 2 402
1 C5835 1 C5836 1 C5837 AH20 AF16
1
10UF 1UF 0.1UF AH29
XW5835
SM
20%
6.3V
2 CERM
10%
6.3V
2 CERM
20%
10V
2 CERM
THE FREQUENCY OF THE 20" PIXEL CLOCK IS 119 MHZ
VDD
805 402 402 AF13 AK13 DEVELOPMENT ALERT*/ 6
1 2 GND_GPU_TXVSSR TXCP TMDS_CKP 58 59
TACH U5890_ALERT_L
VOLTAGE=0V
AF14 TXVDDR TXCM* AH13 TMDS_CKM 6 58 59
58 GPU_DIODE_PLUS 2 D+ U5890 PWM 4 U5890_PWM
TX0P AH14 TMDS_D0P
NOSTUFF AG13 58 59
DEVELOPMENT 3 D- LM63CIMA
L5830 PP1V8_GPU_TPVDD 50
AG14 TX0M* AJ13 TMDS_D0M 58 59
C5892 1 SOI SMBCLK 8 I2C_GPU_DIODE_SCL 18
1.8UH VOLTAGE=1.8V
TXVSSR TX1P AH15 TMDS_D1P SMBDA 7 I2C_GPU_DIODE_SDA
2200PF 18
1 2 MIN_NECK_WIDTH=0.25MM AH12
TMDS TX1M* AJ14 TMDS_D1M 6 58 59
5%
50V
NOSTUFF CERM 2 GND
0805 TX2P AK15 TMDS_D2P
1 C5830 1 C5831 1 C5832 1 C5833 TX2M* AJ15 TMDS_D2M
58 59 603
5
10UF 1UF 1UF 0.1UF 58 59
XW5830 20%
6.3V
10%
6.3V
10%
6.3V
20%
10V
AK12 TPVDD
75MA MAX DDC2CLK AE13 I2C_GPU_TMDS_SCL 59
58 GPU_DIODE_MINUS
B 1
SM
2 GND_GPU_TPVSS
VOLTAGE=0V
2 CERM
805
2 CERM
402
2 CERM
402
2 CERM
402 AJ12 TPVSS DDC2DATA AE14 I2C_GPU_TMDS_SDA 59 B
MIN_LINE_WIDTH=0.5MM GPU_DAC1_VSYNC
L5840 MIN_NECK_WIDTH=0.25MM
AE24 VDD1DI R AK27 NC DEVELOPMENT
1
FERR-220-OHM AE22 VDD2DI G AJ27 NC R5826
1 2
75 GPU_RSET
PP1V8_GPU_VDDDI
AE23 B AJ26 NC 1% MIN_LINE_WIDTH=0.5MM
0805
VOLTAGE=1.8V NOSTUFF VSS1DI HSYNC AG25 TP_HSYNC
1/16W MIN_NECK_WIDTH=0.25MM
MIN_NECK_WIDTH=0.25MM 1 C5840 1 C5841 AE21 VSS2DI
MF-LF
402 2
10UF 1UF DAC1 VSYNC AH25 GPU_STEREOSYNC
R5820
1
XW5840 20%
2 6.3V
10%
2 6.3V 499
SM CERM
805
CERM
402
RSET AH26
R58251 1%
1 2 GND_GPU_VSSDI 10K 1/16W
AH24 AVDD DDC1CLK AF24 TP_DDC1CLK
VOLTAGE=0V
DDC1DATA AF25 TP_DDC1DATA
5%
1/16W XW5847 MF-LF
2 402
GND_GPU_AVSSQ AD24 AVSSQ
MF-LF
402 2
SM
1 2 GND_GPU_AVSSQ
FERR-220-OHM 58
AUXWIN AF26 NC
58
1 2 AH23 STEREOSYNC AG26

PP1V8_GPU_AVDD AVSSN
0805 VOLTAGE=1.8V NOSTUFF
MIN_NECK_WIDTH=0.25MM 1 C5845 1 C5846 AG21 Y_G AJ22 ANALOG_GRN
10UF 1UF 6 58 59
XW5845
SM
20%
6.3V
2 CERM
10%
6.3V
2 CERM
AH21 A2VDD C_R AJ23 ANALOG_RED
ROUTE SIGNALS AT 37.5 OHMS
6 58 59
COMP_B AK22 ANALOG_BLU 6 58 59

1 2 GND_GPU_AVSSN 805 402 AH22
VOLTAGE=0V H2SYNC AJ24 ANALOG_HSYNC
AJ21 A2VSSN 59
MIN_NECK_WIDTH=0.25MM DAC2 V2SYNC AK24 ANALOG_VSYNC 59
R5821 1R5822 1R5823
1
51 50 PP2V5_GPU_A2VDD R2SET AK21 75 75 75

1% 1% 1%
AF22 A2VDDQ 1/16W 1/16W 1/16W
NOSTUFF DDC3CLK AG23 I2C_GPU_MON_SCL 59 MF-LF MF-LF MF-LF
1 C5855 1 C5856 AF23 A2VSSQ DDC3DATA AG24 I2C_GPU_MON_SDA 59
2 402 2 402 2 402
XW5855 VOLTAGE=0V 20%

10UF
6.3V
10%
1UF
6.3V
GPU DVI & DACS
SM MIN_LINE_WIDTH=0.5MM 2 CERM 2 CERM
A 1 2
GND_GPU_A2VSSN
805 402 GPU_R2SET
PLACE R5821-3 & FL5900-2 NEAR MINI-VGA CONNECTOR
SYNC_MASTER=N/A

SYNC_DATE=N/A
A
ROUTE GND IN BETWEEN RGB SIGNALS WITH A VIA EVERY INCH
L5865
FERR-220-OHM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1 2 PP1V8_GPU_A2VDDQ R5824
1 AGREES TO THE FOLLOWING
0805 VOLTAGE=1.8V NOSTUFF 715 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

1%
MIN_NECK_WIDTH=0.25MM 1 C5865 1 C5866 1/16W
MF-LF
10UF 1UF
XW5865
SM
20%
2 6.3V
10%
2 6.3V
2 402 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
CERM CERM
805 402 SIZE DRAWING NUMBER REV.
1 2 GND_GPU_A2VSSQ
VOLTAGE=0V
MIN_NECK_WIDTH=0.25MM APPLE COMPUTER INC.
D 051-6772 E
SCALE SHT OF
NONE 58 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
PLACE R5901-R5904 AS CLOSE TO GPU AS POSSIBLE
NOSTUFF
59 56 50 48 7 =PP3V3_AGP EXTERNAL VGA CONNECTOR R5926 02 PP3V3_GPU R5982 PP3V3_DDC
59 58 56 50 49 6 59
U5970 58 TMDS_D2M 1
1
0 2
1 C5970 14 74LCX125 5%
CRITICAL 0.1UF 12 11
L5902
90-OHM 1
SYM_VER-1
4
R59051 1
R5907 1/8W
MF-LF 1 C5901
0.01UF
20% 1 TD2M 2.0K 2.0K 805
U5970 10V
2 CERM 125 R5904
SM
6 59
5% 5% 10%
14 74LCX125 402 R5971 59 56 50 48 7 =PP3V3_AGP

7 13 TSSOP 332
1%
1/16W
MF-LF
1/16W
MF-LF
2 16V
CERM
2 3 33 1/16W 2 3 402 2 2 402

402
58 ANALOG_VSYNC VGA_VSYNC 1 2 VGA_VSYNC_R 6 59 MF-LF TD2P 6 59
125 2 402 NOSTUFF R5900
5%
7 1 TSSOP 1/16W R5927 02 33
MF-LF 58 TMDS_D2P 1 58 I2C_GPU_TMDS_SCL 1 2 I2C_TMDS_SCL 6 59
402
5%
R5906 1/16W
NOSTUFF 33
D
MF-LF
I2C_GPU_TMDS_SDA 1 2 I2C_TMDS_SDA
D R5928 58 402 6 59
92 PP5V_USB2 R5980 PP5V_VGA 59
TMDS_D1M 1
02
U5970 0
VOLTAGE=5V
58 6 5%
1/16W
14 74LCX125 R5972 1 2 MIN_NECK_WIDTH=0.25MM

1
R5903 L5908
MF-LF
402
33 5% SYM_VER-1
58 ANALOG_HSYNC 5 6 VGA_HSYNC 1 2 VGA_HSYNC_R 6 59 1/8W
MF-LF
1 C5902 332 4 1
90-OHM
SM
TD1M
125 5% NOSTUFF NOSTUFF 805 0.01UF 1%
1/16W
59
7 4 TSSOP 1/16W 10%

MF-LF
402
C5907 1 1 C5908 16V
2 CERM 2
MF-LF
402 INTERNAL TMDS CONNECTOR
22PF 22PF 402 3 2 TD1P 6 59
5% 5% NOSTUFF SDF5900
50V 50V 0
CERM 2
402
2 CERM
402 GND_CHASSIS_VGA 7 59
R5929 STDOFF-118OD-181H-TH
NOSTUFF 58 TMDS_D1P 1 2
FL5900 GND_CHASSIS_VGA 7 59 NOSTUFF 1
LCFILTER R5930 02 CRITICAL

SM-220MHZ 58 TMDS_D0M 1 (516S0241)
ANALOG_RED 1 2 J5902
58 6
L5909 53307-3072
3 4
CRITICAL U5970 1 90-OHM 1
SYM_VER-1
4 TD0M
F-ST-SM PPVCC_TMDS
VOLTAGE=3.3V
6 59
14 74LCX125 R5902 6 59
(514-0201) SM
1 2
9 8
R5940 J5903 59 56 FPD_PWR_ON LED5900_PWR 1%
1/16W 2 3
3 4
0 DV01793 125
R5912
1 MF-LF TD0P 6 59 5 6
1 2 7 10 TSSOP 2 402 NOSTUFF
402 15
F-ST-TH
330 R5931 0 7 8 PP3V3_DDC 6 59
NOSTUFF 5% VOLTAGE=3.3V
FL5901 16
1/10W 58 TMDS_D0P 1 2 59 6 TD0M 9 10
MF-LF NOSTUFF MIN_NECK_WIDTH=0.25MM
LCFILTER 2 603 R5932 02
59 6 TD0P 11 12
SM-220MHZ
1
LED5900_P1 58 6 TMDS_CKM 1 13 14 TCKM 59
58 6 ANALOG_GRN 1 2 2 VGA_VSYNC_R 6 59 59 6 TD2M 15 16 TCKP 6 59

59 6 VGA_HSYNC_R 3 1 L5910
FILT_ANALOG_RED 5
4 (RED_RTN)
LED5900 1 90-OHM
SYM_VER-1 59 6 TD2P 17 18
3 4 GREEN R5901 SM 1 4
6 (GRN_RTN) TCKM 59 19 20 TD1M 59
FILT_ANALOG_GRN 7 2.0X1.25A 332
TD1P
R5941 FILT_ANALOG_BLU 9
8 PP5V_VGA 59 2 1%
1/16W
21 22
6 59
0 10 I2C_MON_SDA_R 59 MF-LF
2 3 59 6 I2C_TMDS_SDA 23 24 I2C_TMDS_SCL 6 59
1 2 59 I2C_MON_SCL_R 11
12(BLU_RTN) 2 402
TCKP 6 59
26
SILKSCREEN: 3 NOSTUFF 25
C 402 NOSTUFF
FL5902
LCFILTER
58 6 MON_DETECT 13
14
1 C5905 1 C5904 1 C5903 58 TMDS_CKP
R5933
1
0
2
27
29
28
30 1 C5916 1 C5900
C
0.01UF 0.01UF 0.01UF
SM-220MHZ 17 10% 10% 10% 10UF 0.01UF
2 16V
2 16V
2 16V
NET_PHYSICAL_TYPE NET_SPACING_TYPE DIFFERENTIAL_PAIR 10% 10%
58 6 ANALOG_BLU 1 2 18 CERM CERM CERM
2 16V 2 16V
402 402 402 CERM CERM
7 6 GND_CHASSIS_TMDS 1210 402
3 4 GND_CHASSIS_VGA 7 59 59 6 TCKP GPU_TMDS GPU_TMDS TCK I885
59 TCKM GPU_TMDS GPU_TMDS TCK I887 SDF5901
STDOFF-118OD-181H-TH
R5942 59 6 TD0P GPU_TMDS GPU_TMDS TD0 I886
1
0 2
59 6 TD0M GPU_TMDS GPU_TMDS TD0 I888
1
59 6 TD1P GPU_TMDS GPU_TMDS TD1 I889

402 PLACE R5821-3 & FL5900-2 CLOSE TO J5903 ON BOTTOM SIDE OF BOARD
59 TD1M GPU_TMDS GPU_TMDS TD1 I890
TABLE FOR PANEL POWER SEQUENCING (LOWER LEFT)
TABLE_5_HEAD
59 6 TD2P GPU_TMDS GPU_TMDS TD2 I892
59 58 56 50 49 PP3V3_GPU PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION 59 6 TD2M GPU_TMDS GPU_TMDS TD2 I891
59 PP5V_VGA TABLE_5_ITEM
59 6 FILT_ANALOG_GRN GPU_VGA_75 GPU_VGA I893

116S0090 1 RES,10K OHM,1/16W,5%,0402 R5913 17_INCH_LCD
TABLE_5_ITEM
59 6 FILT_ANALOG_RED GPU_VGA_75 GPU_VGA I895
R5973 1 1
R5974 R5977 1 1
R5978 116S0114 1 RES,100K OHM,1/16W,5%,0402 R5913 20_INCH_LCD 59 6 FILT_ANALOG_BLU GPU_VGA_75 GPU_VGA I894
10K 10K 4.7K 4.7K TABLE_5_ITEM
5% 5% 2 5% 5% 376S0082 1 XSTR,MOSFET,P-CH,0.007OHM Q5900 17_INCH_LCD

1/16W
MF-LF
1/16W
MF-LF
Q5975 1/16W
MF-LF
1/16W
MF-LF
DEVELOPMENT
2N7002DW
TABLE_5_ITEM
G
402 2 2 402 SOT-363 R5975 402 2 2 402 376S0225 1 XSTR,MOSFET,P-CH,0.02OHM Q5900 20_INCH_LCD
Q5903 INVERTER INTERFACE 17_INCH_LCD
CRITICAL
I2C_GPU_MON_SCL 1 S D 6 I2C_MON_SCL 1
100 2 I2C_MON_SCL_R SI3433DV =PP12V_AGP J5900
58 59 59 50 7 17_INCH_LCD 20" LCD INVERTER NEED +24V.
TSOP 1 17" LCD INVERTER NEED +12V. 90147-1106
5%
1/16W R5984 F-ST-TH
MF-LF
402
2
1
0 2 PP12V_INV 1
5
Q5975 =PP5V_AGP
5
805
VOLTAGE=12V
MIN_LINE_WIDTH=2MM
GND_17_INV 2
G 2N7002DW 50 7
3 6 MIN_NECK_WIDTH=0.25MM VOLTAGE=0V 6
SOT-363 R5976 Q5903_GATE 17_INCH_LCD

R5985 VOLTAGE=5V
MIN_LINE_WIDTH=2MM
MIN_NECK_WIDTH=0.25MM 6 PP5V_AGP_RL 3
100 MIN_LINE_WIDTH=2MM
4
58 I2C_GPU_MON_SDA 4 S D 3 I2C_MON_SDA 1 2 I2C_MON_SDA_R 59
4
1
0 2
MIN_NECK_WIDTH=0.25MM 6 INV_17_LCD_PWM_F
DEVELOPMENT 5
5%
R5920 LAMP_STS NOT USED ON Q45C NC
B 1/16W
MF-LF
402 C5977 1 1 C5978 1
100K 2
DEVELOPMENT
805
6 INV_17_CUR_HI_F 6 B
47PF 47PF 5%
DEVELOPMENT R5986 516-0114
5%
50V
5%
50V 1/16W 1
R5921 0
CERM 2 2 CERM MF-LF PP5V_AGP_P_SEQ 1 2
402 402
402 10K MIN_LINE_WIDTH=2MM PIN 3 IS NC
5% MIN_NECK_WIDTH=0.25MM 805
PP3V3_RUN PP12V_RUN 59 50 7 =PP12V_AGP 1/16W 17_INCH_LCD ON Q45C
59 11 7 PP3V3_ALL
GND_CHASSIS_VGA 7 59
DEVELOPMENT
MF-LF
2 402
R5987 INVERTER
0
NOSTUFF 17_INCH_LCD 20_INCH_LCD 1
R5919 3 NOSTUFF Q5902_DRAIN 59 56 LCD_PWM 1 2
LEAVING CONNECTED
1
R5950
1
R5923
1
R5922 PPVCC_FPD
5%
200K D5901
MMBD914XXG
3
DEVELOPMENT
805
DURING DEVELOPMENT
0 0 0 1/16W SOT23 D Q5902 17_INCH_LCD
5%
1/4W
5%
1/4W
5%
1/4W 5 6 7 8
MF-LF
2 402
1
2N7002 R5988 SO WE CAN USE
MF-LF MF-LF MF-LF SOT23-LF 0 Q45A INVERTERS
2 1206 2 1206 2 1206
Q5902_GATE 1 G S 59 56 INV_CUR_HI 1 2
D DEVELOPMENT
OMIT DEVELOPMENT 805 17_INCH_LCD 17_INCH_LCD DEVELOPMENT 17_INCH_LCD 17_INCH_LCD
Q5900 PP3V3_RUN PP12V_RUN
1
R5916 1 C5920 2 17_INCH_LCD DEVELOPMENT 1
C5910 1
C5913 1
C5911 1
C5912 1
C5915
100K 0.1UF
1
C5921 1
C5922
4
IRF7410 5% 20% 10UF 10UF
0.01UF
20%
0.01UF
20%
0.01UF
20%
220PF
5%
0.01UF
20%
FPD_PWR_SW_G SO-8 1/16W 10V 50V 50V 50V 25V 50V
R5993 G MF-LF 2 CERM 20% 20% 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
2 402
16V 16V
0 S 376S0082 1NOSTUFF 1NOSTUFF R5981 402 2
ELEC
2
ELEC 603 603 603 603 603
59 56 FPD_PWR_ON 1 2
R5934 R5935 SM SM
1 2 3
0
402 0 0 1 2 PPVCC_TMDS 6 59
5% 5% 20_INCH_LCD GND_CHASSIS_17_INCH_INVERTER
FPD_PWR_SW_S 5%
7
1/4W 1/4W CRITICAL
1/8W
VOLTAGE=3.3V MIN_NECK_WIDTH=0.3MM
C5918
MF-LF
2 1206
MF-LF
2 1206
MF-LF
805
J5901
C5919 20_INCH_LCD
53048
0.01UF
0.022UF
VOLTAGE=3.3V 7 =PP24V_GRAPHICS R5989 RT-S-TH
2 1 2 1
MIN_NECK_WIDTH=0.25MM 1 2 VOLTAGE=24V 6 PP24V_INV
MIN_LINE_WIDTH=2MM 2
PP3V3_ALL 1 OMIT
59 11 7
MMBD914XXG
C5917 R5960
20% 20% 1
R5913 1 1 20_INCH_LCD
3
16V
CERM 10K
16V
CERM
D5914 10UF 10K R5990 VOLTAGE=0V
MIN_LINE_WIDTH=2MM
6 GND_20_INV
EXT VGA / TMDS AND INVERTER
1NOSTUFF
402
5%
402 SOT23
10% 5%
1
0 2
R5994 1/16W 1/16W
2 16V
A INV_20_LCD_PWM_ 5 SYNC_MASTER=N/A SYNC_DATE=N/A
MF-LF
A
MF-LF 6
4.7K R5925 3
CERM 805
5% 100K 2 402 1210 2 402 20_INCH_LCD 6 INV_20_CUR_HI_F 6
1/16W
MF-LF
1 2 FPD_PWR_ON_D R5991 NOTICE OF PROPRIETARY PROPERTY
2 402
5% TMDS_EN_R 0 518-0141
1/16W 3
59 56 LCD_PWM 1 2 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
MF-LF PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
D 805
402
Q5901 1
NOTE:REMOVED 2 PINS:LAMP_STATUS &
ON/OFF FOR 20" LCD INVETER.
R5914 20_INCH_LCD
3
2N7002
SOT23-LF 10K R5992 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOSTUFF Q5901_G 1 G S 5% 0 II NOT TO REPRODUCE OR COPY IT
D Q5990 1/16W 59 56 INV_CUR_HI 1 2
NOSTUFF
1 MF-LF III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
2N7002 R5915 2 402 NOSTUFF 20_INCH_LCD 805 20_INCH_LCD 20_INCH_LCD 20_INCH_LCD 20_INCH_LCD
2
50
10 9 8 6
46 22 11
SYS_SLEEP 1 G S
SOT23-LF
100K 56 TMDS_EN C5947 1 1 C5942 1 C5943 1 C5944 1 C5945 1 C5946 SIZE DRAWING NUMBER REV.
5% 20_INCH_LCD 1UF 1UF 0.01UF 0.01UF 220PF 0.01UF
2
1/16W
MF-LF
3 DZ5900 20%
50V
20%
50V
20%
50V
20%
50V
5%
25V
20%
50V D 051-6772 E
402
2 MMBZ5227B CERM 2 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM APPLE COMPUTER INC.
1210 1210 603 603 603 603
SOT23 SCALE SHT OF
1
GND_CHASSIS_20_INCH_INVERTER NONE 59 102
7
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
48 37 28 7 =PP1V5_PWRON_NB_AVDD R6000 64 62 60 HT_NB_TO_SB_CLK_P HT_NB_TO_SB HT_CAD HT_NB_TO_SB HT_NB_TO_SB_CLK I46

2.2 64 62 60 HT_NB_TO_SB_CLK_N HT_NB_TO_SB HT_CAD HT_NB_TO_SB HT_NB_TO_SB_CLK
1 2 PP1V5_PWRON_HT_NB_AVDD =PP2V5_HT 7 60 64
I47
VOLTAGE=1.5V MIN_LINE_WIDTH=0.6MM 64 62 60 HT_NB_TO_SB_CTL_P HT_NB_TO_SB HT_CAD HT_NB_TO_SB HT_NB_TO_SB_CTL I83
1/10W HT_NB_TO_SB_CTL_N HT_NB_TO_SB HT_CAD HT_NB_TO_SB HT_NB_TO_SB_CTL
MF-LF
603
1 C6013 1 C6012 =PP1V2_HT 7 24 60
64 62 60
HT_NB_TO_SB_CAD_P<0> HT_NB_TO_SB HT_CAD HT_NB_TO_SB HT_NB_TO_SB_CAD0

I82
1UF 0.1UF 64 62 60 I51

10% 20% 64 62 60 HT_NB_TO_SB_CAD_N<0> HT_NB_TO_SB HT_CAD HT_NB_TO_SB HT_NB_TO_SB_CAD0
2 6.3V 2 10V
I50
CERM CERM HT_NB_TO_SB_CAD_P<1>
J10
N10
402 402 64 62 60 HT_NB_TO_SB HT_CAD HT_NB_TO_SB HT_NB_TO_SB_CAD1 I52
F8
G6
T4
T8
R9
N2
N6
L9
D HT_CLK
AVDD
VDD_HT
2_5
VDD_HT
1_2
64 62 60
64 62 60
HT_NB_TO_SB_CAD_N<1>
HT_NB_TO_SB_CAD_P<2>
HT_NB_TO_SB
HT_NB_TO_SB
HT_CAD
HT_CAD
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB_CAD1
HT_NB_TO_SB_CAD2
I53
I54
D
HT_NB_TO_SB_CAD_N<2> HT_NB_TO_SB HT_CAD HT_NB_TO_SB HT_NB_TO_SB_CAD2
HT_CLK66M_NB H9 HT_CLK
U3 64 62 60
HT_NB_TO_SB_CAD_P<3>
I55
27 U3LITE 64 62 60 HT_NB_TO_SB HT_CAD HT_NB_TO_SB HT_NB_TO_SB_CAD3 I56
V1.0-300MM 64 62 60 HT_NB_TO_SB_CAD_N<3> HT_NB_TO_SB HT_CAD HT_NB_TO_SB HT_NB_TO_SB_CAD3 I57
N1 HT_CLK_RXP0 PBGA
64 62 60 HT_SB_TO_NB_CLK_P (SYM 5 OF 7) HT_CLK_TXP0 R7 HT_NB_TO_SB_CLK_P 60 62 64 64 62 60 HT_NB_TO_SB_CAD_P<4> HT_NB_TO_SB HT_CAD HT_NB_TO_SB HT_NB_TO_SB_CAD4 I58
HT_SB_TO_NB_CLK_N P1 HT_CLK_RXN0 HT_CLK_TXN0 R8 HT_NB_TO_SB_CLK_N HT_NB_TO_SB_CAD_N<4> HT_NB_TO_SB HT_CAD HT_NB_TO_SB HT_NB_TO_SB_CAD4
64 62 60 HT 60 62 64 64 62 60 I59
INTERFACE 64 62 60 HT_NB_TO_SB_CAD_P<5> HT_NB_TO_SB HT_CAD HT_NB_TO_SB HT_NB_TO_SB_CAD5 I60
64 62 60 HT_SB_TO_NB_CAD_P<0> L1 HT_CAD_RXP0 HT_CAD_TXP0 U8 HT_NB_TO_SB_CAD_P<0> 60 62 64 64 62 60 HT_NB_TO_SB_CAD_N<5> HT_NB_TO_SB HT_CAD HT_NB_TO_SB HT_NB_TO_SB_CAD5 I61
L2 HT_CAD_RXN0 OMIT
64 62 60 HT_SB_TO_NB_CAD_N<0> HT_CAD_TXN0 U7 HT_NB_TO_SB_CAD_N<0> 60 62 64 64 62 60 HT_NB_TO_SB_CAD_P<6> HT_NB_TO_SB HT_CAD HT_NB_TO_SB HT_NB_TO_SB_CAD6 I62
64 62 60 HT_SB_TO_NB_CAD_P<1> L3 HT_CAD_RXP1 HT_CAD_TXP1 U6 HT_NB_TO_SB_CAD_P<1> 60 62 64 64 62 60 HT_NB_TO_SB_CAD_N<6> HT_NB_TO_SB HT_CAD HT_NB_TO_SB HT_NB_TO_SB_CAD6 I63
64 62 60 HT_SB_TO_NB_CAD_N<1> L4 HT_CAD_RXN1 HT_CAD_TXN1 U5 HT_NB_TO_SB_CAD_N<1> 60 62 64 64 62 60 HT_NB_TO_SB_CAD_P<7> HT_NB_TO_SB HT_CAD HT_NB_TO_SB HT_NB_TO_SB_CAD7 I64
64 62 60 HT_SB_TO_NB_CAD_P<2> M4 HT_CAD_RXP2 HT_CAD_TXP2 U4 HT_NB_TO_SB_CAD_P<2> 60 62 64 64 62 60 HT_NB_TO_SB_CAD_N<7> HT_NB_TO_SB HT_CAD HT_NB_TO_SB HT_NB_TO_SB_CAD7 I65
64 62 60 HT_SB_TO_NB_CAD_N<2> M3 HT_CAD_RXN2 HT_CAD_TXN2 U3 HT_NB_TO_SB_CAD_N<2> 60 62 64
64 62 60 HT_SB_TO_NB_CAD_P<3> M2 HT_CAD_RXP3 HT_CAD_TXP3 R5 HT_NB_TO_SB_CAD_P<3> 60 62 64 64 62 60 HT_SB_TO_NB_CLK_P HT_SB_TO_NB HT_CAD HT_SB_TO_NB HT_SB_TO_NB_CLK I48
64 62 60 HT_SB_TO_NB_CAD_N<3> M1 HT_CAD_RXN3 HT_CAD_TXN3 R6 HT_NB_TO_SB_CAD_N<3> 60 62 64 64 62 60 HT_SB_TO_NB_CLK_N HT_SB_TO_NB HT_CAD HT_SB_TO_NB HT_SB_TO_NB_CLK I49
64 62 60 HT_SB_TO_NB_CAD_P<4> P2 HT_CAD_RXP4 HT_CAD_TXP4 P8 HT_NB_TO_SB_CAD_P<4> 60 62 64 64 62 60 HT_SB_TO_NB_CTL_P HT_SB_TO_NB HT_CAD HT_SB_TO_NB HT_SB_TO_NB_CTL I84
64 62 60 HT_SB_TO_NB_CAD_N<4> P3 HT_CAD_RXN4 HT_CAD_TXN4 P7 HT_NB_TO_SB_CAD_N<4> 60 62 64 64 62 60 HT_SB_TO_NB_CTL_N HT_SB_TO_NB HT_CAD HT_SB_TO_NB HT_SB_TO_NB_CTL I85
64 62 60 HT_SB_TO_NB_CAD_P<5> R3 HT_CAD_RXP5 HT_CAD_TXP5 P6 HT_NB_TO_SB_CAD_P<5> 60 62 64 64 62 60 HT_SB_TO_NB_CAD_P<0> HT_SB_TO_NB HT_CAD HT_SB_TO_NB HT_SB_TO_NB_CAD0 I66
64 62 60 HT_SB_TO_NB_CAD_N<5> R2 HT_CAD_RXN5 HT_CAD_TXN5 P5 HT_NB_TO_SB_CAD_N<5> 60 62 64 64 62 60 HT_SB_TO_NB_CAD_N<0> HT_SB_TO_NB HT_CAD HT_SB_TO_NB HT_SB_TO_NB_CAD0
64 60 7 =PP2V5_HT R1 HT_CAD_RXP6
I67
64 62 60 HT_SB_TO_NB_CAD_P<6> HT_CAD_TXP6 M5 HT_NB_TO_SB_CAD_P<6> 60 62 64 64 62 60 HT_SB_TO_NB_CAD_P<1> HT_SB_TO_NB HT_CAD HT_SB_TO_NB HT_SB_TO_NB_CAD1 I68
64 62 60 HT_SB_TO_NB_CAD_N<6> T1 HT_CAD_RXN6 HT_CAD_TXN6 M6 HT_NB_TO_SB_CAD_N<6> 60 62 64 64 62 60 HT_SB_TO_NB_CAD_N<1> HT_SB_TO_NB HT_CAD HT_SB_TO_NB HT_SB_TO_NB_CAD1 I69
64 62 60 HT_SB_TO_NB_CAD_P<7> U1 HT_CAD_RXP7 HT_CAD_TXP7 M7 HT_NB_TO_SB_CAD_P<7> 60 62 64 64 62 60 HT_SB_TO_NB_CAD_P<2> HT_SB_TO_NB HT_CAD HT_SB_TO_NB HT_SB_TO_NB_CAD2
1
R6005 R6004 R6003 R6002
1 1 1
64 62 60 HT_SB_TO_NB_CAD_N<7> U2 HT_CAD_RXN7 HT_CAD_TXN7 M8 HT_NB_TO_SB_CAD_N<7> 60 62 64 64 62 60 HT_SB_TO_NB_CAD_N<2> HT_SB_TO_NB HT_CAD HT_SB_TO_NB HT_SB_TO_NB_CAD2
I70
1K 1K 1K 1K I71
5% 5% 5% 5% 64 62 60 HT_SB_TO_NB_CAD_P<3> HT_SB_TO_NB HT_CAD HT_SB_TO_NB HT_SB_TO_NB_CAD3 I72
1/16W 1/16W 1/16W 1/16W V2 HT_CTL_RXP0
MF-LF MF-LF MF-LF MF-LF 64 62 60 HT_SB_TO_NB_CTL_P HT_CTL_TXP0 L6 HT_NB_TO_SB_CTL_P 60 62 64 64 62 60 HT_SB_TO_NB_CAD_N<3> HT_SB_TO_NB HT_CAD HT_SB_TO_NB HT_SB_TO_NB_CAD3 I73
2 402 2 402 2 402 2 402 64 62 60 HT_SB_TO_NB_CTL_N V1 HT_CTL_RXN0 HT_CTL_TXN0 L5 HT_NB_TO_SB_CTL_N 60 62 64 64 62 60 HT_SB_TO_NB_CAD_P<4> HT_SB_TO_NB HT_CAD HT_SB_TO_NB HT_SB_TO_NB_CAD4
C
I74
C 64 62 60 HT_PWROK F9 HT_PWROK
64 62 60
64 62 60
HT_SB_TO_NB_CAD_N<4>
HT_SB_TO_NB_CAD_P<5>
HT_SB_TO_NB
HT_SB_TO_NB
HT_CAD
HT_CAD
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB_CAD4
HT_SB_TO_NB_CAD5
I75
I76
64 62 60 HT_RESET_L G9 HT_RESET* 64 62 60 HT_SB_TO_NB_CAD_N<5> HT_SB_TO_NB HT_CAD HT_SB_TO_NB HT_SB_TO_NB_CAD5 I77
64 62 60 HT_LDTSTOP_L H8 HT_LDTSTOP* HT_PVTREF0 L7 HT_NB_PVTREF0 64 62 60 HT_SB_TO_NB_CAD_P<6> HT_SB_TO_NB HT_CAD HT_SB_TO_NB HT_SB_TO_NB_CAD6 I78
64 62 60 HT_LDTREQ_L H7 HT_LDTREQ* HT_PVTREF1 L8 HT_NB_PVTREF1 64 62 60 HT_SB_TO_NB_CAD_N<6> HT_SB_TO_NB HT_CAD HT_SB_TO_NB HT_SB_TO_NB_CAD6 I79
HT_CLK_AVSS
1
R6001 64 62 60 HT_SB_TO_NB_CAD_P<7> HT_SB_TO_NB HT_CAD HT_SB_TO_NB HT_SB_TO_NB_CAD7 I80
200 64 62 60 HT_SB_TO_NB_CAD_N<7> HT_SB_TO_NB HT_CAD HT_SB_TO_NB HT_SB_TO_NB_CAD7
G8
I81
1%
1/16W
MF-LF
2 402 64 62 60 HT_PWROK HT_PWROK HT_2V5 HT_2V5 I86
64 62 60 HT_RESET_L HT_CTL HT_2V5 HT_2V5 I87
64 62 60 HT_LDTSTOP_L HT_CTL HT_2V5 HT_2V5 I88
64 62 60 HT_LDTREQ_L HT_CTL HT_2V5 HT_2V5 I89
HT_NB_TO_SB HT_SB_TO_NB HT_2V5

5 MIL SPACING FOR DIFF PAIR 4 MIL SPACING IN GROUP
10 MIL SPACING TO ANYTHING ELSE 8 MIL SPACING TO ANYTHING ELSE
64 60 7 =PP2V5_HT 60 24 7 =PP1V2_HT
1 C6010 1 C6011 1 C6000 1 C6001 1 C6002 1 C6004 1 C6005 1 C6006 1 C6007 1 C6008 LENGTH TOLERENCE CAN BE LOOSE
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF MATCHED GROUP CONSTRAINT IS TIGHT ENOUGH
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
B 2 10V
CERM
402
2 10V
CERM
402
2 10V
CERM
402
2 10V
CERM
402
2 10V
CERM
402
2 10V
CERM
402
2 10V
CERM
402
2 10V
CERM
402
2 10V
CERM
402
2 10V
CERM
402 B
U3LITE HT
A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
D 051-6772 E
APPLE COMPUTER INC.
SCALE SHT OF
NONE 60 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
P25MM HT_CLK66M_SB_C 62
Page Notes
- _PP2V5_PWRON_HT
- _PP1V2_PWRON_HT
D (NONE) D
BOM options provided by this page: =PP2V5_PWRON_HT 7
- SB_HT_200M
Stuffs resistor to select 200MHz HT I/F.
1 C6220
PP1V2_PWRON_HT_PLLDVDD 0.1uF
20%
62 7 =PP1V2_PWRON_HT R6200 VOLTAGE=1.2V
MIN_LINE_WIDTH=0.5MM 10V
2 CERM
1
3.3 2
5%
1/8W
MF-LF
805
1 C6200 1 C6201
10uF 1uF =PP1V2_PWRON_HT 7 62
20% 10%
6.3V 6.3V
2 CERM 2 CERM
1206 402
1 C6230 1 C6231 1 C6232
0.1uF 0.1uF 0.1uF
20% 20% 20%
2 10V
CERM 2 10V
CERM 2 10V
CERM
PP1V2_PWRON_HT_PLLAVDD 402 402 402
R6210 VOLTAGE=1.2V
1
3.3 2
5%
1/8W
MF-LF
805
1 C6210 1 C6211 =PP1V2_PWRON_HT 7 62
10uF 1uF
20% 10%
6.3V 6.3V
2 CERM 2 CERM
B19
B15
B17
G13
B12
G11
1206 402 1 C6240 1 C6241 1 C6242
C7
B6
B9
0.1uF 0.1uF 0.1uF
AVDD DVDD VDDP HT_RXVDD HT_TXVDD 20% 20% 20%
10V 10V 10V
HT_PLL HT OMIT 2 CERM 2 CERM 2 CERM
C U2300
SHASTA
402 402 402
C
V1.0
BGA
HT_NB_TO_SB_CLK_P D15 HT_CLKIN_P B10 HT_SB_TO_NB_CLK_P
64 60 (3 OF 8) HT_CLKOUT_P 60 64
HT_NB_TO_SB_CLK_N C15 HT_CLKIN_N HT_CLKOUT_N A10 HT_SB_TO_NB_CLK_N
HYPERTRANSPORT
64 60 60 64
64 60 HT_NB_TO_SB_CAD_P<0> D17 HT_CADIN_0_P HT_CADOUT_0_P D10 HT_SB_TO_NB_CAD_P<0> 60 64
64 60 HT_NB_TO_SB_CAD_N<0> C17 HT_CADIN_0_N HT_CADOUT_0_N C10 HT_SB_TO_NB_CAD_N<0> 60 64
64 60 HT_NB_TO_SB_CAD_P<1> B18 HT_CADIN_1_P HT_CADOUT_1_P B8 HT_SB_TO_NB_CAD_P<1> 60 64
64 60 HT_NB_TO_SB_CAD_N<1> A18 HT_CADIN_1_N HT_CADOUT_1_N A8 HT_SB_TO_NB_CAD_N<1> 60 64
64 60 HT_NB_TO_SB_CAD_P<2> F15 HT_CADIN_2_P HT_CADOUT_2_P E11 HT_SB_TO_NB_CAD_P<2> 60 64
64 60 HT_NB_TO_SB_CAD_N<2> E15 HT_CADIN_2_N HT_CADOUT_2_N F11 HT_SB_TO_NB_CAD_N<2> 60 64
64 60 HT_NB_TO_SB_CAD_P<3> D16 HT_CADIN_3_P HT_CADOUT_3_P D11 HT_SB_TO_NB_CAD_P<3> 60 64
64 60 HT_NB_TO_SB_CAD_N<3> C16 HT_CADIN_3_N HT_CADOUT_3_N C11 HT_SB_TO_NB_CAD_N<3> 60 64
64 60 HT_NB_TO_SB_CAD_P<4> B16 HT_CADIN_4_P HT_CADOUT_4_P A11 HT_SB_TO_NB_CAD_P<4> 60 64
64 60 HT_NB_TO_SB_CAD_N<4> A16 HT_CADIN_4_N HT_CADOUT_4_N B11 HT_SB_TO_NB_CAD_N<4> 60 64
64 60 HT_NB_TO_SB_CAD_P<5> D14 HT_CADIN_5_P HT_CADOUT_5_P C12 HT_SB_TO_NB_CAD_P<5> 60 64
64 60 HT_NB_TO_SB_CAD_N<5> C14 HT_CADIN_5_N HT_CADOUT_5_N D12 HT_SB_TO_NB_CAD_N<5> 60 64
64 60 HT_NB_TO_SB_CAD_P<6> E14 HT_CADIN_6_P HT_CADOUT_6_P E12 HT_SB_TO_NB_CAD_P<6> 60 64
64 60 HT_NB_TO_SB_CAD_N<6> F14 HT_CADIN_6_N HT_CADOUT_6_N F12 HT_SB_TO_NB_CAD_N<6> 60 64
64 60 HT_NB_TO_SB_CAD_P<7> B14 HT_CADIN_7_P HT_CADOUT_7_P A13 HT_SB_TO_NB_CAD_P<7> 60 64
64 60 HT_NB_TO_SB_CAD_N<7> A14 HT_CADIN_7_N HT_CADOUT_7_N B13 HT_SB_TO_NB_CAD_N<7> 60 64
64 60 HT_NB_TO_SB_CTL_P F13 HT_CTLIN_P HT_CTLOUT_P C13 HT_SB_TO_NB_CTL_P 60 64
64 60 HT_NB_TO_SB_CTL_N E13 HT_CTLIN_N HT_CTLOUT_N D13 HT_SB_TO_NB_CTL_N 60 64
64 60 HT_PWROK E16 HT_PWROK_H

HT_RESET_L C18 HT_RESET_L
B C6255
0.1uF
64 60
64 60 HT_LDTSTOP_L E17 HT_LDTSTOP_L HT_LDTREQ_L A19 HT_LDTREQ_L 60 64 B

27 HT_CLK66M_SB 1 2 62 HT_CLK66M_SB_C C8 HT_REFCLK HT_R100P E10 SB_HT_R100_P
D8 HT_S100M66M HT_R100N F10
20%
SB_HT_S100M66M
V6 SEL_HT00_H
SB_HT_R100_N
R6250
R62551 10V
CERM
SB_SELHT100
1
82.5 2
332 402
1% AC coupled HT_PLL 1%
1/16W 1/16W
MF-LF 1.0V pk-pk AGND DGND HT_RXGND HT_TXGND C6250 1 MF-LF
402
1 C6251
C6
A6
A15
A17
G12
A12
A9
G10
402 2 47pF 47pF
5% 5%
50V 50V
CERM 2 2 CERM
402 402
62 7 =PP1V2_PWRON_HT
NO STUFF
R62521 R62541
4.7K 10K
5% 5%
1/16W 1/16W
MF-LF MF-LF
402 2 402 2
SB_HT_200M
R62531 R62511
4.7K 1K
5% 5%
1/16W
MF-LF
402 2
1/16W
MF-LF
402 2
Shasta HyperTransport
A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
HT RefClk HT I/F Speed PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
1 = 100MHz 1 = 100MHz I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
0 = 66MHz 0 = 200MHz II NOT TO REPRODUCE OR COPY IT
APPLE COMPUTER INC.

D 051-6772 E
SCALE SHT OF
NONE 62 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
SAME CONNECTORS & PINOUT AS D

D
Q37 HYPERTRANSPORT BETWEEN GOLEM AND K2
NOSTUFF
NOSTUFF NOSTUFF
J6400 J6401 J6402
P6860
ST-SM-DF P6860 P6860
SYM_VER1 ST-SM-DF ST-SM-DF
SYM_VER1 SYM_VER1
NOSTUFF
R6400
62 60 HT_NB_TO_SB_CLK_N A15
A15 A15
0
A14 CLK- 62 60 HT_SB_TO_NB_CAD_P<0> 62 60 HT_SB_TO_NB_CLK_N 1 2
CLK- CLK-
GND
B12 HT_NB_TO_SB_CAD_N<7> 60 62
A14 A14 5%
62 60 HT_NB_TO_SB_CLK_P A13 D15 GND
B12 HT_SB_TO_NB_CAD_P<1> 60 62 GND
B12 6 TEK_HT_B12 1/10W
CLK+
B11 62 60 HT_SB_TO_NB_CAD_N<0> A13 D15 62 60 HT_SB_TO_NB_CLK_P A13 D15 MF-LF
GND CLK+
B11 CLK+
B11 603
B10 HT_NB_TO_SB_CAD_P<7> 60 62 GND NOSTUFF GND
A12 B10 B10
62 60 HT_NB_TO_SB_CAD_P<6> D14
62 60 HT_SB_TO_NB_CAD_N<2> A12
HT_SB_TO_NB_CAD_N<1> 60 62
R6403 6 TEK_HT_A12 A12
6 TEK_HT_B10
0
D13 D14 D14
A11 D13 D13
GND
B9 HT_NB_TO_SB_CAD_N<5> 60 62
A11 1 2 A11
62 60 HT_NB_TO_SB_CAD_N<6> A10 D11 GND
B9 HT_SB_TO_NB_CAD_P<3> 60 62 GND
B9 HT_RESET_L 60 62
B8 62 60 HT_SB_TO_NB_CAD_P<2> A10 5% 6 TEK_HT_A10 A10
C
D12 D11 D11
C GND D12
B8 1/10W D12
B8
B7 HT_NB_TO_SB_CAD_P<5> 60 62 GND 603 GND
62 60 HT_NB_TO_SB_CAD_N<4> A9 D10
B7 HT_SB_TO_NB_CAD_N<3> 60 62
B7
D9 62 60 HT_SB_TO_NB_CAD_P<4> A9 D10 6 TEK_HT_A9 A9 D10
A8 D9 NOSTUFF D9
B6 A8 A8
62 60 HT_NB_TO_SB_CAD_P<4> A7 GND HT_NB_TO_SB_CAD_P<3> 60 62
B6 HT_SB_TO_NB_CAD_N<5> 60 62
R6404 B6 HT_LDTREQ_L 60 62
0
D7 GND GND
D8
B5 62 60 HT_SB_TO_NB_CAD_N<4> A7 D7 6 TEK_HT_A7 A7 D7
GND D8
B5 1 2 D8
B5
B4 HT_NB_TO_SB_CAD_N<3> 60 62 GND GND
B4 HT_SB_TO_NB_CAD_P<5> 60 62 5% B4
D5 62 60 HT_SB_TO_NB_CAD_P<6> A6 D6 1/10W A6 D6
A5 D5 MF-LF D5
GND
B3 HT_NB_TO_SB_CAD_P<1> 60 62
A5 603 A5
62 60 HT_NB_TO_SB_CAD_P<2> A4 D3 GND
B3 HT_SB_TO_NB_CAD_N<7> 60 62 GND
B3 HT_NB_TO_SB_CTL_N 60 62
D4
B2 62 60 HT_SB_TO_NB_CAD_N<6> A4 D3 62 60 HT_LDTSTOP_L A4 D3
GND D4
B2 D4
B2
B1 HT_NB_TO_SB_CAD_N<1> 60 62 GND GND
B1 HT_SB_TO_NB_CAD_P<7> 60 62
B1 HT_NB_TO_SB_CTL_P 60 62
D1 62 60 HT_SB_TO_NB_CTL_P A3 D2
A3 D2
A2 D1 D1
GND
A2 A2
62 60 HT_NB_TO_SB_CAD_P<0> A1 GND GND
D0 62 60 HT_SB_TO_NB_CTL_N A1 62 60 HT_PWROK A1
D0 D0
=PP2V5_HT 7 60
DEVELOPMENT
R6401
1
10K
5%
1/16W
MF-LF
2 402
6HT_VREF_DEBUG
VOLTAGE=1.25V DEVELOPMENT
1
10K
5%
1/16W
MF-LF
2 402
B B
HT DEBUG CONN
A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
D 051-6772 E
APPLE COMPUTER INC.
SCALE SHT OF
NONE 64 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
ALL RESISTOR PACKS ARE 47 OHM 1/16W 5%

D D
R PAKS ARE PIN SWAPPABLE ACROSS ALL SIGNALS (EXCEPT IDSELS)
PCI_SB_AD<0> RP7300 2 7 47 PCI_AD<0>

74 6 74 75 76 77
PCI_SB_AD<1> RP7303 1 8 47 PCI_AD<1>

74 6 74 75 76 77
74 PCI_SB_AD<2> RP7303 2 7 47 PCI_AD<2> 6 74 75 76 77
PCI_SB_AD<3> RP7303 4 5 47 PCI_AD<3>

74 6 74 75 76 77
74 PCI_SB_AD<4> RP7309 2 7 47 PCI_AD<4> 6 74 75 76 77
74 PCI_SB_AD<5> RP7300 1 8 47 PCI_AD<5> 6 74 75 76 77
PCI_SB_AD<6> RP7300 3 6 47 PCI_AD<6>

74 6 74 75 76 77
PCI_SB_AD<7> RP7309 4 5 47 PCI_AD<7>

74 6 74 75 76 77
74 PCI_SB_AD<8> RP7300 4 5 47 PCI_AD<8> 6 74 75 76 77
PCI_SB_AD<9> RP7301 2 7 47 PCI_AD<9>

74 6 74 75 76 77
74 PCI_SB_AD<10> RP7301 1 8 47 PCI_AD<10> 6 74 75 76 77
PCI_SB_AD<11> RP7301 4 5 47 PCI_AD<11>

74 6 74 75 76 77
PCI_SB_AD<12> RP7309 1 8 47 PCI_AD<12>

74 6 74 75 76 77
PCI_SB_AD<13> RP7309 3 6 47 PCI_AD<13>

74 6 74 75 76 77
PCI_SB_AD<14> RP7301 3 6 47 PCI_AD<14>

74 6 74 75 76 77
74 PCI_SB_AD<15> RP7307 1 8 47 PCI_AD<15> 6 74 75 76 77
74 PCI_SB_AD<16> RP7308 1 8 47 PCI_AD<16> 6 74 75 76 77
R7300
47
74 PCI_SB_AD<17> 1 2 PCI_AD<17> 6 74 75 76 77
5%
1/16W
MF-LF
C 74 PCI_SB_AD<18> RP7307 2
402
7 47 PCI_AD<18> 6 74 75 76 77
C
PCI_SB_AD<19> RP7306 3 6 47 PCI_AD<19>
74 6 74 75 76 77
74 PCI_SB_AD<20> RP7305 1 8 47 PCI_AD<20> 6 74 75 76 77
PCI_SB_AD<21> RP7305 2 7 47 PCI_AD<21>

74 6 74 76 77
PCI_SB_AD<22> RP7302 1 8 47 PCI_AD<22>

74 6 74 76 77
PCI_SB_AD<23> RP7302 3 6 47 PCI_AD<23>

74 6 74 76 77
PCI_SB_AD<24> RP7304 1 8 47 PCI_AD<24>

74 6 74 75 76 77
74 PCI_SB_AD<25> RP7306 4 5 47 PCI_AD<25> 6 74 75 76 77
74 PCI_SB_AD<26> RP7305 3 6 47 PCI_AD<26> 6 74 75 76 77
R7301
47
74 PCI_SB_AD<27> 1 2 PCI_AD<27> 6 74 75 76 77
5%
1/16W
MF-LF
402
PCI_SB_AD<28> RP7302 2 7 47 PCI_AD<28>
74 6 74 75 76 77
PCI_SB_AD<29> RP7304 4 5 47 PCI_AD<29>

74 6 74 75 76 77
74 PCI_SB_AD<30> RP7302 4 5 47 PCI_AD<30> 6 74 75 76 77
74 PCI_SB_AD<31> RP7304 2 7 47 PCI_AD<31> 6 74 75 76 77
74 PCI_SB_CBE_L<0> RP7303 3 6 47 PCI_CBE_L<0> 6 74 76 77
PCI_SB_CBE_L<1> RP7306 2 7 47 PCI_CBE_L<1>

74 6 74 76 77
74 PCI_SB_CBE_L<2> RP7305 4 5 47 PCI_CBE_L<2> 6 74 76 77
PCI_SB_CBE_L<3> RP7304 3 6 47 PCI_CBE_L<3>

74 6 74 76 77
PCI_SB_DEVSEL_L RP7306 1 8 47 PCI_DEVSEL_L

74 6 74 76 77
74 PCI_SB_FRAME_L RP7307 4 5 47 PCI_FRAME_L 6 74 76 77
B 74
74
PCI_SB_IRDY_L
PCI_SB_TRDY_L
RP7307
RP7308
3
3
6
6
47
47
PCI_IRDY_L
PCI_TRDY_L
6 74 76 77
6 74 76 77
B
74 PCI_SB_STOP_L RP7308 4 5 47 PCI_STOP_L 6 74 76 77
PCI_SB_PAR RP7308 2 7 47 PCI_PAR

74 6 74 76 77
PLACE CLOSE TO SHASTA
AD<17> IS IDSEL FOR AIRPORT

AD<27> IS IDSEL FOR USB
PCI SERIES TERMINATION

A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
D 051-6772 E
APPLE COMPUTER INC.
SCALE SHT OF
NONE 73 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
PCI_AD PCI PCI_AD<31..28> 6 73 75 76 77
PCI_AD27 PCI PCI_AD<27> 6 73 75 76 77
PCI_AD PCI PCI_AD<26..24> 6 73 75 76 77
PCI_AD23 PCI PCI_AD<23> 6 73 76 77
PCI_AD22 PCI PCI_AD<22> 6 73 76 77
PCI_AD21 PCI PCI_AD<21> 6 73 76 77
PCI_AD20 PCI PCI_AD<20> 6 73 75 76 77
PCI_AD PCI PCI_AD<19..18> 6 73 75 76 77
PCI_AD17 PCI PCI_AD<17> 6 73 75 76 77
PCI_AD PCI PCI_AD<16..0>
D PCI PCI PCI_CBE_L<3..0>

6 73 75 76 77
6 73 76 77
D
PCI PCI PCI_PAR 6 73 76 77
PCI_CTL PCI PCI_DEVSEL_L 6 73 74 76 77
PCI_CTL PCI PCI_FRAME_L 6 73 74 76 77
PCI_CTL PCI PCI_IRDY_L 6 73 74 76 77
PCI_CTL PCI PCI_TRDY_L 6 73 74 76 77
PCI_CTL PCI PCI_STOP_L 6 73 74 76 77
Page Notes
- _PP3V3_PCI
- _PP3V3_SB_PCI (can be _PP3V3_PCI)
- _PP3V3_PWRON_SB =PP3V3_SB_PCI
7
- _PP2V5_PWRON_SB
Signal aliases required by this page: NO STUFF
(NONE) 1 C7410 1 C7400 1 C7401 1 C7402 1 C7403 1 C7404
10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
BOM options provided by this page: 20% 20% 20% 20% 20% 20%
2 6.3V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
(NONE) 805 402 402 402 402 402
=PP2V5_PWRON_SB 7 23 25 88
PCI Devices implemented on this page:
AD11 - PCI0 (0x106B/0x0053)
NO STUFF
AD11 - PCI1 (0x106B/0x0054)
AD11 - PCI2 (0x106B/0x0055)
1 C7411 1 C7405 1 C7406 1 C7407 1 C7408 1 C7409 C7420 1 C7421 1 C7422 1 C7423 1
10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
C AD23
AD28
-
-
KeyLargo
SATA 150
(0x106B/0x004F,
(0x1166/0x0240,
PCI1)
PCI0 or 2)
20%
6.3V
2 CERM
805
20%
10V
2 CERM
402
20%
10V
2 CERM
402
20%
10V
2 CERM
402
20%
10V
2 CERM
402
20%
10V
2 CERM
402
20%
10V
CERM 2
402
20%
10V
CERM 2
402
20%
10V
CERM 2
402
20%
10V
CERM 2
402
C
AD29 - UATA 133 (0x106B/0x0050, PCI0 or 2)
AA22
AD30 - FireWire (0x106B/0x0052, PCI0 or 2)
B22
E21
H16
J21
M16
N21
R20
U21
V19
B20
J18
N20
U20
AD31 - Ethernet (0x106B/0x0051, PCI0)
VDDOPC PCIVDDP
U2300 OMIT
SHASTA
V1.0
BGA
PCI_CLK66M_SB_INT AB9 PCIBR_CLK_H PCI1AD_0_H L18 PCI_SB_AD<0>
27 (4 OF 8) 73
PCI1AD_1_H K19 PCI_SB_AD<1> 73
27 8 PCI_CLK33M_SB_EXT U19 PCI1CLK_H PCI1AD_2_H L22 PCI_SB_AD<2> 73
PCI1AD_3_H M22 PCI_SB_AD<3> 73

PCI PCI1AD_4_H M18 PCI_SB_AD<4> 73
PCI1AD_5_H L20 PCI_SB_AD<5> 73
PCI1AD_7_H N16 PCI_SB_AD<7> 73
PCI1AD_9_H P22 PCI_SB_AD<9> 73

"Slot A" - AD17
AB18 PCI1AD_10_H M17 PCI_SB_AD<10> 73
=PP3V3_PCI 7 25 74 75 76 77 76 74 6 PCI_SLOTA_REQ_L PCI1REQ_0_L
AA18 PCI1AD_11_H N18 PCI_SB_AD<11> 73
PCI_SLOTA_GNT_L PCI1GNT_0_L
RP7400 76 74 6
4.7K PCI1AD_13_H N19 PCI_SB_AD<13> 73
2 7 PCI_SLOTA_REQ_L 6 74 76 "Slot G" - AD27
AB20 PCI1AD_14_H P21 PCI_SB_AD<14> 73
5% PCI_SLOTG_REQ_L PCI1REQ_1_L
1/16W
SM-LF
RP7400 77 74
PCI_SLOTG_GNT_L AB19 PCI1GNT_1_L

PCI1AD_15_H R22 PCI_SB_AD<15> 73
4.7K 77 74
PCI1AD_16_H P20 PCI_SB_AD<16>
B 1
5%
8 PCI_SLOTA_GNT_L 6 74 76
"Slot D" - AD20

PCI1AD_17_H V21 PCI_SB_AD<17>
73
73
=PP3V3_PCI
B
RP7400 1/16W
SM-LF PCI_SLOTD_REQ_L V17 PCI1REQ_2_L
PCI1AD_18_H P18 PCI_SB_AD<18> 73
77 76 75 74 25 7
4
4.7K 5
74
V18 PCI1AD_19_H T20 PCI_SB_AD<19> 73 RP7402
PCI_SLOTG_REQ_L PCI_SLOTD_GNT_L PCI1GNT_2_L
74 77 74
3
4.7K 6
5% PCI_DEVSEL_L
1/16W
SM-LF
RP7400 PCI1AD_21_H R17 PCI_SB_AD<21> 73
77 76 74 73 6
5%
4.7K PCI1AD_22_H W21 PCI_SB_AD<22> 73 RP7402 1/16W
3 6 PCI_SLOTG_GNT_L SM-LF
74 77
PCI1AD_23_H Y22 PCI_SB_AD<23> 73
4
4.7K 5
5% PCI_FRAME_L
RP7401 1/16W
SM-LF
77 76 74 73 6
5%
4.7K PCI1AD_25_H T19 PCI_SB_AD<25> 73 1/16W RP7402
3 6 PCI_SLOTD_REQ_L SM-LF
74
PCI1AD_26_H T18 PCI_SB_AD<26> 73 4.7K
5% 77 76 74 73 6 PCI_IRDY_L 2 7
1/16W
SM-LF
RP7401 PCI1AD_27_H Y21 PCI_SB_AD<27> 73
5%
4.7K PCI1AD_28_H W20 PCI_SB_AD<28> 73 RP7402 1/16W
4 5 PCI_SLOTD_GNT_L SM-LF
74
PCI1AD_29_H T16 PCI_SB_AD<29> 73 4.7K
5% 77 76 74 73 6 PCI_TRDY_L 1 8
1/16W PCI1AD_30_H AA21 PCI_SB_AD<30> 73
SM-LF 5%
PCI1AD_31_H T17 PCI_SB_AD<31> 73 1/16W
SM-LF
RP7401
4.7K
PCI1C_BE_0_L L19 PCI_SB_CBE_L<0> 73 77 76 74 73 6 PCI_STOP_L 7 2
PCI1C_BE_1_L P16 PCI_SB_CBE_L<1> 73 5%

V22 1/16W
PCI1C_BE_2_L PCI_SB_CBE_L<2> 73 SM-LF
PCI1C_BE_3_L V20 PCI_SB_CBE_L<3> 73
=PP3V3_PWRON_SB 7 23 25
PCI1DEVSEL_L T22 PCI_SB_DEVSEL_L 73
PCI1FRAME_L T21 PCI_SB_FRAME_L 73
PCI1IRDY_L R21 PCI_SB_IRDY_L 73

1
R7455 1 C7450 1R7450
0.1uF
AB8
PCI1TRDY_L
PCI1STOP_L
P19
P17
PCI_SB_TRDY_L
PCI_SB_STOP_L
73
73
4.7K
5%
1/16W
20%
10V
2 CERM
4.7K
5%
1/16W
Shasta PCI Interface
76 75 6 ROM_CS_L ROMCS_L N17 MF-LF 402 MF-LF
A 76 75 6
76 75 6
ROM_OE_L
ROM_WE_L
AA9
Y10
ROMOE_L
ROMRW_L
PCI1PAR_H
PCI1RST_L U18
PCI_SB_PAR
SB_PCI_RESET_L
73
2 402
1
5
2 402 SYNC_MASTER=N/A

SYNC_DATE=N/A
A
SYS_WARM_RESET_L 2
U7450 4 PCI_RESET_L 6 8 56
77 25 8 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
Shasta drives PCI RESET, but its output 3MC74VHC1G08
SOT23-5 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
may not be valid during power-up, so
it is ANDed with a reset from the SMU.
APPLE COMPUTER INC.

D 051-6772 E
SCALE SHT OF
NONE 74 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
Page Notes
- _PP3V3_PCI
(NONE)
(NONE)
NOTE: This page does not specify a BootROM
part number. Must use a TABLE_x_ITEM
D symbol to declare U7500 part number. D
77 76 75 74 25 7 =PP3V3_PCI
C7500 1 C7501 1 C7502 1

2.2uF
20%
0.1uF
20%
0.1uF
20%
10V 10V 10V
CERM 2 CERM 2 CERM 2
805 402 402
11 30 31
C VPP
U7500
VCC C
PCI_AD<0> 21 90.0ns 25 PCI_AD<24> 6
77 76 74 73 6
A0 TSOP DQ0 73 74 76 77
PCI_AD<1> 20 26 PCI_AD<25> 6
77 76 74 73 6
A1 OMIT DQ1 73 74 76 77
PCI_AD<2> 19 27 PCI_AD<26> 6
77 76 74 73 6
A2 DQ2 73 74 76 77
PCI_AD<3> 18 28 PCI_AD<27> 6
77 76 74 73 6
A3 DQ3 73 74 76 77
PCI_AD<4> 17 32 PCI_AD<28> 6
77 76 74 73 6
A4 DQ4 73 74 76 77
PCI_AD<5> 16 33 PCI_AD<29> 6
77 76 74 73 6
A5 DQ5 73 74 76 77
PCI_AD<6> 15 34 PCI_AD<30> 6
77 76 74 73 6
A6 DQ6 73 74 76 77
PCI_AD<7> 14 35 PCI_AD<31> 6
77 76 74 73 6
A7 DQ7 73 74 76 77
PCI_AD<8> 8
77 76 74 73 6
A8
PCI_AD<9> 7
77 76 74 73 6
A9
PCI_AD<10> 36
77 76 74 73 6
A10
PCI_AD<11> 6
77 76 74 73 6
A11
PCI_AD<12> 5
77 76 74 73 6
A12
PCI_AD<13> 4
77 76 74 73 6
A13
PCI_AD<14> 3
77 76 75 74 25 7 =PP3V3_PCI
77 76 74 73 6
A14
PCI_AD<15> 2
77 76 74 73 6
A15
PCI_AD<16> 1
77 76 74 73 6
A16
PCI_AD<17> 40
R7500 1
R7501
1 77 76 74 73 6
A17
PCI_AD<18> 13
10K 10K 77 76 74 73 6
A18
5% 5% PCI_AD<19> 37
1/16W 1/16W
77 76 74 73 6
A19
MF-LF MF-LF PCI_AD<20> 38
402 2 R7502 2 402
77 76 74 73 6
A20
ROM_CS_L 1
4702 76 6 ROM_ONBOARD_CS_L 22
76 74 6
CE
Allows ROM override module 5% ROM_OE_L 24
B 1/16W
to intercept ROM chip select MF-LF
402
76 74 6
76 74 6 ROM_WE_L 9
12
OE
WE B
6 ROM_WP_L
WP
=PCI_ROM_RESET_L 10
8
PWD
GND
23 39
BootROM
A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
APPLE COMPUTER INC.

D 051-6772 E
SCALE SHT OF
NONE 75 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
PCI_CLK_AIRPORT CLOCKS _PCI_CLK33M_AIRPORT 8 76
Page Notes
- _PP3V3_PCI
- _PCI_CLK33M_AIRPORT (33MHz PCI clock)
D BOM options provided by this page: D

(NONE)
AD17 (Slot "A") - AirPort (0x????/0x????)
NOTE: This AirPort implementation does
Q85 WIRELESS CONNECTOR
not support PME#.
77 75 74 25 7 =PP3V3_PCI
SDF7600 NOSTUFF
STDOFF-3MMOD5MMH-TH 1 C7650 1 C7651 1 C7652
1 10UF
20%
1UF
10%
1UF
10%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
1206 402 402
CRITICAL
J7650
20-5602-080-041-829
F-ST-SM
1 2 PCI_AD<31> 6 73 74 75 77
77 75 74 73 6 PCI_AD<30> 3 4 AIRPORT_CLKRUN_L_PD 6
5 6 TP_AP_PME_L
77 75 74 73 6 PCI_AD<27>
PCI_SLOTA_REQ_L
7
9
8
10
PCI_SLOTA_GNT_L 6 74 R7650
1
74 6 10K
11 12 5%
77 75 74 73 6 PCI_AD<25> 1/16W
13 14 MF-LF
PCI_AD<29> PCI_AD<24>
77 75 74 73 6 6 73 74 75 77
2 402
C 77 74 73 6 PCI_CBE_L<3>
15
17
16
18
PCI_AIRPORT_RESET_L
PCI_AD<28>
8
6 73 74 75 77
C
77 75 74 73 6 PCI_AD<26> 19 20
R7651 77 74 73 6 PCI_AD<22> 21 22 PCI_AD<23> 6 73 74 77
22 23 24
77 76 75 74 73 6 PCI_AD<17> 1 2 6 PCI_SLOTA_IDSEL
5% 25 26 PCI_AD<20> 6 73 74 75 77
1/16W
MF-LF 77 75 74 73 6 PCI_AD<19> 27 28 PCI_FRAME_L 6 73 74 77
402
77 74 73 6 PCI_AD<21> 29 30 PCI_AD<17> 6 73 74 75 76 77
77 74 73 6 PCI_IRDY_L 31 32
77 75 74 73 6 PCI_AD<18> 33 34 PCI_TRDY_L 6 73 74 77
77 74 73 6 PCI_DEVSEL_L 35 36
37 38 PCI_CBE_L<2> 6 73 74 77
76 8 _PCI_CLK33M_AIRPORT 39 40 PCI_AD<16> 6 73 74 75 77
77 74 73 6 PCI_STOP_L 41 42
77 75 74 73 6 PCI_AD<12> 43 44
77 74 73 6 PCI_PAR 45 46
47 48 PCI_AD<14> 6 73 74 75 77
77 75 74 73 6 PCI_AD<8> 49 50 PCI_AD<13> 6 73 74 75 77
77 75 74 73 6 PCI_AD<9> 51 52
77 74 73 6 PCI_CBE_L<0> 53 54 PCI_AD<10> 6 73 74 75 77
55 56 PCI_AD<15> 6 73 74 75 77
77 75 74 73 6 PCI_AD<7> 57 58 AP_ALT_ANT
77 75 74 73 6 PCI_AD<3> 59 60 PCI_CBE_L<1> 6 73 74 77
77 75 74 73 6 PCI_AD<6> 61 62 PCI_AD<4> 6 73 74 75 77
63 64
77 75 74 73 6 PCI_AD<1> 65 66 PCI_AD<11> 6 73 74 75 77
PCI_AD<5> 67 68 ROM_WE_L
B
77 75 74 73 6
77 75 74 73 6 PCI_AD<0> 69
71
70
72
PCI_AD<2>
6 74 75
6 73 74 75 77 B
91 USB2_P<4> 6 USB_BT_P 73 74 PCI_SLOTA_INT_L 6 25
MAKE_BASE=TRUE 75 76
91 USB2_N<4> 6 USB_BT_N ROM_OE_L 6 74 75
MAKE_BASE=TRUE 77 78 ROM_ONBOARD_CS_L 6 75
R7660 1
R7661
1
7 _PP3V3_PWRON_BT 79 80 ROM_CS_L 6 74 75
15K 15K USB2_OC<4>
5% 5% 91
1/16W 1/16W
MF-LF MF-LF
402 2 2 402 516S0285
C7660 1
1UF
10%
6.3V
CERM 2
402
SDF7601
STDOFF-3MMOD5MMH-TH1
1
AIRPORT & BLUETOOTH

A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
APPLE COMPUTER INC.

D 051-6772 E
SCALE SHT OF
NONE 76 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
PCI_CLK_USB2 CLOCKS =PCI_CLK33M_USB2 8 77
Page Notes
- _PPVIO_PCI (to 3.3V or 5V)
- _PCI_CLK33M_USB2 (33MHz PCI clock)
D BOM options provided by this page: D

(NONE) =PPVIO_PCI_USB2
7

AD27 (Slot "G") - USB2 (0x1033/0x0035)
NOTE: This USB2 implementation supports
C7703 1
0.1uF
D3cold. 20%
10V
CERM 2
402
H3
M4
C8
PCI_AD<0> M5
76 75 74 73 6 AD0
VDD_PCI
PCI_AD<1> P5
76 75 74 73 6 AD1
PCI_AD<2> N5
76 75 74 73 6 AD2
PCI_AD<3> P4
76 75 74 73 6 AD3
PCI_AD<4> N4
76 75 74 73 6 AD4
PCI_AD<5> M3
76 75 74 73 6 AD5
PCI_AD<6> N3 CRITICAL
76 75 74 73 6 AD6
76 75 74 73 6 PCI_AD<7>
PCI_AD<8>
M1
L2
AD7
AD8
U7700
76 75 74 73 6
76 75 74 73 6 PCI_AD<9> L1
AD9
NEC_UPD720101_USB2
FBGA
76 75 74 73 6 PCI_AD<10> K2 AD10
PCI_AD<11> L3
76 75 74 73 6 AD11
PCI_AD<12> K1
76 75 74 73 6 AD12
PCI_AD<13> K3
76 75 74 73 6 AD13
PCI_AD<14> J2
76 75 74 73 6 AD14
PCI_AD<15> J1
76 75 74 73 6 AD15
C 76 75 74 73 6 PCI_AD<16>
PCI_AD<17>
F2
E3
AD16 C
76 75 74 73 6 AD17
PCI_AD<18> E1
76 75 74 73 6 AD18
PCI_AD<19> D3
76 75 74 73 6 AD19
PCI_AD<20> D1
76 75 74 73 6 AD20
76 74 73 6 PCI_AD<21> D2 AD21
PCI_AD<22> C2
76 74 73 6 AD22
PCI_AD<23> C1
76 74 73 6 AD23
PCI_AD<24> B4
76 75 74 73 6 AD24
PCI_AD<25> A4
76 75 74 73 6 AD25
PCI_AD<26> B5
76 75 74 73 6 AD26
PCI_AD<27> (PCI_AD<27>) C4
76 75 74 73 6 AD27
6 PCI_AD<28>
A5
76 75 74 73 AD28
6 PCI_AD<29>
C5
76 75 74 73 AD29
6 PCI_AD<30>
B6
76 75 74 73 AD30
6 PCI_AD<31>
A6
76 75 74 73 AD31
PCI_CBE_L<0> M2
76 74 73 6 CBE0
R77141 76 74 73 6 PCI_CBE_L<1> J3
CBE1
22 76 74 73 6 PCI_CBE_L<2> F1
CBE2
5% C3
1/16W 76 74 73 6 PCI_CBE_L<3> CBE3
MF-LF
402 2
PCI_PAR J4
76 74 73 6 PAR
PCI_FRAME_L F3
=PP3V3_PCI
76 74 73 6 FRAME
76 75 74 25 7
PCI_IRDY_L F4
76 74 73 6 IRDY
PCI_TRDY_L G1
76 74 73 6 TRDY
B R77161 R77131
76 74 73 6 PCI_STOP_L
PCI_SLOTG_IDSEL
G3
STOP
B3 IDSEL
B
10K 10K G2
5% 5% 76 74 73 6 PCI_DEVSEL_L DEVSEL
1/16W 1/16W C6
MF-LF MF-LF PCI_SLOTG_REQ_L REQ
RP7703 402 2 402 2
74
PCI_SLOTG_GNT_L D6
GNT
47 74
PCI_SLOTG_INT_L 4 5 NEC_PERR_L_PU H2 IPD NTEST1 M8 TP_NEC_NTEST1

25 PERR 6
NEC_SERR_L_PU H1
5% SERR OD
1/16W
SM-LF
RP7703 NEC_INTA_L C7
INTA OD IPD SMC M7 TP_NEC_SMC
47 6
2 7 NEC_INTB_L B7
INTB OD
NEC_INTC_L A7
5% INTC OD
RP7703 1/16W
SM-LF =PCI_CLK33M_USB2 A8
PCLK IPD TEB N7 TP_NEC_TEB
47 77 8 6
3 6 IPD AMC P7 TP_NEC_AMC
5% NEC_VBBRST_L B8 VBBRST (CHIP RESET)
1/16W
SM-LF
RP7702 NEC_CRUN_L_PD N6
CRUN IPD TEST L8 TP_NEC_TEST
47 6
SYS_WARM_RESET_L 3 6 NEC_PME_L D9
74 25 8 PME OD
NEC_VCCRST_L C9
5% VCCRST (PCI RESET)
RP7702 1/16W
SM-LF TP_NEC_SMI_L L6
SMI OD NANDTEST M10 TP_NEC_NANDTEST
4
47 5
6
M9
25 13 SYS_PME_L SRCLK TP_NEC_SRCLK 6
5% SRDTA N9 TP_NEC_SRDATA
1/16W
SM-LF
RP7702 NEC_LEGC_PD L7
LEGC IPD SRMOD P9 TP_NEC_SRMOD
47 6
8 =PCI_USB2_RESET_L 2 7
5% 8
1/16W
SM-LF
R77151 RP7703
4.7K 47
5%
RP7702 & RP7703 required to
facilitate NAND-tree testing
1/16W
MF-LF
402 2
5%
1/16W
SM-LF
USB 2.0 PCI Interface
1
A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
APPLE COMPUTER INC.

D 051-6772 E
SCALE SHT OF
NONE 77 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
SATA_RXD1
SATA_RXD1
SATA
SATA
SATA
SATA
SATA_RXD1_C
SATA_RXD1_C
SATA_RXD_P1_C
SATA_RXD_N1_C
80 83
80 83
UATA Termination
SATA_TXD1 SATA SATA SATA_TXD1 SATA_TXD_P1 80 83
SATA_TXD1 SATA SATA SATA_TXD1 SATA_TXD_N1 80 83 RP8000

33
SATA_RXD2 SATA SATA SATA_RXD2_C SATA_RXD_P2_C 80 83 80 UATA_DD_R<0> 4 5 UATA_DD<0> 6 80 83
SATA_RXD2 SATA SATA SATA_RXD2_C SATA_RXD_N2_C 5%

80 83
RP8000 1/16W
SM-LF
SATA_TXD2 SATA SATA SATA_TXD2 SATA_TXD_P2 80 83 33
80 UATA_DD_R<1> 3 6 UATA_DD<1> 6 80 83
SATA_TXD2 SATA SATA SATA_TXD2 SATA_TXD_N2 80 83
D UATA_DD UATA_DD<15..8> 6 80 83
5%
1/16W
SM-LF
RP8000
2
33
7
D
UATA_DD7 UATA_DD<7> 6 80 83 80 UATA_DD_R<2> UATA_DD<2> 6 80 83
UATA_DD UATA_DD<6..0> 5%
UATA_HOST UATA_DA<2..0>
6 80 83
RP8003 1/16W
SM-LF
6 80 83
33
UATA_HOST UATA_CS0_L 6 80 83 80 UATA_DD_R<3> 4 5 UATA_DD<3> 6 80 83
UATA_HOST UATA_CS1_L 5%
UATA_HOST UATA_HSTROBE
6 80 83
1/16W
SM-LF
RP8001
6 80 83
33
UATA_HOST UATA_STOP 6 80 83 80 UATA_DD_R<4> 1 8 UATA_DD<4> 6 80 83
UATA_HOST_R UATA_DMACK_L 5%
UATA_HOST_R UATA_RESET_L
6 80 83
RP8001 1/16W
SM-LF
6 80 83
33
UATA_DEV_R_C UATA_DSTROBE 80 83 80 UATA_DD_R<5> 2 7 UATA_DD<5> 6 80 83
UATA_DEV_R UATA_DMARQ 5%
UATA_DEV_R UATA_INTRQ
80 83
1/16W
SM-LF
RP8003
80 83
3
33 6
80 UATA_DD_R<6> UATA_DD<6> 6 80 83
Page Notes
5%
RP8002 1/16W
SM-LF
33
80 UATA_DD_R<7> 1 8 UATA_DD<7> 6 80 83
Power aliases required by this page: 5%

- _PP1V2_PWRON_DISK PP1V2_PWRON_DISK_SB_R R80051
1/16W
SM-LF
RP8002
7 =PP1V2_PWRON_DISK_SB VOLTAGE=1.2V 33
R8010 10K UATA_DD_R<8> 2 7 UATA_DD<8>
0
SATA_VDD x 5 MIN_LINE_WIDTH=0.6MM
1/16W
80
5%
6 80 83
(NONE) 1 2 MF-LF
402 2
RP8003 1/16W
SM-LF
5% 33
BOM options provided by this page: 1/8W UATA_DD_R<9> 2 7 UATA_DD<9>
(NONE)
MF-LF
805
1 C8000 1 C8001 1 C8002 1 C8003 1 C8004 80
5%
6 80 83
1UF 1UF 1UF 1UF 1UF 1/16W RP8000

10% 10% 10% 10% 10% SM-LF
2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 33
Net Spacing Type: SATA CERM
402
CERM
402
CERM
402
CERM
402
CERM
402 80 UATA_DD_R<10> 1 8 UATA_DD<10> 6 80 83
C Line To Line: 15 mils RP8002 5%

1/16W C
AB14
AB17
33 SM-LF
Length Tolerance: 50 mils
T14
W15
Y18
80 UATA_DD_R<11> 4 5 UATA_DD<11> 6 80 83
Primary Max Sep: 10 mils outer
5%
Primary Max Sep: 9 mils inner SATA_VDD 1/16W
SM-LF
RP8001
Secondary Max Sep: 100 mils U2300 OMIT 3
33 6
80 UATA_DD_R<12> UATA_DD<12> 6 80 83
Secondary Length: 500 mils SHASTA 5%
NOTE: Target differential impedance for V1.0 RP8002 1/16W
SM-LF
BGA 33
SATA data pairs is 100 ohms. 80 UATA_DD_R<13> 3 6 UATA_DD<13> 6 80 83
(5 OF 8)
UD_IDEDD_0_H J6 UATA_DD_R<0> 5%
UD_IDEDD_1_H H7 UATA_DD_R<1>
80
1/16W
SM-LF
RP8004
80
33
UD_IDEDD_2_H H6 UATA_DD_R<2> 80 80 UATA_DD_R<14> 1 8 UATA_DD<14> 6 80 83
UD_IDEDD_3_H E2 UATA_DD_R<3> 5%
UD_IDEDD_4_H C1 UATA_DD_R<4>
80
RP8003 1/16W
SM-LF
80
33
UD_IDEDD_5_H C2 UATA_DD_R<5> 80 80 UATA_DD_R<15> 1 8 UATA_DD<15> 6 80 83
UD_IDEDD_6_H E3 UATA_DD_R<6> 5%
UD_IDEDD_7_H G6 UATA_DD_R<7>
80
1/16W
SM-LF
RP8004
80
33
UD_IDEDD_8_H G5 2 7
UATA
UATA_DD_R<8> 80 80 UATA_DA_R<0> UATA_DA<0> 6 80 83
UD_IDEDD_9_H D4 UATA_DD_R<9> 5%
UD_IDEDD_10_H G7 UATA_DD_R<10>
80
RP8001 1/16W
SM-LF
80
33
UD_IDEDD_11_H F6 UATA_DD_R<11> 80 80 UATA_DA_R<1> 4 5 UATA_DA<1> 6 80 83
UD_IDEDD_12_H C3 UATA_DD_R<12> 5%
DSTROBE aka: UD_IDEDD_13_H F5 UATA_DD_R<13>
80
1/16W
SM-LF
RP8004
80
33
IORDY/HDMARDY* UD_IDEDD_14_H E5 UATA_DD_R<14> 80 80 UATA_DA_R<2> 4 5 UATA_DA<2> 6 80 83
UD_IDEDD_15_H D5 UATA_DD_R<15> 5%
HSTROBE aka:
80
RP8004 1/16W
SM-LF
DIOR* UD_IDEDA0_H E6 UATA_DA_R<0> 80
3
33 6
UATA_RESET_L_R UATA_RESET_L
B STOP aka:
UD_IDEDA1_H C4
UD_IDEDA2_H D6
UATA_DA_R<1>
UATA_DA_R<2>
80
80
80
5%
1/16W R8000
6 80 83
B
DIOW* SM-LF
B3 33
UD_IDECS1FX_L UATA_CS0_L_R 80 80 UATA_CS0_L_R 1 2 UATA_CS0_L 6 80 83
83 80 UATA_DSTROBE F9 UD_IDECHRDY_H UD_IDECS3FX_L B4 UATA_CS1_L_R 80 5%
D7 UD_IDEDMARQ_H E8
R8001 1/16W
MF-LF
83 80 UATA_DMARQ UD_IDEDMACK_L UATA_DMACK_L_R 80 33 402
80 UATA_CS1_L_R 1 2 UATA_CS1_L 6 80 83
UD_IDERD_L E4 UATA_HSTROBE_R 80
83 80 UATA_INTRQ C5 UD_IDEINTRQ_H 5%
D3
UD_IDEWR_L
E7
UATA_STOP_R 80 1/16W
MF-LF R8002
UD_IDERST_L UATA_RESET_L_R 80 402 22
80 UATA_HSTROBE_R 1 2 UATA_HSTROBE 6 80 83
83 80 SATA_RXD_P1_C Y17 RXDP1 TXDP1 AA16 SATA_TXD_P1 80 83 5%

83 80 SATA_RXD_N1_C Y16 RXDN1 SATA 0 TXDN1 AB16 SATA_TXD_N1 80 83
R8003 1/16W
MF-LF
22 402
AB15 RXDP2 80 UATA_STOP_R 1 2 UATA_STOP 6 80 83
83 80 SATA_RXD_P2_C TXDP2 Y15 SATA_TXD_P2 80 83
AA15 RXDN2 SATA 1 5%
83 80 SATA_RXD_N2_C TXDN2 Y14 SATA_TXD_N2 80 83 1/16W
R8004
MF-LF
AC coupling required for any SATA pair used. SATA_GND UATA_DMACK_L_R
402
1
22 2 UATA_DMACK_L
80 6 80 83
Recommend 0.1uF cap placed close to Shasta.
AA14
AA17
T13
W16
5%
(Caps provided by device page) 1/16W
MF-LF
402
Shasta Disk
A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
APPLE COMPUTER INC.

D 051-6772 E
SCALE SHT OF
NONE 80 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
83 80 6 UATA_DD<15..8> UATA_DD
83 80 6 UATA_DD<7> UATA_DD7
83 80 6 UATA_DD<6..0> UATA_DD
83 80 6 UATA_DA<2..0> UATA_HOST
83 80 6 UATA_CS0_L UATA_HOST
83 80 6 UATA_CS1_L UATA_HOST
83 80 6 UATA_HSTROBE UATA_HOST
83 80 6 UATA_STOP UATA_HOST
83 80 6 UATA_DMACK_L UATA_HOST_R
UATA_RESET_L UATA_HOST_R
D
83 80 6
83 80 UATA_DSTROBE UATA_DEV_R_C D
83 80 UATA_DMARQ UATA_DEV_R
83 80 UATA_INTRQ UATA_DEV_R
SATA CONNECTORS
PATA CONNECTOR
C8304
0.1UF
SATA_TXD_P1_C 1 2 SATA_TXD_P1 80 83 7 =PP5V_PATA
J8300 C8305 20%

10V =PP3V3_PATA
LD18077-S04 0.1UF CERM
7
ATA-6 spec does not call out R8180 or R8182
M-ST-TH SATA_TXD_N1_C 1 2 402 SATA_TXD_N1 80
1 NO STUFF
C8307
2
20%
10V
0.1UF R8313
NO STUFF
1 R83111
CERM 10K
3 SATA_RXD_N1 402 1 2 SATA_RXD_N1_C 80 10K 5%
4 5% 1/16W
C8308 20%
1/16W CRITICAL
MF-LF
MF-LF 402 2
5 0.1UF 10V
CERM
402 2 J8301
6 SATA_RXD_P1 1 2 402 SATA_RXD_P1_C 80 804RVS-050505R
7
R8314
1 F-ST-SM
1
R8312
20% 51 1K
10V
CERM
4.7K 5%
402
5% 1/16W
518-0157 1/16W MF-LF
C MF-LF
2 402 Per ATA Spec
NC 1
3
2
4
NC
NC
2 402
Obsolete
C
83 80 6 UATA_RESET_L 5 6 UATA_DD<8> 6 80 83
83 80 6 UATA_DD<7> 7 8 UATA_DD<9> 6 80 83
83 80 6 UATA_DD<6> 9 10 UATA_DD<10> 6 80 83
83 80 6 UATA_DD<5> 11 12 UATA_DD<11> 6 80 83
83 80 6 UATA_DD<4> 13 14 UATA_DD<12> 6 80 83
Sourced by drive
83 80 6 UATA_DD<3> 15 16 UATA_DD<13> 6 80 83
Terminate near connector
83 80 6 UATA_DD<2> 17 18 UATA_DD<14> 6 80 83
80 SATA_TXD_P2 TP_SATA_TXD_P2 6
MAKE_BASE=TRUE 83 80 6 UATA_DD<1> 19 20 UATA_DD<15> 6 80 83
83 80 6 UATA_DD<0> 21 22
80 SATA_TXD_N2 TP_SATA_TXD_N2 6 23 24 UATA_HSTROBE 6 80 83
MAKE_BASE=TRUE
83 80 6 UATA_STOP 25 26
6 UATA_DSTROBE_R 27 28 UATA_DMACK_L 6 80 83
80 SATA_RXD_N2_C TP_SATA_RXD_N2_C 6 R8315 6 UATA_INTRQ_R 29 30 UATA_IOCS16_PU 6

MAKE_BASE=TRUE
UATA_DSTROBE 1
82 2 UATA_DA<1> 31 32
83 80 83 80 6 NC
5% 83 80 6 UATA_DA<0> 33 34 UATA_DA<2> 6 80 83
1/16W
80 SATA_RXD_P2_C TP_SATA_RXD_P2_C 6 MF-LF 83 80 6 UATA_CS0_L 35 36 UATA_CS1_L 6 80 83
MAKE_BASE=TRUE 402
6 UATA_DASP_L 37 38
R8316 39 40
82
83 80 UATA_INTRQ 1 2 41 42
NO STUFF 5% 43 44
1/16W
C8301 1 MF-LF
402
45 46
10pF 6 UATA_CSEL_PD 47 48
5%
50V
CERM 2 NC 49 50 NC
402
52
B HD POWER R8320
82
B
83 80 UATA_DMARQ 1 2 6 UATA_DMARQ_R
5% 516S0235
1/16W
MF-LF
402
ATA-6 spec does not call out C8177

=PP5V_DISK 6 7
CRITICAL
=PP5V_PATA R83191 1
R8318 1R8317
J8303 =PP12V_DISK
83 7
5.6K 0 6.2K
S05B-XA 6 7
DEVELOPMENT
5%
1/16W
5%
1/16W
5%
1/16W
M-RT-TH MF-LF MF-LF MF-LF
1 =PP3V3_DISK 7
R8321 1 402 2 2 402 2 402
PER ATA7 SPEC
2
499 Per ATA Spec
1%
3 1/16W Per ATA Spec
MF-LF DEVELOPMENT
4 402 2
5
LED8301
6 UATA_DASP_L_DS 1 2
518-0144
GREEN
2.0X1.25A
"UATA ACTIVE"
DISK CONNECTORS
A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
APPLE COMPUTER INC.

D 051-6772 E
SCALE SHT OF
NONE 83 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
ENET_RX_CLK P25MM ENET_CLK25M_TX 84 86
ENET_RX_CLK P25MM ENET_CLK125M_RX 84 86
ENET_GBE_REF P25MM ENET_CLK125M_GBE_REF 84 86
ENET_TX_CLK P25MM ENET_CLK125M_GTX 84 86
ENET_CLK125M_GTX_R 84
ENET_RX ENET_RXD<7..0> 84 86
ENET_RX_CTL ENET_RX_DV 84 86
ENET_RX_CTL ENET_RX_ER 84 86
ENET_TX ENET_TXD<7..0>
D ENET_TX_CTL ENET_TX_EN
84 86
84 86 D
ENET_TX_CTL ENET_TX_ER 84 86
ENET_RX_CTL ENET_CRS 84 86
ENET_RX_CTL ENET_COL 84 86
ENET_MDC ENET_MDC 84 86
ENET_MDIO ENET_MDIO 84 86
Page Notes
(NONE)
(NONE)
(NONE)
RP8400
0
2 7 ENET_TXD<0> 84 86
C OMIT RP8400 5%
1/16W
C
0 SM-LF
U2300 4 5 ENET_TXD<1> 84 86
SHASTA 5%
1/16W RP8400
V1.0 SM-LF 0
BGA 1 8 ENET_TXD<2> 84 86
(6 OF 8)
5%
86 84 ENET_CLK25M_TX H5 ETH_TX_CLK_H
RP8400 1/16W
ETHERNET
J3 ETH_RX_CLK_H 0 SM-LF
86 84 ENET_CLK125M_RX 3 6 ENET_TXD<3> 84 86
ENET_RXD<0> K1 ETH_RXD_0_H ETH_TXD_0_H G4 ENET_TXD_R<0> 5%

86 84
ENET_RXD<1> L3 ETH_RXD_1_H ETH_TXD_1_H E1 ENET_TXD_R<1>

1/16W
SM-LF
RP8401
86 84
K2 ETH_RXD_2_H
0
86 84 ENET_RXD<2> ETH_TXD_2_H H4 ENET_TXD_R<2> 2 7 ENET_TXD<4> 84 86
ENET_RXD<3> J1 ETH_RXD_3_H ETH_TXD_3_H J5 ENET_TXD_R<3> 5%

86 84
ENET_RXD<4> L4 ETH_RXD_4_H ETH_TXD_4_H G3 ENET_TXD_R<4> RP8401 1/16W

SM-LF
86 84
K3 ETH_RXD_5_H
0
86 84 ENET_RXD<5> ETH_TXD_5_H F2 ENET_TXD_R<5> 4 5 ENET_TXD<5> 84 86
ENET_RXD<6> J2 ETH_RXD_6_H ETH_TXD_6_H J4 ENET_TXD_R<6> 5%

86 84
ENET_RXD<7> G1 ETH_RXD_7_H ETH_TXD_7_H K6 ENET_TXD_R<7>

1/16W
SM-LF
RP8401
86 84
0
1 8 ENET_TXD<6> 84 86
86 84 ENET_RX_DV K4 ETH_RX_DV_H ETH_TX_EN_H H3 ENET_TX_EN_R
5%
86 84 ENET_RX_ER G2 ETH_RX_ER_H ETH_TX_ER_H F1 ENET_TX_ER_R RP8401 1/16W
SM-LF
0
86 84 ENET_CLK125M_GBE_REF M5 ETH_REFCLK_H ETH_GTX_CLK_H K5 84 ENET_CLK125M_GTX_R 3 6 ENET_TXD<7> 84 86
L6 ETH_CRS_H 5%
86 84 ENET_CRS ETH_MDC_H M4 ENET_MDC 84 86 1/16W R8400
SM-LF
L5 ETH_COL_H 0
86 84 ENET_COL ETH_MDIO_H M6 ENET_MDIO 84 86 1 2 ENET_TX_EN 84 86
5%
R8401 1/16W
MF-LF
0 402
B 1
5%
2 ENET_TX_ER 84 86
B
1/16W
MF-LF R8402
402 0
1 2 ENET_CLK125M_GTX 84 86
5%
1/16W
MF-LF
402
Shasta Ethernet
A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
APPLE COMPUTER INC.

D 051-6772 E
SCALE SHT OF
NONE 84 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
NET_TYPE
ELECTRICAL_CONSTRAINT_SET SPACING PHYSICAL DIFFERENTIAL_PAIR
P25MM ENET_CLK125M_GBE_REF_R 86
P25MM ENET_CLK125M_RX_R 86
P25MM ENET_CLK25M_TX_R 86
L8600 PP2V5_VESTA_BIASVDD1
VOLTAGE=2.5V
ENET_MDI ENET ENET ENET_MDI0 ENET_MDI_P<0> 86 87 89 12 =PP2V5_ENETFW FERR-EMI-600-OHM MIN_LINE_WIDTH=0.5 mm
1 2 MIN_NECK_WIDTH=0.25 mm
ENET_MDI ENET ENET ENET_MDI0 ENET_MDI_N<0> 86 87
ENET_MDI ENET ENET ENET_MDI1 ENET_MDI_P<1> 86 87 SM

ENET_MDI ENET ENET ENET_MDI1 ENET_MDI_N<1> 86 87
1 C8601
ENET_MDI ENET ENET ENET_MDI2 ENET_MDI_P<2> 86 87
0.1uF
20%
ENET_MDI_N<2> 10V
ENET_MDI ENET ENET ENET_MDI2 86 87 2 CERM
D ENET_MDI
ENET_MDI
ENET
ENET
ENET
ENET
ENET_MDI3
ENET_MDI3
ENET_MDI_P<3>
ENET_MDI_N<3>
86 87
86 87
402
D
VESTA_CLK25M_XTAL P25MM VESTA_CLK25M_XTALI 86
P25MM VESTA_CLK25M_XTALO 86 L8601 PP2V5_VESTA_XTALVDD1 PP1V2_VESTA_PLLVDD1 L8602

P25MM VESTA_CLK25M_XTALO_R 86
FERR-EMI-600-OHM VOLTAGE=2.5V
MIN_LINE_WIDTH=0.5 mm
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.5 mm FERR-EMI-600-OHM =PP1V2_ENETFW 7 89
1 2 MIN_NECK_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm 1 2
SM SM
Page Notes 1 C8602

10UF
10%
1 C8603
0.001uF
20%
C8604 1
0.001uF
20%
C8605 1
10uF
20%
Power aliases required by this page: 2 6.3V
X5R 2 50V
CERM
50V
CERM 2
6.3V 2
CERM ESR < 0.5 ohms
805 402 402 1206-1
- _PP3V3_ENET
- _PP2V5_ENETFW
- _PP1V2_ENETFW
N1
P1
M1
Signal aliases required by this page: XTALVDD1 BIASVDD1 PLLVDD1
R8600
0
(NONE) 1 2 ENET_CLK125M_GBE_REF 84
5%
84 ENET_CLK125M_GTX A4 GTXCLK CLK125 D1 86 ENET_CLK125M_GBE_REF_R
1/16W
MF-LF R8601
(NONE) OMIT 402 0
1 2 ENET_CLK25M_TX 84
Net Spacing Type: ENET VESTA ENET TXC A6 86 ENET_CLK25M_TX_R 5%
U8600 R8602 1/16W

MF-LF
0 402
Line To Line: 0.38 mms BCM5462 RXC C1 86 ENET_CLK125M_RX_R 1 2 ENET_CLK125M_RX 84
FBGA-200
Length Tolerance: 50 mils 2 OF 3
5%
1/16W
Primary Max Sep: 5 mils 84 ENET_TXD<0> B6 TXD[0] RXD[0] F4 ENET_RXD<0> 84 MF-LF
402
Secondary Max Sep: 100 mils 84 ENET_TXD<1> C6 TXD[1] RXD[1] F5 ENET_RXD<1> 84
Secondary Length: 500 mils 84 ENET_TXD<2> C7 TXD[2] RXD[2] E5 ENET_RXD<2> 84
84 ENET_TXD<3> D6 TXD[3] RXD[3] E4 ENET_RXD<3> 84
C NOTE: Target differential impedance for

ENET data pairs is 100 ohms.
84
84
ENET_TXD<4>
ENET_TXD<5>
E6
C5
TXD[4]
TXD[5]
RXD[4] E3
RXD[5] D5
ENET_RXD<4>
ENET_RXD<5>
84
84
C
87 7 =PP3V3_ENET
84 ENET_TXD<6> B5 TXD[6] RXD[6] D4 ENET_RXD<6> 84
84 ENET_TXD<7> A5 TXD[7] RXD[7] D3 ENET_RXD<7> 84

R86501
1.5K B4
5% 84 ENET_TX_EN TX_EN RX_DV D2 ENET_RX_DV 84
1/16W
MF-LF 84 ENET_TX_ER C4 TX_ER RX_ER C2 ENET_RX_ER 84
402 2
84 ENET_MDC G1 MDC COL F3 ENET_COL 84
84 ENET_MDIO G2 MDIO CRS G3 ENET_CRS 84
12 VESTA_ENET_LOWPWR H5 LOWPWR RBC0 A3 TP_VESTA_RBC0

RBC1 B3 TP_VESTA_RBC1
TP_VESTA_PHYA<0> L5 PHYA[0] TRD+[0] R4 ENET_MDI_P<0> 86 87
TP_VESTA_PHYA<1> L4 PHYA[1] TRD-[0] R5 ENET_MDI_N<0> 86 87
TP_VESTA_PHYA<2> L3 PHYA[2]
L2 TRD+[1] R7 ENET_MDI_P<1> 86 87
TP_VESTA_PHYA<3> PHYA[3]
TP_VESTA_PHYA<4> L1 TRD-[1] R6 ENET_MDI_N<1> 86 87
PHYA[4]
TRD+[2] R8 ENET_MDI_P<2> 86 87
TP_VESTA_EN_10B K3 TRD-[2] R9 ENET_MDI_N<2> 86 87

EN_10B
TP_VESTA_RGMIIEN B8 RGMIIEN TRD+[3] R11 ENET_MDI_P<3> 86 87
TP_VESTA_FDX C8 FDX TRD-[3] R10 ENET_MDI_N<3> 86 87
TP_VESTA_F1000 K4 F1000
TP_VESTA_SPD0 K5 SPD0 INTR*/ENERGYDET D10 ENET_ENERGYDET 25 R8614 1
R8616 1
R8618 1
R8620 1
TP_VESTA_MANMS D9 MANMS 49.9 49.9 49.9 49.9
B TP_VESTA_HUB A9
H3
HUB SLAVE*/AN_EN C10 TP_VESTA_AN_EN
1%
1/16W
MF-LF
1%
1/16W
MF-LF
1%
1/16W
MF-LF
1%
1/16W
MF-LF
B
TP_VESTA_ER ER QUALITY*/TXC_RXC_DELAY A8 TP_VESTA_TXC_RXC_DELAY 402 2 402 2 402 2 402 2
LINK1* A10 TP_VESTA_LINK1_L
Vesta Config Straps: TP_VESTA_TEST<0> M4 TEST[0] LINK2* B11 TP_VESTA_LINK2_L 1
R8615 R8617
1
R8619
1
R8621
1
TP_VESTA_TEST<1> M5 TEST[1] FDXLED* B10 TP_VESTA_FDXLED_L 49.9 49.9 49.9 49.9
PHYA<4..0> - PHY Address Select MANMS - Manual Master/Slave Configuration Select N3 1% 1% 1% 1%
TP_VESTA_TVCO TVCO XMTLED* B12 TP_VESTA_XMTLED_L 87 1/16W 1/16W 1/16W 1/16W
(Internal Pull-downs) Sets manual master/slave configuration enable bit MF-LF MF-LF MF-LF MF-LF
Put crystal circuit close to PHY ACTLED* A11 TP_VESTA_ACTLED_L 87
2 402 2 402 2 402 2 402
(Internal Pull-down) N2
EN_10B - TBI Interface Select 86 VESTA_CLK25M_XTALI XTALI ENET_MDI0 ENET_MDI1 ENET_MDI2 ENET_MDI3
1 - TBI/RTBI Mode HUB - Repeater Select 86 VESTA_CLK25M_XTALO_R P2 XTALO RDAC1 R1 VESTA_RDAC1_PD
0 - GMII/RGMII Mode Sets Hub/DTE bit and master/slave configuration value bit
XTALGND BIASGND PLLGND1 1 C8620 1 C8621 1 C8622 1 C8623
(Internal Pull-down) (Internal Pull-down) R8609
1
R86131 0.01UF 0.01UF 0.01UF 0.01UF
P3
R2
M2
332 1.24K 20%
16V
20%
16V
20%
16V
20%
16V
RGMIIEN - RGMII Enable ER - Edge Rate Select 1% 1% 2 CERM 2 CERM 2 CERM 2 CERM
CRITICAL 1/16W 1/16W 402 402 402 402
1 - RGMII/RTBI Mode 1 - Rise time approx. 5 ns MF-LF MF-LF
0 - GMII/TBI Mode 0 - Rise time approx. 4 ns
Y8600 2 402 402 2
25.0000M PLACE RESISTORS CLOSE TO PHY
(Internal Pull-down) (Internal Pull-down) 1 2
VESTA_CLK25M_XTALO 86
FDX - Full-Duplex Select AN_EN - Auto-Negotiation Select 8X4.5MM-SM
Sets manual duplex mode bit 1 - Auto-negotiation enabled

(Internal Pull-up) 0 - Auto-negotiation disabled
C8618 1 C8619 1
33pF 33pF
(Internal Pull-up) 5% 5%
50V 50V
F1000 - Speed Select CERM 2 CERM 2
See table below TXC_RXC_DELAY 402 402
(Internal Pull-up) 1 - If RGMII Mode enabled, RXC clock and

GTXCLK are delayed by 1.9 ns
SPD0 - Speed Select
See table below
0 - No clock delay
CRYSTAL LOAD CAPACITANCE IS 20PF
Vesta Ethernet PHY
(Internal Pull-down)
A (Internal Pull-down)
AN_EN F1000 SPD0 Description

SYNC_MASTER=N/A

SYNC_DATE=N/A
A
0 0 0 Force 10BASE-T
0 0 1 Force 100BASE-TX PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
0 1 X Force 1000BASE-T (test use only)
1 0 0 Auto-negotiate advertise 10BASE-T
1 0 1 Auto-negotiate advertise 10/100BASE-TX
1 1 0 Auto-negotiate advertise 10/100/1000BASE-T
1 1 1 Auto-negotiate advertise 1000BASE-T SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.

D 051-6772 E
SCALE
NONE
SHT
86 102 OF
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
D D
L8700 PUT DEVELOPMENT LEDS ON TOP SIDE OF BOARD

FERR-EMI-600-OHM
7 =PP2V5_ENET 1 2
SM
87 86 7 =PP3V3_ENET
7 GND_CHASSIS_RJ45
GBIT_2_5V DEVELOPMENT
C8704 1 1
R8701
1 C8700 0.001UF 330
20% 5%
0.1UF 50V
20% CERM 2 (514-0222)
1/10W
MF-LF
2 10V
CERM
603 DEVELOPMENT 2 603
402 CRITICAL R8700
1
10K LED8700_P
J8700 5%
1/16W
ENET_MDI_P<0> MJRR0156 MF-LF
86
F-ST-TH 2 402 DEVELOPMENT
86 ENET_MDI_N<0> 1
LED8700
PRIMARY GREEN
1CT:1CT 2.0X1.25A
C 1 C8701
13
11 75 OHM
VESTA_XMTLED
2
LED8700_N
C
0.1UF
20%
2 10V
CERM 5 ENET_CTAP
6 DEVELOPMENT 3 DEVELOPMENT
402
6 ENET_CTAP 1CT:1CT
D
Q8700 D
Q8700
1 MDI_0+ SECONDARY
2N7002DW
SOT-363
2N7002DW
SOT-363
75 OHM 86 TP_VESTA_XMTLED_L VESTA_XMTLED_L 2 G S 5 G S
2 MDI_0- J1 MAKE_BASE=TRUE
86 ENET_MDI_P<1> 3 MDI_1+ J2 1 4
86 ENET_MDI_N<1> 4 MDI_1- J3
7 MDI_2+ 1CT:1CT J4
8 MDI_2- J5
9 MDI_3+ 75 OHM J6
10 MDI_3- J7
1 C8702 J8
0.1UF 1CT:1CT RJ45
20% 12
2 10V CABLE SIDE
CERM 14 75 OHM
402
RJ45
CHIP SIDE 87 86 7 =PP3V3_ENET
86 ENET_MDI_P<2>
86 ENET_MDI_N<2> DEVELOPMENT
1
R8703
SHIELD 1000PF, 2000V 330
5%
1 C8703 1/10W
MF-LF
0.1UF DEVELOPMENT
20% 2 603
2 10V
CERM R8702
1
402 10K LED8701_P
B 5%
1/16W
MF-LF
B
86 ENET_MDI_P<3> 2 402 DEVELOPMENT 1
ENET_MDI_N<3> LED8701
86
1 C8705 GREEN
0.001UF 2.0X1.25A
20% 2
50V
2 CERM
603 VESTA_ACTLED LED8701_N
6 DEVELOPMENT 3 DEVELOPMENT
D
Q8701
2N7002DW
D
Q8701
2N7002DW
2
SOT-363 5
SOT-363
86 TP_VESTA_ACTLED_L VESTA_ACTLED_L G S G S
MAKE_BASE=TRUE
1 4
ETHERNET CONNECTOR
A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
APPLE COMPUTER INC.

D 051-6772 E
SCALE SHT OF
NONE 87 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
FW FW_DATA<7..0> 88 89
FW FW_CTL<1..0> 88 89
FW_LPS FW_LPS 88 89
FW_LREQ FW_LREQ 88 89
FW_PINT FW_PINT 88 89
FW_LCLK P25MM FW_CLK98M_LCLK 88 89
FW_PCLK P25MM FW_CLK98M_PCLK 88 89
P25MM FW_CLK98M_LCLK_R 88
D Page Notes D
- _PP2V5_PWRON_SB
(NONE)
(NONE)
74 25 23 7 =PP2V5_PWRON_SB
1 C8800 1 C8801 1 C8802

0.1uF 0.1uF 0.1uF
20% 20% 20%
2 10V
CERM 2 10V
CERM 2 10V
CERM
402 402 402
C C
N5
J7
A4
FWVDDP
OMIT
U2300
SHASTA
V1.0
BGA
(7 OF 8)
PHY_DATA_0_H N4 FW_DATA<0> 88 89
PHY_DATA_1_H P5 FW_DATA<1> 88 89
FIREWIRE
PHY_DATA_3_H M7 FW_DATA<3> 88 89
PHY_DATA_5_H L1 FW_DATA<5> 88 89
PHY_DATA_6_H M3 FW_DATA<6> 88 89
PHY_DATA_7_H L2 FW_DATA<7> 88 89
PHY_CTL_0_H N2 FW_CTL<0> 88 89
PHY_CTL_1_H N3 FW_CTL<1> 88 89
PHY_LPS_H P6 FW_LPS 88 89
PHY_LREQ_H P1 FW_LREQ 88 89
R8800
P2 PHY_SCLK_H 22
89 88 FW_CLK98M_PCLK PHY_LCLK_H R1 88 FW_CLK98M_LCLK_R 1 2 FW_CLK98M_LCLK 88 89
5%
89 88 FW_PINT P3 PHY_PINT_L PHY_LINKON_L N7 FW_LINKON 89 1/16W
MF-LF
402
B B
Shasta FireWire
A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
APPLE COMPUTER INC.

D 051-6772 E
SCALE SHT OF
NONE 88 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
NET_TYPE
ELECTRICAL_CONSTRAINT_SET SPACING PHYSICAL DIFFERENTIAL_PAIR
I402 (PROVIDED BY LINK PAGE) P38MM CLOCKS FW_CLK98M_PCLK_R 89
FW_TPA1 FW FW FW_TPA0 FW_TPA_P<0>

I403
FW_TPA1 FW FW FW_TPA0 FW_TPA_N<0>
89 90
L8900 PP1V2_VESTA_PLLVDD2
VOLTAGE=1.2V PP3V3_VESTA_FAVDDH L8906
I405 89 90
=PP1V2_ENETFW FERR-EMI-600-OHM
FW_TPB1 FW FW FW_TPB0 FW_TPB_P<0> 89 90
89 86 7 MIN_LINE_WIDTH=0.5 mm
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5 mm FERR-EMI-600-OHM =PP3V3_ENETFW 7
I404 1 2 MIN_NECK_WIDTH=0.25 mm 1 2
I406 FW_TPB1 FW FW FW_TPB0 FW_TPB_N<0> 89 90
SM
SM
I407 FW_TPA2 FW FW FW_TPA1 FW_TPA_P<1> 89 90
1 C8900 1 C8901 1 C8906 1 C8907 1 C8908 1 C8917
FW_TPA2 FW FW FW_TPA1 FW_TPA_N<1> 10uF 0.001uF
I408 89 90
20% 20% 0.1uF 0.1uF 0.1uF 10UF
FW_TPB_P<1> 6.3V 50V 20% 20% 20% 10%
I410 FW_TPB2 FW FW FW_TPB1 89 90 ESR < 0.5 ohms 2 CERM 2 CERM 10V 10V 10V 6.3V
D I409 FW_TPB2 FW FW FW_TPB1 FW_TPB_N<1> 89 90

1206-1 402 2 CERM
402
2 CERM
402
2 CERM
402
2 X5R
805 D
I412 FW_TPA3 FW FW FW_TPA2 FW_TPA_P<2> 89 90
I411 FW_TPA3 FW FW FW_TPA2 FW_TPA_N<2> 89 90
FW_TPB3 FW FW FW_TPB2 FW_TPB_P<2>

I414
FW_TPB3 FW FW FW_TPB2 FW_TPB_N<2>
89 90
L8901 PP2V5_VESTA_BIASVDD2
VOLTAGE=2.5V
PP2V5_VESTA_FAVDDM
VOLTAGE=2.5V
L8909
I413 89 90
89 86 12 =PP2V5_ENETFW FERR-EMI-600-OHM MIN_LINE_WIDTH=0.5 mm MIN_LINE_WIDTH=0.5 mm
FERR-EMI-600-OHM =PP2V5_ENETFW 12 86 89
I416 VESTA_CLK24M_XTAL P38MM VESTA_CLK24M_XTALI 89
P38MM VESTA_CLK24M_XTALO 89 SM SM
I415
I417 P38MM VESTA_CLK24M_XTALO_R 89

1 C8903 1 C8909 1 C8911 1 C8918
0.1uF 0.1uF 0.1uF 10UF
20% 20% 20% 10%
Page Notes 10V

2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
6.3V
2 X5R
805

- _PPFW_PHY
- _PP3V3_FW L8902 PP2V5_VESTA_XTALVDD2 PP1V2_VESTA_FAVDDL L8913
- _PP3V3_ENETFW FERR-EMI-600-OHM VOLTAGE=2.5V
VOLTAGE=1.2V
FERR-EMI-600-OHM =PP1V2_ENETFW 7 86 89
- _PP2V5_ENETFW
- _PP1V2_ENETFW SM SM

1 C8904 1 C8905 1 C8913 1 C8914 1 C8915 1 C8919
10UF 0.001uF 0.1uF 0.1uF 0.1uF 10UF
(NONE) 10% 20% 20% 20% 20% 10%
2 6.3V
X5R 2 50V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 6.3V
X5R
805 402 402 402 402 805
- VESTA_DS_ONLY_EN0
N15
R14
P15
K11
K12
K13
L11
L12
M11
M12
L10
M10
N11
N12
If stuffed, adds external pull-up to 90 =PPFW_PHY
counter internal pull-down in Vesta.
XTALVDD2
BIASVDD2
PLLVDD2
See straps table for more information. R89141 FAVDDH FAVDDM FAVDDL
C - VESTA_PWR_CLASS_0
If stuffed, adds external pull-down to
390K
5%
1/16W
MF-LF
C
counter internal pull-up in Vesta. 402 2
See straps table for more information. RP8900
1
22 8
FW_CPS R13 CPS OMIT TDBL[0] A14 TP_VESTA_TDBL<0>
88 FW_DATA<0>
=PP3V3_FW TDBL[1] B13 TP_VESTA_TDBL<1>
Net Spacing Type: FW 5%
90 89 7
(Int PU) 89 VESTA_BILINGUAL_EN12_L C11 ESDET0
1/16W RP8900 VESTA_DS_ONLY_EN0 VESTA FW TDBL[2] B14 TP_VESTA_TDBL<2>
Line To Line: 0.38 mms
SM-LF 22 R89111
(Int PU) 89 VESTA_PORT1_DISABLE_L C12 ESDET1 R8902
88 FW_DATA<1> 3 6
1K
(Int PU) 89 VESTA_PORT2_DISABLE_L C13 ESDET2 U8600 22
Length Tolerance: 100 mils BCM5462 PLI_PCLK E15 89 FW_CLK98M_PCLK_R 1 2 FW_CLK98M_PCLK 88
5% 5%
Primary Max Sep: 7.5 mils RP8900 1/16W
SM-LF
1/16W
MF-LF FW_CLK98M_LCLK D15 PLI_LCLK
FBGA-200
3 OF 3
5%
1/16W
Secondary Max Sep: 100 mils 2
22 7 402 2
88
PLI_INT D13 FW_PINT 88 MF-LF
88 FW_DATA<2> 402
Secondary Length: 500 mils FW_DATA_R<0> E12 PLI_LINK D14 FW_LINKON 88
5% PLI_DATA[0]
NOTE: Target differential impedance for
1/16W
SM-LF
RP8901 FW_DATA_R<1> E11 PLI_DATA[1]
FW_TPBIAS<0> 90
22 TPBIAS[0] L13 MIN_NECK_WIDTH=0.25 mm
FW data pairs is 110 ohms. 88 FW_DATA<3> 4 5 FW_DATA_R<2> F11 PLI_DATA[2]
FW_DATA_R<3> F12 TPAP[0] L15 FW_TPA_P<0> 89 90
5% PLI_DATA[3]
RP8901 1/16W
SM-LF FW_DATA_R<4> F13 PLI_DATA[4]
TPAN[0] L14 FW_TPA_N<0> 89 90
22 TPBP[0] M15 FW_TPB_P<0> 89 90
88 FW_DATA<4> 2 7 FW_DATA_R<5> G13 PLI_DATA[5]
FW_DATA_R<6> G12 TPBN[0] M14 FW_TPB_N<0> 89 90
5% PLI_DATA[6]
1/16W
SM-LF
RP8901 FW_DATA_R<7> G11 PLI_DATA[7]
FW_TPBIAS<1> 90
22 TPBIAS[1] J13 MIN_NECK_WIDTH=0.25 mm
88 FW_DATA<5> 1 8
FW_CTL_R<0> E14 TPAP[1] J15 FW_TPA_P<1> 89 90
5% PLI_CTL[0]
RP8901 1/16W
SM-LF FW_CTL_R<1> E13 PLI_CTL[1]
TPAN[1] J14 FW_TPA_N<1> 89 90
22 TPBP[1] K15 FW_TPB_P<1> 89 90
88 FW_DATA<6> 3 6
FW_LPS D11 TPBN[1] K14 FW_TPB_N<1> 89 90
5% PLI_LPS
1/16W
SM-LF
RP8900 88
FW_LREQ D12 PLI_LREQ

FW_TPBIAS<2> 90
22 88
TPBIAS[2] H13 MIN_NECK_WIDTH=0.25 mm
88 FW_DATA<7> 4 5
FW_LOWPWR J3 TPAP[2] G15 FW_TPA_P<2> 89 90
LPWR_1394
B R8900
22
5%
1/16W
SM-LF
25
VESTA_DS_ONLY_EN0 A13
A12
DS_ONLY_EN0 Internal Pull-Down
TPAN[2] G14
TPBP[2] H15
FW_TPA_N<2>
FW_TPB_P<2>
89 90
89 90
B
88 FW_CTL<0> 1 2 VESTA_PWR_CLASS PWR_CLASS Internal Pull-Up
5%
TPBN[2] H14 FW_TPB_N<2> 89 90
VESTA_PWR_CLASS_0
1/16W
MF-LF R8901 R89121 TP_VESTA_TEST_1394<0> J5 TEST_1394[0]
402 22 SDC H1 I2C_VESTA_SCL
88 FW_CTL<1> 1 2 1K TP_VESTA_TEST_1394<1> J4 TEST_1394[1]
5%
TP_VESTA_TVCO_24 N13 SDA H2 I2C_VESTA_SDA
5%
1/16W
1/16W TVCO_24
MF-LF
MF-LF 402 2 Put crystal circuit close to PHY
402
89 VESTA_CLK24M_XTALI P14 RDAC2 R15 VESTA_RDAC2_PD
XTALI_24
89 VESTA_CLK24M_XTALO_R P13 XTALO_24
BIASGND PLLGND2
R89091
2.0K
1
R8921 1%
P12
N14
332 R89031 R8904
1 1/16W
MF-LF
1% 1K 10K 402 2
CRITICAL 1/16W 1% 1%
MF-LF 1/16W 1/16W
Y8920 2 402 MF-LF
402 2
MF-LF
24.576M 2 402
1 2
VESTA_CLK24M_XTALO 89
8X4.5MM-SM
C8920 1 C8921 1 =PP3V3_FW

22pF 22pF 90 89 7
5% 5%
50V 50V
VESTA_BILINGUAL_EN12_L 89
CERM 2 CERM 2
402 402
VESTA_PORT1_DISABLE_L 89 R89151 1
R8916
VESTA_PORT1_DISABLE VESTA_PORT2_DISABLE_L 89 10K 10K
5% 5%
VESTA_BILINGUAL_EN12
R8931 1
VESTA_PORT2_DISABLE
R8933 1
R8935 1
CRYSTAL LOAD CAPACITANCE IS 12PF 1/16W
MF-LF
402 2
1/16W
MF-LF
2 402
Vesta FireWire PHY
Vesta Config Straps: 1K 1K 1K
A PWR_CLASS - FireWire Power Class
5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF
(I2C_VESTA_SDA)
(I2C_VESTA_SCL)
SYNC_MASTER=N/A

SYNC_DATE=N/A
A
1 - Sets Power Class to 0x4 402 2 402 2 402 2
0 - Sets Power Class to 0x0 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
(Internal Pull-up) AGREES TO THE FOLLOWING
DS_ONLY_EN0 - Port 0 Data/Strobe
1 - Port 0 Data/Strobe mode only
0 - Port 0 Bilingual mode
(Internal Pull-down) SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.

D 051-6772 E
SCALE
NONE
SHT
89 102OF
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
NET_TYPE PP24V_RUN
SPACING PHYSICAL DIFFERENTIAL_PAIR
CRITICAL
8 WATTS MAX L9001
I401 FW FW FW_TPA0_FL FW_PORT0_TPA_P_FL 90
R9056 D9000
R9002 FERR-160-OHM
F9002 F9000
FW FW FW_TPA0_FL FW_PORT0_TPA_N_FL 90 0.5AMP 1.5AMP-33V
I400
FW FW FW_TPB0_FL FW_PORT0_TPB_P_FL 90
24 VOLTS 1
1.3 2 PP24V_FW
MURS320XXG
1 2 PP24V_FW_D 1
1.3 2 PP24V_FW_R 1 2 6 FW_VP 1 2 PPFW_PORT0_VP 1 2 PPFW_PORT1_VP 90
I402
MIN_LINE_WIDTH=0.8MM MIN_LINE_WIDTH=0.8MM MIN_LINE_WIDTH=0.8MM VOLTAGE=24V VOLTAGE=33V VOLTAGE=33V
I404 FW FW FW_TPB0_FL FW_PORT0_TPB_N_FL 90 20% MIN_NECK_WIDTH=0.25MM MIN_NECK_WIDTH=0.25MM 20% MIN_NECK_WIDTH=0.25MM 1206
MIN_LINE_WIDTH=0.8MM MIN_LINE_WIDTH=0.6 mm MIN_LINE_WIDTH=0.6 mm
1W VOLTAGE=24V SMC VOLTAGE=24V 1W VOLTAGE=24V MIN_NECK_WIDTH=0.25MM SM MIN_NECK_WIDTH=0.25 mm SM MIN_NECK_WIDTH=0.25 mm
FF MAKE_BASE=TRUE FF
I403 FW FW FW_TPA1_FL FW_PORT1_TPA_P_FL 90 2512 C9009 1 2512
I405 FW FW FW_TPA1_FL FW_PORT1_TPA_N_FL 90

0.1UF
20%
FW_PORT1_TPB_P_FL 50V
I407 FW FW FW_TPB1_FL 90 2
=PPFW_PHY 89
CERM
805
I406 FW FW FW_TPB1_FL FW_PORT1_TPB_N_FL 90
D D
"Snapback" & "Late VG" Protection
90 PP3V3_FW_ESD
DP9010 DP9010
BAV99DW-X-F BAV99DW-X-F
Termination C9010
0.001uF
1
2
SOT-363
C9011
0.001uF
1
5
SOT-363
Place close to FireWire PHY 20%

50V 6
20%
50V 3 PORT 0
CERM 2 CERM 2 FL9010
FW_TPBIAS<1> 402 402
89
89 FW_TPBIAS<0>
1 4
165-OHM
SM
SYM_VER-1
1394A
90 FW_PORT0_TPA_P 1 4
1 C9050 1 C9060 CRITICAL
J9000
1uF 1uF
10% 10% 90 FW_PORT0_TPA_N 2 3 FWS22
2 6.3V
CERM 2 6.3V
CERM F-ST-TH
402 402 FL9011
165-OHM 90 FW_PORT0_TPA_P_FL 6
(TPA+)
SM TPO
SYM_VER-1
90 FW_PORT0_TPA_N_FL 5
(TPA-)
90 FW_PORT0_TPB_P 1 4 TPO#
R90501 1
R9051 R90601 1
R9061 90 FW_PORT0_TPB_P_FL 4
(TPB+)
56.2 56.2 56.2 56.2 TPI
1% 1% 1% 1% 3
1/16W 1/16W 1/16W 1/16W FW_PORT0_TPB_N 2 3 90 FW_PORT0_TPB_N_FL (TPB-)
90
TPI#
402 2 2 402 402 2 2 402
DP9011 DP9011 (PPFW_PORT0_VP) 1
VP
89 FW_TPA_P<0> FW_PORT0_TPA_P 90 BAV99DW-X-F BAV99DW-X-F R9010 2
MAKE_BASE=TRUE SOT-363 SOT-363
VGND
C 89
89
FW_TPA_N<0>
FW_TPB_P<0>
FW_PORT0_TPA_N 90
MAKE_BASE=TRUE
FW_PORT0_TPB_P 90
MAKE_BASE=TRUE
2 5 1
0 2 GND_FW_PORT0_VG
VOLTAGE=0V
MIN_LINE_WIDTH=0.6 mm 7 8 9 10
C
FW_TPB_N<0> FW_PORT0_TPB_N 90 6 3 5% MIN_NECK_WIDTH=0.25 mm
89
MAKE_BASE=TRUE C9012 1 C9013 1 1/8W
MF-LF 1 C9015 C9016 1
0.001uF 1 0.001uF 4 805
89 FW_TPA_P<1> FW_PORT1_TPA_P 90 20% 20% 0.01uF 0.01uF
MAKE_BASE=TRUE 50V 50V 20% 20%
FW_TPA_N<1> FW_PORT1_TPA_N 90 CERM 2 CERM 2 2 16V 16V 514-0202
89 402 402 CERM CERM 2
MAKE_BASE=TRUE 402 402
89 FW_TPB_P<1> FW_PORT1_TPB_P 90
MAKE_BASE=TRUE
89 FW_TPB_N<1> FW_PORT1_TPB_N 90
MAKE_BASE=TRUE GND_CHASSIS_FIREWIRE 7 90
R9052 1 1
R9053 R9062 1 1
R9063
56.2 56.2 56.2 56.2
1% 1% 1% 1%
1/16W 1/16W 1/16W 1/16W
402 2 2 402 402 2 2 402
FW_TPA_C<0> FW_TPA_C<1> "Snapback" & "Late VG" Protection

1
R9054 1
R9064
C9054 1 4.99K C9064 1
1%
4.99K
1%
90 PP3V3_FW_ESD
270pF 1/16W 270pF 1/16W
5% MF-LF 5% MF-LF
25V 25V PPFW_PORT1_VP
CERM 2 2 402 CERM 2 2 402
402 402 DP9020 DP9020 90
BAV99DW-X-F BAV99DW-X-F
SOT-363 SOT-363
C9020 1 2 C9021 1
5
0.001uF 0.001uF
20% 20%
50V
CERM 2
6 50V
CERM 2
3
FL9020 PORT 1
3rd TPA/TPB pair unused 402
1
402
4
165-OHM
SM 1394A
SYM_VER-1
FW_PORT1_TPA_P 1 4
B 89 FW_TPBIAS<2> NC_FW_TPBIAS2
MAKE_BASE=TRUE
NO_TEST=YES
90
CRITICAL
J9001
B
89 FW_TPA_P<2> NC_FW_TPA_P2 90 FW_PORT1_TPA_N 2 3 FWS22
MAKE_BASE=TRUE F-ST-TH
NO_TEST=YES
FL9021 6
FW_TPA_N<2> NC_FW_TPA_N2 165-OHM 90 FW_PORT1_TPA_P_FL (TPA+)
89
MAKE_BASE=TRUE SM TPO
NO_TEST=YES SYM_VER-1
5
90 FW_PORT1_TPA_N_FL (TPA-)
90 FW_PORT1_TPB_P 1 4 TPO#
FW_PORT1_TPB_P_FL 4
90
TPI (TPB+)
89 FW_TPB_P<2> FW_TPB2_PD
MAKE_BASE=TRUE 3
NO_TEST=YES FW_PORT1_TPB_N 2 3 90 FW_PORT1_TPB_N_FL (TPB-)
90
TPI#
FW_TPB_N<2>
89
DP9021 DP9021 (PPFW_PORT1_VP) 1
VP
BAV99DW-X-F BAV99DW-X-F R9020
R90701 SOT-363 SOT-363
0
2
VGND
1K 2 5 1 2 GND_FW_PORT1_VG
5% VOLTAGE=0V 7 8 9 10
1/16W 6 3 MIN_LINE_WIDTH=0.6 mm
MF-LF 5% MIN_NECK_WIDTH=0.25 mm
402 2 C9022 1 C9023 1 1/8W
MF-LF 1 C9025 C9026 1
0.001uF 1 0.001uF 4 805
20% 20% 0.01uF 0.01uF
50V 50V 20% 20%
CERM 2 CERM 2 16V 16V
402 402 2 CERM CERM 2 514-0202
402 402
GND_CHASSIS_FIREWIRE 7 90
ESD Rail
FIREWIRE CONNECTORS
A 89 7 =PP3V3_FW R9090
L9090
400-OHM-EMI
PP3V3_FW_ESD
VOLTAGE=3.3V
90
SYNC_MASTER=N/A

SYNC_DATE=N/A
A
665 1 2 MIN_NECK_WIDTH=0.25 mm
1 2 PP3V3_FW_ESD_F
VOLTAGE=3.3V SM-1
1% MIN_LINE_WIDTH=0.38 mm PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
1/16W MIN_NECK_WIDTH=0.25 mm AGREES TO THE FOLLOWING
MF-LF
3

D9090
SOT23
BZX84C2V7-X-F
1
APPLE COMPUTER INC.

D 051-6772 E
SCALE SHT OF
NONE 90 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
USB2_0 USB2 USB2 USB2_0 USB2_P<0> 91 92
USB2_0 USB2 USB2 USB2_0 USB2_N<0> 91 92
D USB2_4 USB2 USB2 USB2_4 USB2_P<4> 76 91 D

USB2_NEC_XTAL P25MM NEC_CLK30M_XT1

NEC_CLK30M_XT2
91
L9135 PP3V3_PWRON_NEC_AVDD
P25MM 91
91 7 =PP3V3_PWRON_USB FERR-EMI-100-OHM VOLTAGE=3.3V
P25MM NEC_CLK30M_XT2_R 91
SM NOSTUFF
Page Notes R9135

1
4.7 2
C9135
10uF
20%
6.3V
CERM
C9136
0.1uF
20%
10V
CERM 2
1 C9137
0.1uF
20%
10V
1
CERM 2
Power aliases required by this page: 5% 805 402 402
- _PP3V3_PWRON_USB 1/10W
MF-LF
GND_NEC_AVSS_R 91
603
(NONE)
NOSTUFF
P12
A13
A12
L13
J13
H13
F13
D13
G12
N10
N12
BOM options provided by this page: C9120 1 C9121 1 C9122 1 C9123 1 C9124 1 C9125 1
P2
P3
A3
E2
N8
H4
D7
(NONE) 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
VDD
R9100
20%
6.3V 2
20%
10V
20%
10V
20%
10V
20%
10V
20%
10V 1
36 2
CERM CERM 2 CERM 2 CERM 2 CERM 2 CERM 2
AVDD
Net Spacing Type: USB2 805 402 402 402 402 402 1%
1/16W
RSDM1 M14 USB_NEC_N<0> MF-LF
Line To Line: 19.5 mils 402
DM1 M13 (USB2_N<0>) USB2_N<0> 91 92
Length Tolerance: 50 mils
DP1 L14 (USB2_P<0>) USB2_P<0>
Primary Max Sep: 7.5 mils C9126 1 C9127 1 C9128 1 C9129 1 C9130 1
RSDP1 K13 USB_NEC_P<0>
91 92
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

Secondary Max Sep: 100 mils 20%
10V
20%
10V
20%
10V
20%
10V
20%
10V CRITICAL R9101
Secondary Length: 500 mils CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 36
NOTE: Target differential impedance for
402 402 402 402 402 U7700 1
1%
2
USB2 data pairs is 90 ohms.

NEC_UPD720101_USB2 1/16W
MF-LF
C FBGA 402
C
R9102
1
36 2
91 7 =PP3V3_PWRON_USB
1%
1/16W
RSDM2 K14 USB_NEC_N<1> MF-LF
402
DM2 K12 (USB2_N<1>) USB2_N<1> 91 92
8 7 6 5 J14
DP2 (USB2_P<1>) USB2_P<1> 91 92
U2300 R91102 RP9110 RSDP2 J12 USB_NEC_P<1>
SHASTA 10K 10K R9103
5%
V1.0 1/16W 5%
1/16W 1
36 2
MF-LF SM-LF
BGA 402 1
1%
(8 OF 8) 1 2 3 4 1/16W
OMIT NC0 P7 TP_SB_NC_P7 6 MF-LF
402
NC1 P8 TP_SB_NC_P8 6 92 USB2_OC<0> (USB2_OC<0>) B12 OCI1
NC2 R3 TP_SB_NC_R3 6 92 USB2_OC<1> (USB2_OC<1>) B11 OCI2

R9104
NC3 R4 TP_SB_NC_R4 6 92 USB2_OC<2> (USB2_OC<2>) B10 OCI3
1
36 2
NC4 R5 TP_SB_NC_R5 6 92 USB2_OC<3> (USB2_OC<3>) A10 OCI4
1%
NC5 R6 TP_SB_NC_R6 6 76 USB2_OC<4> (USB2_OC<4>) B9 OCI5 1/16W
RSDM3 H11 USB_NEC_N<2> MF-LF
NC6 R7 TP_SB_NC_R7 6 402
DM3 G11 (USB2_N<2>) USB2_N<2> 91 92
NC7 R8 TP_SB_NC_R8 6 92 USB2_PWREN<0> C12 PPON1
DP3 G13 (USB2_P<2>) USB2_P<2> 91 92
NC8 T1 TP_SB_NC_T1 6 92 USB2_PWREN<1> A11 PPON2
RSDP3 G14 USB_NEC_P<2>
NC9 T2 TP_SB_NC_T2 6 92 USB2_PWREN<2> C11 PPON3
R9105
NC10 T3 TP_SB_NC_T3 6 92 USB2_PWREN<3> C10 PPON4 36
1 2
NC11 T4 TP_SB_NC_T4 6 92 USB2_PWREN<4> A9 PPON5
1%
NC12 T5 TP_SB_NC_T5 6 1/16W
MF-LF
NC13 T6 TP_SB_NC_T6 6 402
NC14 T7 TP_SB_NC_T7
B NC15 T8 TP_SB_NC_T8
6
6
R9106
36
B
NC16 U1 TP_SB_NC_U1 6 1 2
NC17 U2 TP_SB_NC_U2 6 1%
1/16W
NC18 U3 TP_SB_NC_U3 6 RSDM4 F12 USB_NEC_N<3> MF-LF
402
NC19 U4 TP_SB_NC_U4 6 91 7 =PP3V3_PWRON_USB DM4 F14 (USB2_N<3>) USB2_N<3> 91 92
NC20 U5 TP_SB_NC_U5 6 DP4 E12 (USB2_P<3>) USB2_P<3> 91 92
NC21 U6 TP_SB_NC_U6 6 RSDP4 E14 USB_NEC_P<3>

NC22 V1 TP_SB_NC_V1 6
R91401 R9141
1 R9107
36
NC23 V2 TP_SB_NC_V2 6 1.5K 1.5K 1 2
5% 5%
NC24 V3 TP_SB_NC_V3 6 1/16W 1/16W 1%
MF-LF MF-LF 1/16W
NC25 V4 TP_SB_NC_V4 6 402 2 2 402
MF-LF
402
NC26 W1 TP_SB_NC_W1 6
P6 NC1
NEC_NC1_PU
NC27 W3 TP_SB_NC_W3 6
M6 NC2 R9108
NEC_NC2_PU
NC28 Y1 TP_SB_NC_Y1 6
1
36 2
NC29 Y3 TP_SB_NC_Y3 6
1%
1/16W
RSDM5 E13 USB_NEC_N<4> MF-LF
402
DM5 D14 (USB2_N<4>) USB2_N<4> 76 91
DP5 C13 (USB2_P<4>) USB2_P<4> 76 91
L9 XT1/SCLK RSDP5 C14 USB_NEC_P<4>

91 NEC_CLK30M_XT1
R9109
91 NEC_CLK30M_XT2_R P8 XT2
1
36 2
1%
R9145
2 1/16W
MF-LF
100
5%
1/16W
402
USB Host Interfaces
MF-LF RREF P11 NEC_RREF_PD
A CRITICAL 1 402 SYNC_MASTER=N/A SYNC_DATE=N/A
A
AVSS(R)
Y9145
30.0000M NEC_CLK30M_XT2 91
R91381 NOTICE OF PROPRIETARY PROPERTY
1 2 9.09K
VSS AVSS 1% THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1/16W PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
P10
N14
H14
B14
N13
B13
M11
L12
H12
D12
J11
F11
P13
M12
N11
11.4X4.7X4.2-SM
B1
N1
A2
B2
N2
G4
D8
C9145 1 1 C9146 XW9100
SM
MF-LF
402 2
22pF 22pF Tie to GND at ball N11
5% 5% 1 2 II NOT TO REPRODUCE OR COPY IT
50V 2 50V
CERM 2 CERM GND_NEC_AVSS_R
402 402 91 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
VOLTAGE=0V
MIN_NECK_WIDTH=0.25MM SIZE DRAWING NUMBER REV.
Y9145 LOAD CAPACITANCE IS ??PF

APPLE COMPUTER INC.
D 051-6772 E
SCALE SHT OF
NONE 91 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
ELECTRICAL_CONSTRAINT_SET NET_SPACING_TYPE DIFFERENTIAL_PAIR NET_PHYSICAL_TYPE
PROVIDED USB2 USB2_PORT1_F USB2 USB2_PORT1_P_F 6 92
BY USB2_PORT1_N_F
USB
USB2
USB2
USB2_PORT1_F
USB2_PORT2_F
USB2
USB2 USB2_PORT2_P_F
6 92
6 92
External USB Ports
CONTROLLER USB2 USB2_PORT2_F USB2 USB2_PORT2_N_F 6 92
I526 USB2 USB2_PORT3_F USB2 USB2_PORT3_P_F 6 92
I527 USB2 USB2_PORT3_F USB2 USB2_PORT3_N_F 6 92 L9210

FERR-250-OHM
59 PP5V_USB2 1 2 6 PP5V_USB2_PORT1_F
VOLTAGE=5V SM VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM NOSTUFF NOSTUFF MIN_LINE_WIDTH=0.6MM
D MIN_NECK_WIDTH=0.25MM 1
C9210 1 C9211
10UF
D
150uF
Page Notes L9211
FERR-250-OHM
1 2
20%
2 6.3V
POLY
SMD
10%
16V
2 CERM
1210
Power aliases required by this page: SM

- _PP5V_PWRON_USB
- _PP5V_PWRON_UDASH
GND_USB2_PORT1
VOLTAGE=0V
C9212 1 C9213 1 CRITICAL
MIN_LINE_WIDTH=0.6MM 0.01uF 0.01uF
- _PP3V3_PWRON_UDASH MIN_NECK_WIDTH=0.5MM 20%
16V
20%
16V J9210
CERM 2 CERM 2 USB-UAS25
- _PP3V3_PWRON_BT 402 402 F-ST-TH
L9212 5
PORT 1
120-OHM
2012 6
(NONE) SYM_VER-1
NOTE: This page is expected to contain the 91 USB2_N<0> USB2_PORT1_N 1 4

MAKE_BASE=TRUE VDD 1
necessary aliases to map the USB2_PORT1_N_F 2
92 6 D-
USB pairs to their appropriate USB2_P<0> USB2_PORT1_P 2 3 USB2_PORT1_P_F 3
91 92 6 D+
destinations and/or to properly MAKE_BASE=TRUE 4
NOSTUFF GND
terminate unused signals. R9212 NO STUFF NO STUFF
0
BOM options provided by this page: 1 2 C9214 1 1 C9215 7
UNUSED PORT
(NONE) 402 33pF 33pF
5% 5%
50V 50V
NOSTUFF CERM 2 2 CERM 514-0199
NOTE: USB pairs are NOT constrained on R9213 402 402 91 USB2_N<3>
this page. It is assumed that the 0
1 2 91 USB2_P<3>
USB Host Controller page will 402
GND_CHASSIS_USB
provide the appropriate constraints R92101 1
R9211 R92501 1
R9251
to apply to entire USB D+/D- XNets. 15K 15K MIN_NECK_WIDTH=0.25MM 15K 15K
5% 5% MIN_LINE_WIDTH=0.6MM 5% 5%
1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF VOLTAGE=0 MF-LF MF-LF
neoBorg Implementation 402 2 2 402 7 92 402 2 2 402
C
C NOTE: This design does not provide power
L9220
FERR-250-OHM
control on USB ports 2-4. Rename 1 2 6 PP5V_USB2_PORT2_F
USB controller outputs to indicate SM
VOLTAGE=5V
NOSTUFF NOSTUFF MIN_LINE_WIDTH=0.6MM
single-pin connections. 1
C9220 1 C9221MIN_NECK_WIDTH=0.25MM
USB2_PWREN<0> TP_USB2_PWREN<0> 150uF 10UF
91
MAKE_BASE=TRUE
6
L9221 20%
2 6.3V
10%
16V
91 USB2_PWREN<1> TP_USB2_PWREN<1> 6
FERR-250-OHM POLY
2 CERM
MAKE_BASE=TRUE SMD 1210
1 2
91 USB2_PWREN<2> TP_USB2_PWREN<2> 6
MAKE_BASE=TRUE SM
91 USB2_PWREN<3> TP_USB2_PWREN<3>
MAKE_BASE=TRUE
6 GND_USB2_PORT2
VOLTAGE=0V
C9222 1 C9223 1
CRITICAL
MIN_LINE_WIDTH=0.6MM 0.01uF 0.01uF
91 USB2_PWREN<4> TP_USB2_PWREN<4>
MAKE_BASE=TRUE
6 MIN_NECK_WIDTH=0.5MM 20%
16V
20%
16V J9220
402 402 F-ST-TH
L9222 5
PORT 2
120-OHM
2012 6
SYM_VER-1
91 USB2_N<1> USB2_PORT2_N 1 4
MAKE_BASE=TRUE VDD 1
92 6 USB2_PORT2_N_F D- 2
91 USB2_P<1> USB2_PORT2_P 2 3 92 6 USB2_PORT2_P_F D+ 3

MAKE_BASE=TRUE 4
NOSTUFF GND
R9222 NO STUFF NO STUFF
0
1 2 C9224 1 1 C9225 7
402 33pF 33pF
5% 5%
50V 50V
NOSTUFF CERM 2 2 CERM 514-0199
R9223 402 402
1
0 2
B 402
GND_CHASSIS_USB 7 92
B
R92201 1
R9221
15K 15K
5% 5%
1/16W 1/16W
MF-LF MF-LF
402 2 2 402
F9200 L9230
2AMP-6V FERR-250-OHM
7 _PP5V_PWRON_USB 1 2 1 2 6 PP5V_USB2_PORT3_F
SM
VOLTAGE=5V
NOSTUFF NOSTUFF MIN_LINE_WIDTH=0.6MM
SM-1 MIN_NECK_WIDTH=0.25MM
1
C9230 1 C9231
150uF 10UF
1
R9200 L9231 20%
2 6.3V
10%
2 16V
160 FERR-250-OHM POLY CERM
SMD 1210
5% 1 2
1/10W
MF-LF SM
2 603
USB2_OC<0> USB_OC
GND_USB2_PORT3
VOLTAGE=0V
C9232 1 C9233 1 CRITICAL
91
MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6MM 0.01uF 0.01uF
USB2_OC<1>
16V
20%
16V J9230
91
1
R9201 402 402 F-ST-TH
91 USB2_OC<2> 300 L9232 5
PORT 3
5% 6
1/10W 120-OHM
91 USB2_OC<3> MF-LF 2012
SYM_VER-1
2 603
91 USB2_P<2> USB2_PORT3_P 1 4 92 6 USB2_PORT3_P_F VDD 1
MAKE_BASE=TRUE 2
D-
91 USB2_N<2> USB2_PORT3_N
MAKE_BASE=TRUE
2 3 92 6 USB2_PORT3_N_F
D+
GND
3
4 USB Device Interfaces
NOSTUFF
A R9232
1
0 2
NO STUFF
C9234 1 1
NO STUFF
C9235 7
SYNC_MASTER=N/A

SYNC_DATE=N/A
A
33pF 33pF
402 5% 5%
50V 2 50V 514-0199
CERM 2 CERM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
NOSTUFF 402 402 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
R9233 AGREES TO THE FOLLOWING
1 2 GND_CHASSIS_USB 7 92
402
R92301 1
15K 15K
5% 5% SIZE DRAWING NUMBER REV.
1/16W 1/16W
MF-LF
402 2
MF-LF
2 402
APPLE COMPUTER INC.
D 051-6772 E
SCALE SHT OF
NONE 92 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
Page Notes
- _PP3V3_PWRON_MODEM
Spec Load: 0.5 A active, 3 mA auxiliary
(NONE)
(NONE)
D D
Q52 Modem Connector

SDF9400
25 UDASH_SDOWN TP_UDASH_SDOWN STDOFF-4MM-9MMH-TH
MAKE_BASE=TRUE
1
CRITICAL
J9401
C104A-H9.0
F-ST-SM
NC 35
NC 31 32 NC
94 7 _PP3V3_PWRON_MODEM NC 1 2 NC
_PP3V3_PWRON_MODEM 7 94
3 4 NC
1 C9450 1 C9451 NC 5 6 MODEM_RING2SYS_L 6 25
1
R9451
10UF 0.1UF NC 7 8 10K
20% 20% 5%
6.3V 10V NC 9 10 NC 1/16W
2 CERM 2 CERM MF-LF
805 402 NC 11 12 NC
2 402
NC 13 14 MODEM_FC_RGDT
C 15
17
16 NC
18 NC
C
19 20
NC 21 22 I2S1_SYNC 6 25
25 6 I2S1_SB_TO_DEV_DTO 23 24 I2S1_DEV_TO_SB_DTI 6 25
25 6 I2S1_RESET_L 25 26
27 28
25 6 I2S1_MCLK 29 30 I2S1_BITCLK 6 25
NC 33 34 NC
NC 36
516S0116
SDF9401
STDOFF-4MM-9MMH-TH
GND_CHASSIS_MODEM 1
RJ11 CONNECTOR
STUFFED AT FATP
B SYMBOL USED FOR PLACEMENT B
OMIT
J9402
RJ11-HGT27.5
ST-TH
1
2
514-0205
From Intel Mobile Audio/Modem

Daughter Card Specification
Rev 1.0, February 22, 1999
1 - MONO_OUT/PC_BEEP 2 - AUDIO_PWRON
3 - GND 4 - MONO_PHONE
5 - AUXA_RIGHT 6 - RESERVED
7 - AUXA_LEFT 8 - GND
9 - CD_GND 10 - 5Vmain
11 - CD_RIGHT 12 - RESERVED
13 - CD_LEFT 14 - RESERVED
15 - GND 16 - PRIMARY_DN
17 - 3.3Vaux 18 - 5Vd
19
21
-
-
GND
3.3Vmain
20
22
-
-
GND
AC97_SYNC
Modem Interface
A 23
25
-
-
AC97_SDATA_OUT
AC97_RESET#
24
26
-
-
AC97_SDATA_INB
AC97_SDATA_INA
SYNC_MASTER=N/A

SYNC_DATE=N/A
A
27 - GND 28 - GND
29 - AC97_MSTRCLK 30 - AC97_BITCLK THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
APPLE COMPUTER INC.

D 051-6772 E
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NONE 94 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
D D
AUDIO CODEC
APPLE P/N 353S0933
VOLTAGE=3.3V
1000-OHM-200MA
102 101 100 7 PP3V3_AUDIO 1 2 PPV_3V3_AUDIO_CODEC PP4V5_AUDIO_ANALOG 96 102
0603
PLACE AT U9500
C9500 1
1 C9501 1 C9502 1 C9503
1UF 1UF 1UF
10UF 10% 10% 10%
R9503
1 20%
6.3V 2 10V
CERM 2 10V
CERM 2 10V
CERM
1K CERM 2 805 805 805 GND_AUDIO_CODEC 95 96 98 102
805
16
23
31
1%
7
1/16W
MF-LF VCC
VDD
2 402
U9500
PCM3052A
I2S0_BITCLK_DELAYED 11 VQFN 2
102 NET_SPACING_TYPE=AUDIO BCK VINL AUD_CODEC_IN_L 96
25 I2S0_SYNC 10 LRCK VINR 6 AUD_CODEC_IN_R 96
C AUDI2S0OUT
AUDSPDIFOUT
13
14
DOUT
DOUTS
VOUTL
VOUTR
25
24
AUD_CODEC_OUT_L
AUD_CODEC_OUT_R
98 100
98 100
C
25 I2S0_SB_TO_DEV_DTO NET_SPACING_TYPE=AUDIO 12 DIN
VCOM 26 AUD_PCM_VCOM 100
21 I2CEN VREF1 4 AUD_PCM_REF1
NC 20 ADR VREF2 5 AUD_PCM_REF2
18 I2C_AUDIO_SCL 19 SCL L/M# 3 AUD_CODEC_LI_SHDN_L 96
18 I2C_AUDIO_SDA 18 SDA REFO 32 AUD_PSEUDO_VREF 96
25 I2S0_RESET_L 9 PDWN* MBIAS 27 AUD_PCM_MBIAS 102

MINM 28 AUD_MICIN_N 102
102 AUD_CODEC_MCLK NET_SPACING_TYPE=AUDIO 17 SCKI
MINP 29 AUD_MICIN_P 102
R9500 NC 1 ATEST
33
25 I2S0_DEV_TO_SB_DTI NET_SPACING_TYPE=AUDIO 1 2
DGND AGND
1 C9504 1
C9506 1
C9508 1
C9510 1
C9512
5% 0.1UF 10UF 10UF 10UF 10UF
15
8
22
30
NOSTUFF 1/16W 10% 20% 20% 20% 20%
R9501
1 MF-LF 2 16V 2 16V 2 16V 2 16V 2 16V
C9513 1
47K
402 X7R
603
ELEC
SM
ELEC
SM
ELEC
SM
ELEC
SM
4.7PF 5%
+/-0.25PF 1/16W
50V
C0G 2 MF-LF
402 2 402 R9502 C9505 1 C9507 1 C9509 1 C9511 1
AUD_SPDIF_OUT 1
33 2 0.1UF 0.1UF 0.1UF 0.1UF
101 NET_SPACING_TYPE=AUDIO 10% 10% 10% 10%
5% 16V 16V 16V 16V
1/16W X7R 2 X7R 2 X7R 2 X7R 2
MF-LF 603 603 603 603
402
102 98 96 95 GND_AUDIO_CODEC
B B
AUDIO: CODEC
A SYNC_MASTER=AUDIO

SYNC_DATE=02/16/2005
A
APPLE COMPUTER INC.

D 051-6772 E
SCALE SHT OF
NONE 95 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
LINE IN PSEUDO-DIFFERENTIAL AMP

AV= 0.49
D D
NOSTUFF
C9603
47PF
102 96 95 PP4V5_AUDIO_ANALOG 1 2
5%
50V
CERM
402
C9600 R9604 R9607
10UF
2 1
20.5K2 10K
101 AUD_LI_L AUD_LI_L1 1 AUD_LI_L2 1 2
1% 1%
20% 1/16W 1/16W
16V MF-LF MF-LF
ELEC 402 CRITICAL 402
SM
D9600 10
U9600
1
R9603 C9602 1 BAV99DW-X-F
SOT-363
2
V+
MAX4253EUB
100K 0.47UF UMAX
R9602 1
1% 20%
10V
2 1 AUD_CODEC_IN_L 95
47K 1/16W CERM 2
5% MF-LF 603 6 3 5
1/16W 2 402 V-
MF-LF
402 2 1
4 APPLE P/N 353S0642
C9601 R9605
10UF
2 1
20.5K2
101 96 AUD_LI_GND AUD_LI_GNDL1 1 AUD_LI_VREFL
1%
20% 1/16W
R9600
1 16V
ELEC
MF-LF
402
165 SM
1%
C 1/16W
MF-LF
2 402 R9606
C
10K
96 95 AUD_PSEUDO_VREF 1 2
1%
1/16W
MF-LF
402
NOSTUFF
R9601
AUD_CODEC_LI_SHDN_L 1
0 2 AUD_CODEC_LI_SHDN_L1
95
5%
1/16W
MF-LF
402
NOSTUFF
C9606
47PF
102 96 95 PP4V5_AUDIO_ANALOG 1 2
5%
50V
CERM
402
C9604 R9609 R9612
10UF 20.5K2 10K
101 AUD_LI_R 2 1 AUD_LI_R1 1 AUD_LI_R2 1 2
1% 1%
20% 1/16W 1/16W
16V MF-LF MF-LF
ELEC 402 CRITICAL 402
SM
D9600 10
U9600
R9608
1 BAV99DW-X-F 8 MAX4253EUB
B 1%
100K 5
SOT-363 V+ UMAX
9 AUD_CODEC_IN_R 95
B
1/16W
MF-LF 3 7 6
2 402 V-
4
4 APPLE P/N 353S0642
C9605 R9610
10UF 20.5K2
101 96 AUD_LI_GND 2 1 AUD_LI_GNDR1 1 AUD_LI_VREFR
1%
20% 1/16W
16V MF-LF
ELEC 402
SM
R9611
10K
96 95 AUD_PSEUDO_VREF 1 2
1%
1/16W
MF-LF
402
AUDIO: LINE INPUT AMP

A SYNC_MASTER=AUDIO

A
APPLE COMPUTER INC.

D 051-6772 E
SCALE SHT OF
NONE 96 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
LINE OUT LOW-PASS FILTER

FC = 37 KHZ, HO = -1.4
R9801
14.0K2
1
1%
1/16W
MF-LF
402
D C9800 R9800 R9802 C9801 D

10UF 270PF
1 2
10K 3.92K2 1 2
100 95 AUD_CODEC_OUT_L AUDCODECOUTL 1 2 AUDCODECOUTL1 1 AUD_LOAMP_OUT_L 98
1% 1%
20% 1/16W 1/16W 5%
16V MF-LF MF-LF 50V
ELEC 402 402 CERM
SM-1 603
AUD_LOAMP_IN_L_M 98
CRITICAL
1 C9802
1.5NF
5%
25V
2 CERM
0603
R9803
AUD_LO_GND_PRB
14.0K2
1 AUD_LOAMP_IN_L_P
101 98
1%
1/16W
MF-LF R9804
1
402 10K
1%
1/16W
MF-LF
2 402 LINE OUT
GROUND NOISE
CANCELLATION
R9805
1
10K
1%
1/16W
MF-LF
102 98 96 95 GND_AUDIO_CODEC R9806 2 402
14.0K2
1 AUD_LOAMP_IN_R_P 98
CRITICAL 1%
C 1 C9804
1.5NF
1/16W
MF-LF
402
C
5% AUD_LOAMP_IN_R_M 98
25V
2 CERM
0603
C9803 R9807 R9808 C9805

10UF 270PF
1 2 10K 3.92K2 1 2
100 95 AUD_CODEC_OUT_R AUDCODECOUTR 1 2 AUDCODECOUTR1 1 AUD_LOAMP_OUT_R 98
1% 1%
20% 1/16W 1/16W 5%
16V MF-LF MF-LF 50V
ELEC 402 402 CERM
SM-1 603
R9809
14.0K2
1
1%
1/16W
MF-LF
402
LINE OUT AMP

APPLE P/N 353S0687
R9810 VOLTAGE=5V
PP5V_AUDIO_ANALOG 1
4.7 2
PP5V_AUDIO_LOAMP
102
5%
1/10W
MF-LF
603
1
C9806
10UF
B 20%
2 16V
ELEC
B
SM
C9807 1 GND_AUD_LOAMP_CHGPMP 98 102
10UF
20% CRITICAL
6.3V AUD_LOAMP_OUT_L
CERM 2 98
805 U9800 R9811
13
GND_AUD_LOAMP_CHGPMP 14
1
102 98 9
1 2 AUD_LO_L
PVDD
VDDR
VDDL
101
MIN_LINE_WIDTH=0.5MM 1% MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM 1/8W MIN_NECK_WIDTH=0.25MM
MF-LF
805
98 AUD_LOAMP_IN_L_M 14 LIN- LOUT 12
98 AUD_LOAMP_IN_L_P LIN+ MIN_NECK_WIDTH=0.25MM
MAX9722AETE MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM R9812
8 QFN 14
98 AUD_LOAMP_IN_R_M RIN- ROUT 10 1 2 AUD_LO_R 101
98 AUD_LOAMP_IN_R_P 7 RIN+ 1%
AUD_MAX9722_C1P 1/8W
C1P 2 MF-LF
805
TO SHASTA GPIO R9816 16 SHDN* C1N 4 1 C9808 1 C9809 AUD_LOAMP_OUT_R 98
1K AUDIO_LO_MUTE_L_F
PGND
SGND
PVSS
AUDIO_LO_MUTE_L 1 2 NC 17 1UF 1UF

VSS
25
10% 10%
5% 10V 10V
2 CERM 2 CERM
1/16W
805 805
R98151 MF-LF
3
11
4.7K C9812 1 402 C9813 1

AUD_MAX9722_C1N MIN_LINE_WIDTH=0.5MM
100PF 100PF
5%
1/16W 5%
50V
5%
50V
R9817
1
R9818
MF-LF CERM 2 CERM 2 1K 1K R9813
402 2 402 402 1% 1%
1/16W 1/16W
1
0 2 AUD_LO_GND 101
MF-LF MF-LF
2 402 2 402 5%
1/8W
AUDIO: LINE OUT AMP
MIN_LINE_WIDTH=0.25MM MF-LF
A 102 98 96 95 GND_AUDIO_CODEC MIN_NECK_WIDTH=0.2MM

AUD_MAX9722_PVSS
805 SYNC_MASTER=AUDIO

A
C9810 1 2
C9811 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1UF 10UF PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
10% 20%
10V 1 16V
CERM 2 ELEC I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
GND_AUD_LOAMP_CHGPMP 805 SM
102 98 II NOT TO REPRODUCE OR COPY IT
GND_AUD_LOAMP 1
0 2
102
5%
1/8W
MF-LF
805
D 051-6772 E
APPLE COMPUTER INC.
SCALE SHT OF
NONE 98 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
MIN_LINE_WIDTH=1MM
NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=1MM MIN_LINE_WIDTH=0.6MM
SPEAKER AMP
MIN_LINE_WIDTH=1MM MIN_NECK_WIDTH=0.25MM MIN_NECK_WIDTH=0.25MM MIN_NECK_WIDTH=0.25MM
VOLTAGE=12V FA000 VOLTAGE=12V
XWA000 VOLTAGE=12V LA000 VOLTAGE=12V APPLE P/N 353S0680
1.5AMP-33V OMIT
FERR-250-OHM
SM
PP12V_AUDIO_SPKRAMP_F PP12V_AUDIO_SPKRAMP_F2 PP12V_AUD_SPKRAMP_PLANE
D 7 PP12V_AUDIO_SPKRAMP 1 2 1 2 1
SM-1
2
D
SM
XWA003
OMIT
SM CA017 1
CA000 1 CA001 1 CA018 1 1 CA002 1 CA019 1 CA003 1 CA023
1 2 220UF 10UF 0.1UF 1UF 0.1UF 10UF 10UF
20% 220UF 10% 20% 20% 20% 10% 10%
16V 2 20%
ELEC 16V 2 16V 16V 16V 16V 16V 16V
SM-2 ELEC CERM 2 CERM 2 2 CERM 2 CERM 2 CERM 2 CERM
SM-2 1210 603 1206 603 1210 1210
102 100 GND_AUDIO_SPKRAMP_PLANE
GND_AUDIO_SPKRAMP_PLANE
AUD_MAX9714_CHOLD
100 102
LA005 CA004 PP3V3_AUDIO_SPKR 100

1000-OHM-200MA 0.47UF
98 95 AUD_CODEC_OUT_L 1 2 AUDSAMPINLN 1 2 NET_SPACING_TYPE=AUDIO
0603
1
RA014 NET_SPACING_TYPE=AUDIO LA001 MIN_LINE_WIDTH=0.5MM
10%
16V 10K MIN_LINE_WIDTH=0.5MM 180-OHM-1.5A
1 CA015 X7R
805 1/16W
MF-LF AUDSAMPOUTLP 1 2 AUD_SPKR_OUTL_P
100PF 101
21
22
5% 2 402 0603
3
4
LA006 2 50V
CERM CA005
1000-OHM-200MA 402
0.47UF VDD CHOLD 7
AUD_SAMP_INL_N 9 INL-
1 2 AUDSAMPINLP 1 2 NET_SPACING_TYPE=AUDIO
OUTL+ 31 MIN_LINE_WIDTH=0.5MM
0603
10% AUD_SAMP_INL_P 10 INL+ OUTL+ 32
LA002 MIN_NECK_WIDTH=0.25MM
16V MIN_NECK_WIDTH=0.25MM 180-OHM-1.5A
X7R
95 AUD_PCM_VCOM 805 OUTL- 29 AUDSAMPOUTLN 1 2 AUD_SPKR_OUTL_N 101
AUD_SAMP_INR_P 16 INR+
LA007 CA006 OUTL- 30 MIN_LINE_WIDTH=0.2MM
0603
1000-OHM-200MA 0.47UF NOSTUFF
1 2 AUDSAMPINRP 1 2
AUD_SAMP_INR_N 15 INR- U9700 C1+ 6 AUDSAMPCPP
0603 AUD_SAMP_G1 17 G1 MAX9714 1 CA008 LA011

800-OHM
10% 100 MIN_LINE_WIDTH=0.2MM 0.1UF
16V QFN MIN_NECK_WIDTH=0.15MM 10% ACM4532
100 AUD_SAMP_G2 18 G2 SYM_VER-1
50V
X7R C1- 5 AUDSAMPCPN 2 X7R
CA016 C
C
1 805 1 4
19 FS1 603-1
100 AUD_SAMP_FS1
100PF OUTR+ 27
5% 100 AUD_SAMP_FS2 20 FS2 NET_SPACING_TYPE=AUDIO
50V
OUTR+ 28 MIN_LINE_WIDTH=0.5MM
LA008 2 CERM
402 CA007 AUD_SAMP_SHDN_L 11
NET_SPACING_TYPE=AUDIO LA003 2 3 MIN_NECK_WIDTH=0.25MM
1000-OHM-200MA 0.47UF
SHDN*
OUTR- 25
180-OHM-1.5A
98 95 AUD_CODEC_OUT_R 1 2 AUDSAMPINRN 1 2 NC 8 NC OUTR- 26 AUDSAMPOURTP 1 2 AUD_SPKR_OUTR_P 101
0603 0603
10%
RA015 16V
AUD_MAX9714_VREG 14 REG
SS 12 NET_SPACING_TYPE=AUDIO
PP3V3_AUDIO_SPKR 1
10K 2 AUDIO_SPKR_MUTE_L_INV
X7R
805 MIN_LINE_WIDTH=0.2MM THM
AGND PAD
PGND NET_SPACING_TYPE=AUDIO LA004 MIN_LINE_WIDTH=0.5MM
100 MIN_NECK_WIDTH=0.15MM MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM 180-OHM-1.5A MIN_NECK_WIDTH=0.25MM
13
33
23
24
1%
1/16W AUDSAMPOUTRN 1 2 AUD_SPKR_OUTR_N 101
MF-LF
402 MIN_LINE_WIDTH=0.2MM 0603
NOSTUFF
TIE TO SHASTA GPIO RA013
D QA000 D QA000 AUDSAMPCSS
1 CA010 1 CA011 1 CA012 1 CA013
47K AUDIO_SPKR_MUTE_L_F
2N7002DW
SOT-363
2N7002DW
SOT-363
LA012
800-OHM 1000PF 1000PF 1000PF 1000PF
25 AUDIO_SPKR_MUTE_L 1 2 2 G S 5 G S ACM4532 5% 5% 5% 5%
SYM_VER-1
2 25V
CERM 2 25V
CERM 2 25V
CERM 2 25V
CERM
5% 603 603 603 603
1/16W 1 4 1 4
MF-LF
402 1 CA009
CA014 0.47UF
RA0121 CA020 1 CA021 1
1
0.47UF
10%
16V
2 3
4.7K 100PF 100PF 2 X7R
5%
1/16W 5% 5%
10%
2 16V 805 APPLE P/N 155S0194
50V 50V X7R
MF-LF CERM 2 CERM 2 805
402 2 402 402
XCA000
50R28
DIFFERENTIAL_PAIR=AUD_SPKRAMP_PWR
MIN_LINE_WIDTH=1MM MIN_LINE_WIDTH=1MM
1
MIN_NECK_WIDTH=0.25MM XWA001 MIN_NECK_WIDTH=0.25MM

B 102 7 GND_AUDIO_SPKRAMP 1
OMITSM
2
B
XWA002OMIT
SM
1 2
GAIN SETTINGS: +19DB

MODULATION SETTING: LOW EMI
GAIN AND SWITCHING FREQUENCY STUFF OPTIONS
MIN_LINE_WIDTH=0.1MM MIN_LINE_WIDTH=0.1MM
MIN_NECK_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MM
RA016 RA017
0 PP3V3_AUDIO_SPKR_EMI 0
102 101 95 7 PP3V3_AUDIO 1 2 1 2 PP3V3_AUDIO_SPKR 100
5% 5%
1/10W 1/10W
MF-LF NOSTUFF MF-LF 8 7 6 5
603 603
CA022 1 RPA000
100PF
5%
50V
47K
5%
CERM 2 1/16W
402 SM-LF
1 2 3 4
AUDIO: SPEAKER AMP
A 100
100
AUD_SAMP_G1
AUD_SAMP_G2
SYNC_MASTER=AUDIO

A
100 AUD_SAMP_FS1
100 AUD_SAMP_FS2 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
RA008
1
RA009
1 1
RA010 RA011
1
0 0 0 0
5% 5% 5% 5% III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1/16W 1/16W 1/16W 1/16W
2 402 2 402 2 402 2 402 SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.

D 051-6772 E
SCALE SHT OF
NONE 100 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
LINE IN JACK SPEAKER CABLE CONNECTOR
APPLE P/N 514-0203 APPLE P/N 518-0138
JA100 MIN_LINE_WIDTH=0.2MM FERR-EMI-100-OHM

LA100 LA104
MIN_LINE_WIDTH=0.2MM FERR-EMI-100-OHM MIN_LINE_WIDTH=0.2MM NET_SPACING_TYPE=AUDIO
AJR23 MIN_NECK_WIDTH=0.15MM MIN_NECK_WIDTH=0.15MM MIN_NECK_WIDTH=0.15MM
LA130 MIN_LINE_WIDTH=0.5MM
MIN_LINE_WIDTH=0.5MM LA133
F-ST-TH AUD_LI_L_JACK 1 2 AUD_LI_L_EMI 1 2 AUD_LI_L 96
5 180-OHM-1.5A MIN_NECK_WIDTH=0.3MM 180-OHM-1.5A
SM SM
6 100 AUD_SPKR_OUTR_P 1 2 AUD_SPKR_OUTR_P_CONN JA101 AUD_SPKR_OUTR_N_CONN 1 2 AUD_SPKR_OUTR_N 100
LA101 LA105 0603 10-89-7082 0603

MIN_LINE_WIDTH=0.2MM FERR-EMI-100-OHM M-ST-TH
MIN_NECK_WIDTH=0.15MM FERR-EMI-100-OHM MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.15MM 2 1
3 AUD_LI_DET_JACK 1 2 AUD_LI_DET_EMI 1 2 AUD_LI_DET_H 101 NET_SPACING_TYPE=AUDIO NET_SPACING_TYPE=AUDIO
LA131 MIN_LINE_WIDTH=0.5MM 4 3 MIN_LINE_WIDTH=0.5MM LA134
D
4
2
SM
SM
180-OHM-1.5A MIN_NECK_WIDTH=0.3MM 5
MIN_NECK_WIDTH=0.3MM 180-OHM-1.5A D
MIN_LINE_WIDTH=0.2MM FERR-EMI-100-OHM
LA102 LA106 100 AUD_SPKR_OUTL_N 1 2 AUD_SPKR_OUTL_N_CONN 8 7 AUD_SPKR_OUTL_P_CONN 1 2 AUD_SPKR_OUTL_P 100
7 MIN_NECK_WIDTH=0.15MM FERR-EMI-100-OHM MIN_LINE_WIDTH=0.2MM

MIN_NECK_WIDTH=0.15MM 0603 0603
AUDIO_GPIO_12_CONN
8 1 2
AUD_LI_R_EMI 1 2 102 101 100 95 7 PP3V3_AUDIO
AUD_LI_R_JACK AUD_LI_R 96
SM SM
1
RA113
47K
LA103 LA107 5%
1/16W
FERR-EMI-100-OHM FERR-EMI-100-OHM MIN_LINE_WIDTH=0.2MM
MF-LF
AUD_LI_GND_JACK 1 2 1 2 AUD_LI_GND 96
2 402 LA132
1000-OHM-200MA 1 CA126 1 CA127
MIN_LINE_WIDTH=0.2MM SM SM
102 101 7 MIN_NECK_WIDTH=0.15MM 25 AUDIO_GPIO_12 1 2 1000PF 1000PF
5% 5%
GND_CHASSIS_AUDIO_EXTERNAL 1 CA100 1 CA101 1 CA102 1 CA103 1 3 NOSTUFF SPEAKER TYPE DETECT 0603 25V
2 CERM
25V
2 CERM
MIN_LINE_WIDTH=0.2MM 100PF 100PF 100PF 100PF DZA100 TO SHASTA GPIO 603 603
2 50V
5%
2 50V
5%
2 50V
5%
2 50V 14V-15A
1 CA119 1 CA125 NOSTUFF NOSTUFF NOSTUFF NOSTUFF
101 AUD_LI_GND_EMI CERM
402
CERM
402
CERM
402
CERM
402 0405 1000PF 1000PF 1 CA104 1 CA105 1 CA106 1 CA107
5% 5%
2 4 2 25V 2 25V 1000PF 1000PF 1000PF 1000PF
CERM CERM 5% 5% 5% 5%
603 603 25V 25V 25V 25V
2 CERM 2 CERM 2 CERM 2 CERM
GND_CHASSIS_AUDIO_EXTERNAL 603 603 603 603
102 101 7
101 7 GND_CHASSIS_AUDIO_INTERNAL
LINE IN PLUG DETECT

AUDIO_IN_DET0_L = LOW: PLUG INSERTED LA108 LA111
AUDIO_IN_DET0_L = HIGH: PLUG NOT INSERTED FERR-EMI-100-OHM FERR-EMI-100-OHM
102 GND_AUDIO_MIC 1 2 GND_AUDIO_MIC_EMI 1 2
102 101 100 95 7 PP3V3_AUDIO
SM SM
JA102
RA101
1
HF28
47K LA109 LA112 M-ST-TH
RA100
1 5% FERR-EMI-100-OHM FERR-EMI-100-OHM
C 100K
5%
1/16W
1/16W
MF-LF
2 402
TO SHASTA GPIO 102 AUD_MIC_IN_P 1 2 AUD_MIC_IN_P_EMI 1 2
GND_AUDIO_MIC_CONN
6 AUD_MIC_IN_P_CONN
1
2 C
MF-LF AUDIO_LI_DET_L 25 SM SM 6 AUD_MIC_IN_N_CONN 3
2 402
3
LA110 LA113 APPLE P/N 518-0034 LINE OUT PLUG DETECTS
RA102
D
QA100 FERR-EMI-100-OHM FERR-EMI-100-OHM
101 AUD_LI_DET_H 1
47K 2 AUDLINDETH 1 G S
2N7002
SOT23-LF 102 AUD_MIC_IN_N 1
SM
2 AUD_MIC_IN_N_EMI 1
SM
2 MIC CABLE CONNECTOR AUDIO_LO_DET_L = LOW: PLUG INSERTED
5%
AUDIO_LO_DET_L = HIGH: PLUG NOT INSERTED
1/16W 2
MF-LF
402
1 CA108 1 CA120 1 CA121 1 CA122 AUDIO_LO_OPTICAL_PLUG_L = LOW: OPTICAL DIGITAL AUDIO PLUG INSERTED
0.1UF AUDIO_LO_OPTICAL_PLUG_L = HIGH: ANALOG AUDIO PLUG INSERTED
20% 1000PF 1000PF 1000PF
10V 10% 10% 10%
2 CERM
402 2 25V
X7R 2 25V
X7R 2 25V
X7R
402 402 402 102 101 100 95 7 PP3V3_AUDIO
101 7 GND_CHASSIS_AUDIO_INTERNAL 1
RA104
47K
LA114 LA122 1
RA103 5%
FERR-EMI-100-OHM FERR-EMI-100-OHM 100K
1/16W
MF-LF TO SHASTA GPIO
1 2 1 2 5% 2 402
95 AUD_SPDIF_OUT AUD_SPDIF_OUT_EMI AUD_SPDIF_OUT_JACK 1/16W
MF-LF AUDIO_LO_DET_L 6 25
SM SM
2 402
3 QA101
2N7002DW
LA115 LA123 MIN_LINE_WIDTH=0.25MM D SOT-363
FERR-EMI-100-OHM MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.2MM FERR-EMI-100-OHM MIN_NECK_WIDTH=0.2MM RA105
PP5V_AUDIO 1 2 PP5V_AUDIO_SPDIF_EMI 1 2
PP5V_AUDIO_SPDIF_JACK 47K 5
7 101 AUD_LO_DET1 1 2 AUD_LO_DET1_1 G S
SM SM
LINE OUT JACK 5%
1/16W
MF-LF 1 CA109 4
LA116 LA124 1 CA117 1 CA118 APPLE P/N 514-0204
402
0.1UF
FERR-EMI-100-OHM FERR-EMI-100-OHM 20%
0.1UF 1UF 2 10V
CERM
AUD_LO_DET1 1 2 AUD_LO_DET1_EMI 1 2 20% 10%
B
101
SM SM
2 10V
CERM
402
2 10V
CERM
805
JA103 402
B
JFJ8210
LA117 LA125 F-ST-TH
FERR-EMI-100-OHM 9 102 101 100 95 7 PP3V3_AUDIO
98 AUD_LO_R 1 2 AUD_LO_R_EMI 1 2 10
SM SM
MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.2MM AUD_LO_GND_JACK 1 RA107
1
TO SHASTA GPIO
47K
LA118 LA126 AUD_LO_DET1_JACK 3 1
RA106 5%
FERR-EMI-100-OHM MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.2MM AUD_LO_R_JACK 4 100K 1/16W
MF-LF
1 2 1 2 2 5% 2 402
98 AUD_LO_L AUD_LO_L_EMI MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.2MM AUD_LO_L_JACK 1/16W
MF-LF AUDIO_LO_OPTICAL_PLUG_L 25
SM SM
5 2 402
AUD_LO_DET2_JACK
6 QA101
LA119 LA127 6 D
2N7002DW
FERR-EMI-100-OHM FERR-EMI-100-OHM VIN SOT-363
7 RA108
LED
VDD
101 AUD_LO_DET2 1 2 AUD_LO_DET2_EMI 1 2
8 47K 2
GND 101 AUD_LO_DET2 1 2 AUD_LO_DET2_1 G S
SM SM
5%
11 NOSTUFF 1/16W 1
LA120 LA128 12
MF-LF 1 CA110
FERR-EMI-100-OHM MIN_LINE_WIDTH=0.25MM FERR-EMI-100-OHM
RA109
1 402
0.1UF
MIN_NECK_WIDTH=0.2MM 100K 20%
1 2 1 2 5% 2 10V
CERM
98 AUD_LO_GND AUD_LO_GND_EMI MIN_LINE_WIDTH=0.25MM 1/16W 402
SM SM MIN_NECK_WIDTH=0.2MM MF-LF
AUD_SPDIF_GND 2 402
RA1121
0
LA121 LA129 5% PLACE NEAR PLACE NEAR
FERR-EMI-100-OHM
1 2
FERR-EMI-100-OHM
1 2
1/16W
MF-LF
402 2
J9801 J700 AUDIO: Q45 CONNECTORS
AUD_LO_GND_PRB AUD_LO_GND_PRB_EMI
98
XCA100 XCA101
A SM SM 50R28 50R28 SYNC_MASTER=AUDIO

A
1 CA123
1 CA111 1 CA113 1 CA115
1
100PF 100PF 100PF AUD_LI_GND_EMI THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
100PF 5% 5% 5% 101
5% 50V 50V 50V
2 CERM 2 CERM 2 CERM AGREES TO THE FOLLOWING
2 50V GND_CHASSIS_AUDIO_INTERNAL
CERM
402
402 402 402
DZA101 101 7
1 CA124 1 CA112 MMBZ15DLT1
2

100PF 100PF
1 CA114 1 CA116 15V III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
5% 5% 100PF
2 50V 2 50V 5% 0.01UF SOT23
CERM CERM 50V 10%
402 402 2 CERM 16V SIZE DRAWING NUMBER REV.
2 CERM
402
D 051-6772 E
3
402
102 101 7 GND_CHASSIS_AUDIO_EXTERNAL APPLE COMPUTER INC.

SCALE SHT OF
NONE 101 102
8 5 4 3 2 1
7 6
www.vinafix.vn
8 7 6 5 4 3 2 1
RA226 RA227
UNUSED GPIO TERMINATIONS
0 0
TABLE_ALT_HEAD
1 2 I2S0_BITCLK_8NS_DELAY 1 2
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: ELECTRICAL_CONSTRAINT_SET=8NS
PART NUMBER 5% 5%
1/16W 1/16W
TABLE_ALT_ITEM
MF-LF MF-LF
353S0655 353S0933 U9500 PCM3052 402 NOSTUFF 402 MIN_LINE_WIDTH=0.3MM
RA225 102 101 100 95 7 PP3V3_AUDIO
0
25 I2S0_BITCLK 1 2 I2S0_BITCLK_DELAYED 95
NET_SPACING_TYPE=AUDIO 5%
1/16W NOSTUFF
D
MF-LF
402 1
RA228 RA206 D
0 AUDIO_LI_OPTICAL_PLUG_L 1
47K 2
5% 25
1/16W
MF-LF 5%
1/16W
2 402 MF-LF
402
RA207
47K
PLACE ACROSS GROUND SPLIT 25 AUDIO_HP_DET_L 1 2
AT RIGHT SIDE OF CA007 5%
5V POWER SUPPLY FOR THE HEADPHONES/LINE OUT AMP NOSTUFF
1/16W
MF-LF
402
RA216
0 RA208
100 GND_AUDIO_SPKRAMP_PLANE 1 2 GND_AUDIO_CODEC 95 96 98 102
47K
5% AUDIO_SPKR_DET_L 1 2
DIFFERENTIAL_PAIR=AUD_CODEC_PWR
APPLE P/N 353S0539 1/8W
MF-LF
25
5%
NET_SPACING_TYPE=AUDIO CRITICAL 805 1/16W
MIN_LINE_WIDTH=1MM MIN_LINE_WIDTH=0.6MM MIN_LINE_WIDTH=0.6MM MIN_LINE_WIDTH=0.6MM MF-LF
VOLTAGE=12V
VOLTAGE=12V
VOLTAGE=12V
VRA200 MIN_NECK_WIDTH=0.25MM
VOLTAGE=5V PLACE NEAR ENTRY TO SPEAKER
402
LA200 AMP GROUND PLANE RA209

FERR-250-OHM RA200 LM1117MPX NOSTUFF 47K
1 2 10 SOT223-4 25 I2S2_DEV_TO_SB_DTI 1 2
7 PP12V_AUDIO_CODEC AUD_12V_CODEC 1 2 AUD_12V_CODEC2 3 IN VOUT 4 PP5V_AUDIO_ANALOG 98 102
RA217 5%
SM-1 5% OUT 2 0 1/16W
1W
ADJ/GND 100 7 GND_AUDIO_SPKRAMP 1 2 MF-LF
FF 402
2512 1 RA2011 5%
1/8W
205 MF-LF
RA210
1% 805
1/16W 47K
1 CA200 1
CA201 1
CA209 MF-LF 25 AUDIO_GPIO_11 1 2
1UF 220UF 220UF 402 2 1
CA203 5%
20%
16V 20% 20% AUD_V5_REF 100UF 1/16W
2 CERM 2 16V 2 16V FC=7HZ 20% MF-LF
C 1206
ELEC
SM-2
ELEC
SM-2
2 16V
ELEC
SM
402
C
CA202 1 RA202 1
100UF 634 PLACE ACROSS GROUND SPLIT RA211

1%
20% 1/16W AT CODEC U9500 47K
16V 2 MF-LF 25 I2S2_BITCLK 1 2
ELEC 402 2
SM 5%
102 98 96 95 GND_AUDIO_CODEC 1/16W
RA205 MF-LF
402
0
102 98 96 95 GND_AUDIO_CODEC 1 2
5% RA212
4.5V POWER SUPPLY FOR CODEC AND LINE IN AMP 1/10W
MF-LF
603
25 I2S2_SYNC 1
47K 2
5%
APPLE P/N 353S0733 1/16W
MF-LF
402
CRITICAL RA213
VRA201 47K
PLACE AT J5903 25 AUDIO_HP_MUTE_L 1 2
MAX8510-4.5V MIN_NECK_WIDTH=0.25MM 5%
SC70-5 VOLTAGE=4.5V 1/16W
MF-LF
102 98 PP5V_AUDIO_ANALOG 1 IN OUT 5 PP4V5_AUDIO_ANALOG 95 96 402
RA229
0 RA214
RA203 1 3 SHDN* BP 4 1 CA206 101 7 GND_CHASSIS_AUDIO_EXTERNAL 1 2
47K
100K 0.01UF 5% 25 AUDIO_EXT_MCLK_SEL 1 2
NOSTUFF 1% 10% 1/8W
16V
1/16W GND 2 CERM MF-LF 5%
RA204 MF-LF
402 2 2
402
805 1/16W
MF-LF
100K 2 6 AUD_4V5_FB 402
102 101 100 95 7 PP3V3_AUDIO 1
1%
1/16W
AUD_4V5_SHDN* 1 CA207 1
CA208 RA215
MF-LF
1UF 10UF 47K
402 I2S2_RESET_L 1 2
B 1 CA204
10UF
1 CA205
0.1UF
10%
2 10V
CERM
805
20%
2 16V
ELEC
25
5%
1/16W
B
20% 10% NOT USED: C9906 SM-1 MF-LF
402
6.3V 16V
2 CERM 2 X7R
805 603
MICROPHONE IMPEDANCE MATCHING CIRCUIT MAKE_BASE=TRUE
TP_I2S2_SB_TO_DEV_DTO
I88
I2S2_SB_TO_DEV_DTO 25
MAKE_BASE=TRUE I89
AUDIO GROUND RETURNS AUD_PCM_MBIAS 95 TP_I2S2_MCLK I2S2_MCLK 25
MAKE_BASE=TRUE I116
DIFFERENTIAL_PAIR=AUD_CODEC_PWR NOSTUFF
NET_SPACING_TYPE=AUDIO 25 I2S0_MCLK AUD_CODEC_MCLK 95
MIN_LINE_WIDTH=1.0MM MIN_LINE_WIDTH=0.6MM
XWA200
VOLTAGE=4.5V
1 CA210 1
CA211
SM OMIT
10UF 10UF
20% 20%
7 GND_AUDIO 1 2 GND_AUDIO_CODEC 95 96 98 102
6.3V
2 CERM 2 16V
ELEC
805 SM-1
NOSTUFF
1
RA218 1
RA223
1K 1K GND_AUDIO_CODEC 95 96 98 102
MIN_LINE_WIDTH=0.25MM 1% 1%
MIN_NECK_WIDTH=0.15MM 1/16W 1/16W
XWA201 VOLTAGE=4.5V MF-LF MF-LF
SM OMIT
2 402 2 402
1 2 GND_AUDIO_MIC 101 102 DIFFERENTIAL_PAIR=AUDIO_MIC
NET_SPACING_TYPE=AUDIO RA219
DIFFERENTIAL_PAIR=AUDIO_MIC_1
NET_SPACING_TYPE=AUDIO CA213 DIFFERENTIAL_PAIR=AUDIO_MIC_2
0.1UF NET_SPACING_TYPE=AUDIO
165 1 2
MIN_LINE_WIDTH=0.6MM 101 AUD_MIC_IN_P 1 2 AUD_MIC_P1 AUD_MICIN_P 95
XWA202OMIT
VOLTAGE=4.5V 1%
1/16W 10% AUDIO: Q45 POWER SUPPLIES
SM
1 2 GND_AUD_LOAMP 98 CA212 1
MF-LF
402 RA2221 16V
X7R
100K
A
603 SYNC_MASTER=AUDIO SYNC_DATE=02/16/2005
DIFFERENTIAL_PAIR=AUDIO_MIC
1000PF
10%
25V 2
X7R
1%
1/16W
MF-LF CA214 NOTICE OF PROPRIETARY PROPERTY
A
NET_SPACING_TYPE=AUDIO 402 RA220 402 2
0.1UF
DIFFERENTIAL_PAIR=AUDIO_MIC_2
XCA201 XWA203
SM OMIT
VOLTAGE=4.5V
101 AUD_MIC_IN_N 1
165 2 AUD_MIC_M1 1 2 AUD_MICIN_N 95
50R28 AGREES TO THE FOLLOWING
1 1 2 GND_AUD_LOAMP_CHGPMP 98 1%
10%
NOSTUFF 1/16W DIFFERENTIAL_PAIR=AUDIO_MIC_1 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
MF-LF NET_SPACING_TYPE=AUDIO 16V
1
RA221 402 1
RA224 X7R
603 II NOT TO REPRODUCE OR COPY IT
1K 1K III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1% 1%
1/16W 1/16W
MF-LF MF-LF SIZE DRAWING NUMBER REV.
2 402 2 402
102 101 GND_AUDIO_MIC APPLE COMPUTER INC.

D 051-6772 E
SCALE SHT OF
NONE 102 102
8 5 4 3 2 1
7 6
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Rev E: Seedy

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Rev E: Seedy

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8 7 6 5 4 3 2 1

E 385505 PRODUCTION RELEASED

A 46 39 VTT VREG X.XX

49 41 GPU AGP GRAPHICS ANGLES

50 42 GRAPHICS VREGS DO NOT SCALE DRAWING

RELEASE SCALE SCH,MLB,SEEDY

SIZE DRAWING NUMBER

AIRPORT USB 2.0

NOTICE OF PROPRIETARY PROPERTY

D PP24V_RUN PP12V_RUN PP5V_RUN PP5V_ALL PP3V3_RUN SMU_PWRSEQ_P9_5 13 (PWR_GOOD_SB_CORE) D

PP3V3_ALL PP1V2_ALL PP3V3_ALL

PP5V_RUN_AUDIO CPU CORE PP2V5_RUN_CPU_AVDD PP5V_PWRON PP3V3_PWRON GPU CORE PP2V5_GPU_A2VDD

C LINEAR SWITCHER ALIAS

POWER BLOCK DIAGRAM

NOTICE OF PROPRIETARY PROPERTY

SIZE DRAWING NUMBER REV.

APPLE COMPUTER INC.

B CONNECTED GPU GPIOS

2.5 V REGULATOR - NEW NARROWER OUTPUT CAPS (C908, C909)

NOTICE OF PROPRIETARY PROPERTY

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION

343S0320 1 IC,U3LITE,NEW LAM,300MM,PBGA U3

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

TABLE_11_HEAD 343S0321 343S0320 U3 U3L,NEW LAM,200MM

337S3061 337S3060 CPU_1_8GHZ U2900 IC,DD3.1,1.8G,JRA 1.25V

337S2970 337S3060 CPU_1_8GHZ U2900 IC,DD3.0,1.8G,BRA 1.25V 343S0283 1 IC,ASIC,SHASTA,V1.1,PBGA U2300

337S2981 337S3060 CPU_1_8GHZ U2900 IC,DD3.0,1.8G,BPL 1.20V

337S2982 337S3060 CPU_1_8GHZ U2900 IC,DD3.0,1.8G,BRL 1.25V TABLE_5_HEAD

337S3056 337S3055 CPU_2_0GHZ U2900 IC,DD3.1,2.0G,KRA 1.25V

337S3058 337S3055 CPU_2_0GHZ U2900 IC,DD3.0,2.0G,CPA 1.20V

337S3059 337S3055 CPU_2_0GHZ U2900 IC,DD3.0,2.0G,CRA 1.25V TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION

062-2082 1 SPEC,VENDOR PACKAGING PROCEDURE VPP1

820-1747 1 PCB,FAB,MLB MLB1

825-6447 1 BARCODE LABEL, MLB, Q45 LBL1

341T1703 1 IC,SMU,Q45C/D U1300

CRITICAL 603-6015 1 HEAT SINK ASSEMBLY 17 IN MECH17 17_INCH_LCD

CRITICAL 603-6016 1 HEAT SINK ASSEMBLY 20 IN MECH20 20_INCH_LCD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

378S0119 378S0114 KINGBRIGHT LED

376S0204 376S0130 MOSFET,N-CH,VISHAY

376S0207 376S0146 MOSFET,N-CH,VISHAY

353S0960 353S0733 VRA201 MAX8510,L-F PART

353S0958 353S0653 U1301 DS1338, L-F PART

353S0687 353S0959 U9800 MAX9722 LEAD

B 353S0539 353S0898 VRA200 LM1117 LEAD

NOTICE OF PROPRIETARY PROPERTY

SIZE DRAWING NUMBER REV.

APPLE COMPUTER INC.

I390 NO_TEST=YES TP_SB_NC_T4 91 NO_TEST=YES RFBD<40> 53 54

I395 NO_TEST=YES TP_SB_NC_U1 91 NO_TEST=YES RFBD<47> 53 54

I402 NO_TEST=YES TP_SB_NC_V4 91 I927 NO_TEST=YES U2200_VC_D 22

I404 NO_TEST=YES TP_SB_NC_W1 91 NO_TEST=YES U2200_VC_R 22

I932 NO_TEST=YES U3320_DRN 33

NOTICE OF PROPRIETARY PROPERTY

I950 NO_TEST=YES TP_SATA_TXD_P2

1 2 _PP3V3_PWRON_MODEM 94 10 PP1V2_ALL PP1V2_VESTA 12

P/N 518-0159 1 2 PP12V_AUDIO_SPKRAMP 100 =PP3V3_PWRON_CPU 36

33 13 11 10 6 SYS_POWERUP_L 2 3 SYS_POWERUP_L_BUF =PP5V_RUN_CPU 3 6 8 31 =PP2V5_PWRON_HT 62

NOTICE OF PROPRIETARY PROPERTY

6 TP_RAM_CS_L_R<3> RAM_CS_L_R<3> 37 MAKE_BASE=TRUE 4.7K DEVELOPMENT

NOSTUFF NOSTUFF NOSTUFF

HSK-NUT-6.5MM HSK-NUT-6.5MM HSK-NUT-6.5MM