2022 International Symposium on Power Electronics,
Electrical Drives, Automation and Motion
Double pulse test method for neutral point clamped
2022 International Symposium on Power Electronics, Electrical Drives, Automation and Motion (SPEEDAM) | 978-1-6654-8459-6/22/$31.00 ©2022 IEEE | DOI: 10.1109/SPEEDAM53979.2022.9842036
inverter switches at the nominal rating while using
only half of the nominal DC link voltage
Juhamatti Korhonen, Aleksi Mattsson, Pasi Nuutinen,
Pasi Peltoniemi, Olli Pyrhönen, and Pertti Silventoinen
School of Energy Systems
Lappeenranta-Lahti University of Technology
Lappeenranta, Finland
Abstract—Double pulse test is the industry standard for
determining the switching characteristics of a semiconductor
switch. The component manufacturers implement the double
pulse test with a dedicated test setup with favorable layout for
minimizing the switching loop inductance. Such layout and min-
imized loop inductances may not be implemented with different
inverter topologies. Therefore, independent tests must be done for
each switch of the phase-leg to ensure the switching behavior for
each possible commutation loop. This procedure becomes more
critical with more complex phase-leg structures of multilevel
inverters. This paper presents a double pulse testing method
dedicated for a phase-leg of a three-level neutral point clamped
inverter. With the proposed method, all of the commutation loops
within the phase-leg can be tested at nominal voltage rating with
half of the nominal DC link voltage as input. The method is
verified with experimental results using a phase-leg of a medium
voltage three-level neutral point clamped inverter using 4.5 kV
rated insulated-gate bipolar transistors.
Index Terms—Pulse width modulation inverters, insulated gate
bipolar transistors, semiconductor device testing
I. I NTRODUCTION
Multilevel inverters are considered a viable solution for
high-power medium voltage applications and as a result several
multilevel inverter topologies have been adopted by the indus-
try [1], [2]. Multilevel inverters have attractive features over
the two-level inverter with the ability to increase the inverter
nominal voltage, reach a higher apparent switching frequency,
and have an improved output power quality.
Reliability of power electronic converters is determined by
testing at different stages of prototyping. A key test at an
early stage is the double pulse test (DPT). DPT is a standard
test for determining the switching behavior of semiconductor
switches. The primary outcomes of DPT are the reverse
recovery peak current at the turn-on, collector-emitter over
voltage during turn-off, and the calculation of the switching
losses of the turn-on and turn-off based on the collector current
(iC ) and collector-emitter voltage (uCE ).
DPT can be implemented to serve different purposes. The
first method is to have a dedicated testbed for testing different
switches with the same module type. This is used especially
by component manufacturers. The layout is conventionally
978-1-6654-8459-6/22/$31.00
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Riku Pöllänen
The Switch Drive Systems Oy
Lappeenranta, Finland
sw 1
+ d 5
H
sw 2
K n
D C K l-n
+ L d 6
sw 3
sw 4
Fig. 1. Single phase-leg of a three-level NPC.
optimized for a low stray inductance for ideal switching
waveforms. This type of dedicated DPT testbeds can be used
with varying pulse lengths to switching characteristics and
losses over the full current range of the switch [3]. This
feature of DPT can be extended to test the switch at different
operational temperatures [4]–[6]. This can be done for example
by adjusting the temperature of the base plate of the switch
module either with a hot plate [5], heating the case [4], or by
using a cryogenic chamber [6].
DPT has been used to compare the variations with different
samples of the same component, to test different switch
modules or housings, or different switch technologies and
semiconductors materials [4], [6]. The device under test (DUT)
of a typical dedicated DPT is the bottom switch of a phase
with an individual switch [6] or a half-bridge module [5], [7].
The switching characteristics of both upper and lower switch
can be tested for example in an H-bridge configuration [8].
Switching characterization may require topology specific DPT
set-ups, as for current source inverter with reverse-blocking
switches [9].
When an inverter or a converter is designed and built,
the switching loops for the commutations are defined by
the layout. Mutual coupling mechanisms will have an effect
on the actual loop inductance [10]. Therefore, the switching
characteristics of each switch should be tested for the inverter.
This approach has been studied with two-level inverters [11],
511
 sw 1 sw 1

D U T

D U T
sw 1 sw 1

C d 5 C d 5
C d 5 C d 5 H H

D U T
D U T
H H
sw 2 sw 2
sw 2 sw 2
n n n n
L L L L
d 6 d 6 d 6 d 6
sw 3 sw 3 sw 3 sw 3
C C C L C L
L L

sw 4 sw 4 sw 4 sw 4

(a) Device under test sw1 (a) Device under test sw2

sw 1 sw 1 sw 1 sw 1

C d 5 C d 5 C C d 5
H H
H d 5 H
sw 2 sw 2 sw 2 sw 2

n n n n
L L
d 6 d 6 L L
sw 3 sw 3 d 6 d 6

D U T
D U T
sw 3 sw 3
C C
L L
C L C L
D U T

D U T

sw 4 sw 4
sw 4 sw 4

(b) Device under test sw4 (b) Device under test sw3

Fig. 2. Short loop double pulse test configurations. The current paths are Fig. 3. Long loop double pulse test configurations. The current paths are
illustrated with red traces. The figures on the left illustrate the current path illustrated with red traces. The figures on the left illustrate the current path
when DUT is conducting and the figures on the right when DUT is not when DUT is conducting and the figures on the right when DUT is not
conducting. conducting.

T-type inverter [12], and active neutral point clamped inverter NPC using 4.5 kV rated insulated-gate bipolar transistors.
(ANPC) [10], [13]–[15]. II. NPC PHASE - LEG DOUBLE PULSE TEST PRINCIPLE
The measurement results from DPT may be used for im- The three-level NPC inverter is able to produce three line-
proving simulation models [16] or simulation of switching to-neutral voltage levels. The three output voltages of the
losses of different inverter topologies using DUT data [7]. phase-leg are produced with the three switching states shown
They can also be used for calculation of the effective switching in Table I. Even though the switching states do not have
loop stray inductances [10]. any redundancy, the current path of the zero output voltage
With different inverter topologies and with different layouts, state depends on the current polarity. These current loops
the commutation path stray inductances may vary significantly. are referred to as short and long loops. For example, when
For example, with a three-level neutral point clamped (NPC) transitioning from the state ul-n = +uDC /2 to ul-n = 0, with
inverter this characteristic was simulated in [17], and demon- positive output current the short loop through diode d5 and
strated with measurements for NPC and ANPC in [10], [18]. sw2 will take place. Alternatively, the same transition with
This paper focuses on testing of the individual switches negative output current will result in the long current loop
within a three-level NPC [19]. A single phase-leg of NPC is through d6 and sw3.
composed of four semiconductor switches and two diodes. The
single-phase presentation of the topology is shown in Fig. 1. TABLE I
NPC has an inherent characteristic in asymmetric loading of NPC SWITCHING STATES
the inner switches (sw2 and sw3) and the outer switches (sw1 ul-n sw1 sw2 sw3 sw4
and sw4) [20]. This asymmetry does not take into account the +uDC /2 1 1 0 0
potential asymmetry caused by the layout and coupling effects. 0 0 1 1 0
−uDC /2 0 0 1 1
This paper proposes a new test set-up for DPT of three-level
NPC. The proposed test configuration uses only half of the
nominal DC link voltage as the input, while being able to test DPT can be performed on each of the four switches of the
all of the phase-leg switches at nominal voltage. The proposed NPC phase-leg. The test can be implemented with either a full
method is verified with DPT of a medium voltage three-level DC link voltage connected to the DC bus, or as proposed in

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 this paper by applying half of the DC link voltage to either the TABLE II
positive side capacitance CH or the negative side capacitance DPT GATE COMMANDS FOR EACH DUT
CL . DUT sw1 sw2 sw3 sw4
The proposed DPT requires modified connections to the sw1 1⇒0⇒1 1 0 0
phase-leg, as shown in Figs. 2 – 3. As only half of the DC link sw2 0 1⇒0⇒1 1 0
sw3 0 1 1⇒0⇒1 0
is used for the testing, the other DC link capacitance must sw4 0 0 1 1⇒0⇒1
be disconnected from the circuit. For example, when DUT is
sw1 or sw2, the negative side DC link capacitance CL must be
disconnected. As for the DPT results, disconnecting the other 4 0 0 V / 1 2 -p u ls e
1 0 0 0 V / re c tifie r
DC link capacitance will not have any effect on the resulting sw 1
1 0 0 0 V
current loop for the DUT. V a ria b le tra n s fo rm e r C H d 5
tra n s fo rm e r
The short loop commutations can be tested when DUT sw 2
is sw1 or sw4, as shown in Fig. 2. During these DPTs,
the load inductor is connected between the phase-leg output C d 6
L
sw 3 L
and the neutral point (n). The device under test runs the
pulse sequence of DPT, while the other switches use the sw 4
corresponding switching states from Table I, and the actual
switching states are given in Table II. For example, when DUT
Fig. 4. Double pulse test setup consisting of a variable transformer connecting
is sw1, the charge pulse of DPT starts when sw1 and sw2 are to the grid, 400V/1000V/1000V transformer, 12-pulse rectifier, NPC phase-
set to conduct. The charge pulse results in a positive output leg, and output inductor L. The connections of the rectifier with the DC link
current to the phase-leg, and corresponds to the switching state capacitors, and the output inductor connections are varied depending on the
device under test.
of ul-n = +uDC /2. The switch sw2 is left to conduct for the
whole duration of DPT. At the end of the charge pulse, DUT
is set to non-conductive state and the current path commutates
from sw1 to d5, through the short loop. The duration of the
rest period (time between the two pulses) and the second pulse
are set at the minimum pulse requirement of the switch, and
as a result sw3 should not be set to conduct. Once DPT is
finished, all of the switches are set to non-conductive states.
The double pulse tests of sw2 and sw3 form long loops,
as illustrated in Fig. 3. Now the load inductor is connected
between the inverter output and one of the DC rails (to DC−
when DUT is sw2, and to DC+ when DUT is sw3). For both
of these tests the starting output voltage state is the zero output
voltage state from Table I. The test for sw3 is as follows.
The pulses of DPT are formed with the long loop current
path, going through sw3 and d6. This pulse causes a negative
current to flow through the load. When the charge pulse ends
as sw3 is turned off, but again sw1 is not set to conduct due to Fig. 5. Double pulse test setup. 1. NPC phase-leg 2. DC link with laminated
the minimum pulse requirement. The current path during the bus bars 3. diode rectifier 4. load inductor L. The inductor L is in a separate
rest period flows through the freewheeling diodes of sw1 and cabinet, because a full back-to-back NPC inverter is to be completed in the
cabinet seen on the left.
sw2, and the switching sw1 to conduct during the rest period
would not contribute to the test. Therefore, the commutations
of the described DPT are identical to the states ul-n = 0 to allows the testing of the switching characteristics of all of the
ul-n = +uDC /2 and back to ul-n = 0 in case of a negative four switches with the actual commutation loops interfacing
load current. Again, when DPT sequence has finished, the gate the DC link capacitors.
commands of all of the switches are set to non-conductive The inverter was designed for 3.3 kV nominal voltage,
values. which means that the DC link voltage with a diode rectifier
will be uDC = 4.67 kV and with an active front-end with
III. E XPERIMENTAL VERIFICATION
a 10 % boost uDC = 5.13 kV. The designed PEBB structure
A. Test setup description allows both rectifier versions. In an ideal case, each switch of
The proposed DPT method was experimentally tested with the phase-leg should withstand half of the DC link voltage,
a three-level NPC phase-leg. The layout of the inverter was but the voltage fluctuations of the DC link capacitors require
implemented with a single NPC phase-leg being connected to an increased tolerance for the voltage over the switch. The
the DC link with laminated bus bars. This kind of a structure capacitor voltage fluctuations are caused by fluctuations on the
for the phase-leg power electronic building block (PEBB) bus voltage, as well as the neutral point voltage fluctuation.

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800
600
i L (A)
400
200
0 sw1
3000
u L (V)
2000
1000
0
0 10 20 30 40 50 60 70
Time (μs)
Fig. 6. Measured DPT inductor current (iL ) (top) and the load voltage (uL )
(bottom).
For this voltage rating 4.5 kV rated IGBTs were selected, as
semiconductor switch manufacturers conventionally set their
testing voltage at uCE = 2.8 kV.
Based on the required voltage rating, the following semi-
conductor modules were selected for the phase-leg PEBB:
• ABB 800A chopper module, 5SNE 0800G450300
• ABB 1200A single switch module, 5SNA 1200G450350
The chopper modules are used to combine a switch that is
connected to a DC rail and a neutral point connected diode,
as follows: sw1 and d5 in one chopper module, and sw4 and d6
in the second chopper module. The switches sw2 and sw3 are
implemented with the single switch modules. The power rating
of the phase-leg is defined by the chopper module current
rating.
The double pulse test setup consists of a variable trans-
former, 400V/1000V/1000V step-up transformer, twelve-pulse
rectifier, DC link, NPC phase-leg, and an output inductor, as
shown in Fig. 4. The 400V/1000V/1000V transformer has two
secondary windings with a 30◦ phase-shift, and the secondary
windings are used to form a 12-pulse rectifier. The output
voltage of the 12-pulse rectifier is 2.83 kV with the 400 V
input. The variable transformer can be used to adjust the DPT
voltage for the full voltage range. The DC link capacitances
are CH = CL = 680 μF. A picture of the double pulse test
setup is shown in Fig. 5.
B. Double pulse test dimensioning
The double pulse test switching pattern is dimensioned to
have two pulses: the first pulse is referred to as the charge
pulse with the duration t1 and the second test pulse with
the duration of t2 . The dimensioned maximum test DC link
voltage uDC /2 was 2.8 kV, and for the test pulse duration
calculation the voltage is assumed to be constant. In the actual
test, the DC link voltage is expected to drop, depending on the
power losses during DPT. The test load inductor was selected
to be L =170 μH. The duration of the pulses are calculated
with the following procedure. First, the overall charge period
ttot can be calculated with
2imax L
ttot = t1 + t2 = , (1)
uDC
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TABLE III
M EASURED PEAK COLLECTOR - EMITTER VOLTAGES DURING TURN - OFF
AND PEAK COLLECTOR CURRENTS AT TURN - ON .
DUT uCE,peak (V) iC,peak (A) iRR (A)
3327 1159 575
sw2 3280 1348 764
sw3 3194 1187 603
sw4 3257 1075 491
80
where imax is the maximum current at the end of DPT. The
test pulse pattern has a limitation of minimum pulse length
set by the switches. The minimum pulse duration is used for
the rest period (time between the two test pulses) and the
duration of the second pulse t2 . The minimum pulse for the
used switches is 10 μs. Therefore, the first pulse has a duration
of t1 = ttot − 10 μs. The time between t1 and t2 is the
minimum pulse length (10 μs), which is not included in ttot .
With the maximum current of imax = 800 A of the chopper
module, the pulse lengths are t1 = 38 μs and t2 = 10 μs. For
the tests presented in this paper, the selected pulse times were
t1 = 36 μs and t2 = 10 μs.
C. Measurement instrumentation
For the double pulse test, the following measurements were
used:
• Rohde & Schwarz RTH1004 oscilloscope
• Tektronix P5210 differential voltage probes, 50 MHz
bandwidth
• CWT Rogowski coil, CWTUM/3/B, 6 kA peak current,
30 MHz bandwidth
For each DPT, the measurements were the voltage over
DUT (uCE ), the current of the switch (iC ), and the load
voltage (uL ). The inductor current (iL ) was measured with
some double pulses, but the inductor current waveform was
assumed constant as the pulse sequence was not modified.
D. Measurement results
The first measurements shown in Fig. 6 illustrate the induc-
tor current (iL ) and the load voltage (uL ) measured between
the NPC phase-leg output and the neutral point (n), as depicted
in Fig. 2(a). The measured switching currents and switching
instants from Fig. 6 are
• iP1,off = 619 A (t = 46 μs)
• iP2,on = 584 A (t = 56 μs)
• iP2,off = 748 A (t = 66 μs)
where iP1 refers to the charge pulse current and iP2 test pulse
currents. Based on the measurements, the inductor current
dropped 35 A during the rest period between the pulses.
The DUT measurement results for all switches sw1–sw4
are shown in Figs. 7 – 10, while using the proposed method as
shown in Figs. 2 – 3. The key results of these measurements are
shown in Table III with peak collector-emitter voltages during
turn-off uCE,peak at the end of the test pulse, peak collector
currents at turn-on of the test pulse iC,peak , and the reverse
recovery current during the test iRR .
514
 1500 1500
1000 1000
i C (A)

i C (A)
500 500
0 0
3000 3000
u CE (V)

u CE (V)
2000 2000
1000 1000
0 0
0 10 20 30 40 50 60 70 80 0 10 20 30 40 50 60 70 80
Time (μs) Time (μs)

Fig. 7. Measured collector current iC and collector-emitter voltage uCE , Fig. 9. Measured collector current iC and collector-emitter voltage uCE ,
when DUT is sw1. when DUT is sw3.

1500 1500
1000 1000
i C (A)

i C (A)
500 500
0 0
3000 3000
u CE (V)

u CE (V)

2000 2000
1000 1000
0 0
0 10 20 30 40 50 60 70 80 0 10 20 30 40 50 60 70 80
Time (μs) Time (μs)

Fig. 8. Measured collector current iC and collector-emitter voltage uCE , Fig. 10. Measured collector current iC and collector-emitter voltage uCE ,
when DUT is sw2. when DUT is sw4.

The test results are evident, that the phase-leg commutation
loops have mutual coupling mechanisms, which effect the loop
inductance, regardless of the symmetrical physical dimensions
of the layout. Even though the same modules were used for
the outer switches and the neutral point diodes (sw1 with d5
and sw4 with d6), and for the inner switches (sw2 and sw3),
the resulting uCE,peak and iC,peak were not the same in any
of the measurements.
The proposed method was found feasible and the required
voltage rating of 2.8 kV per NPC phase-leg semiconductors
was achieved conveniently with the step-up transformer 1 kV
secondary windings. With the proposed method it is possible
to test all of the commutation loops and to provide the full
voltage stress to the switches even when only half of the DC
link voltage is available.
IV. C ONCLUSIONS
Testing of power electronic converters is crucial for
determining safe operation. As for the semiconductor switches,
double pulse test is used for measuring transient peak values
during switching commutations within the converter. The
layout of the converter affects the switching behaviour, and
as a result it is important to test each commutation loop of the
converter. In this paper a method for testing each commutation
loop of a three-level NPC phase-leg PEBB with half input
voltage was proposed and it was verified with experimental
results. The proposed method demonstrates how a PEBB
switching behavior can be tested comprehensively at nominal
voltage of each semiconductor switch, even though a scaled
input voltage is used. Further, the acquired test results show the
importance of switch and commutation loop specific tests in
order to determine the peak values of collector-emitter voltage
and collector current during switching operations, as they may
vary among the phase-leg switches.
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