NAVSEA AD6640 Total Dose Test Report: Surface Warfare Center

NAVSEA AD6640 Total Dose
Test Report
Surface Warfare Center
Final Report
Prepared for:
NASA GSFC/J&T
Code 562.1
GreenBelt, MD 20771
Prepared by:
NAVSEA Crane - Surface Warfare Center Division
John P. Bings, October 30, 2001
Code 6054, Building 2088
300 Highway 361
Crane, IN 47522-5001
Summary
NAVSEA Crane Division performed total dose testing on a total of five Analog Devices AD6640,
12 bit ADC’s; three parts were statically biased, two dynamically biased. Results of the total dose
testing indicate:
• AD6640 experienced no functional or parametric failures up to 30krad(Si).
• Two AD6640s were tested to 100krad(Si) and no functional or parametric failures were
observed.
• No significant changes in aperture uncertainty jitter were noted up to 30krad(Si), nor for the
two devices tested up to 100krad(Si).
Introduction
Purpose
This testing was performed to provide parametric and radiation hardness performance
information on the AD6640 ADC for NASA.
Background
The AD6640 is a commercial 12 bit, 65 MHz monolithic ADC manufactured by Analog Devices
Inc. on their XFCB 1.5 process. The units are packaged in a 44 terminal Plastic Thin Quad
Flatpack (TQFP). A total of 2 Analog Devices evaluation boards were used for testing. The
evaluation boards were pre-manufactured, unpopulated boards made by ADI to aid customers in
evaluation of their product. The evaluation boards were modified for use in Co-60 and populated
by NAVSEA Crane Division.
Test Samples
A total of five AD6640’s (serial numbers 1, 3, 4, 6 and 7) were tested. All devices had a date
code of 9951.
Table 1 gives a summary of the AD6640 specifications of interest.
AD6640
Resolution 12 bits
Speed 65 MSPS
Power Consumption (max) 865 mW
Analog Input 2.0 V peak-peak
DNL ±0.5LSB (typical)
SINAD 68 dB at 2.2 MHz
ENOB 11.0 bits typical at 2.2 MHz
Aperture Uncertainty (Jitter) 0.3 ps rms typical, <1.0ns for NASA testing
Table 1 – AD6640 Specifications of interest
(Refer to AD6640 Specification Sheet in Appendix B for further information.)
Facilities
All testing was performed at NAVSEA Crane Code 6054, using a Shepherd Model 484 Cobalt-60
tunnel irradiator.
Test Setup
The electrical testing was done on a customized ADC test bench. The ADC test bench utilized a
HP6626A System DC Power Supply, two HP 8644(A&B) Synthesized Signal Generators, a HP
3458A Multimeter and an HP8131A Pulse Generator. A HP16500B Logic Analyzer was added
for high-speed data capture facilitating aperture uncertainty (jitter) measurements. An HP82000
ATE was used for parametric tests as well as some dynamic functional testing. ADI provided
evaluation boards that served as a test fixture to route power, input and output signals between
the test device and the acquisition system. A picture of a populated test board used for bias and
testing is shown in Figure 1. Two fully populated boards were used and the three additional parts
tested were swapped into these populated boards. All parts were retained for possible future
testing and analysis, if required.
Figure 1 - Populated Evaluation Board
Three parts were tested with a static bias applied during irradiation and the remaining two parts
were tested with a dynamic bias applied. Static bias devices were irradiated with nominal DC
power applied and the clock, and all other inputs grounded. Dynamic bias used the same
nominal DC power as the static bias condition, a 62.5 MHz Encode clock signal and a 1 MHz, 1.7
volt peak-to-peak amplitude sinusoidal input signal.
The parameters tested were signal-to-noise and distortion (SINAD), effective number of bits
(ENOB), aperture uncertainty jitter, total harmonic distortion (THD) and Differential Non-Linearity
(DNL). Functional power supply currents and the DC Parameters were measured using an
HP82000.
Aperture uncertainty (jitter) is a calculated value of two separate measured values. The Analog
Devices application note containing the procedure for calculating aperture uncertainty (jitter) can
be found in Appendix C.
Bias conditions used for total dose tests:
Static Bias for parts #1 and #6:

DVdd = +3.3V; AVdd = +5.0V
Clock = GND
Ain = GND
Dynamic Bias for parts #3, #4 and #7:

DVdd = +3.3V; AVdd = +5.0V
Clock = 62.5 MHz
Ain = 1.0226 MHz
Voltage output low (Vol) and voltage output high (Voh) were measured at two separate current
loads shown as follows:
Voh -> -6mA Vol -> 6mA

Voh2 -> -4mA Vol2 -> 4mA
Power supply currents were monitored during irradiation. All testing was performed using a dose
rate of 49.5 rad(Si)/sec. The dose increments of interest were 2.5, 5.0, 7.5, 10, 20, 30 and 100
krad (Si).
Test Results
AD6640
No significant degradation was observed on all devices up to 30krad(Si) for all measured
parameters. Two of the five tested devices were taken up to 100krad(Si) and again showed no
significant degradation in any measured parameter. Figure 2 shows the Effective Number of Bits
(ENOB) versus total dose and Figure 3 shows the Aperture Uncertainty Jitter versus total dose.
Figures 4 and 5 show Differential Nonlinearity (DNL) maximum and minimum versus total dose.
As can be seen from these graphs, there was no significant degradation to 100krad(Si).
12
Part #1 - Static Bias
Part #3 - Dynamic Bias
Effective Number of Bits
Dose Rate = 49.5 rad(Si)/sec
11
10
100 103 104 105
Total Dose (rad(Si))
Figure 2
The apparent spike on devices 1 and 3 in Figure 3 was caused by a minor timing problem with
the hardware used to capture the data and was unrelated to radiation exposure. This timing
issue showed up as a higher calculated aperture uncertainty.
10
Aperture Uncertainty Jitter (ps rms) 9 Part #3 - Dynamic Bias
8 Part #6 - Static Bias
7
2
1
100 103 104 105
Figure 3
1
Part #1 - Min DNL
Minimum Differential Non Linearity (LSB)
Part #3 - Min DNL

Part #4 - Min DNL
Part #6 - Min DNL
Part #7 - Min DNL
-1
100 103 104 105
Figure 4
1
Maximum Differential Non Linearity (LSB)
Part #1 - Max DNL

Part #3 - Max DNL
Part #4 - Max DNL
Part #6 - Max DNL
Part #7 - Max DNL
-1
100 103 104 105
Figure 5
Appendix A contains graphs of all the device parameters measured by this test. The DC
parametric data graphs showing Vol, Voh, Vol2 and Voh2 show no significant change with device
dose. The parametric data for Device 1 was taken at a digital supply voltage of 5.0V which
appears as a higher Vol, Voh, Vol2 and Voh2 for that device, however its change with device dose
was also insignificant. The parametric data graphs shown are the average of 12 measurements
taken on the device pins and the variances in these data are shown representationally by error
bars. The graphs of Analog and Digital supply currents likewise show no significant shift with
device dose.
Conclusions
Since the AD6640 was built on Analog Devices’ high speed complimentary bipolar process
(XFCB) it is not surprising there was no significant degradation in any measured parameter for
this total dose test. Even when taken to 100krad(Si) no parameter showed any significant
change. No additional testing of the AD6640 is suggested.
Any questions or comments should be directed to John Bings, 812-854-1672,

bings@atd.crane.navy.mil or John Seiler, 812-854-2074, seiler_john@atd.crane.navy.mil.
Special acknowledgement and thanks to Mark Savage for his help with these graphs.
Appendix A
All Graphs
12
Effective Number of Bits
11
10
100 103 104 105
10
9 Part #3 - Dynamic Bias
Aperture Uncertainty Jitter (ps rms)

8 Part #6 - Static Bias
7
2
1
100 103 104 105
1
Part #1 - Min DNL
Minimum Differential Non Linearity (LSB) Part #3 - Min DNL
Part #4 - Min DNL
Part #6 - Min DNL
Part #7 - Min DNL
-1
100 103 104 105
1
Maximum Differential Non Linearity (LSB)
Part #1 - Max DNL

Part #3 - Max DNL
Part #4 - Max DNL
Part #6 - Max DNL
Part #7 - Max DNL
-1
100 103 104 105
0.1400
0.1395 Part #3 - Dynamic Bias
0.1390 Part #6 - Static Bias
Analog Supply Current (A)
0.1385 Dose Rate = 49.5 rad(Si)/sec
0.1380
0.1375
0.1370
0.1365
0.1360
0.1355
0.1350
100 103 104 105
0.030
0.028 Part #3 - Dynamic Bias
0.026 Part #6 - Static Bias
Digital Supply Current (A)
0.024 Dose Rate = 49.5 rad(Si)/sec
0.022
0.020
0.018
0.016
0.014
0.012
0.010
100 103 104 105
800
Part #1 - Static Bias (DVcc=5.0)
750

650
Vol(mV)
600
550
500
450
400
350
100 103 104 105
5400
Part #1 - Static Bias DVcc=5.0
4500 Dose Rate = 49.5 rad(Si)/sec
4200
Voh(mV)
3900
3600
3300
3000
2700
2400
100 103 104 105
600
540
510
480
Vol2(mV)
450
420
390
360
330
300
100 103 104 105
5800
5500 Part #3 Dynamic Bias
Part #4 Dynamic Bias
5200 Part #6 Static Bias
Part #7 Dynamic Bias
4900
4600
Voh2(mV)
4300
4000
3700
3400
3100
2800
2500
100 103 104 105
-70
-72 Part #3 - Dynamic Bias
Total Harmonic Distortion (dB) Part #4 - Dynamic Bias
-74 Part #6 - Static Bias
-76
-78
-80
-82
-84
-86
-88
-90
100 103 104 105
Appendix B
AD6640 Specification Sheet
a 12-Bit, 65 MSPS
IF Sampling A/D Converter
AD6640
FEATURES FUNCTIONAL BLOCK DIAGRAM
65 MSPS Minimum Sample Rate
80 dB Spurious-Free Dynamic Range
AVCC DVCC
IF-Sampling to 70 MHz
710 mW Power Dissipation AIN
BUF TH1 TH2 TH3 A ADC
Single +5 V Supply AIN
On-Chip T/H and Reference
+2.4V
Twos Complement Output Format VREF REFERENCE
ADC DAC AD6640 7
3.3 V or 5 V CMOS-Compatible Output Levels 6

ENCODE INTERNAL
TIMING DIGITAL ERROR CORRECTION LOGIC
APPLICATIONS ENCODE
MSB LSB
Cellular/PCS Base Stations
GND D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Multichannel, Multimode Receivers
GPS Anti-Jamming Receivers
Communications Receivers
Phased Array Receivers
PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS

The AD6640 is a high speed, high performance, low power, 1. Guaranteed sample rate is 65 MSPS.
monolithic 12-bit analog-to-digital converter. All necessary 2. Fully differential analog input stage specified for frequencies
functions, including track-and-hold (T/H) and reference are up to 70 MHz; enables “IF Sampling.”
included on-chip to provide a complete conversion solution. 3. Low power dissipation: 710 mW off a single +5 V supply.
The AD6640 runs on a single +5 V supply and provides CMOS-
4. Digital outputs may be run on +3.3 V supply for easy inter-
compatible digital outputs at 65 MSPS.
face to digital ASICs.
Specifically designed to address the needs of multichannel, 5. Complete Solution: reference and track-and-hold.
multimode receivers, the AD6640 maintains 80 dB spurious-
6. Packaged in small, surface mount, plastic 44-terminal TQFP.
free dynamic range (SFDR) over a bandwidth of 25 MHz.
Noise performance is also exceptional; typical signal-to-noise
ratio is 68 dB.
The AD6640 is built on Analog Devices’ high speed complemen-
tary bipolar process (XFCB) and uses an innovative multipass
architecture. Units are packaged in a 44-terminal Plastic Thin
Quad Flatpack (TQFP) specified from –40°C to +85°C.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1998
AD6640–SPECIFICATIONS
DC SPECIFICATIONS (AV CC = +5 V, DVCC = +3.3 V; TMIN = –408C, TMAX = +858C)
Test AD6640AST
Parameter Temp Level Min Typ Max Units
RESOLUTION 12 Bits
ACCURACY
No Missing Codes +25°C I GUARANTEED
Offset Error Full VI –10 3.5 +10 mV
Gain Error Full VI –10 4.0 +10 % FS
Differential Nonlinearity (DNL)1 +25°C I –1.0 ± 0.5 +1.5 LSB
Integral Nonlinearity (INL)1 Full V ± 1.25 LSB
TEMPERATURE DRIFT
Offset Error Full V 50 ppm/°C
Gain Error Full V 100 ppm/°C
POWER SUPPLY REJECTION (PSRR) Full V ± 0.5 mV/V
2
REFERENCE OUT (VREF) Full V 2.4 V
ANALOG INPUTS (AIN, AIN)3
Analog Input Common-Mode Range4 Full V VREF ± 0.05 V
Differential Input Voltage Range Full V 2.0 V p-p
Differential Input Resistance Full IV 0.7 0.9 1.1 kΩ
Differential Input Capacitance +25°C V 1.5 pF
POWER SUPPLY
Supply Voltage
AVCC Full VI 4.75 5.0 5.25 V
DVCC Full VI 3.0 3.3 5.25 V
Supply Current
IAVCC (AVCC = 5.0 V) Full VI 135 160 mA
IDVCC (DVCC = 3.3 V) Full VI 10 20 mA
POWER CONSUMPTION Full VI 710 865 mW
NOTES
1
ENCODE = 20 MSPS
2
If VREF is used to provide a dc offset to other circuits, it should first be buffered.
3
The AD6640 is designed to be driven differentially. Both AIN and AIN should be driven at levels VREF ± 0.5 volts. The input signals should be 180 degrees out of phase to
produce a 2 V p-p differential input signal. See Driving the Analog Inputs section for more details.
4
Analog input common-mode range specifies the offset range the analog inputs can tolerate in dc-coupled applications (see Figure 35 for more detail).
Specifications subject to change without notice .
DIGITAL SPECIFICATIONS (AV CC = +5 V, DVCC = +3.3 V; TMIN = –408C, TMAX = +858C)

Test AD6640AST
Parameter Temp Level Min Typ Max Units
LOGIC INPUTS (ENC, ENC)1
Encode Input Common-Mode Range2 Full IV 0.2 2.2 V
Differential Input Voltage Full IV 0.4 V p-p
Single-Ended Encode 10 V p-p
Logic Compatibility3 TTL/CMOS
Logic “1” Voltage Full VI 2.0 5.0 V
Logic “0” Voltage Full VI 0 0.8 V
Logic “1” Current (VINH = 5 V) Full VI 500 650 800 µA
Logic “0” Current (VINL = 0 V) Full VI –400 –320 –200 µA
Input Capacitance +25°C V 2.5 pF
LOGIC OUTPUTS (D11–D0)4
Logic Compatibility CMOS
Logic “1” Voltage (DVCC = +3.3 V) Full VI 2.8 DVCC – 0.2 V
Logic “0” Voltage (DVCC = +3.3 V) Full VI 0.2 0.5 V
Logic “1” Voltage (DVCC = +5.0 V) Full IV 4.5 DVCC – 0.3 V
Logic “0” Voltage (DVCC = +5.0 V) Full IV 0.35 0.5 V
Output Coding Twos Complement
NOTES
1
Best dynamic performance is obtained by driving ENC and ENC differentially. See Encoding the AD6640 section for more details. Performance versus ENC/ENC power is
shown in Figure 18 under Typical Performance Characteristics.
2
For dc-coupled applications, Encode Input Common-Mode Range specifies the common-mode range the encode inputs can tolerate when driven differentially by minimum
differential input voltage of 0.4 V p-p. For differential input voltage swings greater than 0.4 V p-p, the common-mode range will change. The minimum value insures that the
input voltage on either encode pin does not go below 0 V. The maximum value insures that the input voltage on either encode pin does not go below 2.0 V or above AV CC (e.g.,
for a differential input swing of 0.8 V, the min and max common-mode specs become 0.4 V and 2.4 V respectively).
3
ENC or ENC may be driven alone if desired, but performance will likely be degraded. Logic Compatibility specifications are provided to show that TTL or CMOS clock sources
will work. When driving only one encode input, bypass the complementary input to GND with 0.01 µF.
4
Digital output load is one LCX gate.
Specifications subject to change without notice.
–2– REV. 0
AD6640
SWITCHING SPECIFICATIONS1 (AV CC = +5 V, DVCC = +3.3 V; ENCODE & ENCODE = 65 MSPS; TMIN = –408C, TMAX = +858C)
Test AD6640AST
Parameter (Conditions) Temp Level Min Typ Max Units
Maximum Conversion Rate Full VI 65 MSPS
Minimum Conversion Rate2 Full IV 6.5 MSPS
Aperture Delay (tA) +25°C V 400 ps
Aperture Uncertainty (Jitter) +25°C V 0.3 ps rms
ENCODE Pulsewidth High3 +25°C IV 6.5 ns
ENCODE Pulsewidth Low +25°C IV 6.5 ns
Output Delay (tOD) DVCC +3.3 V/5.0 V4 Full IV 8.5 10.5 12.5 ns
NOTES
1
All switching specifications tested by driving ENCODE and ENCODE differentially.
2
A plot of Performance vs. Encode is shown in Figure 16 under Typical Performance Characteristics.
3
A plot of Performance vs. Duty Cycle (Encode = 65 MSPS) is shown in Figure 17 under Typical Performance Characteristics.
4
Outputs driving one LCX gate. Delay is measured from differential crossing of ENC, ENC to the time when all output data bits are within valid logic levels.
AC SPECIFICATIONS1 (AV CC = +5 V, DVCC = +3.3 V; ENCODE & ENCODE = 65 MSPS; TMIN = –408C, TMAX = +858C)
Test AD6640AST
Parameter (Conditions) Temp Level Min Typ Max Units
SNR
Analog Input 2.2 MHz +25°C V 68 dB
@ –1 dBFS 15.5 MHz +25°C I 64 67.7 dB
31.0 MHz +25°C V 67.5 dB
69.0 MHz +25°C V 66 dB
SINAD
Analog Input 2.2 MHz +25°C V 68 dB
@ –1 dBFS 15.5 MHz +25°C I 63.5 67.2 dB
31.0 MHz +25°C V 67.0 dB
69.0 MHz +25°C V 65.5 dB
Worst Harmonic2 (2nd or 3rd)
Analog Input 2.2 MHz +25°C V 80 dBc
@ –1 dBFS 15.5 MHz +25°C I 74 80 dBc
31.0 MHz +25°C V 79.5 dBc
69.0 MHz +25°C V 78.5 dBc
Worst Harmonic2 (4th or Higher)
Analog Input 2.2 MHz +25°C V 85 dBc
@ –1 dBFS 15.5 MHz +25°C I 74 85 dBc
31.0 MHz +25°C V 85 dBc
69.0 MHz +25°C V 84 dBc
Multitone SFDR (w/Dither)3
Eight Tones @ –20 dBFS Full V 90 dBFS
4
Two-Tone IMD Rejection
F1, F2 @ –7 dBFS Full V 80 dBc
5
Analog Input Bandwidth +25°C V 300 MHz
NOTES
1
All ac specifications tested by driving ENCODE and ENCODE differentially.
2
For a single test tone at –1 dBFS, the worst case spectral performance is typically limited by the direct or aliased 2nd or 3rd harmonic. If a system is designed such
that the 2nd and 3rd harmonics fall out-of-band, overall performance in the band of interest is typically improved by 5 dB. Worst Harmonic (4th or Higher) includes
4th and higher order harmonics and all other spurious components. Reference Figure 12 for more detail.
3
See Overcoming Static Nonlinearities with Dither section for details on improving SFDR performance. To measure SFDR, eight tones from 14 MHz to 18 MHz
(0.5 MHz spacing) are swept from –20 dBFS to –90 dBFS. An open channel at 16 MHz is used to monitor SFDR.
4
F1 = 14.9 MHz, F2 = 16 MHz.
5
Specification is small signal bandwidth. Plots of Performance versus Analog Input Frequency are shown in Figures 10, 11 and 12. Sampling wide bandwidths
(5 MHz–15 MHz) should be limited to 70 MHz center frequency.
REV. 0 –3–
AD6640
ABSOLUTE MAXIMUM RATINGS 1
EXPLANATION OF TEST LEVELS
Parameter Min Max Units Test Level
I – 100% production tested.
ELECTRICAL
AVCC Voltage 0 7 V II – 100% production tested at +25°C, and sample tested at
DVCC Voltage 0 7 V specified temperatures. AC testing done on sample
Analog Input Voltage 0 AVCC V basis.
Analog Input Current 25 mA III – Sample tested only.
Digital Input Voltage (ENCODE) 0 AVCC V IV – Parameter is guaranteed by design and characterization
Digital Output Current –10 10 mA testing.
ENVIRONMENTAL2 V – Parameter is a typical value only.
Operating Temperature Range VI – All devices are 100% production tested at +25°C; sample
(Ambient) –40 +85 °C tested at temperature extremes.
Maximum Junction Temperature +150 °C
Lead Temperature (Soldering, 10 sec) +300 °C
Storage Temperature Range (Ambient) –65 +150 °C
NOTES
1
Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2
Typical thermal impedances (44-terminal TQFP); θJA = 55°C/W.
ORDERING GUIDE
Model Temperature Range Package Description Package Option

AD6640AST –40°C to +85°C (Ambient) 44-Terminal TQFP (Thin Quad Plastic Flatpack) ST-44
AD6640ST/PCB Evaluation Board with AD6640AST
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the AD6640 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.
–4– REV. 0
AD6640
PIN FUNCTION DESCRIPTIONS
Pin No. Name Function

1, 2, 36, 37, 40, 41 DVCC +3.3 V/+5 V Power Supply (Digital). Powers output stage only.
3 ENCODE Encode Input. Data conversion initiated on rising edge.
4 ENCODE Complement of ENCODE. Drive differentially with ENCODE or bypass to
Ground for single-ended clock mode. See Encoding the AD6640 section.
5, 6, 13, 14, 17, 18, 21,
22, 24, 34, 35, 38, 39 GND Ground.
7 AIN Analog Input.
8 AIN Complement of Analog Input.
9 VREF Internal Voltage Reference. Nominally +2.4 V. Bypass to Ground with
0.1 µF + 0.01 µF microwave chip capacitor.
10 C1 Internal Bias Point. Bypass to ground with 0.01 µF capacitor.
11, 12, 15, 16, 19, 20 AVCC +5 V Power Supply (Analog).
23 NC No Connect.
25 D0 (LSB) Digital Output Bit (Least Significant Bit).
26–33 D1–D8 Digital Output Bits.
42, 43 D9–D10 Digital Output Bits.
44 D11 (MSB)1 Digital Output Bit (Most Significant Bit).
NOTE
1
Output coded as twos complement.
PIN CONFIGURATION
D11 (MSB)
DVCC
DVCC
DVCC
DVCC
GND
GND
GND
GND
D10
D9
44 43 42 41 40 39 38 37 36 35 34
DVCC 1 33 D8
DVCC 2 PIN 1 32 D7
ENCODE 3 31 D6
ENCODE 4 30 D5
GND 5 29 D4
AD6640
GND 6 TOP VIEW 28 D3
(Not to Scale)
AIN 7 27 D2
AIN 8 26 D1
VREF 9 25 D0 (LSB)
C1 10 24 GND
AVCC 11 23 NC
12 13 14 15 16 17 18 19 20 21 22
AVCC
AVCC
AVCC
AVCC
AVCC
GND
GND
GND
GND
GND
GND
NC = NO CONNECT
REV. 0 –5–
AD6640
DEFINITION OF SPECIFICATIONS Power Supply Rejection Ratio
Analog Bandwidth (Small Signal) The ratio of a change in input offset voltage to a change in
The analog input frequency at which the spectral power of the power supply voltage.
fundamental frequency (as determined by the FFT analysis) is Signal-to-Noise-and-Distortion (SINAD)
reduced by 3 dB. The ratio of the rms signal amplitude (set at 1 dB below full
Aperture Delay scale) to the rms value of the sum of all other spectral compo-
The delay between a differential crossing of ENCODE and nents, including harmonics but excluding dc.
ENCODE and the instant at which the analog input is sampled. Signal-to-Noise Ratio (SNR)
Aperture Uncertainty (Jitter) The ratio of the rms signal amplitude (set at 1 dB below full
The sample-to-sample variation in aperture delay. scale) to the rms value of the sum of all other spectral compo-
Differential Nonlinearity nents, excluding the first five harmonics and dc.
The deviation of any code from an ideal 1 LSB step. Spurious-Free Dynamic Range (SFDR)
Encode Pulsewidth/Duty Cycle The ratio of the rms signal amplitude to the rms value of the
Pulsewidth high is the minimum amount of time that the EN- peak spurious spectral component. The peak spurious compo-
CODE pulse should be left in logic “1” state to achieve rated nent may or may not be a harmonic. May be reported in dBc
performance; pulsewidth low is the minimum time ENCODE (i.e., degrades as signal levels is lowered), or in dBFS (always
pulse should be left in low state. At a given clock rate, these related back to converter full scale).
specs define an acceptable Encode duty cycle. Two-Tone Intermodulation Distortion Rejection
Integral Nonlinearity The ratio of the rms value of either input tone to the rms
The deviation of the transfer function from a reference line value of the worst third order intermodulation product; re-
measured in fractions of 1 LSB using a “best straight line” ported in dBc.
determined by a least square curve fit. Two-Tone SFDR
Minimum Conversion Rate The ratio of the rms value of either input tone to the rms value
The encode rate at which the SNR of the lowest analog signal of the peak spurious component. The peak spurious component
frequency drops by no more than 3 dB below the guaranteed may or may not be an IMD product. May be reported in dBc
limit. (i.e., degrades as signal levels is lowered), or in dBFS (always
related back to converter full scale).
Maximum Conversion Rate
The encode rate at which parametric testing is performed. Worst Harmonic
The ratio of the rms signal amplitude to the rms value of the
Output Propagation Delay worst harmonic component, reported in dBc.
The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.
–6– REV. 0
Equivalent Circuits–AD6640
tA
AIN
N
ANALOG
INPUTS
N+1
AIN
ENCODE INPUTS
(ENCODE)
DIGITAL OUTPUTS
N–2 N–1 N
(D11–D0)
tOD
Figure 1. Timing Diagram
VCH AVCC DVCC
AIN BUF T/H CURRENT

MIRROR
450V
VCL
BUF VREF
VCH AVCC
450V
DVCC
AIN BUF T/H VREF
D0–D11
VCL
Figure 2. Analog Input Stage
AVCC
CURRENT
MIRROR
AVCC AVCC
R1 R1 Figure 5. Digital Output Stage
17kV 17kV
ENCODE ENCODE
TIMING
R2 CIRCUITS R2 AVCC
8kV 8kV AVCC
2.4V
VREF
Figure 3. Encode Inputs
0.5mA
AVCC
Figure 6. 2.4 V Reference
VREF
AVCC
AVCC
CURRENT
MIRROR
C1
Figure 4. Compensation Pin, C1
REV. 0 –7–
AD6640–Typical Performance Characteristics
0
POWER RELATIVE TO ADC FULL SCALE – dB
ENCODE = 65MSPS ENCODE = 65MSPS

AIN = 2.2MHz 81
TEMP = –40 C, +25 C, & +85 C
20
WORST CASE HARMONIC – dBc

80
40
T = +25 C
60 79
2 3 4 5 6 7 8 9
T = –40 C, +85 C
80
78
100
77
120
dc 6.5 13.0 19.5 26.0 32.5 0 7 14 21 28 35 42 49 56 63 70
FREQUENCY – MHz ANALOG INPUT FREQUENCY – MHz
Figure 7. Single Tone at 2.2 MHz Figure 10. Harmonics vs. AIN
0

AIN = 15.5MHz 69
TEMP = –40 C, +25 C, & +85 C
20
68
40 T = –40 C
SNR – dB
T = +25 C
60 67
4 8 9 5 3 7 6 2
T = +85 C
80
66
100
65
120
dc 6.5 13.0 19.5 26.0 32.5 0 7 14 21 28 35 42 49 56 63 70
Figure 8. Single Tone at 15.5 MHz Figure 11. Noise vs. AIN
0 90
WORST OTHER SPUR ENCODE = 65MSPS
ENCODE = 65MSPS
AIN = 31.0MHz
20 80
HARMONICS (2nd, 3rd)
SNR, HARMONICS – dB, dBc
40 70
SNR
60 60
2 4 6 8 9 7 5 3
80 50
100 40
120 30
dc 6.5 13.0 19.5 26.0 32.5 1 2 4 10 20 40 100 200 300
Figure 9. Single Tone at 31.0 MHz Figure 12. Harmonics, Noise vs. AIN
–8– REV. 0
AD6640
0 85
POWER RELATIVE TO ADC FULL SCALE – dB ENCODE = 65MSPS
AIN = 19.5MHz
SNR, WORST CASE SPURIOUS – dB, dBc

AIN = 15.0, 16.0MHz
20 NO DITHER WORST SPUR
80
40
75
60
70
SNR
80
65
100
120 60
dc 6.5 13.0 19.5 26.0 32.5 dc 8 16 24 32 40 48 56 64 72 80
FREQUENCY – MHz SAMPLE RATE – MSPS
Figure 13. Two Tones at 15.0 MHz & 16.0 MHz Figure 16. SNR, Worst Spurious vs. Encode
100 90
SNR, WORST FULL SCALE SPURIOUS – dB, dBc

ENCODE = 65MSPS
90 dBFS 85
WORST CASE SPURIOUS – dBc and dBFS
AIN = 2.2MHz
80 80
WORST SPUR
75
70
70
ENCODE = 65MSPS SNR
60
AIN = 31.0MHz 65
50 60
SFDR = 80dB
40 55
dBc REFERENCE LINE
50
30
45
20
40
10
35
0 30
–80 –70 –60 –50 –40 –30 –20 –10 0 25 30 35 40 45 50 55 60 65 70 75
ANALOG INPUT POWER LEVEL – dBFS ENCODE DUTY CYCLE – %
Figure 14. Single Tone SFDR Figure 17. SNR, Worst Spurious vs. Duty Cycle
100 90
SNR, WORST FULL SCALE SPURIOUS – dB, dBc
90 85 ENCODE = 65MSPS
WORST CASE SPURIOUS – dBc and dBFS
dBFS 2.2MHz WORST SPUR

80 80
69MHz
75
70
dBc 70
ENCODE = 65MSPS
60 2.2MHz
F1 = 15.0MHz 65
F2 = 16.0MHz SNR
50 60
SFDR = 80dB 69MHz
40 55
REFERENCE LINE
30 50
45
20
40
10
35
0 30
–80 –70 –60 –50 –40 –30 –20 –10 0 –15 –12 –9 –6 –3 0 3 6 9 12 15
INPUT POWER LEVEL (F1 = F2) – dBFS ENCODE POWER – dBm
Figure 15. Two Tone SFDR Figure 18. SNR, Worst Spurious vs. Encode Power
REV. 0 –9–
AD6640
0 0

AIN = 19.5MHz @ –36dBFS AIN = 19.5MHz @ –36dBFS
–20 NO DITHER –20 DITHER = –32.5dBm
–40 –40
–60 –60
–80 –80
–100 –100
–120 –120
dc 65 13.0 19.5 26.0 32.5 dc 65 13.0 19.5 26.0 32.5
FREQUENCY – MHz FREQUENCY – MHz
Figure 19. 16K FFT without Dither Figure 22. 16K FFT with Dither
100 100
90 90
WORST CASE SPURIOUS – dBc

WORST CASE SPURIOUS – dBc
80 AIN = 19.5MHz 80 AIN = 19.5MHz

NO DITHER DITHER = –32.5dBm
70 70
60 60
50 50
40 40
30 30
20 20
SFDR = 80dB SFDR = 80dB
10 REFERENCE LINE 10
REFERENCE LINE
0 0
–80 –70 –60 –50 –40 –30 –20 –10 0 –80 –70 –60 –50 –40 –30 –20 –10 0
ANALOG INPUT POWER LEVEL – dBFS ANALOG INPUT POWER LEVEL – dBFS
Figure 20. SFDR without Dither Figure 23. SFDR with Dither
0 0 0 0
ENCODE = 50MSPS
AIN = 65.5, 68.5MHz ENCODE = 50MSPS
–20 NO DITHER AIN = 65.5MHz, 68.5MHz
–20 DITHER = –32.5dBm
–30 –30
ALIASED
–40 SIGNALS –40
ALIASED
SIGNALS
–60 ANALOG IF –60 –60 –60
FILTER MASK
ANALOG IF
–80 FILTER MASK
–80
–90 –90
–100 –100
–120 –120
50 55 60 65 70 75 –120 –120
50 55 60 65 70 75
FREQUENCY – MHz FREQUENCY – MHz
Figure 21. IF-Sampling at 70 MHz without Dither Figure 24. IF-Sampling at 70 MHz with Dither
–10– REV. 0
AD6640
THEORY OF OPERATION
The AD6640 analog-to-digital converter (ADC) employs a two- ENCODE
ENCODE
+5V
SOURCE
stage subrange architecture. This design approach ensures Vl R1
ENCODE
12-bit accuracy, without the need for laser trim, at low power.
0.01mF RX R2
As shown in the functional block diagram, the AD6640 has AD6640
complementary analog input pins, AIN and AIN. Each analog
input is centered at 2.4 volts and should swing ± 0.5 volts
around this reference (ref. Figure 2). Since AIN and AIN are Figure 26. Lower Logic Threshold for Encode
180 degrees out of phase, the differential analog input signal is
2 volts peak-to-peak. 5R2
Vl =
R1RX to raise logic threshold.
Both analog inputs are buffered prior to the first track-and-hold, R2 +
TH1. The high state of the ENCODE pulse places TH1 in R1+ RX
hold mode. The held value of TH1 is applied to the input of a
6-bit coarse ADC. The digital output of the coarse ADC drives AVCC
a 6-bit DAC; the DAC is 12 bits accurate. The output of the 6-
RX
bit DAC is subtracted from the delayed analog signal at the +5V
ENCODE
input of TH3 to generate a residue signal. TH2 is used as an ENCODE
SOURCE
R1
analog pipeline to null out the digital delay of the coarse ADC. Vl ENCODE
The 6-bit coarse ADC word and 7-bit residue word are added 0.01mF AD6640
R2
together and corrected in the digital error correction logic to

generate the output word. The result is a 12-bit parallel digital
CMOS-compatible word, coded as twos complement. Figure 27. Raise Logic Threshold for Encode
While the single-ended encode will work well for many applica-
APPLYING THE AD6640
tions, driving the encode differentially will provide increased
Encoding the AD6640
performance. Depending on circuit layout and system noise, a
Best performance is obtained by driving the encode pins dif-
1 dB to 3 dB improvement in SNR can be realized. It is not
ferentially. However, the AD6640 is also designed to interface
recommended that differential TTL logic be used however,
with TTL and CMOS logic families. The source used to drive
because most TTL families that support complementary outputs
the ENCODE pin(s) must be clean and free from jitter. Sources
are not delay or slew rate matched. Instead, it is recommended
with excessive jitter will limit SNR (reference Equation 1 under
that the encode signal be ac-coupled into the ENCODE and
“Noise Floor and SNR”).
ENCODE pins.
The simplest option is shown below. The low jitter TTL signal
AD6640
is coupled with a limiting resistor, typically 100 ohms, to the
TTL OR CMOS ENCODE
SOURCE primary side of an RF transformer (these transformers are inex-
ENCODE pensive and readily available; part number in Figure 28 is from
0.01mF Mini-Circuits). The secondary side is connected to the EN-
CODE and ENCODE pins of the converter. Since both encode
inputs are self-biased, no additional components are required.
Figure 25. Single-Ended TTL /CMOS Encode
The AD6640 encode inputs are connected to a differential input 100V
0.1mF
T1–1T
stage (see Figure 3 under EQUIVALENT CIRCUITS). With TTL ENCODE
no input signal connected to either ENCODE pin, the voltage AD6640

dividers bias the inputs to 1.6 volts. For TTL or CMOS usage, ENCODE
the encode source should be connected to ENCODE, Pin 3.
ENCODE should be decoupled using a low inductance or mi-
crowave chip capacitor to ground. Figure 28. TTL Source – Differential Encode
If a logic threshold other than the nominal 1.6 V is required, the A clean sine wave may be substituted for a TTL clock. In this
following equations show how to use an external resistor, Rx, to case, the matching network is shown below. Select a transformer
raise or lower the trip point (see Figure 3; R1 = 17 kΩ, R2 = 8 kΩ). ratio to match source and load impedances. The input impedance
of the AD6640 encode is approximately 11 kΩ differentially.
5R2Rx Therefore “R,” shown in the Figure 29, may be any value that is
Vl = to lower logic threshold. convenient for available drive power.
R1R2 + R1Rx + R2Rx
REV. 0 –11–
AD6640
To take full advantage of this high input impedance, a 20:1
T1–1T
SINE
ENCODE transformer would be required. This is a large ratio and could
SOURCE
R AD6640 result in unsatisfactory performance. In this case, a lower
ENCODE
step-up ratio could be used. For example, if RT were set to
260 ohms, along with a 4:1 transformer, the input would match
to a 50 ohm source with a full-scale drive of +4 dBm (Figure
Figure 29. Sine Source – Differential Encode 33). Note that the external load resistor, RT, is in parallel with
If a low jitter ECL clock is available, another option is to ac- the AD6640 analog input resistance of 900 ohms. The external
couple a differential ECL signal to the encode input pins as resistor value can be calculated from the following equation:
shown below. The capacitors shown here should be chip ca-
1
pacitors but do not need to be of the low inductance variety. RT =
1 1
–
Z 900
0.1mF
ECL
ENCODE where Z is the desired impedance (200 Ω for a 4:1 transformer
AD6640
GATE 0.1mF with 50 Ω input source).
ENCODE
510V 510V 1:4

AIN
ANALOG
INPUT RT AD6640
–VS SIGNAL
AIN
Figure 30. Differential ECL for Encode

VREF
As a final alternative, the ECL gate may be replaced by an ECL
comparator. The input to the comparator could then be a logic 0.1mF 0.01mF
signal or a sine signal.

Figure 33. Transformer-Coupled Analog Input Signal
AD96687 (1/2)
0.1mF If the lower drive power is attractive, a combination transformer
ENCODE
AD6640
match and LC match could be employed that would use a 4:1
50V 0.1mF
ENCODE
transformer with an LC as shown in Figure 34. This solution is
useful when good performance in the third Nyquist zone is
510V 510V
required. Such a requirement arises when digitizing high inter-
mediate frequencies in communications receivers.
–VS
Figure 31. ECL Comparator for Encode ANALOG +j100V 1:4

SIGNAL
AIN
Driving the Analog Input AT
–3dBm –j125V AD6640
Because the AD6640 operates from a single +5 volt supply, the
analog input voltage range is offset from ground by 2.4 volt. AIN
Each analog input connects through a 450 ohm resistor to the

VREF
2.4 volt bias voltage and to the input of a differential buffer
0.1mF 0.01mF
(Figure 32). This resistor network on the input properly biases
the followers for maximum linearity and range. Therefore, the
analog source driving the AD6640 should be ac-coupled to the Figure 34. Low Power Drive Circuit
input pins. Since the differential input impedance of the AD6640
is 0.9 kΩ, the analog input power requirement is only –3 dBm, In applications where gain is needed but dc-coupling is not
simplifying the drive amplifier in many cases. necessary, an extension of Figure 34 is recommended. A
50 ohm gain block may be placed in front of the LC matching
network. Such gain blocks are readily available for commercial
applications. These low cost modules can have excellent NF and
AIN BUF
intermodulation performance. This circuit is especially good for
450V AD6640 the “IF” receiver application previously mentioned.
BUF In applications where dc-coupling is required the following
circuit can be used (Figure 35). It should be noted that the
450V
addition of circuitry for dc-coupling may compromise performance
AIN BUF in terms of noise, offset and dynamic performance. This circuit
requires an inverting and noninverting signal path. Additionally,
VREF +2.4V an offset must be generated so that the analog input to each pin
REFERENCE
0.1mF 0.01mF
is centered near 2.4 volts. Since the input is differential, small
differences in the dc voltage at each input can translate into an
offset for the circuit. The same holds true for gain mismatch.
Figure 32. Differential Analog Inputs Therefore, some means of adjusting the gain and offset between
–12– REV. 0
AD6640
the sides should be implemented. The addition of small value the device. A full-scale transition can cause up to 120 mA
resistors between the AD9631 and the AD6640 will prevent (12 bits × 10 mA/bit) of current to flow through the digital
oscillation due to the capacitive input of the ADC. output stages. The series resistor will minimize the output
currents that can flow in the output stage. These switching
AD9631 currents are confined between ground and the DVCC pin. Stan-
SIGNAL 62V
SOURCE
15V
AIN
dard TTL gates should be avoided since they can appreciably
467V
78V add to the dynamic switching currents of the AD6640.
350V
AD6640 Layout Information
1000V
OP279 The schematic of the evaluation board (Figure 36) represents a
OP279 (1/2) typical implementation of the AD6640. The pinout of the
(1/2) 750V VREF
0.1mF 0.01mF AD6640 facilitates ease of use and the implementation of high
frequency/high resolution design practices. All of the digital
0.1mF
425V outputs are on one side while the other sides contain all of the
350V inputs. It is highly recommended that high quality ceramic chip
467V capacitors be used to decouple each supply pin to ground di-
350V
15V rectly at the device. Depending on the configuration used for
AIN the encode and analog inputs, one or more capacitors are required
127V AD9631 on those input pins. The capacitors used on the ENCODE and
VREF pins must be a low inductance chip capacitor as referenced
previously in the data sheet.
Figure 35. DC-Coupled Analog Input Circuit A multilayer board is recommended to achieve best results. Care
Power Supplies should be taken when placing the digital output runs. Because
Care should be taken when selecting a power source. Linear the digital outputs have such a high slew rate, the capacitive
supplies are strongly recommended as switching supplies tend to loading on the digital outputs should be minimized. Circuit
have radiated components that may be “received” by the traces for the digital outputs should be kept short and connect
AD6640. Each of the power supply pins should be decoupled as directly to the receiving gate (broken only by the insertion of the
closely to the package as possible using 0.1 µF chip capacitors. series resistor). Digital data lines should be kept clear of analog
The AD6640 has separate digital and analog +5 V pins. The and encode traces.
analog supplies are denoted AVCC and the digital supply pins Evaluation Boards
are denoted DVCC. Although analog and digital supplies may be The evaluation board for the AD6640 is very straightforward,
tied together, best performance is achieved when the supplies consisting of power, signal inputs and digital outputs. The
are separate. This is because the fast digital output swings can evaluation board includes the option for an onboard clock oscil-
couple switching noise back into the analog supplies. Note that lator for the encode.
AVCC must be held within 5% of 5 volts; however the DVCC Power to the analog supply pins is connected via banana jacks.
supply may be varied according to output digital logic family The analog supply powers the crystal oscillator and the AVCC
(i.e., DVCC should be connected to the same supply as the digi- pins of the AD6640.
tal circuitry). The AD6640 is specified for DVCC = 3.3 V as this
is a common supply for digital ASICs. The DVCC power is supplied via J3, the digital interface. This
digital supply connection also powers the digital gates on the
Output Loading PCB. By maintaining separate analog and digital power supplies,
Care must be taken when designing the data receivers for the degradation in SNR and SFDR is kept to a minimum. Total
AD6640. It is recommended that the digital outputs drive a power requirement is approximately 200 mA. This configuration
series resistor (e.g. 348 ohms) followed by a gate like the allows for easy evaluation of different logic families (i.e., con-
74LCX574. To minimize capacitive loading, there should only nection to a 3.3 volt logic board).
be one gate on each output pin. An example of this is shown in
the evaluation board schematic shown in Figure 36. The digital The analog input is connected via J2 and is transformer-coupled
outputs of the AD6640 have a constant rise time output stage. to the AD6640 (see Driving the Analog Input). The onboard
The output slew rate is about 1 V/ns when DVCC = +5 V. A termination resistor is 270 Ω. This resistor, in parallel with the
typical CMOS gate combined with PCB trace and through hole AD6640’s input resistance (900 Ω), provides a 50 Ω load to the
will have a load of approximately 10 pF. Therefore as each bit analog source driving the 1:4 transformer. If a different input
switches, 10 mA impedance is required, replace R16 by using the following
equation
 1V  1
10 pF × 1ns  of dynamic current per bit will flow in or out of R16 =
  1 1
−
Z 900
where Z is desired input impedance (200 Ω for a 4:1 trans-
former with 50 Ω source).
REV. 0 –13–
AD6640
The analog input range of the PCB is ± 0.5 volts (i.e., signal ac- AD6640 output data is latched using 74LCX574 (U3, U4)
coupled to AD6640). latches following 348 ohm series resistors. The resistors limit
The encode signal may be generated using an onboard crystal the current that would otherwise flow due to the digital output
oscillator, U1. The oscillator is socketed and may be replaced slew rate. The resistor value was chosen to represent a time
by an external encode source via J1. If an external source is constant of ~25% of the data rate at 65 MHz. This reduces slew
used, it should be a high quality TTL source. A transformer rate while not appreciably distorting the data waveform. Data is
converts the single-ended TTL signal to a differential clock (see latched in a pipeline configuration; a rising edge generates the
Encoding the AD6640). Since the encode is coupled with a new AD6640 data sample, latches the previous data at the con-
transformer, a sine wave could have been used; note, however, verter output, and strobes the external data register over J3.
that U5 requires TTL levels to function properly. NOTE: Power and ground must be applied to J3 to power the
digital logic section of the evaluation board.
Table I. AD6640ST/PCB Bill of Material
Item Quantity Reference Description

1 2 +5 VA, GND Banana Jack
2 11 C7–C9, C11–C17, C19 Ceramic Chip Capacitor 0805, 0.1 µF
3 2 C4, C6 Tantalum Chip Capacitor 10 µF
4 1 J3 40-Pin Double Row Male Header
5 3 J1, J2, J4 BNC Coaxial PCB Connector
6 1 R1 Surface Mount Resistor 1206, 348 Ω
7 25 R2–R14, R20–R25, R30–R35 Surface Mount Resistor 1206, 348 Ω
10 2 T1, T2 Surface Mount Transformer Mini-Circuits T4–1T, 1:4 Ratio
11 1 U1 Clock Oscillator (Optional)
12 1 DUT AD6640AST 12-Bit–65 MSPS ADC Converter
13 2 U3, U4 74LCX574 Octal Latch
14 1 U5 74LVQ00 Quad Two Input NAND Gate
15 1 C1, C18 Ceramic Chip Capacitor 0508, 0.01 µF Low Inductance
16 2 C2, C3 Ceramic Chip Capacitor 0508, 0.1 µF Low Inductance
17 2 CR1, CR2 1N2810 Schottky Diode
–14– REV. 0
AD6640
348V
+5VA 74LCX574
348V
U5 (DVCC)
74LVQ00
(+5VA) 9 12 348V
1 4 8D 8Q B06
3 6 8 13 348V
2 5 BUFLAT 7D 7Q B07
7 14 348V
6D 6Q B08
0.1mF 348V 6 15 348V
5D 5Q B09
348V 5 16 348V
J4 4D 4Q B10
348V 4 17 348V
3D 3Q B11
3 18
348V 2D 2Q
E1 DVCC 2 19
1D 1Q
ENCODE 348V CK DVCC (+3.3V OR +5.0V)
INPUT 44 43 42 41 40 39 38 37 36 35 34 OE
E2 1 J3 40
11 1 GND
GND
J1
GND
D11
D10
DVCC
DVCC
GND
DVCC
D9
GND
DVCC
348V 2 39
DVCC B11 GND
38
B10 3 GND
100V 37
T4–1T 1 DVCC D8 33 DVCC B09 4 GND
36
4 3 B08 5 GND
2 DVCC D7 32 6 35
TWO COMPLEMENT B07 GND
2 34
3 ENCODE D6 31 BUFFERED OUTPUTS B06 7 GND
33
6 1 B05 8 GND
4 ENCODE D5 30 9 32
1:4 B04 GND
5 GND 10 31
ANALOG D4 29 GND
BUFLAT 11 30
INPUT T4–1T 6 GND DUT D3 28 12 29
GND
B03 GND
J2
4 3
7 AIN AD6640 D2 27 B02 13 28 GND
2 270V 14 27
B01 GND
8 AIN D1 26
1 B00 15 26 GND
6 9 (LSB) D0 25
VREF GND 16 25 GND
1:4 10 C1 GND 24 GND 17 24 GND
348V 18 23
GND GND
11 AVCC NC 23 U4 GND 19 22
GND
74LCX574 20 21
AVCC
AVCC
AVCC
AVCC
AVCC
0.01mF 0.1mF 348V GND GND

GND
GND
GND
GND
GND
GND
0.01mF (DVCC)
0.1mF 348V
12 13 14 15 16 17 18 19 20 21 22 9 12 348V
8D 8Q B00
348V 8 13 348V
7D 7Q B01
+5VA
GND 348V 7 14 348V
COMMON NC = NO CONNECT 6D 6Q B02
6 15 348V
+5V ANALOG 5D 5Q B03
+5VA 348V 5 16 348V
SUPPLY 4D 4Q B04
4 17 348V
3D 3Q B05
3 18
2D 2Q
2 19
DVCC 1D 1Q
+ C6 C7 C11 C12 C13 C15 C16 CK OE
10mF 0.1mF 0.1mF 0.1mF 0.1mF 0.1mF 0.1mF
11 1
+5VA
+ C4 C8 C9 C17
10mF 0.1mF 0.1mF 0.1mF
Figure 36. AD6640ST/PCB Schematic
REV. 0 –15–
AD6640
Figure 37. AD6640ST/PCB Top Side Silkscreen Figure 39. AD6640ST/PCB Top Side Copper
Figure 38. AD6640ST/PCB Bottom Side Silkscreen Figure 40. AD6640ST/PCB Bottom Side Copper (Positive)
NOTE: Evaluation boards are often updated, consult factory for latest version.
–16– REV. 0
AD6640
Figure 41. AD6640ST/PCB Ground Layer (Negative) Figure 42. AD6640ST/PCB “Split” Power Layer (Negative)
REV. 0 –17–
AD6640
DIGITAL WIDEBAND RECEIVERS is used for demodulation, different routines may be used to
Introduction demodulate different standards such as AM, FM, GMSK or any
Several key technologies are now being introduced that may other desired standard. In addition, as new standards arise or
forever alter the vision of radio. Figure 43 shows the typical new software revisions are generated, they may be field installed
dual conversion superheterodyne receiver. The signal picked up with standard software update channels. A radio that performs
by the antenna is mixed down to an intermediate frequency (IF) demodulation in software as opposed to hardware is often
using a mixer with a variable local oscillator (LO); the variable referred to as a soft radio because it may be changed or modified
LO is used to “tune-in” the desired signal. This first IF is simply through code revision.
mixed down to a second IF using another mixer stage and a System Description
fixed LO. Demodulation takes place at the second or third IF In the wideband digital radio (Figure 44), the first down conver-
using either analog or digital techniques. sion functions in much the same way as a block converter does.
An entire band is shifted in frequency to the desired interme-
ADCs
NARROWBAND NARROWBAND diate frequency. In the case of cellular base station receivers,
LNA FILTER FILTER I
5 MHz to 30 MHz of bandwidth are down-converted simulta-
IF1 IF2 Q
neously to an IF frequency suitable for digitizing with a wide-
RF
e.g. 900MHz band analog-to-digital converter. Once digitized the broadband
digital data stream contains all of the in-band signals. The
VARIABLE FIXED
remainder of the radio is constructed digitally using special
SHARED ONE RECEIVER PER CHANNEL purpose and general purpose programmable DSP to perform
filtering, demodulation and signal conditioning not unlike the
Figure 43. Narrowband Digital Receiver Architecture analog counter parts.
If demodulation takes place in the analog domain then tradi- In the narrowband receiver (Figure 43), the signal to be received
tional discriminators, envelop detectors, phase locked loops or must be tuned. This is accomplished by using a variable local
other synchronous detectors are generally employed to strip the oscillator at the first mix down stage. The first IF then uses a
modulation from the selected carrier. narrow band filter to reject out of band signals and condition
However, as general purpose DSP chips such as the ADSP-2181 the selected carrier for signal demodulation.
become more popular, they will be used in many baseband- In the digital wideband receiver (Figure 44), the variable local
sampled applications like the one shown in Figure 43. As oscillator has been replaced with a fixed oscillator, so tuning
shown in the figure, prior to ADC conversion, the signal must must be accomplished in another manner. Tuning is performed
be mixed down, filtered, and the I and Q components separated. digitally using a digital down conversion and filter chip fre-
These functions are realizable through DSP techniques, how- quently called a channelizer. The term channelizer is used
ever several key technology breakthroughs are required: high because the purpose of these chips is to select one channel out
dynamic range ADCs such as the AD6640, new DSPs (highly of many within the broadband spectrum present in the digital
programmable with onboard memory, fast), digital tuners and data stream of the ADC.
filters such as the AD6620, wide band mixers and amplifiers.
DECIMATION LOW-PASS
I
FILTER FILTER
COS
DIGITAL TUNER/FILTER
WIDEBAND
DSP DIGITAL
WIDEBAND ADC DATA
LNA WIDEBAND FILTER TUNER
MIXER
"n" CHANNELS SIN
TO DSP DECIMATION LOW-PASS
Q
RF FILTER FILTER
e.g. 900MHz 12.5MHz
(416 CHANNELS)
FIXED
DIGITAL TUNER/FILTER
DSP
Figure 45. AD6620 Digital Channelizer
Figure 45 shows the block diagram of a typical channelizer, such
SHARED CHANNEL SELECTION
as the AD6620. Channelizers consist of a complex NCO (Nu-
Figure 44. Wideband Digital Receiver Architecture merically Controlled Oscillator), dual multiplier (mixer), and
matched digital filters. These are the same functions that would
Figure 44 shows such a wideband system. This design shows be required in an analog receiver, however implemented in
that the front end variable local oscillator has been replaced with digital form. The digital output from the channelizer is the
a fixed oscillator and the back end has been replaced with a desired carrier, frequently in I & Q format; all other signals have
wide dynamic range ADC, digital tuner and DSP. This tech- been filtered and removed based on the filtering characteristics
nique offers many benefits. desired. Since the channelizer output consists of one selected
First, many passive discrete components have been eliminated RF channel, one tuner chip is required for each frequency re-
that formed the tuning and filtering functions. These passive ceived, although only one wideband RF receiver is needed for
components often require “tweaking” and special handling the entire band. Data from the channelizer may then be pro-
during assembly and final system alignment. Digital compo- cessed using a digital signal processor such as the ADSP-2181
nents require no such adjustments; tuner and filter characteristics or the SHARC® processor, the ADSP-21062. This data may
are always exactly the same. Moreover, the tuning and filtering then be processed through software to demodulate the informa-
characteristics can be changed through software. Since software tion from the carrier.
SHARC is a registered trademark of Analog Devices, Inc.
–18– REV. 0
AD6640
+5V (A) +3.3V (D) CMOS AD6620
PRESELECT 5–15MHz BUFFER (REF. FIG 45) ADSP-2181
FILTER LNA PASSBAND 348V
D11
AIN
LO AIN I&Q
DRIVE 12 DATA NETWORK
AD6640 CONTROLLER
1900MHz INTERFACE
ENCODE
M/N PLL
SYNTHESIZER REF
IN ENCODE
D0 CLK
65.00MHz
REFERENCE
CLOCK
Figure 46. Simplified Wideband PCS Receiver
System Requirements power dissipation is not a function of sample rate. Thus there is
Figure 46 shows a typical wideband receiver subsystem based no penalty paid in power by operating at faster sample rates. All
around the AD6640. This strip consists of a wideband IF filter, of this is good because, by carefully selecting input frequency
amplifier, ADC, latches, channelizer and interface to a digital range and sample rate, some of the drive amplifier and ADC
signal processor. This design shows a typical clocking scheme harmonics can actually be placed out-of-band.
used in many receiver designs. All timing within the system is
For example, if the system has second and third harmonics that
referenced back to a single clock. While this is not necessary, it
are unacceptably high, by carefully selecting the encode rate and
does facilitate PLL design, ease of manufacturing, system test,
signal bandwidth, these second and third harmonics can be
and calibration. Keeping in mind that the overall performance
placed out-of-band. For the case of an encode rate equal to
goal is to maintain the best possible dynamic range, many con-
60 MSPS and a signal bandwidth of 7.5 MHz, placing the fun-
siderations must be made.
damental at 7.5 MHz places the second and third harmonics out
One of the biggest challenges is selecting the amplifier used to of band as shown in the table below.
drive the AD6640. Since this is a communications application,
it is common to directly sample an intermediate frequency (IF) Table II.
signal. As such, IF gain blocks can be implemented instead of
baseband op amps. For these gain block amplifiers, the critical Encode Rate 60 MSPS
specifications are third order intercept point and noise figure. A Fundamental 7.5 MHz–15 MHz
bandpass filter will remove harmonics generated within the Second Harmonic 15 MHz–30 MHz
amplifier, but intermods should be better than the performance Third Harmonic 22.5 MHz–30 MHz, 30 MHz–15 MHz
of the A/D converter. In the case of the AD6640, amplifier
intermods must be better than –80 dBFS when driving full- Another option can be found through bandpass sampling. If the
scale power. As mentioned earlier, there are several amplifiers analog input signal range is from dc to FS/2, then the amplifier
to choose from and the specifications depend on the end and filter combination must perform to the specification re-
application. Figure 47 shows a typical multitone test. quired. However, if the signal is placed in the third Nyquist
zone (FS to 3 FS/2), the amplifier is no longer required to meet
0 the harmonic performance required by the system specifications
since all harmonics would fall outside the passband filter. For
–20 example, the passband filter would range from FS to 3 FS/2.

ENCODE = 65MSPS The second harmonic would span from 2 FS to 3 FS, well out-
–40
side the passband filter’s range. The burden then has been passed
off to the filter design provided that the ADC meets the basic
–60
specifications at the frequency of interest. In many applications,
this is a worthwhile tradeoff since many complex filters can
easily be realized using SAW and LCR techniques alike at these
–80
relatively high IF frequencies. Although harmonic performance
of the drive amplifier is relaxed by this technique, intermodula-
–100
tion performance cannot be sacrificed since intermods must be
assumed to fall in-band for both amplifiers and converters.
–120
dc 6.5 13.0 19.5 26.0 32.5 Noise Floor and SNR
FREQUENCY – MHz
Oversampling is sampling at a rate that is greater than twice the
Figure 47. Multitone Performance bandwidth of the signal desired. Oversampling does not have
Two other key considerations for the digital wideband receiver anything to do with the actual frequency of the sampled sig-
are converter sample rate and IF frequency range. Since per- nal, it is the bandwidth of the signal that is key. Bandpass or
formance of the AD6640 converter is largely independent of “IF” sampling refers to sampling a frequency that is higher than
both sample rate and analog input frequency (Figures 10, 11 Nyquist and often provides additional benefits such as down
and 16), the designer has greater flexibility in the selection of conversion using the ADC and replacing a mixer with a track-
these parameters. Also, since the AD6640 is a bipolar device, and-hold. Oversampling leads to processing gains because the
REV. 0 –19–
AD6640
faster the signal is digitized, the wider the distribution of noise. Overcoming Static Nonlinearities with Dither
Since the integrated noise must remain constant, the actual Typically, high resolution data converters use multistage
noise floor is lowered by 3 dB each time the sample rate is techniques to achieve high bit resolution without large com-
doubled. The effective noise density for an ADC may be calcu- parator arrays that would be required if traditional “flash” ADC
lated by the equation: techniques were employed. The multistage converter typically
provides better wafer yields meaning lower cost and much lower
10 − SNR /20
V NOISE rms / Hz = power. However, since it is a multistage device, certain portions
4 FS of the circuit are used repetitively as the analog input sweeps
from one end of the converter range to the other. Although the
For a typical SNR of 68 dB and a sample rate of 65 MSPS, this worst DNL error may be less than an LSB, the repetitive nature
is equivalent to 25 nV/√Hz. This equation shows the relation- of the transfer function can play havoc with low level dynamic
ship between SNR of the converter and the sample rate FS. signals. Spurious signals for a full-scale input may be –80 dBc.
This equation may be used for computational purposes to deter- However at 36 dB below full scale, these repetitive DNL errors
mine overall receiver noise. may cause spurious-free dynamic range (SFDR) to fall below
The signal-to-noise ratio (SNR) for an ADC can be predicted. 80 dBFS as shown in Figure 20.
When normalized to ADC codes, the following equation accu- A common technique for randomizing and reducing the effects
rately predicts the SNR based on three terms. These are jitter, of repetitive static linearity is through the use of dither. The
average DNL error and thermal noise. Each of these terms purpose of dither is to force the repetitive nature of static linear-
contributes to the noise within the converter. ity to appear as if it were random. Then, the average linearity
Equation 1: over the range of dither will dominate SFDR performance. In
1/2
the AD6640, the repetitive cycle is every 15.625 mV p-p.
 2
1+ ε VNOISE rms  
2
(
SNR = –20 log  2 πFANALOG t J rms ) To ensure adequate randomization, 5.3 mV rms is required;
2
+  +  
  212   212   this equates to a total dither power of –32.5 dBm. This will
  randomize the DNL errors over the complete range of the
FANALOG = analog input frequency residue converter. Although lower levels of dither such as that
t J rms = rms jitter of the encode (rms sum of encode source from previous analog stages will reduce some of the linearity
and internal encode circuitry) errors, the full effect will only be gained with this larger dither.
ε = average DNL of the ADC (typically 0.51 LSB) Increasing dither even more may be used to reduce some of the
global INL errors. However, signals much larger than the mVs
VNOISE rms = V rms thermal noise referred to the analog input of proposed here begin to reduce the usable dynamic range of the
the ADC (typically 0.707 LSB) converter.
Processing Gain Even with the 5.3 mV rms of noise suggested, SNR would be
Processing gain is the improvement in signal-to-noise ratio limited to 36 dB if injected as broadband noise. To avoid this
(SNR) gained through oversampling and digital filtering. Most problem, noise may be injected as an out-of-band signal. Typically,
of this processing gain is accomplished using the channelizer this may be around dc but may just as well be at FS/2 or at
chips. These special purpose DSP chips not only provide chan- some other frequency not used by the receiver. The bandwidth
nel selection and filtering but also provide a data rate reduction. of the noise is several hundred kilohertz. By band-limiting and
The required rate reduction is accomplished through a process controlling its location in frequency, large levels of dither may
called decimation. The term decimation rate is used to indicate be introduced into the receiver without seriously disrupting
the ratio of input data rate to output data rate. For example, if receiver performance. The result can be a marked improvement
the input data rate is 65 MSPS and the output data rate is in the SFDR of the data converter.
1.25 MSPS, then the decimation rate is 52. Figure 23 shows the same converter shown earlier but with this
Large processing gains may be achieved in the decimation and injection of dither (reference Figure 20).
filtering process. The purpose of the channelizer, beyond tun-
ing, is to provide the narrowband filtering and selectivity that +15V
traditionally has been provided by the ceramic or crystal filters 16kV LOW CONTROL
of a narrowband receiver. This narrowband filtering is the 1mF (0–1 VOLT)
source of the processing gain associated with a wideband re- NC202 A
ceiver and is simply the ratio of the passband to whole band NOISE 2.2kV
DIODE +5V
expressed in dB. For example, if a 30 kHz AMPS signal is (NoiseCom) REF 2kV
being digitized with an AD6640 sampling at 65 MSPS, the ratio –5V
1kV
would be 0.015 MHz/32.5 MHz. Expressed in log form, the
processing gain is –10 × log (0.015 MHz/32.5 MHz) or 33.4 dB.
A
OP27
Additional filtering and noise reduction techniques can be 0.1mF AD600 OPTIONAL HIGH
achieved through DSP techniques; many applications do use POWER DRIVE
additional process gains through proprietary noise reduction CIRCUIT
39V 390V
algorithms.
Figure 48. Noise Source (Dither Generator)
–20– REV. 0
AD6640
The simplest method for generating dither is through the use of The first noise calculation to make is based on the signal band-
a noise diode (Figure 48). In this circuit, the noise diode NC202 width at the antenna. In a typical broadband cellular receiver,
generates the reference noise that is gained up and driven by the the IF bandwidth is 12.5 MHz. Given that the power of noise in
AD600 and OP27 amplifier chain. The level of noise may be a given bandwidth is defined by P n = kTB, where B is band-
controlled by either presetting the control voltage when the width, k = 1.38 × 10–23 is Boltzman’s constant and T = 300k
system is set up, or by using a digital-to-analog converter (DAC) is absolute temperature, this gives an input noise power of
to adjust the noise level based on input signal conditions. Once 5.18 × 10–14 watts or –102.86 dBm. If our receiver front end has
generated, the signal must be introduced to the receiver strip. a gain of 30 dB and a noise figure of 10 dB, then the total noise
The easiest method is to inject the signal into the drive chain presented to the ADC input becomes –62.86 dBm (–102.86 + 30
after the last down conversion as shown in Figure 49. + 10) or 0.16 mV rms. Comparing receiver noise to dither re-
quired for good SFDR, we see that in this example, our receiver
IF AMP
BPF supplies about 3% of the dither required for good SFDR.
FROM Based on a typical ADC SNR specification of 68 dB, the
RF/IF
equivalent internal converter noise is 0.140 mV rms. There-
AIN
fore total broadband noise is 0.21 mV rms. Before process-
ing gain, this is an equivalent SNR (with respect to full scale)
COMBINER
of 64.5 dB. Assuming a 30 kHz AMPS signal and a sample
AIN
rate of 61.44 MSPS, the SNR through processing gain is in-
NOISE SOURCE LPF
AD6640 creased by approximately 33 dB to 97.5 dB. However, if eight
(REF. FIGURE 48)
strong and equal signals are present in the ADC bandwidth,
VREF then each must be placed 18 dB below full scale to prevent
0.1mF 0.01mF ADC overdrive. Therefore we give away 18 dB of range and
reduce the carrier-to-noise ratio (C/N) to 79.5 dB.
Assuming that the C/N ratio must be 10 dB or better for
Figure 49. Using the AD6640 with Dither
accurate demodulation, one of the eight signals may be reduced by
Receiver Example 66.5 dB before demodulation becomes unreliable. At this point,
To determine how the ADC performance relates to overall re- the input signal power would be –90.5 dBm. Referenced to the
ceiver sensitivity, the simple receiver in Figure 50 will be exam- antenna, this is –120.5 dBm.
ined. This example assumes that the overall down conversion
To improve sensitivity, several things can be done. First, the
process can be grouped into one set of specifications, instead of
noise figure of the receiver can be reduced. Since front end
individually examining all components within the system and
noise dominates the 0.16 mV rms, each dB reduction in noise
summing them together. Although a more detailed analysis
figure translates to an additional dB of sensitivity. Second, pro-
should be employed in a real design, this model will provide a
viding broadband AGC can improve sensitivity by the range of
good approximation.
the AGC. However, the AGC would only provide useful im-
In examining a wideband digital receiver, several considerations provements if all in-band signals are kept to an absolute minimal
must be applied. Although other specifications are important, power level so that AGC can be kept near the maximum gain.
receiver sensitivity determines the absolute limits of a radio
This noise limited example does not adequately demonstrate the
excluding the effects of other outside influences. Assuming that
true limitations in a wideband receiver. Other limitations such
receiver sensitivity is limited by noise and not adjacent signal
as SFDR are more restrictive than SNR and noise. Assume that
strength, several sources of noise can be identified and their
the analog-to-digital converter has an SFDR specification of
overall contribution to receiver sensitivity calculated.
–80 dBFS or –76 dBm (Full scale = +4 dBm). Also assume
GAIN = 30dB
that a tolerable carrier-to-interferer (C/I) (different from C/N)
NF = 10dB SINGLE CHANNEL ratio is 18 dB. This means that the minimum signal level is
BW =12.5MHz BW = 30kHz –62 dBFS (–80 plus 18) or –58 dBm. At the antenna, this is
RF/IF AD6640
–88 dBm. Therefore, as can be seen, SFDR (single or multi-
CHANNELIZER DSP
REF IN ENC
tone) would limit receiver performance in this example. How-
ever, as shown previously, SFDR can be greatly improved
61.44MHz through the use of dither (Figures 19, 22). In many cases, the
Figure 50. Receiver Analysis addition of the out-of-band dither can improve receiver sensitiv-
ity nearly to that limited by thermal noise.
REV. 0 –21–
AD6640
IF Sampling, Using the AD6640 as a Mix-Down Stage Figures 21 and 24 in Typical Performance Characteristics illus-
Since performance of the AD6640 extends beyond the baseband trate a multicarrier, IF Sampling System. By using dither, all
region into the third Nyquist zone, the converter has many uses spurious components are forced below 90 dBFS (Figure 24).
as a mix-down converter in both narrowband and wideband The dashed line illustrates how a 5 MHz bandpass filter could
applications. This application is called bandpass sampling. Do- be centered at 67.5 MHz. As discussed earlier, this approach
ing this has several positive implications in terms of the selection greatly reduces the size and complexity of the receiver’s RF/IF
of the IF drive amplifier. Not only is filtering a bit easier, the section.
selection of drive amplifiers is extended to classical IF gain
blocks. In the third Nyquist zone and above, the second and 0

third harmonics are easily filtered with a bandpass filter. Now
ALIASED
only in-band spurs that result from third order products are 20 SIGNALS
important.
In narrowband applications, harmonics of the ADC can be ALIASED
3RD HARMONIC
40
placed out-of-band. One example is the digitization of a ANALOG IF ALIASED
201 MHz IF signal using a 17.333 MHz clock. As shown in FILTER MASK 2ND HARMONIC
Figure 51, the spurious performance has diminished due to 60
internal slew rate limitations of the ADC. However, the SNR of
the converter is still quite good. Subsequent digital filtering with
80
a channelizer chip such as the AD6620 will yield even better SNR.
For multicarrier applications, third order intercept of the drive
100
amplifier is important. If the input network is matched to the 198 199.8 201.6 203.4 205.2 207
internal 900 ohm input impedance, the required full-scale drive FREQUENCY – MHz
level is –3 dBm. If spurious products delivered to the ADC are Figure 51. IF-Sampling a 201 MHz Input
required to be below –90 dBFS, the typical performance of the
ADC with dither applied, then the required third order intercept RECEIVE CHAIN FOR A PHASED ARRAY CELLULAR
point for the drive amplifier can be calculated. BASE STATION
For multicarrier applications, the AD6640 is useful up to about The AD6640 is an excellent digitizer for beam forming in
80 MHz analog in. For single channel applications, the AD6640 phased array antenna systems. The price performance of the
is useful to 200 MHz as shown from the bandwidth charts. In AD6640 followed by AD6620 channelizers allows for a very
either case, many common IF frequencies exist in this range of competitive solution. Phase array base stations allow better
frequencies. If the ADC is used to sample these signals, they will coverage by focusing the receivers’ sensitivity in the direction
be aliased down to baseband during the sampling process in needed. Phased array systems allow for the electronic beam to
much the same manner that a mixer will down-convert a signal. form on the receive antennas.
For signals in various Nyquist zones, the following equations A typical phased array system may have eight antennas as shown
may be used to determine the final frequency after aliasing. in Figure 52. Since a typical base station will handle 32 calls,
each antenna would have to be connected to 32 receivers. If
f 1NYQUISTS = f SAMPLE − f SIGNAL done with analog or traditional radios, the system grows quite
f 2NYQUISTS = abs ( f SAMPLE − f SIGNAL ) rapidly. With a multicarrier receiver, however, the design is
quite compact. Each antenna will have a wideband down-
f 3NYQUISTS = 2 × f SAMPLE − f SIGNAL converter with one AD6640 per receiver. The output of each
f 4NYQUISTS = abs (2 × f SAMPLE − f SIGNAL ) AD6640 would drive 32 AD6620 channelizers, which are phase
locked in groups of eight—one per antenna. This allows each
Using the converter to alias down these narrowband or wideband group of eight AD6620’s to tune and lock onto a different user.
signals has many potential benefits. First and foremost is the When the incoming signal direction is determined, the relative
elimination of a complete mixer stage along with amplifiers, phase of each AD6620 in the group can be adjusted such the
filters and other devices, reducing cost and power dissipation. In output signals sum together in a constructive manner, giving
some cases, the elimination of two IF stages is possible. high gain and directivity in the direction of the caller. This ap-
plication would not be possible with traditional receiver designs.
–22– REV. 0
AD6640
SYNC 1
EIGHT WIDEBAND FRONT ENDS AD6620 (1)
ANTENNA 1 AD6620 (2)
AD6620 (3)
AD6640
AD6620 (30)
COMMON LO
AD6620 (31)
AD6620 (32)
ANTENNA 2
AD6640 AD6620s (32 CHANNELS)
COMBINE SIGNALS
SYNC 1 FROM EIGHT ANTENNA'S
AD6620 (1) ADSP-21xx

SUM (1)
AD6620 (3)
AD6640 ADSP-21xx
SUM (2)
AD6620 (30)
AD6620 (31)
ANTENNA 4 ADSP-21xx
AD6620 (32) SUM (3)
AD6640 AD6620s (32 CHANNELS) 32 CHANNELS OUT

EACH CHANNEL IS SUMMATION
FROM EIGHT ANTENNA'S
SYNC 1
AD6620 (1) ADSP-21xx

SUM (30)
AD6620 (3)
ADSP-21xx
AD6640 SUM (31)
AD6620 (30)
AD6620 (31)
ANTENNA 6 ADSP-21xx
AD6620 (32) SUM (32)
SYNC 1
AD6620 (1)
AD6620 (3)
AD6640
AD6620 (30)
AD6620 (31)
ANTENNA 8
AD6620 (32)
Figure 52. Receive Chain for a Phased Array Cellular Base Station with Eight Antennas and 32 Channels
REV. 0 –23–
AD6640
AD6640AST OUTLINE DIMENSIONS
Dimensions shown in inches and (mm)
44-Terminal Plastic Thin Quad Flatpack

(ST-44)
0.063 (1.60)
MAX
C3141–8–1/98
0.472 (12.00) SQ
0.030 (0.75)
0.018 (0.45) 33 23
34 22
SEATING
PLANE
0.394
TOP VIEW (10.0)
(PINS DOWN) SQ
44 12
1 11
0.006 (0.15)
0.002 (0.05) 0.018 (0.45)
0.031 (0.80)
0.057 (1.45) BSC 0.012 (0.30)
0.053 (1.35)
PRINTED IN U.S.A.
–24– REV. 0
Appendix C
Analog Devices Application Note
a AN-501
APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • 781/329-4700 • World Wide Web Site: http://www.analog.com
Aperture Uncertainty and ADC System Performance

by Brad Brannon
Aperture Uncertainty In a sine wave, the maximum slew rate is at the zero
One of the key concerns when performing IF sampling is crossing. At this point, the slew rate is defined by the
that of aperture jitter or aperture uncertainty. The terms first derivative of the sine function evaluated at t = 0.
aperture jitter and aperture uncertainty are frequently d
interchanged in text. In this application, they have the v (t ) = A sin(2 π ft ) v (t ) = A 2 πf cos (2 π ft ) (1)
dt
same meaning. Aperture uncertainty is the sample-to-
sample variation in the encode process. Aperture uncer- evaluated at t = 0, the cosine function evaluates to 1 and
tainty has three residual effects: the first is an increase in the equation simplifies to:
system noise, the second is an uncertainty in the actual
d
phase of the sampled signal itself and third is v (t ) = A 2 πf = t JITTER (2)
dt
intersymbol interference. To achieve required noise per-
formance, aperture uncertainty of less than 1 ps is The units of slew rate are volts per second and yields
required when IF sampling. In terms of phase accuracy how fast the signal is slewing through the zero crossing
and intersymbol interference, the effects of aperture of the input signal. In a sampling system, a reference
uncertainty are small. In a worst case scenario of 1 ps clock is used to sample the input signal. If the sample
rms at an IF of 250 MHz, the phase uncertainty of error is clock has aperture uncertainty, an error voltage is gener-
0.09 degrees rms. This is quite acceptable even for a ated. This error voltage can be determined by multiply-
demanding specification such as GSM. The focus of this ing the input slew rate by the jitter.
analysis will therefore be on overall noise contribution
due to aperture uncertainty. VERROR = Slew Rate × t JITTER (3)
By analyzing the units, it can be seen that this yields unit

of volts. Usually, aperture uncertainty is expressed in
seconds rms and, therefore, the error voltage would be
in volts rms. Additional analysis of Equation 3 shows
that as analog input frequency increases, the rms error
voltage also increases in direct proportion to the aper-
ture uncertainty.
dV
Contribution to Overall System Performance
In IF sampling converters, clock purity is of extreme
importance. As with the mixing process, the input signal
is multiplied by a local oscillator or in this case, a sam-
pling clock. Since multiplication in time is convolution in
the frequency domain, the spectrum of the sample clock
ENCODE is convolved with the spectrum of the input signal. Since
aperture uncertainty is wideband noise on the clock, it
dt shows up as wideband noise in the sampled spectrum
Figure 1. RMS Jitter vs. RMS Noise as well. And since an ADC is a sampling system, the
spectrum is periodic and repeated around the sample
rate. This wideband noise therefore degrades the noise
REV. 0
AN-501
floor performance of the ADC. The theoretical SNR for At this high frequency, we can assume that jitter is a
an ADC, as limited by aperture uncertainty, is deter- contributor to noise. From the previous data measure-
mined by the following equation. ment we know the average quantization and thermal
noise; we can solve the general form equation for jitter
[
SNR = −20 log ( 2 πfanalog t JITTER rms) ] (4) as shown.
If Equation 4 is evaluated for an analog input of 201 MHz 2
and 0.7 ps rms “jitter,” the theoretical SNR is limited  –SNR  1+ ε 2
10 20  –  N 
to 61 dB. Therefore, systems that require very high   2 
dynamic range and very high analog input frequencies t JITTER rms = (7)
2 πfIF
also require a very low jitter encode source. When using
standard TTL/CMOS clock oscillators modules, 0.7 ps rms SNR is the high frequency SNR
has been verified for both the ADC and oscillator. Better N is the number of converter bits
numbers can be achieved with low noise modules. ε = average DNL from above and thermal noise
When considering overall system performance, a more fIF is the IF analog input frequency
generalized equation may be used. This equation builds Putting the Calculations to the Test
on the previous equation but includes the effects of The following data was collected using the AD9042ST/
thermal noise and differential nonlinearity. PCB evaluation board. No modifications were made.

1/ 2 The clock oscillator (M1280, manufactured by MF Elec-
rms  
2 2
1 + e  V
SNR = −20 log (2 πf analog t JITTER rms) 2 +  N  +  noiseN   (5) tronics) supplied with the evaluation board was used to
  2   2  

generate the encode signal which was delivered to the
AD9042 differentially via a transformer (Mini-Circuits
fanalog = analog IF Frequency
T1-1). The analog input was generated by a Rohde &
tJITTER rms = aperture uncertainty
Schwarz synthesizer. For more information about the
ε = average DNL of converter (~ 0.4 LSB)
evaluation board, please see the AD9042 data sheet.
Vnoise rms = thermal noise in LSBs
N = number of bits
0.00
Although this is a simple equation, it provides much –10.00
insight into the noise performance that can be expected –20.00

from a data converter. –30.00
–40.00
Measurement of Sub-Picosecond Aperture Uncertainty
–50.00
Aperture uncertainty is easily measured by looking at
–60.00
degraded SNR performance as a function of analog
input frequency. Since SNR degrades as analog input –70.00
frequency increases due to jitter, two FFTs are required –80.00
for the calculation. The first FFT should be done at a suf- –90.00
ficiently low analog frequency where the effects of aper- –100.00
ture uncertainty are negligible. Record the SNR –110.00
excluding all harmonics and higher order spurs. Then Figure 2. 2.3 MHz FFT
solve Equation 5, above, for general converter perfor-
Figure 2 is a 16K FFT of the AD9042 sampling a 2.3 MHz
mance by assuming that thermal noise is rolled up into
sine wave at 40.96 MSPS. Since we must exclude higher
the quantization noise and jitter is neglected. This gives
order harmonics from the SNR calculation, × represents
the equation below.
the unintegrated noise floor, or the mean noise floor.
–SNR
(6) Instead of integrating all of the noise spikes, this num-
ε = 2N ×10 20 –1
ber is summed across the entire spectrum, thus elimi-
nating the higher (and lower) order harmonics. Using
SNR is the low frequency SNR
Equation 8:
N is the number of converter bits
ε = average DNL (+ thermal noise)
SNR = –(–108 + 10 log (8192)) (8)
Then an FFT is done at very high frequency. The high fre-
SNR is found to be 69 dB. When this is used to
quency should be chosen to be near the 3 dB bandwidth
solve Equation 6 for ε the average DNL (and thermal
of the converter. Again, the SNR without harmonics
noise) for this converter is 0.4533 LSBs.
should be measured.
–2– REV. 0
AN-501
0.00 Table I.
–10.00
–20.00
Jitter Equivalent NF
–30.00 74LS00 4.94 28
3
–40.00 74ACT00 0.99 15
–50.00 74HCT00 2.20 21.84
2
E01399–1–9/00 (rev. 0)
4
–60.00
–70.00 Table I shows that the 74ACT00 gate delivers the low-
–80.00
est jitter of almost 1 ps rms. In many applications,
–90.00
even this is unacceptable. For receiver applications,
–100.00
the equivalent noise figure is shown for reference
–110.00
(valid at 201 MHz analog input only). Thus when using
logic gates for ADC clock distribute, they must be
Figure 3. 201 MHz FFT used minimally or not at all.
Next, the degradation in SNR must be found as a func-
Recent ADC developments require differential clock
tion of analog input frequency. Figure 3 is the same
drive. With this comes the ability to drive the encode
AD9042 and clock, but running an analog input fre-
with a sinusoidal signal instead of a square wave.
quency of 201 MHz. This time the unintegrated noise
floor has risen by almost 10 dB. Integrating with this
value of x yields an SNR of 60 dB. Using this SNR and SINE T1-1T
ENCODE
SOURCE
the previous solution for ε, the jitter can be found as fol- AD9042
R
lows using Equation 7:
ENCODE
2
 –60  1 + 0.4533 
2
10  –  
20
  2 12
 (9) Figure 5. Transformer Differential Encode
t JITTER rms = = 0.74 ps rms
2 π 201 × 10 6 As shown above, a sine source can be distributed to
encode the ADC. Sine sources can easily be distributed
Therefore, the combined aperture uncertainty for the
using power dividers and transformers to match imped-
AD9042 plus the clock oscillator is found to be less than
ances. Since ADC encode pins are high impedance, very
three quarters of a picosecond rms. At this time, it is not
little power is required to encode the devices and thus,
possible to determine which part is from the ADC and
when driving multiple devices, low encode drive power
which from the clock oscillator; however, these simple
is required. Since the sine source is spectrally pure,
measurements indicate that it is possible to measure
fewer problems can be expected in receiver applications
very small aperture uncertainty numbers using readily
with harmonics of the ADC encode clock.
available hardware and simple numeric calculations.
The chart following, Figure 6, is a useful guide for
AD9042 quickly determining jitter requirements based on analog
HIGH SPEED
ROHDE & BANDPASS EVALUATION FFT input frequency and converter bits. This chart is from
CACHE
SCHWARZ FILTER BOARD PROCESSOR
MEMORY
AD9042ST/PCB Analog Devices' publication, High Speed Design Seminar
(ISBN 0-916550-07-9).
Figure 4. Aperture Uncertainty Measurement Setup
110
Many applications require that a master clock be distrib- 1
100 t a = 0.5ps SNR = 20 log10
2 ␲ ft a
uted to many different sources. Many systems have
PRINTED IN U.S.A.
90 t a = 1ps
multiple ADCs such as cellular basestations or ultra-
80 14
sound equipment. The question quickly arises, however, t a = 2ps
70 12
how much jitter is introduced into a system when placed
SNR – dB
t a = 10ps
in a distribution system. The first option in distributing 60 10
ENOB
an ADC clock is to use logic gates to fan out the encode 50 t a = 50ps 8
signal, but this rapidly increases the amount of jitter 40
6
t a = 250ps
introduced into the system. 30
4
20 t a = 1250ps
By using the technique described above, the jitter per
10
gate (74xx00) for several logic families was measured
0
and summarized below. 1 2 3 5 7 10 20 30 50 70 100
FREQUENCY OF FULL SCALE SINE WAVE INPUT – MHz
Figure 6. Signal-to-Noise Ratio Due to Aperture Jitter
REV. 0 –3–

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NAVSEA AD6640 Total Dose

Surface Warfare Center

Table 1 gives a summary of the AD6640 specifications of interest.

Figure 1 - Populated Evaluation Board

Static Bias for parts #1 and #6:

Dynamic Bias for parts #3, #4 and #7:

Voh -> -6mA Vol -> 6mA

Dose Rate = 49.5 rad(Si)/sec

Part #3 - Min DNL

Dose Rate = 49.5 rad(Si)/sec

Maximum Differential Non Linearity (LSB)

Part #1 - Max DNL

Dose Rate = 49.5 rad(Si)/sec

Any questions or comments should be directed to John Bings, 812-854-1672,

Dose Rate = 49.5 rad(Si)/sec

Part #4 - Dynamic Bias

Dose Rate = 49.5 rad(Si)/sec

Part #1 - Max DNL

Dose Rate = 49.5 rad(Si)/sec

0.1385 Dose Rate = 49.5 rad(Si)/sec

0.024 Dose Rate = 49.5 rad(Si)/sec

Dose Rate = 49.5 rad(Si)/sec

4500 Dose Rate = 49.5 rad(Si)/sec

3.3 V or 5 V CMOS-Compatible Output Levels 6

PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS

DIGITAL SPECIFICATIONS (AV CC = +5 V, DVCC = +3.3 V; TMIN = –408C, TMAX = +858C)

Model Temperature Range Package Description Package Option

Pin No. Name Function

Figure 1. Timing Diagram

VCH AVCC DVCC

AIN BUF T/H CURRENT

Figure 2. Analog Input Stage

Figure 6. 2.4 V Reference

Figure 4. Compensation Pin, C1

ENCODE = 65MSPS ENCODE = 65MSPS

WORST CASE HARMONIC – dBc

ENCODE = 65MSPS ENCODE = 65MSPS

SNR, WORST CASE SPURIOUS – dB, dBc

SNR, WORST FULL SCALE SPURIOUS – dB, dBc

dBFS 2.2MHz WORST SPUR

POWER RELATIVE TO ADC FULL SCALE – dB

WORST CASE SPURIOUS – dBc

80 AIN = 19.5MHz 80 AIN = 19.5MHz

POWER RELATIVE TO ADC FULL SCALE – dB

together and corrected in the digital error correction logic to

no input signal connected to either ENCODE pin, the voltage AD6640

510V 510V 1:4

Figure 30. Differential ECL for Encode

signal or a sine signal.

Figure 31. ECL Comparator for Encode ANALOG +j100V 1:4

Each analog input connects through a 450 ohm resistor to the

Table I. AD6640ST/PCB Bill of Material

Item Quantity Reference Description

0.01mF 0.1mF 348V GND GND

Figure 36. AD6640ST/PCB Schematic

SHARC is a registered trademark of Analog Devices, Inc.

Figure 46. Simplified Wideband PCS Receiver

–20 example, the passband filter would range from FS to 3 FS/2.