AMC ENGINEERING COLLEGE

DEPARTMENT OF ELECTRONICS AND

COMMUNICATION ENGINEERING

2021 SCHEME: LAB MANUAL

(Academic year: 2022-23)

LAB CODE: 21EC35

LAB NAME: Analog and Digital Electronics Lab

SEMESTER: III
 INDEX TABLE

S. no. Description Page no.

I Vision and Mission statement 3

II PO and PSO statement 4

III CO statement with mapping 5

IV Syllabus 6

V Rubrics 8

VI List of Experiments 9
 VISION MISSION AND PROGRAM EDUCATIONAL OBJECTIVES

INSTITUTE VISION

To be a leader in imparting value based Technical Education and

Research for the benefit of society.

INSTITUTE MISSION

 To provide state of the art Infrastructure facilities.

 To implement modern pedagogical methods in delivering the academic
programs with experienced and committed faculty.
 To create a vibrant ambience that promotes Learning, Research, Invention and
Innovation.
 To undertake manpower and skill development programmes for Academic
Institutions and Industries.
 To enhance Institute Industry Interface through Collaborative Research and
Consultancy
 To generate and disseminate knowledge through training
programme/workshops/seminars/conferences/publications.
 To be a more comprehensive college in terms of the number of programs offered.
 To relentlessly pursue professional excellence with ethical and moral values.

DEPARTMENT VISION

To develop outstanding Electronics and Communication Engineers to

meet the ever changing Social and Technological needs of the Society.

DEPARTMENT MISSION

To provide State-of-the-Art infrastructure in Electronics and

M1
Communication Engineering.

To disseminate strong theoretical and practical exposure to

M2
meet the emerging trends in the industry.

To promote a free thinking environment with innovative

M3
teaching-learning pedagogy.

To develop value based socially responsible professionals for the

M4
betterment of the Society.
 PROGRAM EDUCATIONAL OBJECTIVES (PEO)

Develop and excel in their chosen profession on technical front and/or

PE01 progress towards advanced continuing education, Inter-disciplinary
Research and Entrepreneurship.
PE02 Become reputed and innovative solution provider to complex system design
problems or challenges relevant to Electronics and Communication
PE03 Progress as effective team members and achieve a leadership position with trust,
mutual respect and professional ethics
PE04 Become responsible and pro-active citizens for the overall welfare and progress of
the Society

PO AND PSO STATEMENT

Engineering knowledge: Apply the knowledge of mathematics, science,

P01 engineering fundamentals, and an engineering specialization to the
solution of complex engineering problems.
Problem analysis: Identify, formulate, review research literature, and analyze
P02 complex engineering problems reaching substantiated conclusions using first
principles of mathematics, natural sciences, and engineering sciences
Design/development of solutions: Design solutions for complex engineering
P03 problems and design system components or processes that meet the specified
needs with appropriate consideration for the public health and safety, and the
cultural, societal, and environmental considerations
Conduct investigations of complex problems: Use research-based knowledge
P04 and research methods including design of experiments, analysis and
interpretation of data, and synthesis of the information to provide valid
conclusions.
Modern tool usage: Create, select, and apply appropriate techniques, resources,
P05 and modern engineering and IT tools including prediction and modelling to
complex engineering activities with an understanding of the limitations
The engineer and society: Apply reasoning informed by the contextual
P06 knowledge to assess societal, health, safety, legal and cultural issues and the
consequent responsibilities relevant to the professional engineering practice
Environment and sustainability: Understand the impact of the professional
P07 engineering solutions in societal and environmental contexts, and demonstrate
the knowledge of, and need for sustainable development
P08 Ethics: Apply ethical principles and commit to professional ethics and
responsibilities and norms of the engineering practice
P09 Individual and team work: Function effectively as an individual, and as a
member or leader in diverse teams, and in multidisciplinary settings
P10 Communication: Communicate effectively on complex engineering activities
with the engineering community and with society at large, such as, being able to
 comprehend and write effective reports and design documentation, make effective
presentations, and give and receive clear instructions
Project management and finance: Demonstrate knowledge and understanding
P11 of the engineering and management principles and apply these to one’s own work,
as a member and leader in a team, to manage projects and in multidisciplinary
environments
Life-long learning: Recognize the need for, and have the preparation and ability
P12 to engage in independent and life-long learning in the broadest context of
technological change
Develop the components for analog and digital systems, communication systems,
PSO1 control and signal processing systems using acquired knowledge of basic
skills and various design tools
Formulate the solution for interdisciplinary problems through acquired
PSO2 programming knowledge in the respective domain by complying real-time
constraints

COURSE OUTCOMES (CO)-PO/PSO Mapping

OUTCOMES Bloom’s
CO.No. After completing the course, the student will be Cognitive PO PSO
able to: Level

Understand the electronic circuit schematic and

C305.1 Understand -- 1
its working

Realize and test the amplifier & Oscillator for the

C305.2 Analyze 2,5 1,2
given Specifications

Realize the opamp circuits for the applications

C305.3 such as DAC, implement mathematical Analyze 2,5 1,2
functions and precision rectifiers

Study the characteristics of SCR and test the

C305.4 Create 3,5 1
RC triggering circuits

Design and test the combinational and

sequential logic circuits for their functionalities
C305.5 Apply 2,5,9 1,2
Use suitable ICs based on the specifications and
functions
 Syllabus
VISVESVARAYA TECHNOLOGICAL UNIVERSITY, BELAGAVI
B.E: Electronics & Communication Engineering / B.E: Electronics & Telecommunication
Engineering NEP, Outcome Based Education (OBE) and Choice Based Credit System (CBCS)
(Effective from the academic year 2021 – 22)
Analog and Digital Electronics Lab
Course Code 21ECL35 CIE Marks 50
Teaching Hours/Week (L:T:P: S) 0:0:2:0 SEE Marks 50
Credits 1 Exam Hours 3

Course objectives:
This laboratory course enables students to
 Understand the electronic circuit schematic and its working
 Realize and test amplifier and oscillator circuits for the given specifications
 Realize the opamp circuits for the applications such as DAC, implement mathematical
functions and precision rectifiers.
 Study the static characteristics of SCR and test the RC triggering circuit.
 Design and test the combinational and sequential logic circuits for their functionalities.
 Use the suitable ICs based on the specifications and functions.
Sl.No Experiments
.
1 Design and set up the BJT common emitter voltage amplifier with and without feedback
and determine the gain- bandwidth product, input and output impedances.

2 Design and set-up BJT/FET

i) Colpitts Oscillator, ii) Crystal Oscillator and iii) RC Phase shift oscillator

3 Design and set up the circuits using opamp:

i) Adder, ii) Integrator, iii) Differentiator and iv) Comparator

4 Obtain the static characteristics of SCR and test SCR Controlled HWR and FWR using
RC triggering circuit.

5 Design and implement

(a) Half Adder & Full Adder using basic gates and NAND gates,
(b) Half subtractor & Full subtractor using NAND gates,
(c) 4-variable function using IC74151(8:1MUX).
6 Realize
(i) Binary to Gray code conversion & vice-versa (IC74139),
(ii) BCD to Excess-3 code conversion and vice versa
7 a) Realize using NAND Gates:
i) Master-Slave JK Flip-Flop, ii) D Flip-Flop and iii) T Flip-Flop
b) Realize the shift registers using IC7474/7495:
(i) SISO (ii) SIPO (iii) PISO (iv) PIPO (v) Ring counter and (vi) Johnson counter.
8 Realize
a) Design Mod - N Synchronous Up Counter & Down Counter using 7476 JK Flip-
flop
b) Mod-N Counter using IC7490 / 7476
c) Synchronous counter using IC74192
 9 Design 4-bit R - 2R Op-Amp Digital to Analog Converter
(i) for a 4-bit binary input using toggle switches
(ii) by generating digital inputs using mod-16
10 Pseudorandom sequence generator using IC7495

11 Test the precision rectifiers using opamp: i) Half wave rectifier ii) Full wave rectifier
12 Design and test Monostable and Astable Multivibrator using 555 Timer
Course outcomes (Course Skill Set):
At the end of the course the student will be able to:
1. Design and analyze the BJT/FET amplifier and oscillator circuits.
2. Design and test Opamp circuits to realize the mathematical computations, DAC and
precision rectifiers.
3. Design and test the combinational logic circuits for the given specifications.
4. Test the sequential logic circuits for the given functionality.
5. Demonstrate the basic electronic circuit experiments using SCR and 555 timer.
Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam
(SEE) is 50%. The minimum passing mark for the CIE is 40% of the maximum marks (20
marks). A student shall be deemed to have satisfied the academic requirements and earned the
credits allotted to each course. The student has to secure not less than 35% (18 Marks out of
50) in the semester-end examination (SEE).
Continuous Internal Evaluation (CIE):
CIE marks for the practical course is 50 Marks.
The split-up of CIE marks for record/ journal and test are in the ratio 60:40.
 Each experiment to be evaluated for conduction with observation sheet and record write -
up. Rubrics for the evaluation of the journal/write-up for hardware/software experiments
designed by the faculty who is handling the laboratory session and is made known to
students at the beginning of the practical session.
 Record should contain all the specified experiments in the syllabus and each experiment
write-up will be evaluated for 10 marks.
 Total marks scored by the students are scaled downed to 30 marks (60% of maximum
marks).
 Weightage to be given for neatness and submission of record/write-up on time.
 Department shall conduct 02 tests for 100 marks, the first test shall be conducted after
the 8th week of the semester and the second test shall be conducted after the 14th week of
the semester.
 In each test, test write-up, conduction of experiment, acceptable result, and procedural
knowledge will carry a weightage of 60% and the rest 40% for viva-voce.
 The suitable rubrics can be designed to evaluate each student’s performance and learning
ability. Rubrics suggested in Annexure-II of Regulation book
 The average of 02 tests is scaled down to 20 marks (40% of the maximum marks).
The Sum of scaled-down marks scored in the report write-up/journal and average marks of two
tests is the total CIE marks scored by the student.
Semester End Evaluation (SEE):
SEE marks for the practical course is 50 Marks.
SEE shall be conducted jointly by the two examiners of the same institute, examiners are
appointed by the University
All laboratory experiments are to be included for practical examination.
(Rubrics) Breakup of marks and the instructions printed on the cover page of the answer
script to be strictly adhered to by the examiners. OR based on the course requirement
evaluation rubrics shall be decided jointly by examiners.

Students can pick one question (experiment) from the questions lot prepared by the internal
/external examiners jointly.

Evaluation of test write-up/ conduction procedure and result/viva will be conducted

jointly by examiners.

General rubrics suggested for SEE are mentioned here, writeup-20%, Conduction procedure
and result in -60%, Viva-voce 20% of maximum marks. SEE for practical shall be
evaluated for 100 marks and scored marks shall be scaled down to 50 marks (however,
based on course type, rubrics shall be decided by the examiners)

Change of experiment is allowed only once and 15% Marks allotted to the procedure part
to be made zero.

The duration of SEE is 03 hours

Rubrics suggested in Annexure-II of Regulation book

Suggested Learning Resources:

1. Fundamentals of Electronic Devices and Circuits Lab Manual, David A Bell, 5th
Edition, 2009, Oxford University Press.
2. Op-Amps and Linear Integrated Circuits, Ramakant A Gayakwad, 4th Edition,
Pearson Education, 2018. ISBN: 978-93-325-4991-3.
3. Fundamentals of Logic Design, Charles H Roth Jr., Larry L Kinney, Cengage Learning,
7th Edition.
 List of Experiments
Bloom’s
Exp. No. Experiment Name cognitive CO PO PSO
level
Design and set up the BJT common emitter
voltage amplifier with and without feedback and
1) Apply
determine the gain- bandwidth product, input
1 1,10 1
and output impedances.

Design and set-up BJT/FET

2) i)Colpitts Oscillator, ii) Crystal Oscillator and iii) Apply 1 1,10 1
RC Phase shift oscillator

Design and set up the circuits using opamp: i)

3) Adder, ii) Integrator, iii) Differentiator and iv)
Comparator. Apply 1 1,10 1

Obtain the static characteristics of SCR and

4) test SCR Controlled HWR and FWR using RC
Create 2 3,10 1,2
triggering circuit.

Design and implement

(a) Half Adder & Full Adder using basic gates

and NAND gates,
5)
(b) Half subtractor & Full subtractor using Apply 2 3,10 1,2
NAND gates,
(c) 4-variable function using IC74151(8:1MUX).

Realize

(i) Binary to Gray code conversion & vice-versa

6) (IC74139), Create 2 3,10 1,2
(ii) BCD to Excess-3 code conversion and vice
versa

Realize using NAND Gates:

a) i)Master-Slave JK Flip-Flop, ii) D Flip-Flop

and iii) T Flip-Flop
7)
b) Realize the shift registers using Create 2 3,10 1,2
IC7474/7495:
SIS0 (ii) SIPO (iii) PIS0 (iv) PIPO (v) Ring counter
and (vi) Johnson counter

Realize
8)
a) Design Mod — N Synchronous Up Counter Create 2 3,10 1
& Down Counter using 7476 JK Flip-flop
 b) Mod-N Counter using IC7490 / 7476
c) Synchronous counter using IC74192.
Design 4-bit R — 2R Op-Amp Digital to Analog
Converter
9) (i) for a 4-bit binary input using toggle Apply 2 3,10 1,2
switches
by generating digital inputs using mod-16
Pseudorandom sequence generator using
10)
IC7495 Create 2 3,10 1,2

Test the precision rectifiers using opamp: i) Half

11)
wave rectifier ii) Full wave rectifier Create 2 3,10 1,2

Design and test Monostable and Astable

12) Multivibrator using 555 Timer Apply 2 3,10 1,2
 EXPERIMENT 1
BJT Common Emitter Voltage Amplifier
AIM: Design and set up the BJT common emitter voltage amplifier with and without feedback
and determine the gain- bandwidth product, input and output impedances
COMPONENTS REQUIRED:

NPN transistor (SL100), Resistors, Capacitors, Signal generator, DC power supply (0-30v),
DMM and CRO.
THEORY:
In RC coupled amplifier the input capacitor is used to couple the input signal to the base of
transistor. Since the coupling from one stage to next stage can be achieved by a coupling
capacitor followed by a connection to a shunt resistor such amplifiers are called resistance
capacitance (RC) coupled amplifiers. When an ac signal is applied to the input of the first stage
it is amplified with a phase reversal by the transistor. The frequency response is a graph of the
gain (in decibels) versus the frequency (in logarithmic scale). This characteristic can be
subdivided into low, medium and high frequency regions. In the low frequency range, the gain
drops due to increasing reactance of coupling capacitor, source capacitance and emitter
capacitor. As the frequency increases, the capacitive reactance reduces and the gain increases.
After this if the frequency is increased further, i.e. in the high frequency range, the gain drops
due to the increased flow of the a.c signal through CE. To fix the boundaries of frequency where
the gain is relatively high and constant, 0.707Amid is chosen to be the voltage gain at the cut-
off levels. The corresponding frequencies f1 and f2 are generally called the corner, cut-off,
band, break or half power frequencies. The multiplier 0.707 is chosen because at this level the
output power is half the mid-band power output. This is illustrated in the Ideal graph.
DESIGN:

Let minimum required midband voltage gain Let Vcc =12 V, Ic =4.5 mA, BETA =100(SL
= 50. 100)
(ii) To find RC :
(i) To find RE :
Choose VCE =Vcc/2= 12/2 =
Choose VE = (Vcc/10 )= 12/10 = 1.2V
6V Apply KVL in CE loop :
VE = =VRE = IE × RE = 1.2V therefore , RE = (VE
VCC -(ICRC) -VCE -VRE = 0
/ IE ) and IE =IC 12 -(4.5 ×Rc) -6-1.2 = 0
therefore RE = 1.2/ IC = 1.2/4.5ma = 0. 267K CALCULATING WE GET Rc = 1:07K
, RE = 270 Ω
Choose Rc = 1k Ω (standard value)
(iii) To find R1 & R2 :
(iv) To find Bypass cap. CE :
wkt VB =Vbe+VE = 0.7+1.2 = 1.9V
(at f = 100Hz) Let Xce = RE/10
Also IB = Ic/ β = 4.5mA/100 = 0. 045mA Assume
therefore 1/(2 π × f ×CE )= (RE/10)
10Ib flows through R1 & 9Ib flows through R2
Putting values and calculating CE =
Then R1 = (Vcc -VB)/10Ib = 22K Ω and R2
59μF Choose CE = 47μF(electrolytic)
=VB/9Ib = 4.7K Ω
(v) To find CC1 and CC2 :
hie = Xcc1 = (Hie||Rb)/10, Xcc1 = 1/(2π ∗ f
∗ CC1),CC1 =?
 Xcc2 = (Rc||Rl)/10, Xcc2 = 1/(2π ∗ f ∗
CC2),CC2 =?

CIRCUIT DIAGRAM

OBSERVATION TABLE 1:
(Without feedback, CE present)

INPUT VOLTAGE Vi = 20 mv PEAK = (20 /√2 ) = 14 mv rms

Frequency(H Output Voltage(Vo)
Voltage Gain =(Vo/Vi) Gain = 20 log (Vo/Vi) dB
z) RMS value from DMM.

100
200
400
600
800
900
1k
1.5K
2k
5k
10k
20k
30k
50k
100k
200k
300k
400k
500k
700k
900k
1Mega

OBSERVATION TABLE 2:
(With feedback, CE removed) [USE THE SAME OBSERVATION TABLE AGAIN]
PROCEDURE

INPUT VOLTAGE Vi = 20 mv PEAK = (20 /√2 ) = 14 mv rms

Frequency(H Output Voltage(Vo)
Voltage Gain =(Vo/Vi) Gain = 20 log (Vo/Vi) dB
z) RMS value from DMM.

100
200
400
600
800
900
1k
1.5K
2k
5k
10k
20k
30k
50k
100k
200k
300k
400k
500k
700k
900k
1Mega

1. Without feedback means CE is present in the circuit.

(a) Connect the circuit as shown in fig. 1 without applying Vin, check the DC voltage
conditions
VCE = 6V and VBE = 0.7V as per design.

(b) Connect the sine wave input signal of amplitude 40mV (Vp-p), 10KHz from signal
generator and CRO CH 1 and check if a proper sine wave output appears on channel 2 of CRO.
Measure the peak to peak amplitude of input and output and also observe the 180-degree
phase shift between input and output.

(c) Now Vary the input sine wave frequency from 50Hz to 1MHz in suitable steps. Note
down RMS output voltage at each step using DMM.
(d) Calculate the gain in decibels(dBs), Plot Gain in dB versus frequency on the semi log
graph, determine Bandwidth and G.B.W product from the plot.
2. With feedback

(a) without disturbing the circuit, REMOVE CAPAITOR CE from the circuit and repeat the
above steps c and d as it is

EXPECTED /IDEAL GRAPH (FREQUENCY RESPONSE):

TO FIND INPUT RESISTANCE

PROCEDURE

1. Connect a DRB (value should be Zero) in series for the existing RC coupled amplifier
circuit as
shown above.
2. Put the frequency of the input in midband (around 10kHz), keeping Vin same(20mV),
note down
the value of output voltage.

3. Increase the value of DRB linearly such that the output voltage should be half of its
initial value,
the current value of DRB is the Input Resistance Zin.

TO FIND OUTPUT RESISTANCE

PROCEDURE
1. Connect a DRB (value should be maximum) in parallel for the existing RC coupled
amplifier circuit as shown above.

2. Put the frequency of the input in midband (around 10 kHz), keeping Vin same (20mV),
note down the value of output voltage.

3. Decrease the value of DRB linearly such that the output voltage should be half of its
initial value, the current value of DRB is the Output Resistance.
RESULT:
Thus the RC Coupled Amplifier has following features.

CONCLUSION VIVA QUESTIONS:

What is an amplifier?
What is a CE amplifier? Why is it called as an RC coupled amplifier?

Define Bandwidth, gain, gain –bandwidth product, midband, lower cutoff and upper cutoff
frequencies.
What is 3 dB FREQUENCY? What is half power FREQUENCY?

What is the purpose of bypass capacitor CE? What is the purpose of coupling capacitor CC1
and CC2?
Which type of biasing is used in this circuit?
 EXPERIMENT 2
BJT OSCILLATORS

AIM: Design and set up the BJT i) Colpitts Oscillator, and ii) Crystal Oscillator iii) RC Phase
Shift Oscillator for a given output frequency.
COMPONENTS REQUIRED:
NPN transistor (SL100), Resistors, Potentiometer, Capacitors, Inductors, DC power supply
(0- 30V) and CRO.
THEORY:
These oscillators produce sinusoidal output waveforms. These are radio frequency oscillators.
To get higher frequency of oscillation, feedback circuit uses inductor and capacitors or a quartz
crystal in the feedback loop. The oscillators that use L&C elements are called tuned oscillators.
Hartley and Colpitts oscillators are LC tuned oscillator. An oscillator is made up of an amplifier
and a feedback network.
A Hartley oscillator has a Potential divider biased BJT amplifier and LC feedback circuit. Its
feedback or tank circuit consists of 2 inductors in series and one capacitor in parallel. Colpitts
oscillator is similar to the Hartley oscillator except the change in the tank circuit. Here the
tank/ feedback circuit consists of 2 capacitors in series and one capacitor. The amplifier is
single stage amplifier and provides 180°phase shift. So this tank circuit provides 180°phase
shift due to inductor &capacitor connection to make total phase shift of the circuit as 360°at
the frequency of oscillations. When the feedback is adjusted, Barkhausen criteria are satisfied
and sustained oscillations occur at the output.

Crystal oscillators are made from quartz (piezoelectric material). A crystal can be operated in
the series resonant or parallel resonant mode. In the series mode crystal offers minimum
impedance at resonance and in parallel mode it offers maximum impedance and is
inductive. Since the parallel resonant frequency of a crystal is slightly higher than its series
resonant frequency, the method of connection is important. They are used for generating
accurate, stable and fixed values of frequencies in the order of few Mega Hertz, which cannot
be achieved through LC or RC circuits.

DESIGN:
Amplifier design is same for Colpitts and Crystal oscillator.
Let minimum required midband
voltage gain = 50.
(i) To find RE:
Choose VE = (Vcc/10) = 12/10 = 1.2V
VE = =VRE = IE × RE = 1.2V
therefore, RE = (VE / IE) and IE
=IC
therefore, RE = 1.2/ IC = 1.2/4.5ma
= 0. 267K , RE = 270 Ω
(iii) To find R1 & R2:
wkt VB =Vbe+VE = 0.7+1.2 = 1.9V
Also IB = Ic/ β = 4.5mA/100 = 0.
045mA
Let Vcc =12 V, Ic =4.5 mA, BETA =100(SL
100)
(ii) To find RC:
Choose VCE =Vcc/2= 12/2 = 6V
Apply KVL in CE loop: VCC -
(ICRC) -VCE -VRE = 0
12-(4.5×Rc)-6-1.2 = 0
CALCULATING WE GET Rc =1:07K
Choose Rc = 1k Ω (standard value)
(iv) To find Bypass cap. CE:
(at f = 100Hz) Let Xce = RE/10
therefore 1/(2 π × f ×CE )=
(RE/10)
Putting values and calculating CE =
59μF
 DESIGN OF TANK CIRCUIT for Colpitt

Assume 10Ib flows through R1 & 9Ib

flows through R2
Then R1 = (Vcc -VB)/10Ib = 22K Ω
and
R2 =VB/9Ib = 4.7K Ω
Choose CE = 47μF(electrolytic)
(v) To find CC1 and CC2: choose
CC1 & CC2 = 0:1μF
(ceramic)

Osc.
Therefore, choose C1 = C2 = 1000PF
(102 ceramic)

CIRCUIT DIAGRAM:

COLPITT OSCILLATOR CRYSTAL OSCILLATOR

OUTPUT WAVEFORM: SAME FOR COLPITT AND CRYSTAL OSCILLATOR.

PROCEDURE (same for both)

1. make connections only for the amplifier part of the circuit without connecting
tank circuit.
2. check the DC voltage conditions VCE = 6V and VBE = 0.7V as per design using millimeter
and then connect tank circuit.
3. The potentiometer (1K pot) is varied till stable oscillations are observed on the CRO.
4. measure the peak to peak amplitude and time period of the output. Calculate the
frequency and verify whether it matches with the designed value

RC phase shift Oscillator:

Design:
Given Vcc = +12V , Ic = 4mA and h f e = 100 Let Ve = 2V,Vce = 6V .
RE = Ve/(Ie or Ic)= 500 (use 470Ω)
Vcc – IcRc – Vce = 0
Rc = (Vcc- Vce)/Ic= 1kΩ
From the circuit,
Vb(voltage across R2∗) = (Vcc ∗R2)/(R1 R2) and
Vb = Vbe + Ve
= 2 + 0.7
= 2.7V
Then by using previous equation,
R1 = 3.44R2 If R2 = 6.8kΩ, then R1 = 23.3kΩ (use 22kΩ) Use CE = 47µF, Co = 0.47µF.

For RC-network:
√
fo = 1/(2πRC (6 + 4K))
 Let fo = 2kHz and R =
2.2kΩWhere K = R + C/R
= 0.454.
Then C = 0.01µF.

Result and Conclusion:

VIVA QUESTIONS:

What is an oscillator ? What are different types of oscillators ?

Compare RC , LC and crystal oscillators based on the circuits, feedback
elements and frequency range of output .
What is Barkhausen criteria? Explain how sustained
oscillations are generated . Identify the amplifier part and
feedback part of your circuits.
Explain how 360 phase shift is
produced in your circuit. How will you
change the frequency of output ?
Which type of feedback is used in oscillators? What are the advantages of crystal
oscillator ?
What are different modes of crystal? Which mode is used in this circuit?
 EXPERIMENT 3
Adder, Integrator, Differentiator, Comparator
AIM: To design a 2 input Inverting Adder circuit using IC 741 and experimentally verify its
operation.

COMPONENTS REQUIRED: Function Generator, CRO, Dual PS, Bread/Spring Board Op-
Amp IC 741, Resistors, Capacitors (as per design), Connecting wires and probes.
THEORY
The figure 1 shows a circuit that amplifies the sum of two or more inputs. This is essentially
an inverting amplifier with two input voltages and two input resistors. The output voltage is
equal to the negative of sum of 2 input voltages. The summing amplifier can function as a
multichannel audiomixer for several audio channels. No interference (feedback from one
channel to the input of another channel) occurs because each signal source is applied via one
resistor with its opposite end at ground potential. Making the input resistors adjustable allows
the output volume from each channel to be separately controlled.

CIRCUIT DIAGRAM and DESIGN

5A) OP-AMP AS INVERTING ADDER

For a simple adder

minimum value of voltage gain is AV
= 1 To Calculate Resistor Values:
Take for IC 741, IBmax=500nA
We know for an inverting Amplifier, closed loop gain AV =
-RF/R1. Choose Resistance R = R1 = R2 = 10k ohms (less
than 140kohms)
Therefore 1 = RF /10kohms. Thus RF = 10 kohms (Choose Standard Resistance)
PROCEDURE
1. Make connections as per the circuit diagram.
2. Set a square wave input signal of 2 Vpp, 1 KHz using a function
generator and connect it to the circuit.
3. If required, slowly increase the input frequency to get a proper
triangular waveform. Measure the amplitude & timing of input & output
voltage waveforms simultaneously on the CRO.
5. Verify that the circuit works as good integrator only when f > 1KHz
6. Repeat steps 2,3,& 4 for a sine wave input.
7. Draw the waveforms.
OBSERVATIONS:
SL.NO. V1= V2= Vo= PRACTICAL GAIN = VO/Vi
1 2V 1V
2 1V 2Vpp,1KHz

RESULT:
5B) OP-AMP AS INVERTING INTEGRATOR
AIM: To design an Inverting integrator circuit for a given input signal
using IC 741 and experimentally
verify its operation.
THEORY: An integrator is an opamp circuit whose output is proportional
to negative integral of the input voltage.

DESIGN Let the frequency of input signal to be integrated = 1KHz

This is the frequency at which gain of the
circuit will become 0 dB. It is given by fo =
1/ (2 πR1×CF) = 1KHz
Let C = 0.01μF thus calculating we get R1 = 15.9k (Choose
standard 15 K Ω resistance)

CIRCUIT

AND
WAVEFORMS

PROCEDURE: SAME FOR INTEGRATOR AND DIFFERENTIATOR

1. Make connections as per the circuit diagram.
2. Set a square wave input signal of 2 Vpp, 1 KHz using a function
generator and connect it to the circuit.
3. If required ,Slowly increase the input frequency to get a proper
triangular waveform. Measure the amplitude & timing of input & output
voltage waveforms simultaneously on the CRO.
5. Verify that the circuit works as good integrator only when f > 1KHz
6. Repeat steps 2,3,& 4 for a sine wave input.
7. Draw the waveforms.
5C) OP-AMP AS INVERTING DIFFERENTIATOR
AIM: T o design an Inverting differentiator circuit for a given input
signal using IC 741 and experimentally
verify its operation.
THEORY: A differentiator is an opamp circuit whose output is
proportional to negative of differentiation of the input voltage.

DESIGN Let the frequency of input signal to be integrated = 1KHz

This is the frequency at which gain of the circuit will
become 0 dB. It is given by fo = 1/ (2 πRF×C1) = 1KHz
Let C1 = 0.01μF thus calculating we get RF = 15.9k (Choose
standard 15 K Ω resistance)

CIRCUIT AND
WAVEFORMS

RESULT AND CONCLUSION:

VIVA QUESTIONS:
Define an adder/ integrator / differentiator?
What are the applications an adder/ integrator / differentiator? What is the use of
opamp in this circuit?
EXPERIMENT NO 5:

DESIGN AND IMPLEMENT

(A) HALFADDER AND FULLADDER USING: BASIC

GATES, NAND GATES.

AIM:
 To Realize Half adder and Full adder by using I. X-OR and Basic Gates, II.
NAND Gate only
APPARATUS REQUIRED:
 IC 7486, IC 7432, IC 7408, IC 7400, Trainer Kit, Patch Chords.

PROCEDURE:
 Verify the gates.
 Make the connections as per the circuit diagram.
 Switch on VCC and apply various combinations of input
according to the truth table.
,
TRUTH TABLES:
1. Truth Table of Half Adder

INPUTS OUTPUTS
A B Sum (s) Carry(c)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
CIRCUIT DIAGRAMS:

1. Half Adder by using basic gates:

2. Half Adder by using NAND gates only:

CIRCUIT DIAGRAMS:

i. Truth Table of Full Adder

INPUTS OUTPUTS
A B C Sum(S) Carry(Cin)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
(ii). Full Adder by using basic gates:
(ii). Full Adder by using NAND gates only:

RESULT:
(B) HALFSUBTRACTOR AND FULL SUBTRACTOR
USING NAND GATES.
(C) AIM:

 To Realize Half Subtractor and Full Subtractor by using

I. Nand Gate
APPARATUS REQUIRED:
 IC 7486, IC 7432, IC 7408, IC 7400
PROCEDURE:
 Verify the gates.
 Make the connections as per the circuit diagram.
 Switch on VCC and apply various combinations of input
according to the truthtable.

Truth Table of Half Subtractor

INPUTS OUTPUTS
A B Difference( Borrow(Br)
D)
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
CIRCUIT DIAGRAMS:
1. Half Subtractor by using NAND gates only:

(C) - 4 VARIABLE FUNCTION USING IC 74151(8:1 MUX).

AIM:
 To REALIIZE 4-VARIABLE FUNCTION USING IC 74151(8:1 MUX)..
APPARATUS REQUIRED:
IC 74151, IC 7404, patch Cords , IC trainer kit, power supply.

PIN DIAGRAM;

(i)Implement the following Boolean

function using 8:1 multiplexer, F(A, B, C,
D)= ∑m (0,2,3,6,8,9,13,14).
TRUTH TABLE
A B C D Y
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 1
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0

DESIGN TABLE AND CIRCUIT DIAGRAM:

PROCEDURE REQUIRED:

1. Connections are made as per the circuit diagram

2. Switch on the power supply
3. Apply different combinations of inputs and observe
the outputs; compare the outputs with the truth tables.

EXERCISE: Obtain the expressions for MULTIPLEXER by

using K-map method

RESULT:
VIVA QUESTIONS:

Define Multiplexer
Define 4:1 and 8:1 Multiplexer
Implement the 4:1Mux by using only NAND gate
Implement 8:1 by using two 4:1 Mux.
Expirement - 6
REALIZE
(i) BINARY TO GRAY CODE CONVERSION AND VICE-VERSA.

AIM:
To REALIZE BINARY TO GRAY CODE CONVERSION AND VICE-VERSA.

APPARATUS REQUIRED:
IC7486,IC7400

PROCEDURE:
The circuit connections are made as shown in
fig. Pin (14) is connected to +Vcc and Pin (7) to
ground.
In the case of binary to gray conversion, the inputs B0, B1,
B2 and B3 are given at respective pins and outputs G0, G1, G2,
and G3 are taken for all the 16 combinations of the input.
In the case of gray to binary conversion, the inputs G0,
G1, G2 and G3 are given at respective pins and outputs B0,
B1, B2, and B3 are taken for all the 16 combinations of
inputs.
The values of the outputs are tabulated
Truth Table for Binary to Gray Code Conversion:

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

CIRCUIT DIAGRAM:

Binary to Gray code Conversion by using Basic Gates

Binary to Gray code Conversion by using Nand Gates

Truth Table for Gray to Binary Code Conversion:

G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1
Gray to Binary code Conversion by using Basic Gates

Gray to Binary code Conversion by using Nand Gates

EXERCISE:

Obtain the Expressions for Binary to Gray by using K-Map Method Obtain the
Expressions for Gray to Binary by using K-Map method
RESULT:

VIVA QUESTIONS;

Define Binary Code

Define Gray Code
What are Reflected Codes? Give an example for reflected code
What is self-Complementary Code? Give an for Self
Complementary code Explain binary logic?
Represent the following Decimal number 8620 in Gray Code

(ii) BCD TO EXCESS-3 CODE CONVERSION AND

VICE-VERSA.

AIM:
 To Realize IC7483 as 4-bit BCD to Excess-3 and Excess-3
to BCD code conversion.
APPARATUS REQUIRED:
 IC 7483, IC 7404.IC7486, Trainer Kit, Patch Chords
PARALLEL ADDER:
The adders discussed in the previous section have been limited to adding single digit
binary numbers and carries. The largest sum that can be obtained using a full adder
11. Parallel adders let us add multiple digit numbers. If we place full adders in
parallel. We can add two or four digit numbers or any size desired. Figure show a
parallel adder capable of adding two, two digit binary numbers. The addend would
be input on the inputs (A2=MSD, A1=LSD), and the augends input on the B inputs
(B2=MSD, B1=LSD). For this explanation we will assume there is no input to C
(Carry from a previous circuit).
Now let’s add some two-digit numbers. To add 10 (addend) and 01 (augends) assume
there are numbers at the appropriate inputs. The addend will be 1 on A2 and 0 on A1.
The augends inputs will be 0 on B2 and 1 on B1. Working from right to left, as we do
in normal addition, let’s calculate the outputs of each full adder. With A1 at 0 and B2
at 1, the output of adder 1 will be sum (S1) of with no carry (C1). Since A2 is 1 and
B2 is 0, we have a sum (S2) of 1 with no carry (C2) from adder.

To determine the sum, read the outputs (C2, S2, and S1) from left to right. In this
case, C2=0, S2=1 and S1=1. The sum then, of 102and 012 is 0112 or 112. To add 112
and 012, assume one number is applied to A1 and A2 and the other to B1 and B2, as
shown in figure. Adder 1 produces a sum (S1) of and a carry (C2) 1. Adder 2 gives a
sum (S2).

PIN DETAILS OF IC 7483:

IC 7483

Logic Design: 4-bit BCD to Excess-3 code conversion:

Realization of BCD to Excess-3 by using IC 7483

S Input BCD Output Excess-3

No B3 B2 B1 B0 x3 x2 x1 x0

1 0000 0011
2 0001 0100
3 0010 0101
4 0011 0110
5 0100 0111
6 0101 1000
7 0110 1001
8 0111 1010
9 1000 1011
10 1001 1100
Truth table of BCD to Excess-3 by using IC 7483

Logic Design: Excess-3 code to 4-bit BCD conversion:

S Input Excess- 3 Output BCD B3

No x3 x2 x1 x0 B2 B1 B0

1 0011 0000
2 0100 0001
3 0101 0010
4 0110 0011
5 0111 0100
6 1000 0101
7 1001 0110
8 1010 0111
9 1011 1000
10 1100 1001
Truth Table of Excess-3 code to 4-bit

BCD conversion PROCEDURE:

 Verify the Logic Design.
 Make the connections as per the Logic diagram.
 Switch on VCC and apply various combinations of
input according to the truth table.

Result:

Viva Question:
Truth Table of Full Subtractor

INPUTS OUTPUTS

A B C Difference(D) Borrow(Br)

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1
(i). Full Subtractor by using basic gates:

(ii). Full Subtractor by using NAND gates only:

RESULT:
VIVA QUESTIONS:
 Define Half Subtractor
 Define full Subtractor
 implement the full Subtractor by using only NAND gate
 Implement full Subtractor by using two Half Subtractor
Experiment 7
REALIZE THE FOLLOWING FLIP-FLOPS USING NAND GATES:

i) Master-Slave JK, ii) D Flip-flop, iii) T Flip-Flop.

AIM:

Truth Table verification of Flip-Flops:

 Master Slave JK Flip Flop

 D-Flip Flop
 T- Flip Flop
APPARATUS REQUIRED:

 IC 7410, IC 7400.
CIRCUIT DIAGRAM: Symbol

MASTER-SLAVE JK USING NAND GATE:

D FLIPFLOP:

SYMBOL AND TRUTH TABLE

CIRCUIT DIAGRAM:

T FLIPFLOP:

SYMBOL AND TRUTH TABLE

18ECL38-Digital System Design Lab Manual

CIRCUIT DIAGRAM:

PROCEDURE REQUIRED:

1 Connections are made as per the circuit diagram

2 Switch on the power supply
3 Apply different combinations of inputs and observe the outputs;
compare the outputs with the truth tables.

RESULT:

VIVA QUESTIONS;

 Define flip- flop

 Give an example of one Bit Memory Cell?
 Explain the working of one bit memory Cell
 What are the functions of Preset and clear in a Flip-Flop
 What are asynchronous inputs in a flip flop?
 Define timing diagram in a Flip Flop
 Define Characteristic Equation?
 write the Characteristic Equation of SR,JK, T,D Flip Flop
 What do S-R, T, and D in the flip Flop stand for?
 What is an edge Triggered flip flop?
 How many different kinds of Edge trigger flip flop are there. Explain
 What are the applications of Flip Flops?
 Where are they used?
 Explain any one application of flip flop
EXPERIMENT NO 8:

REALIZE THE FOLLOWING SHIFT REGISTER USING IC7474 a) SIPO

b) SISO c) PISO d) PIPO.

AIM:

 To Realize the following operations by using IC 7495 SIPO, SISO,

PIPO, PISO.
APPARATUS REQIURED:

THEORY:

The binary information (data) in a register can be moved within or into or out of the register
upon application of clock pulses. This type of bit movement or shifting is essential for certain
arithmetic and logic operations used in microprocessors. This gives rise to group of registers called
shift registers. They are very important in applications involving the storage and transfer of data in
a digital system. The four types of shift registers are as follows:

Serial In Serial Out [SISO]:

In this type of register, the output of one flip-flop is connected to the input of the next flip-
flop. Output of the register is obtained from the last flip-flop. Depending on the direction of the
input given shifting takes place in this. Bit by bit loading is done with every clock pulse and shifting
takes place with every clock pulse.

Serial In Parallel Out [SIPO]:

This is similar to SISO except that the output is taken from each flip- flop. Thereby the
shifted value is shown at once.
 Parallel In Parallel Out [PIPO]:

Upon giving clock pulse, data is loaded in parallel in all flip-flops.

Output is taken from each of the flip-flop.

Parallel in Serial out [PISO]:

Here we use a control input Load/ (Shift)’ such that if Load/ (Shift)’
= 1, data is loaded in all flip-flops in parallel and when the Load/ (Shift)’ = 0, data is shifted with
every clock pulse. Output is obtained from the last flip-flop.

IC 7474 consists of two D flip-flops with PRESET & CLEAR. The pin diagram is as
shown in figure.

PROCEDURE:

1. Test all the ICs manually/ using IC tester.

2. Connect VCC and the ground.
3. Connect the appropriate pins to the input and output LEDs and switches.
4. Verify the truth table with respect to the clock.

CIRCUIT DIAGRAM: PIN

DETAILS OF IC7474:
 RESULT:

All the shift register operations using IC 7474 is verified.

VIVA QUESTIONS:

 Define Shift Register?

 What are the applications of Shift Register?
 define transition table
 Define present state and next state.
 REALIZE THE RING COUNTER AND JOHNSON COUNTER USING IC7495

AIM:

 To realize the ring counter and Johnson counter using IC7495

COMPONENTS REQUIRED:

 Digital IC trainer kit, IC 7495

PROCEDURE:
 Check all the components for their working.
 Insert the appropriate IC into the IC base.
 Make connections as shown in the circuit diagram.
 Apply clock to pin number 9 and observe the output.

THEORY

Ring counter is a basic register with direct feedback such that the contents of the register simply
circulate around the register when the clock is running. Here the last output that is QD in a shift
register is connected back to the serial input. A basic ring counter can be slightly modified to
produce another type of shift register counter called Johnson counter. Here complement of last
output is connected back to the not gate input and not gate output is connected back to serial
input. A four bit Johnson counter gives 8 state output.
As it can be seen from the truth table there are four unique output stages for this
counter. The modulus value of a ring counter is n, where n is the number of flip flops.
Ring counter is called divided by N counter where N is the number of FF.

Johnson counter (Twisted ring counter)

The modulus value of a ring counter can be doubled by making a small change in the
ring counter circuit. The Q’ and Q of the last FFS are connected to the J and K input of
the first FF respectively. This is the Johnson counter
RESULT:

The truth table & working of Ring and Johnson counters is verified
using IC7495.

VIVA QUESTIONS:

 Design a ring counter using D flip flop

 Design a Johnson counter using D flip flop
 Design a ring counter/Johnson counter with mode control using JK
flip flop
Experiment 11
REALIZE AND DESIGN MOD-N SYNCHRONOUS UP COUNTER AND
DOWN COUNTER USING IC7476 JK FLIP FLOP

AIM:

 To realize the Mod-n synchronous up-counter and down-counter

COMPONENTS REQUIRED:

 Digital IC trainer kit, IC 7476

Truth table for Mod 8 Synchronous up counter

MOD 8 synchronous down counter

Truth table for Mod 8 Synchronous down counter

Count Q Q Q0
er 2 1
state
7 1 1 1
6 1 1 0
5 1 0 1
4 1 0 0
3 0 1 1
2 0 1 0
1 0 0 1
0 0 0 0

PIN DETAILS OF IC7476:

Result: Mod 8 synchronous up and down counters using 7476 has been realized
and verified.
REALIZE MOD-N COUNTER USING IC7490/7476.

AIM: Design and Implement the mod N counter by using IC7490/IC7476

COMPONENTS REQUIRED: IC7490, Patch cords, trainer kit.

FOR IC7476:

 Connections are made as shown in the circuit diagram.

 Switch ON the power supply of IC trainer
 Keep Pr, Cr, J, K inputs in the respective logic levels as shown in
the circuit diagram
 Apply clock pulses and verify the truth table
 Apply a continuous clock (Square waveform) of frequency f=1 KHz
and 10 KHz and observe the output waveform at Q0, Q1, Q2, w.r.t
the clock input on the CRO

REALIZATION OF COUNTER BY USING IC

7490: LOGIC DIAGRAM OF IC7490:

NOTE:

 MR1 and MR2 are reset inputs

 MS1 and MS2 are set inputs
MODE SELECTION TABLE

PIN DETAILS OF IC7490

TRUTH TABLE FOR DECADE COUNTER BY USING IC7490

CLK Q3 Q2 Q1 Q0

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 0 0 0 0
 CIRCUIT DIAGRAM FOR IC7490:

MOD N COUNTER BY USING IC 7490(N=5)

DECODING LOGIC

LOGIC DIAGRAM
 TRUTH TABLE FOR N=5 COUNTER BY USING IC7490

CLK Q3 Q2 Q1 Q0

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 1

COUNTER BY USING IC
7476: PIN DETAILS OF
IC7476:

SYNCHRONOUS COUNTER BY USING 7476:

EXERCISE:

 Obtain the truth table, state table, excitation table and hence obtain
the expressions forthe 3-Bit counter by using K-MAP method

RESULT:

VIVA QUESTIONS;

 Define Counter?
 What is Binary ripple Counter?
 What are synchronous counters?
 What are Asynchronous counter?
 Differentiate Between synchronous and Asynchronous counter
 What are the applications of Counters?
 What are the functions of MR1, MR2, MS1 and MS2 in IC7490?
 What are clocked flip flop?
 Define Excitation table?
 Define State table?
 Obtain the excitation table for JK Flip Flop , T- Flip Flop,D-Filp Flop
 What are the functions of load and clear?
REALIZE SYNCHRONOUS COUNTER USING IC 74192.

AIM: To design and test Synchronous counter using IC 74192 for the given
sequence.

COMPONENTS REQUIRED: IC 74192, Trainer kit, Patch chords.

Function Table

PROCEDURE:

 Check all the components for their working.

 Insert the appropriate IC into the IC base.
 Make connections as shown in the circuit diagram.
 Verify the Truth Table and observe the outputs.

RESULT:
Synchronous Counter is realized.

VIVA Questions
 1.Differentiate between Asynchronous & Synchronous Counters
 2.What are the applications of a Counter?
 3.Explain the different types of Counters.
EXPERIMENT 12:

DESIGN PSEUDO RANDOM SEQUENCE GENERATOR USING 7495.

AIM: DESIGN PSEUDO RANDOM SEQUENCE GENERATOR USING 7495.

COMPONENTS REQUIRED: IC 7495, IC Trainer Kit, Patch Cords.

PROCEDURE:
 Check all the components for their working.
 Insert the appropriate IC into the IC base.
 Make connections as shown in the circuit diagram.
 Verify the Truth Table and observe the outputs.

RESULT:

Pseudo Random Sequence generator is verified.