Received December 7, 2019, accepted December 16, 2019, date of publication December 19, 2019,

date of current version December 31, 2019.

Digital Object Identifier 10.1109/ACCESS.2019.2960839

A High Throughput Implementation

of QC-LDPC Codes for 5G NR
HAO WU 1,2 , (Member, IEEE), AND HUAYONG WANG 3
1 Department of Wireless Product Research and Design Institute, ZTE Corporation, Shenzhen 518055, China
2 State Key Laboratory of Mobile Network and Mobile Multimedia Technology, ZTE Corporation, Shenzhen 518055, China
3 Microelectronics Research Institute, ZTE Corporation, Shenzhen 518055, China

Corresponding author: Hao Wu (wu.hao19@zte.com.cn)

ABSTRACT Quasi-cyclic low-density parity-check (QC-LDPC) codes are the choice for data channels in
the fifth generation (5G) new radio (NR). At the transmitter side, code bits from the QC-LDPC encoder
are delivered to the rate matcher. The task of the rate matcher is to select an appropriate number of code
bits via puncturing and/or repetition. Code bits that are not selected do not need to be encoded. At the
receiver side, the de-rate matcher combines code bits of different transmission attempts and sends them to
the QC-LDPC decoder. The output of the QC-LDPC decoder only needs to include necessary systematic
bits. Unnecessary systematic bits and parity bits can be completely removed from the decoding process.
Taking these considerations into account, a smaller sub-base matrix instead of a full-base matrix can be used
in the encoding and decoding process. In this paper, we propose an efficient implementation of QC-LDPC
codes for 5G NR. The full-base matrix is pruned before being used. Compared to the traditional schemes,
the proposed scheme improves the throughput of QC-LDPC codes in 5G NR.

INDEX TERMS 5G NR, QC-LDPC, encoder, decoder, base matrix.

I. INTRODUCTION In 5G NR, the physical downlink shared channel (PDSCH)

Fifth generation (5G) new radio (NR) is the next gen-
eration of mobile networks beyond the fourth generation
(4G) long term evolution (LTE) [1], [2]. 5G NR sup-
ports three scenarios: enhanced mobile broadband (eMBB),
ultra-reliable and low-latency communications (uRLLC) and
massive machine type communications (mMTC). These three
scenarios have requirements that include low latency and
high throughput [3]. The peak throughput requirement is
10 Gbps for uplink and 20 Gbps for downlink. The user
plane latency requirement is 4ms for eMBB and 1ms for
uRLLC. The control plane latency requirement is 20ms. Tak-
ing these requirements into consideration, quasi-cyclic low-
density parity-check (QC-LDPC) codes are adopted by the
5G NR standard for data channels [4], [5]. To simplify the
implementation, QC-LDPC codes have the core part with a
dual-diagonal structure and the extension part with a diagonal
structure. Two base matrices, BG1 and BG2, are defined
to guarantee the decoding performance for full ranges of
transport block sizes and code rates. For BG1, the mother
code rate is 1/3. For BG2, the mother code rate is 1/5.
The associate editor coordinating the review of this manuscript and
approving it for publication was Martin Reisslein . bits and parity bits can be completely removed from the
and the physical uplink shared channel (PUSCH) are used
for unicast data transmissions. The data from the medium
access control layer to the physical layer is organized in the
form of the transport block. Fig. 1 illustrates the processing
of the transport block in 5G NR [6]. At the transmitter side,
the following steps are carried out for a transport block: cyclic
redundancy check (CRC) attachment, code block segmenta-
tion, QC-LDPC encoding, rate matching, bit interleaving and
code block concatenation. The task of the rate matcher is to
select an appropriate number of code bits from the output
of the QC-LDPC encoder via puncturing and/or repetition to
match the available radio resources. The redundancy version
determines the exact set of code bits to be selected. As a
consequence, code bits that are not selected do not need to
be encoded. At the receiver side, the following steps are
carried out for a transport block: code block segmentation,
bit de-interleaving, de-rate matching, QC-LDPC decoding,
code block concatenation, transport block CRC check. The
de-rate matcher combines code bits of different transmission
attempts and sends them to the QC-LDPC decoder. The out-
put of the QC-LDPC decoder only needs to include necessary
systematic bits. As a consequence, unnecessary systematic

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 H. Wu, H. Wang: High Throughput Implementation of QC-LDPC Codes for 5G NR
FIGURE 1. The processing of the transport block in 5G NR.
decoding process. Taking these considerations into account,
a smaller sub-base matrix instead of a full-base matrix can be
used in the encoding and decoding process.
The architectures of the QC-LDPC encoder include:
dual-diagonal [7]–[10], Richardson-Urbanke [11]–[13],
LU decomposition [14], [15], etc. In 5G NR, the dual-
diagonal architecture is usually used to reduce the com-
plexity of the encoder. The throughput of the dual-diagonal
architecture is approximately inverse proportional to the
row number of the base matrix. The architectures of the
QC-LDPC decoder include: block parallel [16]–[18], row
parallel [19], [20], full parallel [21], [22], etc. [23]. In 5G
NR, the block parallel architecture is usually used to reduce
the complexity of the decoder. The throughput of the block
parallel architecture is approximately inverse proportional
to the number of circulant blocks in the base matrix. As a
consequence, the throughput of QC-LDPC codes can be
improved by using a smaller sub-base matrix instead of a
full-base matrix.
Reference [24] only describes the encoding procedure for
QC-LDPC codes in 5G NR. The scheme of constructing
the sub-base matrix is not described. Reference [7] uses the
full-base matrix in the encoding process. It is a waste of
resources for the transmitter to encode unnecessary code bits.
The sub-base matrix constructed in references [25]–[30] is
a leading sub-base matrix [31]. That is, the sub-base matrix
is obtained by selecting the intersection of the first i rows
and the first j columns of the full-base matrix. The sub-base
matrix constructed in [25]–[30] can be further pruned to
increase the throughput.
This paper proposes an efficient implementation of
QC-LDPC codes for 5G NR. Unlike the traditional schemes,
the sub-base matrix constructed by the proposed scheme is
not restricted to the leading sub-base matrix. In addition,
the proposed scheme takes into account the difference in the
construction of the sub-base matrix between the encoder and
the decoder. Compared to the traditional schemes, the pro-
posed scheme improves the throughput of QC-LDPC codes
in 5G NR. The rest of the paper is organized as follows:
Section II describes the processing of the transport block
in 5G NR. Section III gives the scheme of constructing the
sub-base matrix for the encoder and the decoder. Section IV
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presents the architecture of the proposed scheme. Numerical
results and computational complexity are shown in Section V
and Section VI respectively. Finally, the conclusion is given
in Section VII.
II. TRANSPORT BLOCK PROCESSING IN 5G NR
In this section, we focus on the processing of the transport
block in 5G NR [6]. Let T be the transport block size.
A A-bit CRC is attached at the end of the transport block,
where A is equal to 24 if T > 3824 and 16 otherwise. The
transport block, including the CRC, is divided into C equal
size code blocks. C is equal to
(
1, T ≤ζ
C= (1)
dB/(ζ − 24)e, T > ζ
where B is equal to T + A and ζ is equal to 8448 for BG1 and
3840 for BG2. The size of each code block is equal to
K = B/C + τ (2)
where τ is equal to 0 for C = 1 and 24 otherwise. Note
that the procedure of the transport block size determination
guarantees that B is divisible by C [32].
Let R be the target code rate for the initial transmission.
BG1 is used if T > 3824 and R > 0.25 or T > 292 and
R > 0.67. Otherwise, BG2 is used. Let ω be the number of
systematic columns. For BG1, ω is equal to 22. For BG2, ω is
determined based on the value of B. That is, ω = 10 if B ∈
(640, ∞); ω = 9 if B ∈ (560, 640]; ω = 8 if B ∈ (192, 560]
and ω = 6 otherwise. The lifting size Z is equal to
Z = min{η : η ∈ 8, η ≥ B/ω} (3)
where 8 is the set of supported lifting size. 8 includes all
values of the form j × 2i for j ∈ {2, 3, 5, 7, 9, 11, 13, 15}
and i ∈ {0, 1, 2, 3, 4, 5, 6, 7} that range from 2 to 384.
8 is categorized into eight sets according to j. There is an
exponent matrix Pj associated with j for each base matrix.
We assume that Z can be expressed as m × 2n . The full-base
matrix Pm is pruned to the sub-base matrix P0m . The detail
of the pruning is described in Section III. The parity check
matrix H is constructed by lifting the sub-base matrix P0m .
That is, each non-negative element of P0m is replaced by a
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H. Wu, H. Wang: High Throughput Implementation of QC-LDPC Codes for 5G NR

TABLE 1. The value of TLBRM as a function of LM , QM and PM .

Z × Z permutation matrix and each negative element of P0m Let d = [d0 , d1 , . . . , dN −1 ] be the circular buffer. The initial
is replaced by a Z × Z zero matrix. If the size of the sub-base values of the circular buffer are nulls. After writing the code-
matrix P0m is R × C, the size of the parity check matrix H is word c into the circular buffer, the values of d are as follows
RZ × CZ . The task of the encoding is to find a codeword c
s2Z +i , 0 ≤ i < K − 2Z


that satisfies the following equation
K − 2Z ≤ i < ξ

null,
di = (9)
HcT = 0T (4) pi−ξ , ξ ≤ i < β


β≤i<N

null,
where (·)T denotes the transpose of the enclosed vector. Let
the codeword c be where β = min(N , ξ + RZ ) and ξ is equal to 20Z for
BG1 and 8Z for BG2. Then code bits e = [e0 , e1 , . . . , eE−1 ]
c = [s0 , s1 , . . . , sC Z −RZ −1 , p0 , p1 , . . . , pRZ −1 ] (5) are read out from the starting position k in the circular buffer,
skipping the code bit with a value of null. k is a function of
where s = [s0 , s1 , . . . , sC Z −RZ −1 ] is the systematic bits and the redundancy version rv and is given by Table 2.
p = [p0 , p1 , . . . , pRZ −1 ] is the parity bits. c is written into
a circular buffer of length N . To reduce the complexity of TABLE 2. The value of k as a function of the redundancy version rv .
the implementation, the limit buffer rate matching (LBRM)
is introduced in 5G NR. If LBRM is disable, N is equal to 3,
where 3 is equal to 66Z for BG1 and 50Z for BG2. If LBRM
is enable, N is equal to
1 TLBRM
N = min(3, b c) (6)
C RLBRM
where RLBRM = 2/3. TLBRM is a function of the maxi-
mum number of layers LM , the maximum modulation order
QM and the maximum number of physical resource blocks
PM [6], [32]. The values of TLBRM are listed in Table 1.
LBRM is usually enable to reduce the size of the circular
buffer and increase the throughput of the QC-LDPC codes. Next, bit interleaving is carried out with a row-column
Let G be the number of code bits available for transmission interleaver. The number of rows is equal to the modulation
of the transport block. Let L be the number of layers. Let Q order. Code bits of each code block are written row-by-
be the modulation order. If code block groups (CBGs) are row into the interleaver and read out column-by-column.
not supported, the rate matching output length E of the first This increases the reliability of systematic bits and improves
C − mod(G/(LQ), C) code blocks is equal to the performance of QC-LDPC codes [2], [33]. Let f =
[f0 , f1 , . . . , fE−1 ] be the output of the interleaver. e and f are
G
Em = LQb c (7) related by
LQC
fi+jQ = eiE/Q+j (10)
and that of the last mod(G/(LQ), C) code blocks is equal to
where i ∈ {0, 1, . . . , Q − 1} and j ∈ {0, 1, . . . , E/Q − 1}.
G Finally, code block concatenation collects the output of the
Ep = LQd e (8)
LQC rate matching.

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III. THE SCHEME OF CONSTRUCTING THE As a result, parity bits should consist of [p0 , p1 , . . . , pδ−1 ],
SUB-BASE MATRIX where δ is equal to
In this section, we give the scheme of constructing the
sub-base matrix for the encoder and the decoder. Before delv- δ = min(Np , N − ξ ) (13)
ing into the details, let us explore the general structure of the If Np is larger than N − ξ , the selection of code bits wraps
base matrix. The structure of BG2 is illustrated in Fig. 2. The around to the beginning of the circular buffer.
structure of BG1 is similar. The base matrix consists of five Now, let us not restrict the value of k. That is, the starting
submatrices: A, C, B, I and O. A and C are non-zero matrices. point of the selection may be anywhere of the circular buffer.
B has a dual-diagonal structure. I is an identity matrix. O is The number of systematic bits to be selected is
a zero matrix. A and B constitute the core part. C, I and
O constitute the extension part. This structure is similar to Ns = max(K − 2Z − k, 0) (14)
QC-LDPC codes introduced in [34]. The core part can not be
and the number of parity bits to be selected is
pruned [4]. The first two columns of the base matrix are not
transmitted. This procedure improves the performance of the Np = E − max(K − 2Z − k, 0) (15)
decoding [35]. The rows of C are designed to be orthogonal or
quasi-orthogonal. Since the layered decoding is widely used If k < ξ , the starting point of the selection is in the middle of
in QC-LDPC codes [36], [37], this design reduces the decod- the systematic bits. If k ≥ ξ , the starting point of the selection
ing latency and improves the system throughput [38], [39]. is in the middle of the parity bits. Let λ = N −k +K −2Z −θ,
where

0,
 k≥ξ
θ = ξ − k, K − 2Z ≤ k < ξ (16)
ξ − (K − 2Z ), 0 ≤ k < K − 2Z



The ending point of the selection in the circular buffer is sK −1

when E is equal to λ. If E ≤ λ, parity bits should consist of
[pδs , pδs +1 , . . . , pδe −1 ], where δs is equal to
δs = max(0, k − ξ ) (17)
and δe is equal to
δe = min(Np + δs , N − ξ ) (18)
If E > λ, parity bits should consist of [pδs0 , pδs0 +1 , . . . ,
FIGURE 2. The general structure of the base matrix. pN −ξ −1 ] and [p0 , p1 . . . , pδe0 −1 ], where δs0 is equal to
δs0 = max(0, k − ξ ) (19)
A. CONSTRUCTION OF THE SUB-BASE MATRIX
FOR THE ENCODER and δe0 is equal to
The output of the QC-LDPC encoder should consist of
δe0 = min(E − λ, δs0 ) (20)
[s0 , s1 , . . . , sK −1 ] and some parity bits. In the following,
we derive the parity bits that need to be included. In order to The size of the systematic bits is at most (ξ + 2)Z . The
gain some insight, let us first focus on the case where k = 0. last (ξ + 2)Z − K systematic bits are filler bits and are not
That is, the starting point of the selection is at the beginning transmitted over the air. Since filler bits are set to zeros,
of the circular buffer. Since the first 2Z systematic bits are the values of parity bits are not affected by the last (ξ + 2)Z −
punctured, the number of systematic bits to be selected is K systematic bits. As a result, the columns corresponding to
these systematic bits can be pruned.
Ns = K − 2Z (11)
If the full-base matrix Pm is pruned to a sub-base
and the number of parity bits to be selected is matrix P0m , Pm and P0m are related by
Np = E − (K − 2Z ) (12) P0m = Pm (µ, ν) (21)


δ δ δ −1
[b s c, b s c + 1, . . . , b e E ≤λ

 c] ∪ [0, 1, 2, 3],
µ= Z Z Z (22)
[b δs c, b δs c + 1, . . . , b N − ξ − 1 c] ∪ [0, 1, . . . , max(3, b δe − 1 c)], E > λ
 0 0 0

Z Z Z Z

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H. Wu, H. Wang: High Throughput Implementation of QC-LDPC Codes for 5G NR
FIGURE 3. The construction of the sub-base matrix for the encoder. P02 is
obtained by selecting the intersection of the rows [0, 1, . . . , 5] and the
columns [0, 1, . . . , 5, 10, 11, . . . , 15] of P2 . Here rv = 0, T = 80, G = 160
and TLBRM = 1277992.
FIGURE 4. The construction of the sub-base matrix for the encoder. P02 is
obtained by selecting the intersection of the rows [0, 1, . . . , 3, 17, 18,
. . . , 26] and the columns [0, 1, . . . , 5, 10, 11, . . . , 13, 27, 28, . . . , 36]
of P2 . Here rv = 2, T = 80, G = 160 and TLBRM = 1277992.
where µ is give by (22), as shown at the bottom of the
previous page, and ν is equal to
K −1 ξ
ν = [0, 1, . . . , bc, µ + 2 + ] (23)
Z Z
The symbol ∪ means the union of two vectors [40]. The
expression (21) means that P0m is obtained by selecting the
intersection of the rows µ and the columns ν of Pm . Note that
B can not be pruned.
Two examples of constructing the sub-base matrix for the
encoder are shown in Fig. 3 and Fig. 4. From these figures,
we see that P0m is only a small portion of Pm . Code bits
that are not selected are not encoded. The throughput of the
QC-LDPC encoder is expected to be increased.
B. CONSTRUCTION OF THE SUB-BASE MATRIX
FOR THE DECODER
Hybrid automatic repeat request (HARQ) is widely used to
improve the transmission efficiency [41]–[43]. Log likeli-
hood ratios (LLRs) of the transport block received in error
are stored in a buffer. The receiver generates the positive
acknowledgement or the negative acknowledgement to drive
the retransmission. When the retransmission is received,
the decoding is performed by the buffered LLRs combined
with the retransmission LLRs. As a result, the sub-base
VOLUME 7, 2019
FIGURE 5. The construction of the sub-base matrix for the decoder. P00 2
is
obtained by selecting the intersection of the rows [0, 1, . . . , 5] and the
columns [0, 1, . . . , 5, 10, 11, . . . , 15] of P2 . Here rv = 0, T = 80, G = 160
and TLBRM = 1277992.
FIGURE 6. The construction of the sub-base matrix for the decoder. P00 2
is
obtained by selecting the intersection of the rows [0, 1, . . . , 5, 17, 18, . . . ,
26] and the columns [0, 1, . . . , 5, 10, 11, . . . , 15, 27, 28, . . . , 36] of P2 .
Here rv = 2, T = 80, G = 160 and TLBRM = 1277992.
matrix used in the last transmission should be considered
when constructing the sub-base matrix in the retransmission.
Let µ0 equals to ∅ for the initial transmission and the
selected rows in the last transmission for the retransmission.
Let ν 0 equals to ∅ for the initial transmission and the selected
columns in the last transmission for the retransmission. If the
full-base matrix Pm is pruned to a sub-base matrix P00m ,
Pm and P00m are related by
P00m = Pm (µ ∪ µ0 , ν ∪ ν 0 ) (24)
where µ and ν are given in the preceding subsection.
Two examples of constructing the sub-base matrix for the
decoder are shown in Fig. 5 and Fig. 6. From these figures,
we see that P00m is only a small portion of Pm . Unnecessary
systematic bits and parity bits are removed from the decod-
ing process. The throughput of the QC-LDPC decoder is
expected to be increased. In the initial transmission, the sizes
of sub-base matrices of the encoder and decoder are the same.
In the retransmission, the sizes of the sub-base matrix of the
decoder is larger than that of the encoder.
IV. THE ARCHITECTURE OF THE PROPOSED SCHEME
In this section, the architecture of the proposed scheme is
described. In the processing of the transport block, we need to
know the lifting size, the size of the circular buffer, the type
of the base matrix, etc. These parameters are derived from
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 H. Wu, H. Wang: High Throughput Implementation of QC-LDPC Codes for 5G NR

FIGURE 7. The proposed architecture of the encoder.

the scheduling information [2], [6]. However, this deriva- There are many dual-diagonal encoder architectures that
tion is not appropriate to be done in the hardware. Usu- offer a variety of parallelism orders [7]–[10]. The architec-
ally, these parameters are calculated by the software and ture with the high parallelism provides the high throughput.
then are passed to the hardware through the configura- However, this benefit comes at the cost of increased area.
tion [17], [29], [30], [44], [45]. Based on this configuration, The architecture supports various base matrices specified by
the control signals are generate by the controller. The size the protocol [6], [46], [47]. The controller of the architec-
†
of the configuration needs to be small as possible to reduce ture obtains the particular base matrix Pm used for encoding
the memory. It is clear that the configuration includes the through the configuration and then generates the control sig-
following fields: E, K , N , Z , the type of the base matrix, etc. †
nals based on Pm , Z , etc. Then the codeword c is produced
Compared to the traditional schemes, the proposed scheme under the control of these signals. The existing architectures
mainly affects the QC-LDPC encoding module at the trans- can easily support the proposed scheme by modifying the
mitter and the QC-LDPC decoding module at the receiver. For configuration and the controller. That is, b† that indicates
the sake of brevity, we only focus on these modules in this the sub-base matrix P0m is added to the configuration and the
section. logic that generates the sub-base matrix P0m is added to the
controller. Compared to the overall area of the architecture,
A. ARCHITECTURE OF THE ENCODER the area of the logic is negligible. Since the logic that gen-
Before giving the proposed architecture, the number of bits erates the sub-base matrix P0m is not on the critical path, this
needed to indicate the sub-base matrix P0m is derived. These modification does not affect the operating frequency of the
bits should be added to the configuration. In the following, architecture.
we show that 13 bits are needed to indicate the sub-base For example, one proposed architecture is shown in Fig. 7.
† † † †
matrix P0m . Let b† = [b0 , b1 , b2 ], where b0 is equal to 1 if The difference between the proposed architecture and the
†
E is smaller than or equal to λ and 0 otherwise, b1 is equal to reference architecture [7] is in the configuration and the
 controller, which are marked in red in the figure. The area of
δ this architecture can be reduced by using few cyclic shifts at
b s c, b† = 1


† Z 0 the expense of lower throughput. The proposed architecture
b1 = (25)
b δs c, b† = 0
0

 is briefly discussed as follows. First, the intermediate variable
Z 0 t is obtained by accumulating the cyclic shifts of the the
† systematic bits s in 4 clock cycles. t is stored in the core
and b2 is equal to unit and s is stored in the systematic buffer. In the following,
p0 = [p0 , p1 , . . . , p4Z −1 ] is generated by the core unit in 2

δ −1 †
b e

c, b0 = 1 clock cycles. p0 is stored in the parity buffer 1. Finally,

† Z
b2 = (26) p00 = [p4Z , p4Z +1 , . . . , pRZ −1 ] is obtained by accumulating
max(3, b δe − 1 c), b† = 0
 0
the cyclic shifts of the the systematic bits s and p0 in (R − 4)

Z 0
clock cycles. p00 are stored in parity buffer 2. The proposed
† † † scheme needs a total of (R + 2) clock cycles.
b0 , b1 and b2 can be represented by 1bit, 6bits and 6bits
respectively. From (22), we see that µ can be easily obtained
from the fields already exist in the configuration and b† . B. ARCHITECTURES OF THE DECODER
From (23), we see that ν can be easily obtained from the fields Before giving the proposed architecture, the number of bits
already exist in the configuration and µ. As a result, only b† needed to indicate the sub-base matrix P00m is derived. These
needs to be added to the configuration to indicate the sub-base bits should be added to the configuration. In the following,
matrix P0m . we show that 42 bits are needed to indicate the sub-base

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H. Wu, H. Wang: High Throughput Implementation of QC-LDPC Codes for 5G NR
FIGURE 8. The proposed architecture of the decoder.
‡ ‡ ‡
matrix P00m . Let b‡ = [b0 , b1 , . . . , b41 ] be the bit masks of
length 42. The ith element of b‡ is equal to 1 if i is a member
of µ ∪ µ0 − [0, 1, 2, 3] and 0 otherwise, where the symbol −
means the difference of two vectors [48]. From (22), we see
that µ ∪ µ0 can be easily obtained from b‡ since B can not be
pruned. From (23), we see that ν ∪ ν 0 can be easily obtained
from the fields already exist in the configuration and µ ∪ µ0 .
As a result, only b‡ needs to be added to the configuration to
indicate the sub-base matrix P00m .
There are many block parallel architectures [16]–[18]. The
architecture supports various base matrices specified by the
protocol [46], [49], [50]. The controller of the architecture
‡
obtains the particular base matrix Pm used for decoding
through the configuration and then generates the control sig-
‡ are listed below. There is a total of 14 orthogonal frequency
nals based on Pm , Z , etc. Then the systematic bits s is obtained
under the control of these signals. The existing architectures
can easily support the proposed scheme by modifying the
configuration and the controller. That is, b‡ that indicates
the sub-base matrix P00m is added to the configuration and the
logic that generates the sub-base matrix P00m is added to the
controller. Compared to the overall area of the architecture,
the area of the logic is negligible. Since the logic that gen-
erates the sub-base matrix P00m is not on the critical path, this
modification does not affect the operating frequency of the
architecture.
For example, one proposed architecture is shown in Fig. 8.
The difference between the proposed architecture and the
reference architecture [17] is in the configuration and the con-
troller, which are marked in red in the figure. The proposed
architecture is briefly discussed as follows. First, the log
likelihood ratio (LLR) buffer is initialized to LLR values
of each bit and the extrinsic buffer is initialized to zeros.
Then, at each time instant, the LLR values corresponding to a
non-negative element of the sub-base matrix P00m are read from
the LLR buffer and the extrinsic information corresponding
to the same non-negative element of the sub-base matrix P00m
is read from the extrinsic buffer. The difference between the
cyclic shifted LLR values and the extrinsic information is fed
to the min-sum unit. When all non-negative elements in a row
VOLUME 7, 2019
of the sub-base matrix P00m are processed, the min-sum unit
and the adder output the updated extrinsic information and
the updated LLR values respectively. The updated extrinsic
information is written back to the extrinsic buffer. And after
passing through the de-cyclic shifter, the updated LLR values
are written back to the LLR buffer. The decoded bits can
be obtained by the hard decision on the LLR values. This
decoding process continues until the parity check passes or
the maximum number of iterations is reached.
V. NUMERICAL RESULTS
Numerical results are given in this section to compare the
throughput and the block error rate (BLER) of the traditional
schemes and the proposed scheme. The detail configurations
division multiplexing (OFDM) symbols in the slot. Demodu-
lation reference signal (DMRS) is located in the first 2 sym-
bols of the slot. Physical uplink shared channel (PUSCH)
is located in the last 12 symbols of the slot. The trans-
port block is mapped to the resource elements (REs) in a
frequency-first manner. Note that the front-loaded DMRS and
the frequency-first mapping enable the transport block to be
processed on the fly. It is not necessary to collect all the
symbols in the slot before starting the decoding the transport
block. The number of physical resource blocks is Pa . The
number of layers is 1. The transport block size T is deter-
mined according the procedure in 5.1.3.2 in [32]. The LBRM
is applied and TLBRM is equal to 1277992. Let ψ be the index
of the modulation and code scheme, which is obtained from
the Table 5.1.3.1-2 in [32]. The target code rate R and the
modulation order Q are derived from ψ. The sequence of
redundancy versions is 0, 2, 3, 1. The parameters of the initial
transmission and the retransmission are the same except for
the redundancy version.
A. THROUGHPUT PERFORMANCE
In this subsection, the throughput of the proposed scheme and
the traditional schemes are compared. In 5G NR, the through-
put is usually defined as the number of systematic bits
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 H. Wu, H. Wang: High Throughput Implementation of QC-LDPC Codes for 5G NR
p
FIGURE 9. dt /dtf and dtl /dtf as a function of ψ for different Pa . The
redundancy version is equal to 0.
p
FIGURE 10. dt /dtf and dtl /dtf as a function of ψ for different Pa .
The redundancy version is equal to 2.
(excluding filler bits) that the system can process within
a specified time [51], [52]. This definition is used in this
subsection.
1) DECODER
The pipeline block parallel architecture is usually used to
reduce the complexity of the decoder. The pipeline stall due to
the pipeline hazard can be kept to a minimum level [53], [54].
If one circulant block in the sub-base matrix needs one clock
cycle for processing, the decoding throughput dt is approxi-
mately equal to
fd
dt = K (27)
id u d
where fd is the operating frequency for the decoder, id is the
number of iterations, ud is the number of circulant blocks in
the sub-base matrix. Note that this scheme is widely used in
evaluating the decoding throughput [52], [55].
f p
Let dt be the decoding throughput of the full-base matrix
scheme. Let dtl be the decoding throughput of the leading
p
sub-base matrix scheme. Let dt be the decoding throughput
of the proposed scheme. These three schemes mainly differ in
the logic that generates the sub-base matrix used for decod-
ing. Since this logic is not on the critical path, the operating
185380
p
FIGURE 11. dt /dtf and dtl /dtf as a function of ψ for different Pa .
The redundancy version is equal to 3.
p
FIGURE 12. dt /dtf and dtl /dtf as a function of ψ for different Pa .
The redundancy version is equal to 1.
frequencies of these three schemes are the same. Fig. 9 to
p f f
Fig. 12 illustrate dt /dt and dtl /dt as a function of ψ for
different Pa when the number of iterations for these three
schemes are the same. From these figures, we see that the
full-base matrix scheme yields the lowest decoding through-
put. The effective code rate decreases as the number of trans-
p f f
missions increases, and thus dt /dt and dtl /dt approach one
as the number of transmissions increases.
Now, we compare the leading sub-base matrix scheme and
p
the proposed scheme. In the initial transmission, dt is slightly
l
larger than dt in a few cases. The main reason is that the
proposed scheme prunes the systematic bits but the leading
p
sub-base matrix scheme does not. For example, dt gets up
to a 1.05 fold improvement as compared to dt when ψ is
l
p
equal to 27 and Pa is equal to 6. In the retransmission, dt is
l
much larger than dt in most cases. The main reason is that the
parity bits pruned by the proposed scheme is larger than the
parity bits pruned by the leading sub-base matrix scheme. For
example, dt gets up to a 1.40 fold improvement as compared
to dt when ψ is equal to 27, Pa is equal to 6 and rv is
l
equal to 2.
The gain of the proposed scheme can be clearly observed
in the retransmission. The decoder provided to implement
the peak throughput requirement may not be able to decode
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H. Wu, H. Wang: High Throughput Implementation of QC-LDPC Codes for 5G NR
p p
FIGURE 13. et /eft and elt /eft as a function of ψ for different Pa .
The redundancy version is equal to 0.
p p
FIGURE 14. et /eft and elt /eft as a function of ψ for different Pa .
The redundancy version is equal to 2.
transport blocks with the lower code rate over the same
radio resources in the same time duration [51]. The effective
code rate decreases as the number of transmissions increases.
The peak throughput requirement is difficult to meet in the
retransmission [28]. The proposed scheme can alleviate this
problem to a large extent.
2) ENCODER
We assume that the dual-diagonal architecture in the refer-
ence [7] is used to reduce the complexity of the encoder. This
architecture needs a total of (mb + 2) clock cycles to encode
the systematic bits s, where mb is the number of rows of the
sub-base matrix. Then, the encoding throughput et is equal to
fe
et = K
mb + 2
where fe is the operating frequency of the encoder.
f
Let et be the encoding throughput of the full-base matrix
scheme. Let elt be the encoding throughput of the leading
p
sub-base matrix scheme. Let et be the encoding throughput
of the proposed scheme. These three schemes mainly differ in
the logic that generates the sub-base matrix used for encod-
ing. Since this logic is not on the critical path, the operating
frequencies of these three schemes are the same. Fig. 13 to
VOLUME 7, 2019
FIGURE 15. et /dtf and elt /eft as a function of ψ for different Pa .
The redundancy version is equal to 3.
FIGURE 16. et /eft and elt /eft as a function of ψ for different Pa .
The redundancy version is equal to 1.
p f f
Fig. 16. illustrate et /et and elt /et as a function of ψ for
different Pa . From these figures, we see that the full-base
matrix scheme yields the lowest encoding throughput. The
effective code rate decreases as the number of transmissions
p f f
increases, and thus et /et and elt /et approach one as the
number of transmissions increases.
The encoding throughput comparison between the leading
sub-base matrix scheme and the proposed scheme is similar
to the decoding throughput comparison between the leading
sub-base matrix scheme and the proposed scheme. And it is
omitted for the sake of brevity.
B. BLER PERFORMANCE
In this subsection, the BLER performances of the pro-
(28) posed scheme and the traditional schemes are compared.
The parameters of the simulation are listed as follows. The
decoding algorithm is the layered normalized min-sum [56].
The scaling factor is equal to 0.85. The maximum itera-
tion number is equal to 12. ψ is equal to 27. From the
Table 5.1.3.1.-2 in [32], we can derive that R is equal to
0.9258 and Q is equal to 8. The encoded bits are transmitted
over the additive white Gaussian noise (AWGN) channel.
Based on the scheduling information, we can derive that T
is equal to 295176 and G is equal to 314496 when Pa is equal
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 H. Wu, H. Wang: High Throughput Implementation of QC-LDPC Codes for 5G NR
FIGURE 17. Comparison of the BLER performance between the proposed
scheme and the traditional schemes. Here, Pa is equal to 6.
FIGURE 18. Comparison of the BLER performance between the proposed
scheme and the traditional schemes. Here, Pa is equal to 273.
to 273 and T is equal to 6400 and G is equal to 6912 when
Pa is equal to 6.
The BLER performances of the proposed scheme and
the traditional schemes as a function of the signal-to-noise
ratio (SNR) are illustrated in Fig. 17 and Fig. 18. From
these figures, we see that the BLER performances of the
proposed scheme and the traditional schemes are almost the
same. The difference between the BLER performance of
the proposed scheme and that of the traditional schemes is
negligible. These simulation results verify the correctness of
the proposed scheme for the encoder and decoder.
VI. COMPUTATIONAL COMPLEXITY
The difference between the proposed scheme and the tradi-
tional schemes is mainly the sub-base matrix used for encod-
ing and decoding. In this section, we consider the amount of
computation required to obtain the sub-base matrix used for
encoding and decoding. It is clear that the full-base matrix
scheme can directly obtain the sub-base matrix used for
encoding and decoding. To obtain the sub-base matrix used
185382
for the encoding, the leading sub-base matrix scheme requires
up to 2 divisions, 4 comparisons and 6 additions and the
proposed scheme requires up to 5 divisions, 8 comparisons
and 17 additions. To obtain the sub-base matrix used for
the decoding, the leading sub-base matrix scheme requires
up to 2 divisions, 5 comparisons and 6 additions and the
proposed scheme requires up to 5 divisions, 8 comparisons,
17 additions and 2 union operations. Note that the amount of
computation required to obtain the sub-base matrix used for
encoding and decoding is amortized over C code blocks and
is negligible when C is large.
VII. CONCLUSION
In many applications, the code rate of the data transmission
is larger than the mother code rate. In these case, substantial
throughput improvement can be achieved by pruning the
full-base matrix of QC-LDPC codes to the desired size. In this
paper, a scheme is developed keeping in mind the difference
between the pruning of the full-base matrix for encoder and
that for the decoder. The transport block of higher code rate
is encoded and decoded by using a smaller sub-base matrix
instead of a full-base matrix. As a consequence, the compu-
tational efficiency and energy efficiency are improved. These
features make the proposed scheme attractive for QC-LDPC
codes in 5G NR.
ACKNOWLEDGMENT
This article was presented at the Proceedings of the
25th International Telecommunication Networks and Appli-
cation Conference (ITNAC), Auckland, New Zealand,
November 2019 [28].
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 H. Wu, H. Wang: High Throughput Implementation of QC-LDPC Codes for 5G NR

HAO WU received the M.S. degree in commu-
nication and information systems from Tianjin
University, in 2009. He is currently a Senior Engi-
neer with ZTE corporation, where he develops
technologies to improve the performance of wire-
less broadband communication systems. He has
authored a number of articles. He holds a number
of patents. His research interests include wireless
communication systems, digital signal processing,
and error control coding.
HUAYONG WANG received the M.S. degree in
IC design engineering from Peking University,
in 2007. He is currently a Senior Engineer with
ZTE Corporation, Shenzhen, China. His research
interests include wireless communications sys-
tems and VLSI design.

185384 VOLUME 7, 2019