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Chunghsing2021 Mid Term
Chunghsing2021 Mid Term
1
Question 7 F (b) (ii) and (iii).
X: US made atomic bombs in the 1940s.
Y : US had at least one computer in the 1940s. (c) (i) and (iii).
2
Diagram for Questions 13-18 Question 16
The following schematic diagram is for Question 13 What are the output values X and Y if A is an OR
to Question 18. It is a circuit consisting of two logic gate, B is an NAND gate and the input (from left to
gates. right) is 111?
X Y (a) X = 0, Y = 0.
(b) X = 0, Y = 1.
(c) X = 1, Y = 0.
A B
(d) X = 1, Y = 1.
Question 17
What are the output values X and Y if A is an NAND
gate and B is an NAND gate and the input (from left
Question 13 to right) is 111?
What are the output values X and Y if A is an XOR (a) X = 0, Y = 0.
gate, B is an AND gate and the input (from left to
right) is 101? (b) X = 0, Y = 1.
(a) X = 0, Y = 0. (c) X = 1, Y = 0.
(b) X = 0, Y = 1. (d) X = 1, Y = 1.
(c) X = 1, Y = 0.
Question 18
(d) X = 1, Y = 1. What are the output values X and Y if A is an OR
gate, B is an AND gate and the input (from left to
right) is 1x1? Here, ’x’ means that the second input
Question 14 is unknown.
What are the output values X and Y if A is an OR
(a) X = 0, Y = 0.
gate, B is an OR gate and the input (from left to
right) is 111? (b) X = 0, Y = 1.
(a) X = 0, Y = 0. (c) X = 1, Y = 0.
(b) X = 0, Y = 1. (d) X = 1, Y = 1.
(c) X = 1, Y = 0.
Question 19
(d) X = 1, Y = 1. Here are three different sign-magnitude fixed point
number presentation formats.
Question 15 (i) 16-bit format.
What are the output values X and Y if A is an AND
gate, B is an XOR gate and the input (from left to sxxxxx.yyyyyyyyyy
right) is 101?
(ii) 12-bit format.
(a) X = 0, Y = 0.
sxxxxx.yyyyyy
(b) X = 0, Y = 1.
(d) X = 1, Y = 1. sxxxxx.yy
3
Here, s is the sign-bit. x · · · x is the integer part and (a) 2−2 .
y · · · y is the fractional part. In term of the range
of the numbers that can be represented, from the (b) 2−3 .
longest to the shortest, which of the following is the
correct order? (c) 2−4 .
Answer:
(d) 2−5 .
(a) (i) > (ii) > (iii).
(e) None of the above.
(b) (i) > (iii) > (ii).
(c) (ii) > (i) > (iii).
Question 22
(d) (iii) > (ii) > (i).
Which of the following factor(s) will affect the pro-
(e) None of the above. cessing time of an instruction?
sxxxxx.yyyyyyyyyy Answer:
Here, s is the sign-bit. x · · · x is the integer part and (e) None of the above.
y · · · y is the fractional part. In term of precision er-
ror, from the largest to the smallest, which of the
following is the correct order? Question 23
Answer: Which of the following factor(s) will affect the in-
(a) (i) > (ii) > (iii). structions to be included in the set of instructions for
a processor?
(b) (i) > (iii) > (ii).
(i) Clock frequency of a processor.
(c) (ii) > (i) > (iii).
(d) (iii) > (ii) > (i). (ii) Architecture of a processor.
Question 21 Answer:
Suppose a number represented in the following 16-bit
sign-magnitude fix-point format. (a) (i) and (ii).
4
Question 24 (b) R1 = 0, R2 = 1.
With reference to the simple processor as shown in (c) R1 = 1, R2 = 0.
the Appendix, Figure 1, suppose that the registers
are preset as RA = 1, RB = 1, RZ = 0, R1 = (d) R1 = 1, R2 = 1.
R2 = R3 = R4 = 0. What will be the contents of
the registers RA and RB after the following micro-
instructions (S1, S2, S3 and S4) have been executed? Question 26
With reference to the simple processor as shown in
S1: S1 = S8 = 1. The control signals to other con-
the Appendix, Figure 1, suppose that the registers
nectors are set to 0. The signals to all two-way
are preset as RA = 0, RB = 1, RZ = 0, R1 =
switches are set to 00.
R2 = R3 = R4 = 0. What will be the contents of
S2: S14 = 01. S12 = S15 = 10. The control signals the registers R3 and R4 after the following micro-
to all connectors are set to 0. The signals to instructions (S1, S2, S3 and S4) have been executed?
other two-way switches are set to 00.
S1: S1 = S8 = 1. The control signals to other con-
S3: S2 = S5 = S9 = 1. The control signals to other nectors are set to 0. The signals to all two-way
connectors are set to 0. The signals to other switches are set to 00.
two-way switches are set to 00.
S2: S14 = 01. S12 = S15 = 10. The control signals
S4: S12 = 10. S14 = 01. S16 = 10. The control to all connectors are set to 0. The signals to
signals to other connectors are set to 0. The other two-way switches are set to 00.
signals to other two-way switches are set to 00.
S3: S2 = S5 = S9 = 1. The control signals to other
Answer : connectors are set to 0. The signals to other
two-way switches are set to 00.
(a) RA = 0, RB = 0.
S4: S12 = 10. S14 = 01. S16 = 10. The control
(b) RA = 0, RB = 1. signals to other connectors are set to 0. The
signals to other two-way switches are set to 00.
(c) RA = 1, RB = 0.
(d) RA = 1, RB = 1. Answer :
(a) R3 = 0, R4 = 0.
Question 25
(b) R3 = 0, R4 = 1.
With reference to the simple processor as shown in
the Appendix, Figure 1, suppose that the registers (c) R3 = 1, R4 = 0.
are preset as RA = 1, RB = 0, RZ = 0, R1 =
R2 = R3 = R4 = 0. What will be the contents of (d) R3 = 1, R4 = 1.
the registers R1 and R2 after the following micro-
instructions (S1, S2, S3 and S4) have been executed?
Question 27
S1: S1 = S8 = 1. The control signals to other con-
nectors are set to 0. The signals to all two-way With reference to the simple processor as shown in
switches are set to 00. the Appendix, Figure 1, it is assumed that the data
in the memory locations M 1 and M 2 have already
S2: S14 = 01. S12 = S15 = 10. The control signals been copied to the registers RA and RB. What will
to all connectors are set to 0. The signals to be the logical operation once the following micro-
other two-way switches are set to 00. instructions have been executed?
S3: S2 = S5 = S9 = 1. The control signals to other S1: S12 = 01 and S15 = 10. The control signals to
connectors are set to 0. The signals to other other connectors are set to 0. The signals to all
two-way switches are set to 00. two-way switches are set to 00.
S4: S12 = 10. S14 = 01. S16 = 10. The control S2: S12 = 10 and S13 = 01. The control signals to
signals to other connectors are set to 0. The other connectors are set to 0. The signals to all
signals to other two-way switches are set to 00. two-way switches are set to 00.
5
S4: S12 = 10, S14 = 01 and S16 = 10. The control (ii) 8-Step micro-program.
signals to all connectors are set to 0. The signals
to other two-way switches are set to 00. S1: S1 = S8 = 1. Other connectors and
switches are set to ’Disconnection’ mode.
S5: S13 = 10 and S15 = 01. The control signals to S2: S14 = 01 and S16 = 10. Other connec-
all connectors are set to 0. The signals to other tors and switches are set to ’Disconnection’
two-way switches are set to 00. mode.
S6: S2 = S5 = S9 = 1. The control signals to other S3: S13 = 01 and S12 = 10. Other connec-
connectors are set to 0. The signals to other tors and switches are set to ’Disconnection’
two-way switches are set to 00. mode.
S7: S12 = 10, S14 = 01 and S15 = 10. The control S4: S1 = S8 = 1. Other connectors and
signals to other connectors are set to 0. The switches are set to ’Disconnection’ mode.
signals to other two-way switches are set to 00. S5: S14 = 01 and S13 = 10. Other connec-
tors and switches are set to ’Disconnection’
What of the following instruction have been exe- mode.
cuted?
S6: S16 = 01 and S12 = 10. Other connec-
Answer : tors and switches are set to ’Disconnection’
(a) R1 = (¬RA)RB and R2 = ¬RA. mode.
S7: S4 = S7 = S11 = 1. Other connectors and
(b) R1 = RA(¬RB) and R2 = ¬RA. switches are set to ’Disconnection’ mode.
(c) R1 = (¬RA)RB and R2 = ¬RB. S8: S14 = 01 and S15 = 10. Other connec-
tors and switches are set to ’Disconnection’
(d) R1 = RA(¬RB) and R2 = ¬RB. mode.
(e) None of the above. (iii) One-step micro-program.
S1: S4 = S7 = S11 = 1. Other connectors and
Question 28 switches are set to ’Disconnection’ mode.
With reference to the simple processor as shown in
the Appendix, Figure 1, which of the following micro- Answer:
program(s) can perform the logical operation.
(a) (i) and (ii).
Z = ¬A ⊕ ¬B,
(b) (ii) and (iii).
where ¬A refers to logical NOT A.
(c) (i) and (iii).
(i) 7-Step micro-program.
(d) (i), (ii) and (iii).
S1: S1 = S8 = 1. Other connectors and
switches are set to ’Disconnection’ mode. (e) None of the above.
S2: S14 = 01 and S15 = 10. Other connec-
tors and switches are set to ’Disconnection’ Question 29
mode.
With reference to the figure as shown in Figure 2, the
S3: S13 = 01 and S12 = 10. Other connec- initial conditions of the processor is set to be follow-
tors and switches are set to ’Disconnection’ ing.
mode.
S4: S1 = S8 = 1. Other connectors and S1 = S2 = S3 = 0. S12 = S13 = S14 = 00.
switches are set to ’Disconnection’ mode.
A1 = A2 = 0. R/W = 00.
S5: S14 = 01 and S13 = 10. Other connec-
tors and switches are set to ’Disconnection’ R1 = R2 = R3 = R4 = 0.
mode. RA = 1. RB = 0. RZ = 0.
S6: S15 = 01 and S12 = 10. Other connec-
tors and switches are set to ’Disconnection’ What will be the content of RZ and R1 if the follow-
mode. ing micro-program has been executed?
S7: S4 = S7 = S11 = 1. Other connectors and S1: S1 = S2 = S3 = 1. S12 = S13 = S14 = 00.
switches are set to ’Disconnection’ mode. A1 = A2 = 0. R/W = 00.
6
S2: S1 = S2 = S3 = 0. S12 = S13 = 10. S14 = 01. Question 31
A1 = A2 = 0. R/W = 00.
With reference to the figure as shown in Figure 2, the
S3: S1 = S2 = S3 = 1. S12 = S13 = S14 = 00. initial conditions of the processor is set to be follow-
A1 = A2 = 0. R/W = 00. ing.
S1 = S2 = S3 = 0. S12 = S13 = S14 = 00.
S4: S1 = S2 = S3 = 0. S12 = S13 = 00. S14 = 01.
A1 = A2 = 0. R/W = 00.
A1 = A2 = 0. R/W = 10.
R1 = R2 = R3 = R4 = 0.
RA = 0. RB = 1. RZ = 0.
Answer :
What will be the content of R1 and R2 if the following
(a) RZ = 0, R1 = 0. micro-program has been executed?
S1: S1 = S2 = S3 = 0. S12 = 00. S13 = 01. S14 =
(b) RZ = 0, R1 = 1. 00. A1 = 0. A2 = 0. R/W = 10.
7
Question 33 MOV IB M3
MUL IA IB
What will be the content of RA and RB if the micro- MOV M4 OUT
program in Question 31, with the same initial condi-
tions, has been executed?
Answer :
Answer :
(a) 16.
(a) RA = 0, RB = 0.
(b) 21.
(b) RA = 0, RB = 1.
(c) 26.
(c) RA = 1, RB = 0.
(d) 32.
(d) RA = 1, RB = 1.
(e) None of the above.
Question 34
Question 36
Here are four memory locations, M 1, M 2, M 3 and
M 4. Refer to the artificial CPU and its commands, Here are four memory locations, M 1, M 2, M 3 and
what will be the content of M 4 if the following com- M 4. Refer to the artificial CPU and its commands,
mands are executed? what will be the contents of the registers IB and
OU T if the following commands are executed?
DEF M1 3
DEF M2 5 DEF M1 3
DEF M3 2 DEF M2 5
DEF M3 2
MOV IA M1
MOV IB M2 MOV IA M1
ADD IA IB MOV IB M2
MOV IA OUT ADD IA IB
MOV IB M3 MOV IA OUT
MUL IA IB MOV IB M3
MOV M4 OUT ADD IA IB
MOV M4 OUT
Answer :
Answer :
(a) 16.
(a) IB = 0 and OU T = 0.
(b) 21.
(b) IB = 2 and OU T = 0.
(c) 25.
(c) IB = 0 and OU T = 10.
(d) 30.
(d) IB = 2 and OU T = 10.
(e) None of the above.
(e) None of the above.
Question 35
Question 37
Here are four memory locations, M 1, M 2, M 3 and
M 4. Refer to the artificial CPU and its commands, What will be the content of M 4 if the following pro-
what will be the content of M 4 if the following com- gram segment is executed?
mands are executed?
DEF M1 16
DEF M1 3 DEF M2 22
DEF M2 5 DEF M3 10
DEF M3 2
MOV IA M1
MOV IA M1 MOV IB M2
MOV IB M2 CMP IA IB
ADD IA IB MOV M4 OUT
ADD IA IB MOV IA M2
MOV IA OUT MOV IB M3
8
CMP IA IB MOV IB M3
MOV IA OUT ADD IA IB
MOV IB M4 MOV M4 OUT
ADD IA IB ELSE
MOV M4 OUT MOV IA M1
SHL IA 00000100
Answer : MOV IA OUT
MOV IB M3
(a) 28. ADD IA IB
MOV M4 OUT
(b) 30. ENDIF
(c) 32.
(d) 34. Answer :
(b) 9.
Question 38
Find the value of M 3 after the following program (c) 13.
segment has been executed.
(d) 21.
----------------
DEF M1 13 (e) None of the above.
DEF M2 12
MOV IA M1 Question 40
SHL IA 00000100
MOV IA OUT Refer to the artificial CPU and its commands, what
MOV IB M2 will be the content of M 4 if the following commands
ADD IA IB are executed?
MOV M3 OUT
---------------- DEF M1 2
DEF M2 2
Answer : DEF M3 5
DEF M1 2 (a) 7.
DEF M2 2
DEF M3 5 (b) 9.
9
Question 41 (c) M 2 = 7 × M 1.
Given that there are five memories M1, M2, M3, M4 (d) M 2 = 9 × M 1.
and M5. Here is the program segment to instruct the
circuit. (e) None of the above.
----------------
MOV IA M1
Question 43
MOV IB M2 Given that there are four memory slots M 1, M 2, M 3
MUL IA IB and M 4. Here is the program segment to instruct the
MOV IA OUT circuit.
MOV IB M3
MUL IA IB ----------------
MOV IA OUT MOV IA M1
MOV IB M4 MOV IB M2
SUB IA IB SHL IA 00000100
MOV M5 OUT MOV IA OUT
---------------- SHL IB 00000010
MOV IB OUT
Which of the following mathematical equation is ADD IA IB
identical to the operation of the following program MOV IB OUT
segment? MOV IA M3
ADD IA IB
Answer :
MOV M4 OUT
(a) M 5 = M 4 − M 1 × M 2 × M 3. ----------------
10
Question 45 Question 48
Which of the following statement(s) is(are) true? Which of the following method(s) is(are) for a user
(i) Once a computer has been power on, the first to control an operating system?
instruction the processor (CPU) has to execute (i) Text command.
is got from BIOS.
(ii) GUI-based command.
(ii) BIOS is a random access memory (RAM).
(iii) Once a computer has been power off, the con- (iii) Voice command.
tents in the BIOS will be gone.
Answer:
Answer:
(a) (i) and (ii).
(a) (i) and (ii).
(b) (ii) and (iii).
(b) (ii) and (iii).
(c) (i) and (iii).
(c) (i) and (iii).
(d) (i), (ii) and (iii). (d) (i), (ii) and (iii).
Question 46 Question 49
Which of the following system(s) is(are) an operating In a computer lab, you have found that a computer
system? has no response to any typing. What of the following
action(s) you cannot do?
(i) Apple iOS for iPhone.
(ii) Apple MacOS for Macintosh. (i) Plug out the power cord and reconnect it. So
that, the computer will be restarted.
(iii) Microsoft Windows for Acer notebook comput-
ers. (ii) Press the power on button to re-start the com-
puter.
Answer:
(iii) Press CTRL-ALT-DEL. If the task manager win-
(a) (i) and (ii). dow appears, select ’restart the computer’ op-
(b) (ii) and (iii). tion.
11
Clearly, John and Tom do not want their files to APPENDIX
be readable to each other. Note that some settings
depicted in the above table are set by the file owner. In this appendix, it includes the information about
Some settings are default setting. Even the file owner a simple processor, an artificial CPU and the source
does not know the setting. codes of five programs. Please read them carefully!
In accordance with the above setting, which of the
following leakage(s) could/will happen?
A. Processor with 4 Logic Gates
(i) The content of file X could be leaked to Tom.
A simple processor, with a sector of four logic gates
(ii) The content of file Y will be leaked to both John and a sector of four registers, shown in Figure 1. Each
and Tom. register is associated with a two-way switch. The
(iii) The content of file Z could be leaked to John. signals to be fed to the switch and the corresponding
actions are depicted in the following table.
Answer: Si Action
00 Disconnect.
(a) (i) and (ii). 01 Read from register.
(b) (ii) and (iii). 10 Write to register.
(c) (i) and (iii). For each connector, its control signal is either ’0’ (for
disconnection) and ’1’ (for connection).
(d) (i), (ii) and (iii). {
Connect if Si = 1,
(e) None of the above. Connection =
Disconnect if Si = 0.
S1 NOT S8
R1 R2 R3 R4
S2
AND S9
S5
S3
OR S10
S6
S4
XOR S11
S7
RA RB RZ
S12 S13 S14 S15 S16 S17 S18
12
switches (i.e. connectors). S12 , S13 and S14 are two- Eleven commands (MOV, ADD, SUB, MUL, DIV,
way switches. The signals sending to A1, A2 and CMP, SHL, SHR, DEF, MSK and IF) are provided
R/W together with the corresponding actions are de- for instructing the above circuit. The syntax and
picted in the following table. the descriptions of these commands are depicted in
Table 1.
A1 A2 R/W Action
0 0 01 Read data from R1
0 1 01 Read data from R2 Table 1: Commands for using the CPU.
1 0 01 Read data from R3
1 1 01 Read data from R4 Syntax Description
0 0 10 Write data to R1 MOV X Y Copy the content of Y to X
0 1 10 Write data to R2 ADD X Y OU T = X + Y .
1 0 10 Write data to R3 SUB X Y OU T = X − Y .
1 1 10 Write data to R4 MUL X Y OU T = X × Y .
x x 00 Disconnection DIV X Y OU T = X/Y .
CMP X Y OU T = b1 b2 b3 b4 b5 b6 b7 b8 .
bi = 0 if Xi = Yi .
R1 R2 R3 R4 bi = 1 if Xi ̸= Yi .
SHL X Y OU T is the content of X
A1 shifting left Y bits.
SHR X Y OU T is the content of X
A2 shifting right Y bits.
DEF X N Define X as the number N.
S1
MSK X M Mask the value of X by M.
NAND S3 R/W IF ELSE Condition statement.
S2
RA RB RZ
S12 S13 S14 S21
Figure 2: A processor with single NAND gate. 2. For ”SHL” and ”SHR” commands, the content
of Y can only be one of the following.
Y Meaning
C. Artificial CPU 10000000 (Shift 7 bits)
01000000 (Shift 6 bits)
Below is a simple circuit. It consists of a memory 00100000 (Shift 5 bits)
with 16 memory spaces (from M1 to M16), an ALU 00010000 (Shift 4 bits)
block, 2 input registers (IA and IB) and one out- 00001000 (Shift 3 bits)
put register (OUT). M1 to M16, IA, IB and OUT 00000100 (Shift 2 bits)
are all 8 bits long. Numbers are represented in 2’s 00000010 (Shift 1 bits)
compliment format. 00000001 (No shift)
X = 00011000, Y = 00000100,
ALU the OU T of ”SHL X Y” is 01100000 and the
OU T of ”SHR X Y” is 00000110.
13
M 1 will be assigned with a value 12. Therefore, DEF M3 1
M 1 = 00001100.
MOV IA M1
4. For the ”MSK” command, it is used for masking IF IA == 0
a register (either IA or IB) by the mask M (in MOV IA M2
binary). The mask must be 8 bits long. MOV IB M3
Suppose that the content of IA and M are de- ADD IA IB
fined as follows : MOV M4 OUT
ENDIF
IA = 01001001, M = 11110000. ------------------------
Then, the output OU T will be ”01000000”. The In this example, the CPU performs M 2 + M 3
last four bits are masked. Here is an example. only if IA is zero. Otherwise, it performs noth-
ing.
------------------------
DEF M1 45 6. For the ”IF-ELSE” command, the following con-
MOV IA M1 ditions are allowed for you to define. Here N U M
MSK IA 00001111 must be stated in decimal form but not in binary.
MOV M2 OUT
------------------------ ------------------------
IA == NUM
Initially, M 1 is assigned with value 45. In binary IA > NUM
form, the content reads ”00101101”. Thus, the IA >= NUM
output OU T is ”00001101”. IA < NUM
IA <= NUM
5. The ”IF-ELSE” command is an advanced level ------------------------
command. It is for conditional statement. Once
it is executed, the CPU will performs multiple
steps in order to make it works. You do not
need to know the detail how it works. In term
of its usage, it is simple. Here is an example.
------------------------
DEF M1 1
DEF M2 2
DEF M3 1
MOV IA M1
IF IA == 0
MOV IA M2
MOV IB M3
ADD IA IB
MOV M4 OUT
ELSE
MOV IA M1
ADD IB M2
MOV M4 OUT
ENDIF
------------------------
------------------------
DEF M1 1
DEF M2 2
14