• F1P rication Pro ces s Seq uen ce

• NMOS
• CMOS
 1. The starting Si wafer is a lightly
81-albr&IU doped p - type substrate.
 1. The startin g Si wafer is a lightly
doped p - type substr ate.

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2. Oxidize Si to form layer of Si02
SI • substra le

3. Coat the Si with photo resist.

r
J 1 l J I II1l I
, 4. To form ~ e_and drain_region, so
the next st~ is litho~ phy.
lL ___ .. ~.
'l

-----·-
I
,,, £
' .,' ......, , ...
•·••

5. Now, the Si02 regions which are not

covered by hardened photoresist can be
etched away either by e-H.hing.
 1
1 6. The remaining photoresist can
8'0aCOldde)-- 1. . .
____._ • ._
, . ._
. ,.
_ ___
.._ ·_1 be removes by using another
solvent.

7. Now deposit a laye_r_of (t_!lin o~e

in- order to _form gate oxide or the
Si • aubltrale
NMOS transistor.
Polys~
Thlnoallde - - - 8. Now on the top of the thin oxide
layer, a layer of polysilicon is
810a <OJdde>-- k~LJJ~~!!!!!!'!~-----l deposited. It is used as gate
electr ode material for MOS to
interc onnec t it.

9. After depos ition of the polysilicon

Thklo>dde - - ---- layer, it is patter n~ and etched to
form the interc onnec ts and the MOS
transi stor gate
Si - aubstrate
 10. The thin oxjde not covered by
polysilicon is also etched away so
that source and drain junctions
may be formed.
Si·IUbdale

...,_mean
11. The entire silicon surface is then
doped with a hi~~ ~~~ ion of
ao.<O.W.)- - impurities either ~ } ion
~ ~ -------1~""-
c §plantatio}0
 --~ 12. Once the source and drain
regions are completed, the entire
surface is again covered with and
insulating layer of Si02

13. The insulating oxide is then

910a(Oldde)-- patterned in order to provide
~~;..;...--.--::-
contact window for drain and source
junctions
 14. The surface is now covered
with evaporated aluminum which
will form the interconnections.

15. Finally the metal layer is

patterned and etched, completing
the interconnections of the MOS
transistor on the surface.
Sl • eubell--
• Fab'1cation Process Sequence
• NMOS
• CMOS
1. Grow Field Oxide ox.

p-type substrate

ox.
□
2. Etch Oxide for pMOSFET
p-type StbSbate
 Vl -"I I echnology ( Kl~COS:t J

ox.
3. Diffuse n-well.
p-type subsbate T
~
4. Etch oxide for nMOSFET.
p-type SllbstJate Cn- T
ox. I I
5. Grow gate oxide.
p-type sulsbate ~- )
6. Deposit Polysilicon.
p-type sutsbate

ox.
7. Etch polysilicon and oxide. U
IKYJ>e.SWibate

8. Implant source and drains.

~ subsbate
9. Grow Nitride. ~
~
p-type subsbate

10. Etch Nitride. p-type subsbate

 Vl-~I Tl.:'chnolugy (KEC05J)

11. Deposit Meta I

p-type subsbate

12. Etch Metal

p-type subsbate
 CMOS Fabrication using N-well and P-
well Technology

The Fabrication Process of CMOS Transistor

There was an era. where compu ters w ere such mamm oth In size
that
to install them, easily a room space was required. But today they
are
so evolved that we can even carry them as notebooks easily. The
innovation that made this possible was the concep t of Int egrated
Circui ts. In ~gait ed Circuits, a large number of active and paaslve
elements along with their interconnections are developed over a small
silicon w afer typically of 50 by 50 mils in cross section. The basic
processes follow ed for produc tion of such circuits include epitaxia
l
growt h, maske d impurity diffusion, oxide growth , and oxide etching
,
using photoh t hography for making pattern

The compo nents over the wafer include resistors. transis tors,
diodes,
capaci tors etc ... The most compli cated elemen t to manufa cture
over
IC's is transis tors Transis tors are of various tYRil such as CMOS,
BJT, FET. We choose the type o f t ransist or technology to be
implemented over an IC based on requirements. In this art icle let
us
get familiarized wi t h the concep t of CMOS fabrication (or) fabrica
tion
of transis tors as CMOS.

CMOS Fabrication

For less power dissipa tion requirement CMOS technology is used

for
implem enting transistors If we require a faster circuit then
transis tors are implem ented over l.C.Yfilno BJT. Fabrication of CMOS
transistors as IC's can be done in t hree different method s.

The N-well / P-well technology, where n-type diffusio n is done over

a
p-type substra t e or p-type diffusion is done over n-type substra
te
respec tively.

The Twin well technology, where NMOS and PMOS transistor are
developed over the w afer by simult aneous diffusio n over an epitaxia
l
growth base, rather than a substra te.

The silicon On Insulat or process, where rather than using silicon

as the
subst rate an insulat or material is used to improve speed and latch-u
p
susceptibili t y.

N- welV P- well Technology

CMOS can be obtained by integra ting bo th NMOS and PMOS

transistOfs over the same silicon wafer. In N-well techno logy an n-
type w ell Is diffuse d on a p- type substra te whereas m P· well 1t
is vice-
verse.
The Twin well technology, where ~ and PMOS transistor are
developed over the wafer by simultaneous diffusion over an epit axial
growth base, ra ther than a substrate.

The silicon On Insulator process, where rather than using silicon as

the substrate an insulator material is used to improve speed and
latch-up susceptibility.

N- weJA/ P- well Technology

CMOS can be obtained by integrating both NMOS and PMOS

trensistors over the same silicon wafer In N-well technology an n-
type well is diffused on a p-type substrate whereas in P· well it is
vice· verse.

CMOS Fabrication Steps

The CMOS fabrication process flow is conducted using twenty basic
fabrication steps while manufactured using N· well/ P· well
technology.

Making of CMOS usilg N wel

Step 1: First we choose a substrate as a base for fabrication. For N-

well, a P-type sihcon substrate is selected.

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Substrate

Step 2 - Oxidation: The selective di Husion of n-type impurities is

accomplished using SiO2 as a barrier which protects portions of the
wafer against contaminatio n of the substrate. SiO2 is laid out by
oxidation process done exposing the substrate to high-quality
oxygen and hydrogen in an oXJdation chamber at approximatel y
1000°c

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Oxidation

Step 3 - Growing of Photoreslst: At this stage to permit the

selective etching, the SiO2 layer is subjected to the photolithogra phy
 ,.,,_,n&t
ODtltltlo•

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Growing of Photores1st

Step 4- Masking: This step is the continuation of the

photolithography process. In this step, a desired pattern of
openness is made using a stencil. This stencil Is used as a mask
over the photoresist. The substrate is now exposed to UV rays the
photoresist present under the exposed regions of mask gets
polymerized.

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Masking of Photores1st

Step 5 - Removal of Unexposed Photoreslst: The mask is removed

and the unexposed region of photo resist is dissolved by developing
wafer using a chemical such as Trichloroethylene.

.AN-.,aiJt
oxldalloi,

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Removal of Photores1st

Step 6 - Etching: The wafer is immersed in an etching solution of

hydrofluoric acid, which removes the oxide from the areas through
which dopants are to be diffused.
Step 6 - Etching: The wafer is immersed in an etching solution of
hydrofluoric acid, which removes the oxide from the areas through
which dopants are to be diffused.

,. er,....,

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E1chlng o f S102

Step 7 - Removal of Whole Photoresist Layer: During the etching

process. those portions of Si02 which are protected by the
photoresist l ayer are not affected. The photoresist mask is now
stripped off with a chemical solvent (hot H2S04).

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Removal of Pho1ores1s 1Layer

Step 8 - Formation of N-well: Then-type impurities are diffused into

the p-type substrate through the exposed region thus forming an N-
well.

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 ;: Elprocus.com

Forma11on of N-well

Step 9 - Removal of $102: The layer of Si02 is now removed by using

hyaofluoric acid.

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Removal of Si02

Step 10 - Deposition of PolyslNcon: The misaligrvnent of the gate of a

CMOS tranlliator would lead to the unwanted capacitance which could
harm circuit. So to prevent this 'Self-aligned gate process· is preferred
where gate regions are formed before the formation of source and
drain using ion implantation

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Oepos11Ion of Polysihcon

Polys1hcon is used for formatlOll of the gate because it can Withstand

the high temperature greater than eooo0c when a wafer is sooiected to
annealing methods for formation of source and drain. Polysilicon is
deposited by using Chemlca.l Deposltlon Process over a thin layer of
gate oxide. This thin gate made under the Polysificon layer prevents
further doping under the gate region.
Step 11 - Formation of Gate Region: Except the two regions required
for formation of the gate for NMOS ind PMOS transistoni the
remaining portion of Polysilicon is stripped off

■ ■

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Formation of Gate Region

Step 12- Oxidation Process: An oxidation layer is deposited over the

wafer which acts as a shield for further diffusion end metallzatlon
processes.

■ ■

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Ox1dat1on Process

Step 13 - Maskilg end Diffusion: For makilg regions for diffusion of n-

type impurities using masking process small gaps are made.

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Masking

Using diffusion process three n+ regions are developed for the

formation of terminals of NMOS.
 ■
•
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N-diffus,on

Step 14 - Removal of Oxide: The oxide layer is stripped off.

■ ■
mm
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Removal or Oxide

Step 15 - P-type Diffusion: Similar to then-type diffusion for

forming the terminals of PMOS p-type diffusion are carried out.

■ mm
• ■

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P-Type Diffusion

St.ep 16 - La)'ing of Thick Field oxide: Before formmg the metal

terminals a thick field oxide is laid out to form a protective layer for
the regions of the wafer where no terminals are required.

■
■ mm
Step 16 - Le)'ing of Thick Field oxide: Before forming 1he me1af
terminals a thick field oxide is laid out to form a protec1Ive layer for
the regions of the wafer where no terminals are required.

II
■ mm
II TI •

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Thick Field oxide Layer

Step 17 - Metalization: This s1ep is used for 1he formation of me1al

1erminals which can provide interconnec110ns. Aluminum Is spread on
1he whole wafer.

U-L.■1
■ mm
,..,, -
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Me1allizat1on

Step 18 - Removal of Excess Metal: The excess metal Is removed

f rom the wafer.

Step 19 - Formation of Tenninels: In the gaps formed after removal

of excess me tal terminals are formed for the in1erconnections

rtr~ r------ 11
■ mm ,1
r r: •

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Forma1Ion of Tem,inals

Step 20 - Assi!,ling the Terminal Nemes: Names are assigned t o 1he

1ermmals of NMOS end PMOS transistors
 Step 20 -Aasi!,ling the Terminal Names: Names are assigned to the
terminals of NMOS and PMOS transistors.

,........____
PMOS

B S GD S GD B
I.~-, I.-, L ..__ _ _c--t C""' .._--, I,..-,
1
11' l u 1'
1
.1 M~l l'
■ mm ~
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Assigning Tenninal names

Making of CMOS using P well Technology

The p-well process is similar to N well process except that here n-

type substrate is used and p-type diffusions are carried out. For
simplicity usually, N well process is preferred.

TWln Tube Fabrication of CMOS

Using Twin-tube process one can control the gain of P and N-type
devices. Various steps involved in the fabrication of CMOS uting
Twin-ttbe method are as follows

• o A lightly doped nor p-type substrate is taken and the epitaxial

layer is used. Epitaxial layer protects the latch-up problem in the
chip.

• o The high purity silicon layers with measured thickness and exact
dopant concentration are grown.

• o Formation of tubes for P and N well

• o Thin oxide construction for protection from contamination

during diffusion processes.

• o Source and drain are formed using ion implantation methods.

• o Cuts are made for making portions for metal contacts.

o Metallization is done for drawing metal contacts

CMOS IC Layout

The upper view of a CMOS fabrication and layout is given. Here

various metal contacts and N well diffusions can be viewed clearly.