Combinational Logic Design –

BCD Adder, Multiplier

Dr. Chandan Karfa

Department of Computer Science and Engineering
• Chapter 4: M. M. Mano and M. D. Ciletti, Digital Design, 5th Ed.,
Pearson Education.
Decimal adder
• Arithmetic operations directly in the decimal number system
represent decimal numbers in binary coded form
• An adder for such a computer must employ arithmetic circuits that
accept coded decimal numbers and present results in the same code.
• A decimal adder requires a minimum of nine inputs and five outputs,
since four bits are required to code each decimal digit and the circuit
must have an input and output carry
• Depends on the code used.
 BCD adder
• Numbers range
0-9.
• Adder results:
0-19 (including
input carry)

When the binary sum is equal to or less than 1001, the corresponding BCD number
is identical, and therefore no conversion is needed.
When the binary sum is greater than 1001, the addition of binary 6 (0110) to the
binary sum converts it to the correct BCD representation and also produces an
output carry as required
BCD Adder
Corrections needed when
• K = 1.
• The other six combinations from 1010 through 1111 that need
• when 1 in position Z8.
• To distinguish them from binary 1000 and 1001, which also have a 1 in
position Z8, either Z4 or Z2 must have a 1.
BCD Adder
module bcd_adder (A, B, Cin, S, Cout);
input [3:0] A, B;
input Cin;
output [3:0] S;
output Cout;

wire carry, carry1;

wire [3:0] sum, b;
wire z;

four_bit_adder Add1 (.A(A), .B(B), .C0(Cin), .S(sum), .C4(carry));

four_bit_adder Add2 (.A(sum), .B(b), .C0(1'b0), .S(S), .C4(carry1));
assign z = (sum[3] & sum[2]) | (sum[3] & sum[1]) | carry;
assign b = {1'b0,z,z,1'b0};
assign Cout = z;

endmodule
 // Clock generator
module testbench ( );
always begin
reg [3:0] a;
#10 clk = ~clk; 10: a = xxxx, b = xxxx, cin = x, sum = xxxx, cout = x
reg [3:0] b;
end
reg cin; 30: a = 0110, b = 1001, cin = 0, sum = 0101, cout = 1
// Test sequence
50: a = 1001, b = 1001, cin = 1, sum = 1001, cout = 1
wire [3:0] sum; 70: a = 0101, b = 0101, cin = 1, sum = 0001, cout = 1
reg [3:0] i;
wire cout; 90: a = 0111, b = 0100, cin = 1, sum = 0010, cout = 1
always @(posedge clk, posedge rst) begin
if (rst) begin 110: a = 1001, b = 0111, cin = 1, sum = 0111, cout = 1
bcd_adder DUT(
.A(a),
i = 0; 130: a = 0110, b = 0101, cin = 1, sum = 0010, cout = 1
end else begin 150: a = 0111, b = 0000, cin = 1, sum = 1000, cout = 0
.B(b),
// Apply all possible val values (0-9) 170: a = 0111, b = 1000, cin = 0, sum = 0101, cout = 1
.Cin(cin),
a <= $urandom%10;
.S(sum), 190: a = 1001, b = 0100, cin = 1, sum = 0100, cout = 1
b <= $urandom%10;
.Cout(cout) 210: a = 0011, b = 0111, cin = 1, sum = 0001, cout = 1
cin <= $random%2;
);
#20;
reg clk;
i = i + 1;
reg rst;
if (i == 10) $finish;
end
// Initial values
$monitor("%d: a = %b, b = %b, cin = %b, sum = %b, cout = %b",
initial begin
$time, a, b, cin, sum, cout);
clk = 0;
end
rst = 1;
endmodule
#20;
rst = 0;
end
Binary Multiplier
• A bit of the multiplier is ANDed with each bit of the
• multiplicand in as many levels as there are bits in the
multiplier.
• The binary output in each level of AND gates is added
with the partial product of the previous level to form a
new partial product.
• The last level produces the product.
• For J multiplier bits and K multiplicand bits, we need J *
K2AND gates and (J – 1) * K bit adders to produce a
product of (J + K) bits.
Binary Multiplier
module product(a,b,res);
input [3:0] b;
input [2:0] a;
output [6:0] res;
assign r1[4]=1'b0;
wire [4:0] r1;
wire [3:0] r2,r3; assign res[0]=r1[0];
wire [4:0] i1; CLA_Adder a1(r1[4:1], r2, 1'b0, i1[3:0], i1[4]);
assign res[1]=i1[0];
assign r1[0]=b[0]&a[0]; CLA_Adder a2(i1[4:1], r3, 1'b0, res[5:2], res[6]);
assign r1[1]=b[1]&a[0]; endmodule
assign r1[2]=b[2]&a[0];
assign r1[3]=b[3]&a[0];

assign r2[0]=b[0]&a[1];
assign r2[1]=b[1]&a[1];
assign r2[2]=b[2]&a[1];
assign r2[3]=b[3]&a[1];

assign r3[0]=b[0]&a[2];
assign r3[1]=b[1]&a[2];
assign r3[2]=b[2]&a[2];
assign r3[3]=b[3]&a[2];
module testbench ( );
// Inputs
reg [2:0] a; 10: a = xxx, b = xxxx, res = xxxxxxx
reg [3:0] b; 30: a = 100, b = 0001, res = 0000100
// Clock generator
// Outputs 50: a = 001, b = 0011, res = 0000011
always begin
wire [6:0] out; 70: a = 101, b = 1101, res = 1000001
#10 clk = ~clk;
// Instantiate the Design 90: a = 101, b = 0010, res = 0001010
end
Under Test (DUT)
110: a = 001, b = 1101, res = 0001101
product dut (
// Test sequence 130: a = 110, b = 1101, res = 1001110
.a(a),
reg [3:0] i; 150: a = 101, b = 1100, res = 0111100
.b(b),
always @(posedge clk, posedge rst) begin 170: a = 001, b = 0110, res = 0000110
.res(out)
if (rst) begin
); 190: a = 101, b = 1010, res = 0110010
i = 0;
end else begin 210: a = 101, b = 0111, res = 0100011
// Clock and reset signals
// Apply all possible val values (0-9)
reg clk;
a <= $random%8;
reg rst;
b <= $random%16;
#20;
// Initial values
i = i + 1;
initial begin
if (i == 10) $finish;
clk = 0;
end
rst = 1;
$monitor("%d: a = %b, b = %b, res = %b", $time, a, b, out);
#20;
end
rst = 0;
endmodule
end
Other Multipliers
• Wallace tree multiplier
• Booth multiplier
Thank You