02-03-2024

Hello Friend!
These notes are not free, the fee of these notes is that
you should pray for me.
Please remember me in your prayers
: Dr. Shameem Ahmad
(Sarcastic Teacher)

Micro-Processor
SE-CS
UNIT 2

UNIT-2:
1. Flag Register(PSW)/EFLAGS

• Carry Flag (CF): This flag is set when the carry is generated out of the MSB.
• Parity Flag (PF): This flag is set if the result contains an even number of 1s.
• Auxiliary Carry Flag (AF): This flag is set when carry is transferred from D3bit (lower
nibble to higher nibble) in 8-bit arithmetic operations.
• Zero Flag (ZF): This flag is set if the result of an operation is zero.
• Sign Flag (SF): This flag is set if the result of an operation is negative.
• Trap Flag (TF): This flag is used to enable single-step mode, which allows the processor to
execute one instruction at a time, which is useful for debugging.
• Interrupt Flag (IF): This flag is used to enable or disable maskable interrupts.
• Direction Flag (DF): This flag is used to control the direction of string operations, such as
move and compare.
• Overflow Flag (OF): This flag is set when the result of an arithmetic is out of range.

1
 02-03-2024

UNIT-2:
1. Flag Register(PSW)/EFLAGS

• Input output privilege level: These two bits

shows the I/O privilege level of current
program.
• Nested Task Flag: the processor shows that the
interrupt or call function is being executed.
• Resume Flag: if SET disables debug
exceptions and gets cleared after first debug
breakpoint.
• Virtual 8086mode: it is used to enter virtual
8086 mode.
• 1 :80386 is executing an 8086 program
• 0: otherwise

2. PIN Diagram

2
 02-03-2024

2. PIN Diagram • CLK2 is twice the frequency of the actual system clock.
• RESET: This signal is used to reset the 80386.
• 𝑅𝐸𝐴𝐷𝑌 pin is used to synchronize the µP with slower
peripherals
• If 𝑅𝐸𝐴𝐷𝑌 pin is = 0, that means device is ready and hence
µP continues.
• If 𝑅𝐸𝐴𝐷𝑌 pin is = 1, it means device is not ready hence µP
inserts “Wait States”.

• NMI and INTR are hardware interrupt pins

• HOLD and HLDA are used for DMA purposes. DMA
Interrupts Pins means transferring data directly between Memory and I/O
without involving the µP.
• To do DMA transfer, the DMA Controller requires control
of the system bus. It gives HOLD to the µP (i.e. HOLD =1).
• Now µP finishes the current bus cycle (machine cycle) and
releases control of the system bus, and
gives HLDA.
• PEREQ: (Peripheral Extension Request)
DMA interface • If the coprocessor makes PEREQ = 1, it requests the µP to
initiate the bus operation.
• 𝑬𝑹𝑹𝑶𝑹 : (Co-Processor Error)
• Whenever any of the unmasked errors occur, 80387 makes
𝐸𝑅𝑅𝑂𝑅 = 0.

Coprocessor • 𝑩𝑼𝑺𝒀 : (Co-Processor Busy)

• If 80387 is busy, it makes 𝑩𝑼𝑺𝒀 = 0
interface

• Address Bus (A31 – A2) (output signals).

2. PIN Diagram • 80386 has a “32 bit” address bus. The lower 2
lines A1and A0are used internally by the µP to
produce the four bank-enable signals
• 𝑩𝑬𝟑 … 𝑩𝑬𝟎 - Bank Enable Signals (active low
output signals).
• 𝑅𝐸𝐴𝐷𝑌 pin is used to synchronize the µP with
slower peripherals
• If 𝑅𝐸𝐴𝐷𝑌 pin is = 0, that means device is
ready and hence µP continues.
• If 𝑅𝐸𝐴𝐷𝑌 pin is = 1, it means device is not
ready hence µP inserts “Wait States”.
• D31 – D0 (32-bit data bus) (bidirectional signals)
• 𝐵𝑆16 - Dynamic Data Bus Sizing (active low
input signal)if 0:16bit data bus is selected(D15-D0)
• Control Signals: M/ 𝐼𝑂 : 1 = Memory, 0 = I/O
• D/ 𝐶ҧ : 1 = Data, 0 = Control
ത 1 = Write, 0 = Read.
• W/ 𝑅:

3
 02-03-2024

• 𝐿𝑂𝐶𝐾 : (active low output signal)

2. PIN Diagram • if a bus request occurs during an
instruction:
• 1=µP releases the bus just after
finishing the current machine cycle
• 0=µP will only release the bus after
completing the current instruction
• 𝐴𝐷𝑆 : Address Status
• This pin is made low, when a new
address is put on the address bus.
• 𝑁𝐴 : Next Address
• 1= Address pipelining OFF
• 0=Address pipelining ON

3. Memory organization (Banks)

• 80386 has 32bit data bus.
• But one memory location contains only one byte (8bits).
• So to get 32 bits 4 consecutive memory locations will
be used.
• As 32 bit data has to be accessed from 4 locations, the
80386 memory is divided into 4 banks.
• Each bank is enabled by its respective bank enable
signal. Each bank is of 1GB, making it total 4 GB.
• The addresses are distributed in such a way that the 4
consecutive locations carrying 32-bit data are spread
across 4 different chips (banks).

4
 02-03-2024

4. Memory management registers

• GDTR (Global Descriptor Table Register ) 48bit
• Holds the base address and size of the Global Descriptor
Table (GDT) in protected mode
• LDTR (Local Descriptor Table Register) 16bit
• Holds the segment selector for the Local Descriptor
Table (LDT) in protected mode.
• IDTR (Interrupt Descriptor Table Register) 48bit
• It is used to search the IDT
• TR
• Holds information about the currently executing task in
protected mode.

5
 02-03-2024

On reset, by default PE bit is “0”. It is the only bit of CR0 which

is also available in Real Mode.

• Programmers model:
• In real mode:
• 6, 16-bit segment registers: CS, SS, DS, ES,
Extras: FS and GS.
• 5, 16-bit offset registers IP,SP,BP,SI,DI.
• Processor State after Reset:
• 4, 16-bit data registers :AX, BX CX and DX
• On reset 80386 goes to ROM location
• lower 12-bits of the Flag Register
FFFF FFF0 h, called the Reset Vector
• Only the LSB of CR0 (PE)is available in
Address of 80386 and executes a BIOS
Real Mode
program (also called Monitor Program).
• 8 addressing modes are available
• Additionally 80386 may also execute a
POST (Power-On Self Test), used to test • In Protected mode.
its internal hardware. • six, 16-bit segment registers.
• The Self Test optional. It is only • five, 32-bit extended offset
executed if the BUSY pin is held low registers(EIP,ESP,EBP,EDI,ESI)
during Reset. • Four, 32-bit general purpose registers
• Self Test takes approx 26 milliseconds. EAX,EBX,ECX,EDX
• 32 bit flag register called EFLAGS (or PSW)
• After the test, the result is stored in
EAX register. If EAX = 00H, then the • Four 32bit control registers:
Self Test was successful, else the test CR0,CR1,CR2,CR3
was unsuccessful. • All memory management registers are
available. 8 debug and 2 test registers are
available.

6
 02-03-2024

Thank You
Like Share & Subscribe to
SarcasticTeacher
@ShameemSir