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System Level Modelling Presentation
System Level Modelling Presentation
Low frequency and low amplitude signals Detection difficult as coupled with flicker noise, Common mode noise and voltage. Electrodes eliminate common mode gain. DC component eliminated - choppers
electrode offset
Input Signal BW=05 Hz to 1KHz OSR= 1024 Order of Modulator= 2 LP or BP= LP DR= 70dB ENOB= 18 QUANTIZATION BITS=1
Performance Parameters
Calculating coefficients
The calculation of these coefficients is based on the fact that the pulse response of filter is weighted response of the all the pulses generated by each feedback in DSM architecture. This yields us with a system of linear equations ..
non-idealities
Variations from ideal clock edges vary the feedback pulse length
Clock jitter causes error sequence in CT : e(z) = { y(n) y(n-1) } * bn /Ts Adds additional noise in DAC through feedback which is NOT shaped by loop filter Simulation show NRZ codes & multi bit quantization are less sensitive to jitter
thermal noise - caused by random fluctuations of carriers due to thermal energy white spectrum and wide band, limited the BW of the operational amplifiers Flicker noise - 1/f noise decrease with frequency increase Time domain emulated sources of both noises are sum of N sine waves with random phase
Ideally infinite but actually limited by circuit constraints & op amp open loop gain
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else
Slew rate of 1 st integrator is important!!! Insufficient slew rate increase noise floor & cause harmonic distortion
Alpha 1 &2 can be extracted from circuit behavior & curve-fitting method
Output of integrator is clipped because the transistors connected to supply rails are not in saturation
SIMULATION RESULTS