energies
Article
Modular Transformerless Static Synchronous Series
Compensator with Self-Balancing for Ultra High Current Using
a Paralleling Scheme
Antonio E. Ginart
Citation: Ginart, A.E. Modular
Transformerless Static Synchronous
Series Compensator with Self-
Balancing for Ultra High Current
Using a Paralleling Scheme. Energies
2022, 15, 4666. https://doi.org/
10.3390/en15134666
Academic Editor: Abdelali El Aroudi
Received: 29 April 2022
Accepted: 20 June 2022
Published: 25 June 2022
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Copyright: © 2022 by the author.
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4.0/).
Energies 2022, 15, 4666. https://doi.org/10.3390/en15134666
Katerra, Inc., Menlo Park, CA 94025, USA; aginart@ieee.org
Abstract: A novel modular Transformerless, Self-balanced, Static Synchronous Series Compensator
(TSB-SSSC) capable of delivering ultra-high current, with the objective of dynamically balancing the
impedance of the transmission power grid, is proposed. Balancing transmission lines is crucial in
power optimization and delivery because it increases the power transfer capability without building
new power lines. The transformerless SSSC needs to support and control the line current from a few
hundred to several thousand amperes. This paper presents how the ultra-high current architecture
of the TSB-SSSC is achieved by operating multiple converters with self-balancing capabilities in
parallel. The mechanism of self-balancing is based on the intrinsic physics of the capacitor and is
enabled by a passive network of capacitor equalizers that keep the capacitor voltage equal during
switching disconnection. The second self-balancing system consists of an inductive component that
balances possible differences among delay switching caused by the aging of the multiple IGBTs from
the different converters that form the SSSC. This work presents the analytical set of equations that
describes the system and a complete set of simulations where the effectiveness of self-balancing
paralleling topology is shown.
Keywords: SSSC; transmissions lines; FACTS
1. Introduction
The traditional power system was centralized, well-planned, and with firm control at
the generation center and reasonable control on the centers of consumption. Under these
conditions, utility companies could plan the expansion and tie tune of the power system
infrastructure. In other words, power lines on the power system could be passively tuned
to be able to carry power at close to their potential limits, thereby maximizing installed
assets, especially related to transmission power lines.
The arrival of solar and wind power produced a fundamental transformation in the
power system’s morphology and control, shifting it from a centralized generation of power
to a distributed generation, reducing the controllability of the power system, and adding
significant degrees of randomness. Nowadays, there are no specific generation centers
anymore, but instead a steadily growing, diversified generation of all the parts of the
power system, including what used to be the traditional loads. The modern, distributed
power system has dynamics that shift within minutes, depending on solar radiation and
wind intensity.
Unbalanced power lines limit the total power transfer from one point to another. The
use of passive compensation such as capacitors and inductors to balance the lines is less
effective because of the fast changes—within minutes—in power generation. Consequently,
the current distribution in power transmission lines has drifted from a design condition to a
sub-utilized system, with some power transmission lines carrying more current than others.
When a power line reaches its maximum current limit, the overall power transmission is
limited as well. Then, power transmission reaches its ceiling regardless of whether other
power lines are carrying lower than nominal current.
https://www.mdpi.com/journal/energies
 power transmission is limited as well. Then, power transmission reaches its ceiling re
gardless of whether other power lines are carrying lower than nominal current.
Energies 2022, 15, 4666 To solve this problem, there are two effective solutions. The traditional2solution of 16 con
sists of constructing more power transmission lines in the congested areas of the powe
system. Construction of power lines is a complicated and expensive proposition that re
quires obtaining
To solve pass-through
this problem, there permits, buying private
are two effective solutions. land, and
The usually facing
traditional solution significan
politicalofopposition
consists constructing from
morepeople
powerobjecting
transmission to power
lines lines
in thenear their homes
congested areas of (see
theFigure 1
power system.solution
The second Construction of power
discussed lineswork
in this is a complicated
is using a and expensive
flexible proposition
alternating current trans
that requires
mission obtaining
system (FACTS) pass-through
to balance permits,
the powerbuying private
lines. land, in
FACTS, and usuallyare
general, facing
power elec
significant
tronics converters to control and enhance the power system’s capabilities.(see
political opposition from people objecting to power lines near their homes Traditiona
Figure 1). The second solution discussed in this work is using a flexible alternating current
FACTS are based on shunt structures such as Static synchronous compensator (STAT
transmission system (FACTS) to balance the power lines. FACTS, in general, are power
COM) and static var compensator (SVC). The best representative of a series structure i
electronics converters to control and enhance the power system’s capabilities. Traditional
the SSSC.
FACTS This on
are based workshuntis concentrated
structures suchin asan SSSC
Static that dynamically
synchronous compensatorchanges the impedanc
(STATCOM)
and static var compensator (SVC). The best representative of a series structure is the SSSC. near th
of the power line to balance the current and allow the system to reach levels
respective
This work isnominal
concentratedpower.in anAny compensators
SSSC that dynamicallycan bechanges
appliedthetoimpedance
balance power of thelines. Th
power line todevice
successful balanceneeds
the current and allow
to provide the system
the best to reachpossible.
cost-benefit levels near the respective
Devices in series intrin
nominal power.
sically deal Anysignificantly
with compensatorslower can bevoltages,
applied totherefore
balance power they lines.
haveThe successful
a better chance to b
device needs to provide the best cost-benefit possible. Devices in
successful if a low-cost high-current architecture is achieved as proposed in this workseries intrinsically deal
with significantly lower voltages, therefore they have a better chance to be successful if a
Consequently, to be practical SSSCs l require an active device with reliable device-manu
low-cost high-current architecture is achieved as proposed in this work. Consequently, to
facturability and self-balance mechanisms at a relatively low cost. A transformerless sel
be practical SSSCs l require an active device with reliable device-manufacturability and
balanced SSSC
self-balance (TSB-SSSC)
mechanisms is discussed
at a relatively in this
low cost. work as the solution
A transformerless to thisSSSC
self-balanced problem be
cause it can
(TSB-SSSC) is shift fromin
discussed anthis
inductive
work asto thea capacitive function,
solution to this problembalancing
because the transmission
it can shift o
the power
from system
an inductive to ain either case.
capacitive As an
function, example,
balancing thethe top diagram
transmission of theofpower
Figure 2 shows how
system
inunbalanced
either case. As power lines limit
an example, thediagram
the top transferofof power.
Figure Oncehow
2 shows oneunbalanced
line reaches power100% of it
lines limit the
nominal transfer
power of power.
(in this case, Once one is
the line line reaches 100%
indicated as a ofreditsarrow),
nominalthe power (in this
parallel lines (blu
case, the line is indicated as a red arrow), the parallel lines (blue arrow)
arrow) cannot increase their power; in this example, the parallel line cannot go above 40% cannot increase
their power; in this example, the parallel line cannot go above 40% of its line nominal
of its line nominal power. The maximum power the system can transfer is limited to 70%
power. The maximum power the system can transfer is limited to 70% for the top diagram
for the top diagram (power of each line/number of lines); however, the bottom diagram
(power of each line/number of lines); however, the bottom diagram of Figure 2 shows
anofexample
Figure 2inshowswhich aan examplebalances
TSB-SSSC in which the acurrent,
TSB-SSSC allowingbalances the current,
the system to regainallowing
the th
system toofregain
possibility the possibility
increasing the power toof100%increasing
on eachthe power
parallel tothus
line, 100% on each30%
regaining parallel
of theline, thu
regaining 30% of the nominal
nominal power compared to the unbalanced case.power compared to the unbalanced case.

Figure1. 1.
Figure Parallel
Parallel transmission
transmission power
power lines lines in a suburban
in a suburban area in area
SantainClarita,
Santa CA,
Clarita,
USA.CA.
 Energies2022,
Energies 2022,15,
15,4666
x FOR PEER REVIEW 33 of
of 16
17

Figure2.2.The
Figure Theunbalance
unbalancein
inthe
thetransmission
transmissionpower
powerlines
linescan
canbe
becompensated
compensatedwith
withTSB-SSSC.
TSB-SSSC.

2.2.Background:
Background:Static
StaticSynchronous
SynchronousSeries
SeriesCompensator
Compensator(SSSC)
(SSSC)
The
TheSSSC
SSSCisisan
aninverter
inverterconnected
connectedin inseries
serieswith
withan anAC
ACtransmission
transmissionline.
line.The
TheSSSC
SSSC
does
doesnot
nothave
haveaasource
sourceof ofreal
realpower
powerconnected
connectedto toits
itsDC
DCcapacitor.
capacitor.The
Theinverter
invertercancanbe be
connected
connecteddirectly
directlytotoa transmission
a transmission line, or it
line, orcan be connected
it can through
be connected a transformer.
through The
a transformer.
traditional configuration
The traditional uses auses
configuration transformer that reduces
a transformer the current
that reduces that thethat
the current semiconduc-
the semi-
tors receive by the turn ratio of the transformer
conductors receive by the turn ratio of the transformer [1].[1].
The
The SSSC
SSSC can control the
can control theflow
flowofofreal
realpower
power onon
thethe transmission
transmission lineline
whenwhen
it is itcon-
is
connected in series
nected in series withwith
thatthat
line.line. Figure
Figure 3 shows
3 shows how how the power
the power flowsflows
alongalong
any ACanytrans-
AC
transmission
mission line line between
between bus 1bus
and 1 and
bus bus
2, and2, and
it is it is given
given by, by,
V𝑉 V2𝑉
P12𝑃 = = 1 sinδ
𝑠𝑖𝑛12𝛿 (1)
(1)
𝑋
X12

V1 ∠θ1 𝑉
wherewhere and∠𝜃V ∠ and 𝑉 ∠𝜃 are the voltage phasors for bus 1 and bus 2, respectively,
2 θ2 are the voltage phasors for bus 1 and bus 2, respectively, δ = θ2 − θ1 .
𝛿 = 𝜃 − 𝜃 . 𝑋 = 𝑗𝜔𝐿
X12 = jωLline is the inductive isreactance
the inductiveof thereactance
transmissionof theline,
transmission
and P12 is line, 𝑃 is
andpower
the real
the real power flowing along the transmission line. Transmission
flowing along the transmission line. Transmission line voltages are generally regulatedline voltages are gener-
ally tightly,
very regulated so itvery tightly,
is fair so it that
to assume is fair
V1 to
=V assume that 𝑉 = 𝑉 = 𝑉. Power flow on AC
2 = V. Power flow on AC transmission lines
is mostly uncontrollable: the only level of control thatlevel
transmission lines is mostly uncontrollable: the only of controlline
transmission thatoperators
transmission
have line
on
operators
the network have on the network
is through modifyingis through modifying
its topology, its topology,
i.e., they can havei.e., they
a line can have to
connected a line
or
connected to from
disconnected or disconnected from the
the AC network. TheACSSSCnetwork. The SSSC can
can dynamically dynamically
modify the power modify
flow
the power
along the ACflow along the AC
transmission linetransmission
as, line as,

V 2 𝑠𝑖𝑛 𝛿 VV
P12 𝑃
= = sinδ12 +
+ SSSC cos
𝑐𝑜𝑠δ12 (2)
(2)
X12 X12 2
whereV𝑉
where SSSC isisthe
theAC
ACvoltage
voltageinjected
injectedby bythe
theSSSC
SSSCininseries
series with
with the
the transmission
transmission line.
line.
Theabove
The aboveequation
equationshows
showsthatthatthe
theSSSC
SSSCcan canmodify
modifythe
thepower
powerflow
flowalong
alongaatransmission
transmission
lineby
line byeither
eitherincreasing
increasingor ordecreasing
decreasingit,it,depending
dependingon onthe
thephase
phaseangle
anglebetween 𝑉
betweenVSSSC
andthe
and thetransmission
transmissionlinelinecurrent
current(± ( 9090°).
◦ ). The
Theamount
amountof ofreal
realpower
powerthat
thatcan
canbe
bechanged
changed
onthe
on thetransmission
transmissionlinelinealso
alsohas
hasaalinear
linearrelationship
relationshipwith 𝑉 . .This
withVSSSC Thisgives
givesSSSC
SSSCaagreat
great
advantageover
advantage overother
othertypes
typesof of series
series compensators,
compensators, mostmost of which
of which typically
typically havehave an in-
an inverse
verse relationship
relationship between between
the powerthe power
flow and flowtheand the control
control variable.
variable.
This linear control of the power flow along a transmission line makes the SSSC a great
tool for transmission line operators and provides them with a lot of flexibility with the
changing generation and load profiles in modern power networks. SSSCs are a good option
for utilities that generally do not have the flexibility to install additional transmission lines
Energies 2022, 15, 4666 4 of 16

Energies 2022, 15, x FOR PEER REVIEW 4 of 17

to meet the changes in generation centers resulting from renewables such as offshore wind
and distributed solar.

Figure 3. Basic operation of SSSC with phasor diagram.

This linear control of the power flow along a transmission line makes the SSSC a great
tool for transmission line operators and provides them with a lot of flexibility with the
changing generation and load profiles in modern power networks. SSSCs are a good op-
tion for utilities that generally do not have the flexibility to install additional transmission
lines to meet the changes in generation centers resulting from renewables such as offshore
wind and distributed solar.
Figure
Figure 3.
3. Basic
Basic operation
operation of
of SSSC
SSSC with
with phasor
phasor diagram.
diagram.
3. Modular SSSC Converter
3. Modular SSSC
This linear Converter
control of the power flow along a transmission line makes the SSSC a great
To balance power system transmission lines, an effective SSSC needs to be capable of
tool for transmission
To balance powerline systemoperators and provides
transmission lines, an them with SSSC
effective a lot needs
of flexibility with the
to be capable of
injecting from a few to several hundred MWs of reactive power. To inject this amount of
changing
injecting fromgeneration
a few to and load profiles
several hundred inMWs
modern power networks.
of reactive power. ToSSSCs are aamount
inject this good op- of
reactive power in power lines of several thousand amperes, the SSSC needs to withstand
reactive
tion power in
for utilities thatpower lines do
generally of several
not have thousand amperes,
the flexibility the SSSC
to install needs transmission
additional to withstand
tens of kilovolts. Under these circumstances, the best way to produce a high-power con-
lines to meet the changes in generation centers resulting from renewables suchhigh-power
tens of kilovolts. Under these circumstances, the best way to produce a as offshore
verter is with a modular design such as the one used by Modular Multilevel Converter
converter
wind and is with a modular
distributed solar. design such as the one used by Modular Multilevel Converter
(MMC) [2–4],
(MMC) [2–4], but
but with
with thethe difference
difference that that the
the SSSC
SSSC is is aa series
series converter
converter thatthat needs
needs to to carry
carry
the total
theModular
3. current
total current of the
SSSCofConverter line at a fraction of the hundreds of kilovolts
the line at a fraction of the hundreds of kilovolts of the transmission of the transmission
powerlines.
power lines.OnOnthe theother
otherhand,hand,the the
MMCMMC is typically
is typically used used
for for transmission
transmission power sys-
tems To balance
that sustainpower
the system
total transmission
voltage, usually lines,
tens ankilovolts,
of effective SSSC
but needs
only at topower
a fraction
systems
be capable of of
the
that sustain
injecting from the
a totaltovoltage,
few several usually
hundred tens
MWs of ofkilovolts,
reactive but onlyTo
power. at inject
a fraction
this of the line
amount of
line current,
current, suchsuch as
asininpowerin HVDC
HVDC or STATCOM
or STATCOM applications.
applications.
reactive power
Designing aa viable
viable SSSC lines of
SSSC product several
product must thousand
must rely
rely ononamperes, the SSSCmanufactured
using large-scale
large-scale needs to withstand power
tens Designing
of kilovolts. currently
Under these circumstances, the bestusingway reliable
to produce manufactured
a high-power power
con-
semiconductors
semiconductors currentlydesignon the
on the such market.
market. Lower
Lower cost
cost and
and reliable power
power semiconductors
semiconductors
verter is
nowadays arewith a modular
are centered
centered on on silicon
silicon IGBTs as the
IGBTs with one used
with aa nominal by Modular
nominal voltage
voltage of Multilevel
of 1200–1700
1200–1700 V Converter
V and
and aa
nowadays
(MMC)
current [2–4],
of but awith
about the difference
thousand amperes. that theoperational
The SSSC is a series converter
frequency that be
should needs to carry
limited to aa
current of about a thousand amperes. The operational frequency should be limited to
the total
single current
pulse or a of
PWMthe line
of a at
fewa fraction
hundred ofhertz
the hundreds
to avoid of kilovoltsswitching
significant of the transmission
losses. The
single pulse or a PWM of a few hundred hertz to avoid significant switching losses. The
power lines. On
proposed architecture the other
architecture uses hand,
uses the the MMC
the paralleling is typically
paralleling converters
converters to used
to carryfor transmission
carry large
large line power
line currents
currents in sys-
in the
the
proposed
tems
orderthat sustain theoftotal
of thousands
thousands voltage,
amperes, usually
and series tens of kilovolts,
converters butlarger
to inject
inject only at a fraction
voltages of the
in tens
tens of
order of of amperes, and series converters to larger voltages in of
line current,
kilovolts [5].such
Figure as in HVDC oraSTATCOM applications.capable of meeting the require-
kilovolts [5]. Figure 4 4presents
presents modular
a modular arrangement
arrangement capable of meeting the requirements
ments Designing
necessary a viable
to developSSSCthe product must rely on
transformerless using
SSSC large-scale
present in thismanufactured
work. power
necessary to develop the transformerless SSSC present in this work.
semiconductors currently on the market. Lower cost and reliable power semiconductors
nowadays are centered on silicon IGBTs with a nominal voltage of 1200–1700 V and a
current of about a thousand amperes. The operational frequency should be limited to a
single pulse or a PWM of a few hundred hertz to avoid significant switching losses. The
proposed architecture uses the paralleling converters to carry large line currents in the
order of thousands of amperes, and series converters to inject larger voltages in tens of
kilovolts [5]. Figure 4 presents a modular arrangement capable of meeting the require-
ments necessary to develop the transformerless SSSC present in this work.

Figure 4. Modular SSSC scheme (a) diagram (b) 3-seres SCCC single pulse.

The limitation of having a single pulse or a low-frequency wide pulse modulation is

that these produce a larger harmonics content compared to a high-frequency PWM. Low
harmonics content is addressed with the arrangement of a series converter. Figure 4b shows
 Figure 4. Modular SSSC scheme (a) diagram (b) 3-seres SCCC single pulse.

The limitation of having a single pulse or a low-frequency wide pulse modulation is

Energies 2022, 15, 4666 5 of 16
that these produce a larger harmonics content compared to a high-frequency PWM. Low
harmonics content is addressed with the arrangement of a series converter. Figure 4b
shows the scheme for three single pulse converters in series [6]. The concept can be ex-
the scheme
tended for three
to many single pulse
converters converters
in series that, in in series [6]. The
combination, concept
produce can be extended
relatively a very lowto
many converters in series that, in combination, produce relatively a very low
harmonics content. The analysis of this system for MCC shows the effectiveness of this harmonics
content. The
technique, analysis
even of this
with only system
a small for MCC
number shows theineffectiveness
of converters series [7]. of this technique,
even with only a small number of converters in series [7].
Strategies to Achieve Large Current in Power Converters
Strategies to Achieve Large Current in Power Converters
Power converters with large current requirements rely primarily on paralleling mod-
Power converters with large current requirements rely primarily on paralleling mod-
ules with self-balancing capabilities before taking advantages of paralleling power con-
ules with self-balancing capabilities before taking advantages of paralleling power con-
verters. Standard power converters require active current balancing [8]. Self-balancing at
verters. Standard power converters require active current balancing [8]. Self-balancing
dies or module levels requires a positive thermal coefficient that intrinsically increases the
at dies or module levels requires a positive thermal coefficient that intrinsically increases
effective resistance while its temperature increases. As a result of the phenomena, the hot-
the effective resistance while its temperature increases. As a result of the phenomena, the
ter element pushes the current to the less hot dies, generating an equilibrium when the
hotter element pushes the current to the less hot dies, generating an equilibrium when the
junction temperatureof
junction temperature ofthe
thedifferent
differentparallel
parallelelements
elementsisissimilar.
similar.The Thepower
power semiconduc-
semiconductor
tor is based on two fundamental structural components,
is based on two fundamental structural components, MOSFETs and IGBTs. The MOSFETs and IGBTs. The Field
Field
Electric
Electric Transistor (FET) family
Transistor (FET) family isis naturally
naturally easy
easy to
to parallel
parallel because
because its its conduction
conduction is is based
based
on the resistive channel with a positive thermal resistance. Based
on the resistive channel with a positive thermal resistance. Based on bipolar technology,on bipolar technology,
IGBT has an
IGBT has an intrinsically
intrinsically negative
negative thermal
thermal coefficient
coefficient because
because higher
higher temperature
temperature helps helps
increase the minority carriers’ capacity, effectively increasing the conduction.
increase the minority carriers’ capacity, effectively increasing the conduction. The modern The modern
manufacturers
manufacturers of of the
thepower
powerIGBT IGBTand anddiodes
diodesaddadda aresistive
resistive thermal
thermal positive
positive channel
channel to
create a net
to create effect
a net of positive
effect of positivethermal coefficient,
thermal allowing
coefficient, paralleling
allowing parallelingof IGBT dies with
of IGBT dies
diodes [9].
with diodes [9].
Nowadays,
Nowadays, large large power
power modules
modules (Figure
(Figure 5)5) are
are the
the designer’s
designer’s first
first tool
tool for
for producing
producing
aa sizeable
sizeable current
current converter. A large module can be built with up to five or six
converter. A large module can be built with up to five or six dies
dies per
per
device. The next step for low-frequency PWM converters is
device. The next step for low-frequency PWM converters is the arrangement of power the arrangement of power
modules in parallel. A good good self-balanced
self-balanced design allows up to to four
four oror five
five power
power modules;
modules;
larger quantities
quantities of ofmodules
modulesrequire
requireactive
activegating.
gating.TheTheunbalanced
unbalanced currents
currents happen
happen dur-
during
ing conduction
conduction and switching.
and switching. Logically,
Logically, balancingbalancing
control is control is moreduring
more difficult difficult during
switching.
switching.
Some authors Some authors
[10–15] [10–15]active
propose propose active balancing
balancing control ascontrol as a solution,
a solution, especially especially
for con-
for converters with high-frequency PWM where switching
verters with high-frequency PWM where switching power losses become dominant. power losses become domi-To
nant.
achieveTohigher
achieve higher with
currents currents
a good with a good performance
performance after the
after the number ofnumber
modulesofinmodules
parallel
in parallelout,
is maxed is maxed
the nextout,step
the of
nextthestep of theis
solution solution is toin
to connect connect
parallel in active
parallel activebridges
control control
bridges or converters.
or converters. SSSCs haveSSSCs have particular
particular advantages
advantages that canthat can be exploited
be exploited to connectto connect
a large
anumber of converters
large number in parallel,
of converters and thisand
in parallel, is the
thiscentral
is the contribution of this work.
central contribution of this work.

Figure 5. Modules
Figure 5. Modules as
as single
single dies
dies paralleling.
paralleling. Panel
Panel 11 on
on the
the left
left are
are the
the IGBTs and Module.
IGBTs and Module. Panel
Panel 22
on the right are the MOSFETs.
on the right are the MOSFETs.

4. Single Pulse Analysis of SSSC

Another way that the SSSC can be understood is as a variable impedance that behaves
as capacitive or inductive, depending on whether the voltage applied to the line is leading
or lagging the current. To simplify the explanation, we will use a single pulse injection that
presents harmonics related to the pulse’s width, defined by the firing angle α. A simple
 4. Single Pulse Analysis of SSSC
Another way that the SSSC can be understood is as a variable impedance that be-
Energies 2022, 15, 4666
haves as capacitive or inductive, depending on whether the voltage applied to the line is
6 of 16
leading or lagging the current. To simplify the explanation, we will use a single pulse
injection that presents harmonics related to the pulse’s width, defined by the firing angle
α. A simple way to reduce harmonics is to find α that provides the same area below and
way
aboveto the
reduce harmonics
sinusoidal wave.isThis
to find α thatisprovides
concept the
illustrated in same
Figurearea
6. below and above the
sinusoidal wave. This concept is illustrated in Figure 6.

I(t)
V(t)

A2

Vp
A1
32.70
π−α π
α Same area
A1=A2
α=(π/2)-1= 32.7o

Figure6.6.Square
Figure Squarevoltage
voltageinjection
injectionand
andequalized
equalizedarea
areafor
forharmonics
harmonicscontent
contentminimization.
minimization.

Foraagiven
For givenfiring
firingangle
angle(α),
(α),the
thefirst
firstharmonics
harmonicsof ofthe
thefundamental
fundamentalvoltage
voltageinjection
injection
canbe
can becalculated
calculatedas:
as:
2 π −α
Z
VAC1 = 2·VP sin (ωt)d(ωt) (3)
𝑉 π = α 2 ∙ 𝑉 sin (𝜔𝑡)𝑑(𝜔𝑡) (3)
By ◦
Bythe
thesame
samearea
areacriteria,
criteria,angle
angleααisiscalculated
calculatedto tobe
be32.7
32.7°,, generating
generatingaafirst
firstharmonic
harmonic
of 1.07 V
of 1.07 V P P, yielding 7% of overmodulation and total harmonic content of less one-third,
, yielding 7% of overmodulation and total harmonic content of less than than one-
which
third, is a relatively
which small THD
is a relatively small(Total
THD Harmonic Distortion),
(Total Harmonic with verywith
Distortion), low very
zero-sequence
low zero-
harmonics
sequence harmonics such as 3rd and 9th harmonics. The maximum injection of
such as 3rd and 9th harmonics. The maximum injection possible the first
possible of
harmonic with α equal to zero produces an overmodulation of 4/π (1.27)
the first harmonic with α equal to zero produces an overmodulation of 4/π (1.27) with with respect to
the capacitor voltage, but with one-third of the 3rd harmonic.
respect to the capacitor voltage, but with one-third of the 3rd harmonic.
The SSSC energy storage is a capacitor limited to a few millifarads; consequently, the
The SSSC energy storage is a capacitor limited to a few millifarads; consequently, the
voltage of the capacitor does not remain constant. It decreases if the current is leaving or
voltage of the capacitor does not remain constant. It decreases if the current is leaving or
increases if the current fills the capacitor. The depletion of the voltage happens when the
increases if the current fills the capacitor. The depletion of the voltage happens when the
inverter is behaving as an inductor; the voltage increase happens when it is behaving as
inverter is behaving as an inductor; the voltage increase happens when it is behaving as a
a capacitor. Regardless of behavior, capacitive or inductive, the initial and final capacitor
capacitor. Regardless of behavior, capacitive or inductive, the initial and final capacitor
voltage needs to be the same to maintain steady-state operation. Figure 7 shows the
voltage needs to be the same to maintain steady-state operation. Figure 7 shows the
“bumping” of the injected AC voltage that can be concave for capacitive injection and
“bumping” of the injected AC voltage that can be concave for capacitive injection and
convex for inductive injection. The concave or convex shape generates different harmonics
Energies 2022, 15, x FOR PEER REVIEW 7 of 17
convex for inductive injection. The concave or convex shape generates different harmon-
content, with the capacitive injection producing less harmonic content. The first harmonics
icsthe
in content, with the are
two conditions capacitive
shown injection
in Figure producing
7. less harmonic content. The first har-
monics in the two conditions are shown in Figure 7b.

DC capacitor Voltages Actual AC voltages

Eo ILpeak
E C.ω

I(t) First Harmonics

Injected

π−α π α
α Inductive

Eo
ILpeak
E
C.ω
Average Capacitor = E -/+ bump
Eo Capacitive

Figure
Figure 7.
7. Concave
Concaveor
orconvex
convex shape
shape of
of the
the voltage
voltage depending
depending on
on inductive
inductive or
or capacitive
capacitive mode.
mode.

A set of Equations (4)–(7) is derived for sizing purposes to compute the first harmon-
ics and the relation with the average capacitor voltages. The equation below shows VAC1
(first harmonic) the relation of line current (IL), firing angle (α), and the initial and final
voltage of the capacitor (E). E is defined as open capacitor voltage.
Energies 2022, 15, 4666 7 of 16

A set of Equations (4)–(7) is derived for sizing purposes to compute the first harmonics
and the relation with the average capacitor voltages. The equation below shows VAC1 (first
harmonic) the relation of line current (IL ), firing angle (α), and the initial and final voltage
of the capacitor (E). E is defined as open capacitor voltage.
For capacitive mode.
 
2 IL
VAC1 = 2.E.cos(α) + (π − 2α − sin(2.α)) (4)
π 2.C.ω

The average voltage on the capacitor is shown in the equation,

√
2 VRMS π − 2α − sin(2.α)
 
π I 1
VDC = + L + 2sin(α) − (5)
4cos(α) 2.C.ω 2cos(α) π

For inductive mode,

 
2 IL
VAC1 = 2.E.cos(α) − (π − 2α − sin(2.α)) (6)
π 2.C.ω
√
2 VRMS π − 2α − sin(2.α)
 
π I 1
VDC = − L + 2sin(α) − (7)
4cos(α) 2.C.ω 2cos(α) π

5. Static Series Synchronous Compensator (SSSC) Principle

The fundamental principle of the proposed topology is based on the capacitor as the
only energy source. Capacitors connected in parallel share the same voltage. For this reason,
the only factor that determines their current is the value of their capacitances. Therefore,
SSSC converters in parallel in the architecture presented in Figure 4a, are naturally self-
balanced (see Equation (8) below). For standard converters, the power is fed by a voltage
source that does not have intrinsic regulation of the current that takes different paths
based on each path’s impedance. For this reason, a voltage source converter needs active
Energies 2022, 15, x FOR PEER REVIEW 8 of 17
compensation to balance the current for each converter in parallel. Details of the self-
balancing SSSC are explained in Figure 8.

Figure 8. Self-balancing Principle.

Figure 8. Self-balancing Principle.

InFigure
In Figure8,8,the
thepower
powerline
lineisisrepresented
representedas asaacurrent
currentsource
source(I(ILL),), and
and the
the two
two con-
con-
verters (inverters) at any given moment can be represented as a capacitor
verters (inverters) at any given moment can be represented as a capacitor (C1 and/or C2) (C1 and/or C2)
connected through a small impedance, representing the power
connected through a small impedance, representing the power semiconductor switches’semiconductor switches’
impedance during
impedance during conduction
conduction (R (RDSON
DSON ) )plus
plusthe
thebus
busbar and
bar and itsits
connections,
connections, which
whichis the
is
lumped
the lumped impedance
impedance defined as Zas
defined IGBTZat each
IGBT at converter.
each It is
converter. clear
It isthese
clear equivalent
these imped-
equivalent
ances are not
impedances arelinear and have
not linear a higha dependency
and have high dependency on temperature,
on temperature, and may significantly
and may signifi-
differ differ
cantly from from
one toone another. However,
to another. However, the voltage drops
the voltage across
drops acrossthem
them areare
quite
quitesmall
smallas
compared to the capacitor voltage at line frequencies,
as compared to the capacitor voltage at line frequencies, so so the capacitor voltage tends
voltage tends to to
dominatethe
dominate thecurrent
currentsharing
sharingasasseen
seenbelow.
below.
For any capacitor:

𝑉 = 𝐼(𝑡)𝑑𝑡

Per Kirchhoff’s law:

Energies 2022, 15, 4666 8 of 16

For any capacitor:

1
Z
VC = I (t)dt
C
Per Kirchhoff’s law:

VC1 + IC1 Z IGBT1 = VC2 + IC2 Z IGBT2

Since the IGBT impedances during conduction are very small:

VC1 and VC2  IC1 Z IGBT1 and IC2 Z IGBT2 for f < 100 Hz
Then,
1 1
Z Z
VC1 = VC2 = IC1 (t)dt = IC2 (t)dt (8)
C1 C2
The self-balancing methodology consists of simply ensuring the same voltage in the
capacitor banks, mainly by utilizing the same capacitance value C1 = C2 for each converter.
Consequently, the current IC1 and IC2 will be the same, and, therefore, half of the line
current. This principle is extensible to many inverters in parallel (Figure 4a), and as long
the capacitors are the same, the current will be distributed equally among the converters.
Any slight difference in the capacitor banks will be reflected in current differences, which is
the only practical limitation of this application.

6. SSSC Self-Current Balancing Network Equalizer

When the capacitors are in parallel, the value of the capacitances defines the current, as
was discussed before. However, the capacitors are connected and disconnected at the PWM
frequency by the inverter. After the capacitors are disconnected, they may not have the
same voltage anymore. In addition, when reconnected, they may not connect at precisely
the same time, allowing a discharge of the first capacitor that is connected, changing its
voltage. This condition generates two problems that are analyzed here.
• When the capacitors are disconnected: The voltages of independent capacitor banks
can drift differently because of different internal losses and, more critically, if the
disconnection did not happen precisely at the same time (a small difference in turn-
off time), then the last converter capacitor bank to be disconnected loses or gains
additional charge, leading to different voltage among the now-disconnected capacitor
banks from each converter.
• When capacitors are reconnected: Even if the disconnected capacitor banks have the
same voltage, when they are reconnected, different delays in switching to connection (a
small difference in turn-on time) will cause the first converter capacitor bank connected
to charge or discharge to a voltage different than the second converter capacitor
bank connected.
In both cases, it produces different voltages in the capacitor banks during reconnec-
tion, which will create ultra-high circulating currents on the order of tens to hundreds
of thousands of amperes between the capacitors. This is because the busbars and the
power modules only offer a few nanohenries of inductance to limit the di/dt between the
capacitors. This destroys the converter or ages it very quickly. To avoid the described
problems, the following two equalizer circuits are designed:
The resistive network equalizer whose role is to ensure very similar voltages when
the capacitors are disconnected. The resistance of the network equalizer needs to be large
enough compared to the Ron of the semiconductors but low enough to equalize the voltage
of the capacitors.
The criterion is,
R equalizer > 100 Ron semiconductor (9)
The differential-mode chokes are inductors (L) that function to limit the current that
can occur due to the differences in the turn-on and turn-off among the semiconductors
within each converter.
Energies 2022, 15, 4666 9 of 16

Differences in semiconductors’ turn-on and turn-off times are due to slight differences
during the manufacturing process and are accentuated as semiconductors’ aging takes
place. Different usages, such as in the example in Figure 4b, where each of the SSSCs in
series has different conduction times, imply that the IGBTs will not age at the same rate
Energies 2022, 15, x FOR PEER REVIEW
over time [16,17]. 10 of 17
These inductors are small, on the order of several of microhenries, and the criterion
for how to dimension them is explained below.
The criterion
completely is:
or partially on. This situation can lead to a shoot-through wherein the di/dt is
V
only being controlled by the bus bars’Lsmall= Linductance.
∆t To prevent a rapid current(10)
in-
∆I
crease, an alternate inductor L is added to the topology, enabling di/dt control.
where:Figure 9b shows four inductors L between the two inverters. Generally, all inductors
haveVthe
L = same
Module nominal
value. voltage; of L can be carried out based on:
The selection
∆I = Line current;
(a) the DC bus voltage level
∆t = 50% of the semiconductor turn-off time.
(b) the time when the two switches are inappropriately connected (typical worst-case
The general goal of the power systems industry is to connect multiple IGBTs in parallel
switching transient overlap between the top and bottom switches), and
(Figure 9a) to achieve higher continuous current conduction ratings. As discussed in the
(c) the transient current handling capability of the IGBTs selected.
previous section, paralleling of H-bridges (Figure 4a) in addition to IGBTs, gives extra
The inductors can be split into two to make the design of both inverter units identical
advantages over only paralleling IGBTs directly, but presents some challenges previously
to each other. The specification of L is denoted in Equation (10),
introduced and further reviewed below.

Figure9.9.Embedding
Figure Embedding paralleling
paralleling strategy from dices to modules
modules to
to converters
converters with
withinductive
inductiveand
and
resistivebalancing
resistive balancingnetwork
network(R (R and
and L).L). (a)
(a) Four
Four parallel
parallel modules
modules form
form one
one IGBT;
IGBT; (b)
(b) One
One converter
converter
leg(red
leg (reddotted
dottedline
lineon
onpanel
panel(b))
b) isisformed
formedby byfour
fourmodules
modulesasasindicated
indicatedin
intop
topportion
portionof
ofpanel
panela,(a),
or
bottom circuit diagram of panel
or bottom circuit diagram of panel (a).a

The
In theequalizer networks
ideal case, can be are
two inverters extended toconnected
directly more thanat two converters.
their In contrast,
AC terminals, whereasthe
two inductors
their capacitor L and the terminals
terminals of theinconverter
are connected parallel. can be generalized
In real circuits the in the same
capacitor fashion
voltages
for multiple
could converters
be different, in parallel,
generating butcurrent;
a large in the case of thethis
to limit resistors R, both
current, the network needs
converters area
special geometrical
connected arrangement.
through resistances Figure
R (see 10 shows
Figure 9b). Thehow the network
purpose equalizer
of having is extended
R in the circuit is
toequalize
to three and five
the DCconverters in parallel.
voltage that develops across the capacitors C1 and C2 before and after
voltage injection. Adding resistor R, as in Figure 9b, mitigates the effect resulting when all
the IGBTs in parallel inverters perform differently during transient; i.e., they turn on and
off at different times. The selection of the value of R is described in Equation (9).
The second problem introduced in the previous section occurs when there are different
turn-on and turn-off times across the IGBTs, which can create a shoot-through. To explain
this further, let’s consider the example where the positive and negative rails of the DC bus
are connected in transients when T11 and T42 (from Figure 9b) are either completely or
Energies 2022, 15, 4666 10 of 16

partially on. This situation can lead to a shoot-through wherein the di/dt is only being
controlled by the bus bars’ small inductance. To prevent a rapid current increase, an
alternate inductor L is added to the topology, enabling di/dt control.
Figure 9b shows four inductors L between the two inverters. Generally, all inductors
have the same value. The selection of L can be carried out based on:
(a) the DC bus voltage level,
Figure(b)9.the
Embedding paralleling
time when the twostrategy from
switches aredices to modules toconnected
inappropriately converters(typical
with inductive and
worst-case
resistive balancing network (R and L). (a) Four parallel modules form one IGBT; (b) One converter
switching transient overlap between the top and bottom switches), and
leg (red dotted line on panel b) is formed by four modules as indicated in top portion of panel a, or
(c) the transient current handling capability of the IGBTs selected.
bottom circuit diagram of panel a
The inductors can be split into two to make the design of both inverter units identical
to each other. The specification of L is denoted in Equation (10).
The equalizer networks can be extended to more than two converters. In contrast, the
The equalizer networks can be extended to more than two converters. In contrast, the
two inductors L and the terminals of the converter can be generalized in the same fashion
two inductors L and the terminals of the converter can be generalized in the same fashion
for multiple converters in parallel, but in the case of the resistors R, the network needs a
for multiple converters in parallel, but in the case of the resistors R, the network needs a
special geometrical arrangement. Figure 10 shows how the network equalizer is extended
special geometrical arrangement. Figure 10 shows how the network equalizer is extended
to three and five converters in parallel.
to three and five converters in parallel.

Figure 10. Resistive equalizer networks for three and five inverter networks. (a) Detailed three
converters in paralleling; (b) Simplified view of five converters in paralleling.

7. Results from Analyses and Simulations

The analysis performed for the SSSC is validated by the simulation with PSIM, ac-
cording to the diagram in Figure 11. The IGBTs assume 1200 V nominal, setting the design
limit to the capacitor’s (DC) voltages at 800 V; consequently, the maximum nominal voltage
without overmodulation is 560 Vrms. The two converters (S1 and S2) carry half of the line
current set at 2000 A rms. The network equalizer parameters are defined as R and L. The
parameters are set and defined in Table 1.

7.1. Single-Pulse Validation Analysis

The single pulse of the voltage injected for capacitive and inductive modes with a
firing angle of 32.7◦ is shown in Figure 12a,b, respectively. The maximum operating voltage
of the capacitors is set at 800 V as a requirement for protecting the power semiconductors
(1200 V). Due to its convex form, the capacitor voltage has an “open” voltage (E) set below
the maximum capacitor voltage allowed (800 V), giving space to grow inside a safe area of
operation. In contrast, the inductive mode depletes the capacitor that exhibits the convex
form and defines the open or not connected voltage (E) as the maximum voltage of the
system. This process is expected because “electrical energy” accumulated in the capacitor
must be transformed or mimic a “magnetic energy” to behave as an inductor. In Figure 12,
the capacitive wave is closer to the sinusoidal shape than the inductive injection for a
similar reason to the explanation above.
 7. Results from Analyses and Simulations
The analysis performed for the SSSC is validated by the simulation with PSIM, ac-
cording to the diagram in Figure 11. The IGBTs assume 1200 V nominal, setting the design
limit to the capacitor’s (DC) voltages at 800 V; consequently, the maximum nominal volt-
age without overmodulation is 560 Vrms. The two converters (S1 and S2) carry half of the
Energies 2022, 15, 4666 11 of 16
line current set at 2000 A rms. The network equalizer parameters are defined as R and L.
The parameters are set and defined in Table 1.

Figure 11. Two SSSC converters diagram.

Figure 11. Two SSSC converters diagram
Table 1. Parameter.
Table 1. Parameter.
Parameter
Parameter
VC 800 V
VC MaxMax Pick
Pick
800 V
IGBT Nominal Voltages 1200 V
IGBT Nominal
RDS ON Voltages 1 mΩ1200 V
RDSLON (equalizer inductance) 1 µH1 mΩ
R (equalizerinductance)
L (equalizer resistance) 10 Ω1 μH
Firing Angle (α) 32.7o
R (equalizer resistance) 10 Ω
I line 2000 A RMS
Firing Angle (α)
I converter (IS1 = IS2 ) 1000 A RMS32.7o
I line
Capacitor Bank (C1 = C2 ) 2000
10 mf A RMS
Reactive Power
I converter (IS1 = IS2) (injected) 1 MVAR
1000 A RMS
Capacitor Bank (C1 = C2) 10 mf
Reactive The voltage injected for the first harmonic approximationMVAR
Power (injected) 1 and presented in
Equations (4) and (6) is compared using several open voltages (E). The open voltages are
7.1.varied
Single-Pulse
from 300 Validation
to 800 V,Analysis
and three conditions are calculated for injection capacitive (CAP)
and inductive (IND) modes.
The single pulse of the voltage The first condition
injected consists ofand
for capacitive computing
inductivethe first harmonic
modes with a
of the injected RMS voltage by using Equations (4) and (6), which
firing angle of 32.7° is shown in Figure 12a,b, respectively. The maximum operating is denoted as volt-
IND-F
ageand ofCAP-F for inductive
the capacitors andatcapacitive
is set 800 V as first
a harmonic voltage,
requirement respectively.the
for protecting The second
power
condition consists of determining the same first harmonic but computed by simulation (S1),
where the capacitive and inductive first harmonic voltages are denoted CAP-S1 and IND-S1,
respectively. The last condition uses PSIM as well, to compute the total RMS of the injected
wave that includes all the harmonics generated for the no sinusoidal shape and is defined as
CAP-RMS and IND-RMS as total harmonics capacitive or inductive voltage, respectively.
Figure 13 compares the formula results with the simulation. As can be seen, both
results are nearly the same, mainly because the simulation does not have an ideal capacitor,
bus bar, and IGBTs with an RDSon of 1 ohm, but it includes its parasitic component. These
results validate the derivation of the relationship between E and the injected AC voltage.
They provide an important tool for setpoint in open-loop control and design in general.

Energies 2022, 15, 4666
grow inside a safe area of operation. In contrast, the inductive mode depletes the capacitor
that exhibits the convex form and defines the open or not connected voltage (E) as the
maximum voltage of the system. This process is expected because “electrical energy” ac-
cumulated in the capacitor must be transformed or mimic a “magnetic energy” to behave
as an inductor. In Figure 12, the capacitive wave is closer to the sinusoidal shape
12 ofthan
16 the
inductive injection for a similar reason to the explanation above.

IS1 V_AC_Injected IS1 V_AC_Injected

1.5k 1.5k
1k
500
(a) 1k
500
(b)
0 0
-500
-500
-1k
-1k
-1.5k
-1.5k

Voltage_DC_C1 Voltage_DC_C1
900 Time (s) 900 Time (s)
800 800
700 700
600 600
500 500
400 400
300 300
0 10m 20m 30m 40m 50m 0 10m 20m 30m 40m 50m
OR PEER REVIEW Time (s)
1 2 13 of 17
Time (s)

Figure 12.12.
Figure PSIM output
PSIM outputvoltage
voltage and currentfor
and current for(a)(a)capacitive;
capacitive;
(b) and (b) inductive
inductive injection mode.
injection mode.

The voltage injected for the first harmonic approximation and presented in Equations
(4) and (6) is compared using several open voltages (E). The open voltages are varied from
300 to 800 V, and three conditions are calculated for injection capacitive (CAP) and induc-
tive (IND) modes. The first condition consists of computing the first harmonic of the in-
jected RMS voltage by using Equations (4) and (6), which is denoted as IND-F and CAP-
F for inductive and capacitive first harmonic voltage, respectively. The second condition
consists of determining the same first harmonic but computed by simulation (S1), where
the capacitive and inductive first harmonic voltages are denoted CAP-S1 and IND-S1, re-
spectively. The last condition uses PSIM as well, to compute the total RMS of the injected
wave that includes all the harmonics generated for the no sinusoidal shape and is defined
as CAP-RMS and IND-RMS as total harmonics capacitive or inductive voltage, respec-
tively.
Figure 13 compares the formula results with the simulation. As can be seen, both
results are nearly the same, mainly because the simulation does not have an ideal capaci-
tor, bus bar, and IGBTs with an RDSon of 1 ohm, but it includes its parasitic component.
These results validate the derivation of the relationship between E and the injected AC
voltage. They provide an important tool for setpoint in open-loop control and design in
general.
Figure 13. Comparison of the
Figure
Another first harmonics
13. Comparison
critical aspect and
of the first totalresults
harmonics
of these Vrms
and by simulation
total Vrms
is that byRMS
the and theoretical
simulation
value and calcula-
is theoretical calculation
very similar to the first
tion in capacitive andininductive mode.
capacitive and inductive mode.
harmonics, denoting a low harmonic content; it is very low for the capacitor, reaching only
3%, while for inductive
Another mode,
critical aspect it is slightly
of these results ishigher,
that thereaching
RMS value10% on average.
is very similar toThe
the capacitor
first
7.2. Self-Balancingmode
and Network
can inject Equalizer
about 12% under
more Time Delay
reactive powerin Semiconductor
than the inductive injection
harmonics, denoting a low harmonic content; it is very low for the capacitor, reaching only can.
The proposed3%, while for inductive
self-balanced system mode, it is slightly
is tested at a higher,
low PWM reaching 10% on average.
switching The capacitor
frequency of
mode can inject about 12% more reactive power than the inductive
360 Hz, and its simulation is shown Figure 14a. Top plots of this figure show the inductive injection can.

voltage injected and half

7.2. of line current
Self-Balancing in order
and Network to provide
Equalizer under Timea better
Delay inscale for voltage com-
Semiconductor
parison. The middle plot The shows
proposed that the two currents
self-balanced of theatconverters
system is tested IS1 and-IS2
a low PWM switching are of
frequency
identical. For illustration
360 Hz, purposes, the Converter
and its simulation 2 current
is shown Figure is shifted
14a. Top 180o
plots of this to avoid
figure super-
show the inductive
voltage injected and half of line current in order to provide
position with the Converter 1 current. The bottom panel displays the circulating current a better scale for voltage
comparison. The middle plot shows that the two currents of the converters IS1 and IS2
(ICIR) as zero, confirming full balance operation.
are identical. For illustration purposes, the Converter 2 current is shifted 180o to avoid
To verify the superposition
effectivenesswith of the self-balance
the Converter mechanisms,
1 current. The bottom Converter
panel displays2 (S2)
the is as-
circulating
signed with 20% more currentimpedance
(ICIR) as zero,across all itsfull
confirming components, including RDSON from all
balance operation.
IGBTs, the bus bar, and the capacitors’ internal parasitic impedances. Figure 14b shows
that even after increasing all Converter 2 parameters by 20%, the dominant effect of the
capacitor bank is that it creates a very similar current in both converters, with a difference
of less than 2%, showing the effectiveness of the proposed technology, independent of
natural differences in converters due to manufacturing and aging. Note that the circuit
Energies
Energies2022,
2022,15,
15,x4666
FOR PEER REVIEW 1413ofof17
16

V_AC_Injected ILine/2 V_AC_Injected ILine/2

1k 1k
A
0 0
V
-1k -1k

IS1 IS2*(-1) IS1 IS2*(-1)

Time (s) Time (s)
1k 1k

A 0 0

-1k -1k

Icir Icir
Time (s) Time (s)
2.5
40n

A 0 0
-40n
-2.5
0 10m 20m 30m 40m 50m 0 10m 20m 30m 40m 50m

(a) Time (s) (b) Time (s)

V_AC_Injected ILine/2
V_AC_Injected ILine/2
1k
1k
A 0
0
V -1k
-1k

IS1 IS2*(-1) IS1 IS2*(-1)

Time (s) Time (s)

1k 1k

0 0
2020-02-14 SWG-063
A -1k -1k

Icir Icir
Time (s) Time (s)
40
2
0 0

-2 -40
A
0 10m 20m 30m 40m 50m 0 10m 20m 30m 40m 50m
(c) Time (s) (d) Time (s)

Figure14.
Figure Outputsof
14.Outputs ofthe
thesystem
systemwith:
with:(a)
(a)two
twoidentical
identicalconverters;
converters;(b)
(b)Converter
Converter22with
with20%
20%higher
higher
impedancethan
impedance thanconverter
converter1;1;(c)
(c)20%
20%different
differentcapacitors’
capacitors’banks;
banks;(d)
(d)10%
10%different
differentcapacitors’
capacitors’bank
bank
and
and11us
usIGBTs’
IGBTs’ time
time delay.
delay.

To verify
The the effectiveness
simulation in Figure 15ofisthe self-balance
a repetition ofmechanisms, Converter
Case (d) from Figure 142 without
(S2) is assigned
R and
L, which means R is infinite (open circuit), and L is zero (short circuit) to show the IGBTs,
with 20% more impedance across all its components, including RDSON from all effec-
the bus bar,
tiveness and
of the the capacitors’
proposed internal
balancing parasitic
network. impedances.
The results shownFigure 14b15
in Figure shows that even
demonstrates
afterthe
that increasing
current in alleach
Converter 2 parameters
converter grows over by2520%,
kA,the
anddominant
the IGBTseffect
are of the capacitor
subject to over
bank is that it creates a very similar current in both converters,
voltages close to 2 kV; thus, both conditions will destroy the IGBTs. with a difference of less
than 2%, showing the effectiveness of the proposed technology, independent of natural
differences in converters due to manufacturing and aging. Note that the circuit current
(ICIR) is less than 200 mA. Figure 14c shows the unbalances in the capacitor banks when
they are 20% different, with C1 = 10 mF and C2 = 8 mF. The capacitors’ proportional
difference is transferred to the current, but the parallel converters work in a stable fashion.
The current IS1 increases by 10%, and IS2 reduces by the same amount, accounting for a
total of 20% variation between the capacitances. The circulating current (ICIR) grows to 1.5
A, demonstrating a stable system. The three previous examples indicate how the circulating
current can be used as feature indicator of premature aging of the capacitor banks.
Energies 2022, 15, 4666 14 of 16

A more demanding test is combining two major unbalanced conditions. The first is
a 10% difference in the capacitor banks, setting C1 = 10 mF and C2 = 9 mF, and, more
critically, the second is a forced 1 us delay in the turn-on command of IGBTs T11 and T21 in
Converter 1. Figure 14d shows that the current of each converter becomes distorted, but
in a nearly balanced and complementary fashion. The only unbalance is in proportion to
the corresponding differences in the capacitors’ bank and the transient unbalance due to
the switching delay that is reduced by the equalizer network. The circulating current, ICIR ,
shows a fast peak of 40 A. and an RMS value less than 8 A.
The simulation in Figure 15 is a repetition of Case (d) from Figure 14 without R and L,
which means R is infinite (open circuit), and L is zero (short circuit) to show the effectiveness
of the proposed balancing network. The results shown in Figure 15 demonstrates that
Energies 2022, 15, x FOR PEER REVIEW 15 ofthe
17
current in each converter grows over 25 kA, and the IGBTs are subject to over voltages
close to 2 kV; thus, both conditions will destroy the IGBTs.

V_AC_Injected ILine/2
2k

1k

-1k

IS1 -IS2
Time (s)
20k

10k

-10k

-20k

0 10m 20m 30m 40m 50m

Time (s)

Figure 15. Repetition of case (d) from Figure 14 without balancing network.

7.3. Network Equalizer Components Tolerance Evaluation

7.3. Network Equalizer Components Tolerance Evaluation
The network equalizer tolerance to variation in its components is evaluated under
The network equalizer tolerance to variation in its components is evaluated under
changes of 50% of its set of resistances (R) and inductances (L) values. Four unbalanced
changes of 50% of its set of resistances (R) and inductances (L) values. Four unbalanced
SSSC converters with the corresponding network equalizers were simulated (doubling
SSSC converters with the corresponding network equalizers were simulated (doubling
the system in Figure 11). For two of the SSSC converters as illustrated in Figure 11, the
the system in Figure 11). For two of the SSSC converters as illustrated in Figure 11, the
simulated network equalizer consisted of a perfect equalizer with two resistors of 10 ohms
simulated network equalizer consisted of a perfect equalizer with two resistors of 10 ohms
and four inductances of 1 uH. For the other two unbalanced SSSC converters the network
and four inductances of 1 uH. For the other two unbalanced SSSC converters the network
equalizer was unbalanced by varying its resistances by 50%, which was achieved by leaving
equalizer was unbalanced
the top resistor R1 = 10 ohm byand
varying its resistances
increasing the bottomby to
50%,
R2 which was achieved
= 15 ohms. by leav-
Similar variation
ing the top resistor R1 = 10 ohm and increasing the bottom to R2 = 15 ohms.
was applied to the inductances of the second pair of SSSC converters, augmenting their Similar vari-
ation was
value fromapplied
1 to 1.5to uH.
the inductances
The top plotofinthe second
Figure 16pair of SSSC
shows converters,inaugmenting
the difference circulating
their value from 1 to 1.5 uH. The top plot in Figure 16 shows the difference
current between the two pair of SSSC converter, which is very small. The RMS in circulating
value of
current between
the difference the two
is less thanpair
1.25of
ASSSC
underconverter,
currents ofwhich
1000isAvery
rms.small.
TheseThe RMSverify
results valuethe
of
the difference is less than 1.25 A under currents of 1000 A rms. These results
effectiveness and robustness of the equalizing system, and its high tolerance for network verify the
effectiveness
resistance andand robustness
inductance of the equalizing system, and its high tolerance for network
variations.
resistance and inductance variations.
Energies 2022, 15, x FOR PEER REVIEW
4666 1615of
of 17
16

Icir1-Icir3
15
10
5
0
-5
-10
-15
IS1 IS3
2k Time (s)

1k
0
-1k
-2k
IS1-IS3
80 Time (s)

40
0
-40
-80
0 10m 20m 30m 40m 50m
Time (s)

Figure
Figure 16. Evaluation
Evaluation of
of the
the network
network equalizer
equalizer tolerance to variation.

8. Conclusions
8. Conclusions
The viability
The viability of
of the
the scalable
scalable architecture
architecture to
to alleviate
alleviate and
and improve
improve congested
congested power
power
transmission lines based on a modular transformerless self-balanced SSSC
transmission lines based on a modular transformerless self-balanced SSSC (TSB-SSSC) is (TSB-SSSC)
is proposed
proposed andand validated
validated by simulation.
by simulation. An inductive
An inductive and resistive
and resistive equalizer
equalizer network
network com-
compensates for the unsymmetric operation of each converter caused by
pensates for the unsymmetric operation of each converter caused by manufacturing pro-manufacturing
process,
cess, aging,
aging, and/or
and/or semiconductor
semiconductor gating
gating delays.The
delays. Thenetwork
networkequalizer’s
equalizer’sfundamental
fundamental
operation principles are described, and criteria for resistive and inductive components’
operation principles are described, and criteria for resistive and inductive components’
selection and
selection and arrangement
arrangementare areestablished.
established.The
Themathematical
mathematicalanalysis forfor
analysis one pulse
one voltage
pulse volt-
injection for inductive and capacitive mode was demonstrated and verified in simulations.
age injection for inductive and capacitive mode was demonstrated and verified in simu-
lations.
Funding: This research received no external funding.
Institutional
Funding: ThisReview Board
research Statement:
received Not funding.
no external applicable.
Informed Consent
Institutional Statement:
Review Not applicable.
Board Statement: Not applicable.
Informed Statement:Not
ConsentStatement:
Data Availability Notapplicable.
applicable.
Data Availability Statement:
Acknowledgments: Notthanks
The author applicable.
Govind Chavan for his contribution on the symmetrical
arrangement of the inductor equalizer network, and him and Shreesha Adiga Manoor for their time
Acknowledgments: The author thanks Govind Chavan for his contribution on the symmetrical ar-
discussing the presented architecture. Thanks to Haroon Inam for his vision, leadership, and support
rangement of the inductor equalizer network, and him and Shreesha Adiga Manoor for their time
in this project, and lastly, many thanks to technical writer Bridget Heneghan for her excellent editing
discussing the presented architecture. Thanks to Haroon Inam for his vision, leadership, and sup-
of this work.
port in this project, and lastly, many thanks to technical writer Bridget Heneghan for her excellent
editing
Conflictsof of
this work. The author declares no conflict of interest.
Interest:
Conflicts of Interest: The author declares no conflict of interest.
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