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5 4 3 2 1

RK3588S(Power&Gnd)

U1000S
VDD_GPU_S0 VDD_CPU_BIG0_S0

GPU CPU_BIG0
AH18 M24 VDD_CPU_BIG0_S0
VDD_GPU_S0 VDD_GPU_1 VDD_CPU_BIG0_1
AH19 M25
C1006 C1000 C1070 C1071 C1072 C1001 C1007 AH20 VDD_GPU_2 VDD_CPU_BIG0_2 M28
C1087 47uF 1uF 1uF 1uF 100nF 100nF 100nF AH21 VDD_GPU_3 VDD_CPU_BIG0_3 M29 C1009 C1003 C1073 C1074 C1002 C1075 C1008 C32 C33 C34 C35

1
D C8 C29 C30 C31 VDD_GPU_4 VDD_CPU_BIG0_4 D
C1050 C1051 22uF X5R X5R X5R X5R X5R X5R X5R AJ19 M30 100nF 100nF 100nF 1uF 1uF 1uF 47uF C1052 C1053 100nF 1uF 1uF 1uF

1
100nF 1uF 1uF 1uF VDD_GPU_5 VDD_CPU_BIG0_5
1

1
22uF 22uF X5R 6.3V 4V 4V 4V 10V 10V 10V AJ20 N24 X5R X5R X5R X5R X5R X5R X5R 22uF 47uF X5R X5R X5R X5R
X5R X5R X5R X5R VDD_GPU_6 VDD_CPU_BIG0_6

2
X5R 10V X5R 10V 6.3V C0603 C0201 C0201 C0201 C0201 C0201 C0201 AJ21 N25 10V 10V 10V 4V 4V 4V 6.3V X5R 10V X5R 10V 10V 4V 4V 4V
10V 4V 4V 4V VDD_GPU_7 VDD_CPU_BIG0_7

2
C0603 C0603 C0603 AK21 P23 C0201 C0201 C0201 C0201 C0201 C0201 C0603 C0603 C0603 C0201 C0201 C0201 C0201
2

2
C0201 C0201 C0201 C0201 VDD_GPU_8 VDD_CPU_BIG0_8
AL21 R23
AM21 VDD_GPU_9 VDD_CPU_BIG0_9 R24
AM22 VDD_GPU_10 VDD_CPU_BIG0_10
AN21 VDD_GPU_11 K27
AN22 VDD_GPU_12 VDD_CPU_BIG0_MEM_1 K28 C1010 C1011

n
VDD_GPU_13 VDD_CPU_BIG0_MEM_2 K29 1uF 100nF

1
C1004 C1005 AJ18 VDD_CPU_BIG0_MEM_3 K30 X5R X5R
1uF 100nF AK18 VDD_GPU_MEM_1 VDD_CPU_BIG0_MEM_4 4V 10V

1
VDD_GPU_MEM_2

2
X5R X5R AL18 C0201 C0201

i
VDD_LOGIC_S0 4V 10V VDD_GPU_MEM_3 VDD_CPU_BIG1_S0

LOGIC CPU_BIG1
VDD_LOGIC_S0 VDD_CPU_BIG1_S0

2
C0201 C0201

t
H27 R26
J27 VDD_LOGIC_1 VDD_CPU_BIG1_1 R27
VDD_LOGIC_2 VDD_CPU_BIG1_2

a
C48 C49 C50 C51 W33 R28 C36 C37 C38 C39
100nF 1uF 1uF 1uF C1017 C1019 C1020 C1021 C1022 C1023 C1024 Y33 VDD_LOGIC_3 VDD_CPU_BIG1_3 R29 C1014 C1015 C1077 C1078 C1079 C1013 C1012 C1056 C1057 100nF 1uF 1uF 1uF
1

1
X5R X5R X5R X5R C1058 C1059 10uF 10uF 1uF 1uF 100nF 100nF 100nF AF12 VDD_LOGIC_4 VDD_CPU_BIG1_4 R30 100nF 100nF 100nF 1uF 1uF 1uF 22uF 22uF 22uF X5R X5R X5R X5R

1
10V 4V 4V 4V 22uF 22uF X5R X5R X5R X5R X5R X5R X5R AF13 VDD_LOGIC_5 VDD_CPU_BIG1_5 R31 X5R X5R X5R X5R X5R C0201 X5R X5R 10V X5R 10V 10V 4V 4V 4V
VDD_LOGIC_6 VDD_CPU_BIG1_6
2

2
C0201 C0201 C0201 C0201 X5R 10V X5R 10V 4V 4V 4V 4V 10V 10V 10V AH11 R32 10V 10V 10V 4V 4V X5R 6.3V C0603 C0603 C0201 C0201 C0201 C0201

m sB
2 VDD_LOGIC_7 VDD_CPU_BIG1_7

2
C0603 C0603 C0402 C0402 C0201 C0201 C0201 C0201 C0201 AH12 R33 C0201 C0201 C0201 C0201 C0201 4V C0603
AH13 VDD_LOGIC_8 VDD_CPU_BIG1_8 T26

r
AH14 VDD_LOGIC_9 VDD_CPU_BIG1_9 U26
AH15 VDD_LOGIC_10 VDD_CPU_BIG1_10 VDD_CPU_BIG1_MEM_S0
AH23 VDD_LOGIC_11

o
VDD_LOGIC_12

s
AH24 V26
AJ15 VDD_LOGIC_13 VDD_CPU_BIG1_MEM_1 V27

f
AJ31 VDD_LOGIC_14 VDD_CPU_BIG1_MEM_2 V28 C1026 C1076 C1025
VDD_LOGIC_15 VDD_CPU_BIG1_MEM_3

a
AJ32 V29 100nF 100nF 1uF

1
VDD_LOGIC_16 VDD_CPU_BIG1_MEM_4

l
AK15 X5R X5R X5R

n
AL31 VDD_LOGIC_17 10V 10V 4V

i :C
VDD_LOGIC_18 VDD_CPU_LIT_S0

2
C0201 C0201 C0201
VDD_VDENC_S0 VDD_CPU_LIT_S0
AB31

l
VDENC CPU_LIT
P15 VDD_CPU_LIT_1 AC27
R15 VDD_VDENC_1 VDD_CPU_LIT_2 AC28 C1029 C1081 C1082 C1083 C1028 C1027 C40 C41 C42 C43
VDD_VDENC_2 VDD_CPU_LIT_3

a
C1030 C1063 C1031 C1032 C1033 C1080 T15 AC29 100nF 100nF 100nF 1uF 1uF 47uF C1060 C1061 100nF 1uF 1uF 1uF

1
10uF 1uF 1uF 1uF 100nF 100nF U15 VDD_VDENC_3 VDD_CPU_LIT_4 AC30 X5R X5R X5R X5R X5R X5R 47uF 22uF X5R X5R X5R X5R

1
C1090 X5R X5R X5R X5R X5R X5R W16 VDD_VDENC_4 VDD_CPU_LIT_5 AC31 10V 10V 10V 4V 4V 6.3V X5R 10V X5R 10V 10V 4V 4V 4V
1

C C
VDD_VDENC_5 VDD_CPU_LIT_6

n
47uF

2
4V 4V 4V 4V 10V 10V AC16 AD26 C0201 C0201 C0201 C0201 C0201 C0603 C0603 C0603 C0201 C0201 C0201 C0201
VDD_VDENC_6 VDD_CPU_LIT_7

2
X5R 10V C0402 C0201 C0201 C0201 C0201 C0201 AD15 AD27
VDD_VDENC_7 VDD_CPU_LIT_8

r
2

C0603 AE27

v
VDD_CPU_LIT_9
W17 AA28

e
C1036 C1037 Y17 VDD_VDENC_MEM_1 VDD_CPU_LIT_MEM_1 AA29 C1034 C1035

e
1uF 100nF VDD_VDENC_MEM_2 VDD_CPU_LIT_MEM_2 AA30 100nF 1uF

t
1

1
l
X5R X5R VDD_CPU_LIT_MEM_3 X5R X5R
4V 10V 10V 4V VDD_NPU_S0
VDD_NPU_S0

2
C0201 C0201 C0201 C0201

n
NPU
VDD_NPU_S0 AK27

i y
VDD_NPU_1 AK28 C1084 C1085 C1040 C1041 C1039 C1038
AH25 VDD_NPU_2 AK29 100nF 100nF 100nF 1uF 1uF 47uF C44 C45 C46 C47

1
1

1
t
AH26 VDD_NPU_MEM_1 VDD_NPU_3 AL28 X5R X5R X5R X5R X5R X5R C1054 C1055 100nF 1uF 1uF 1uF

1
i
C1042 C1043 AJ25 VDD_NPU_MEM_2 VDD_NPU_4 AL29 10V 10V 10V 4V 4V 6.3V 22uF 22uF X5R X5R X5R X5R
VDD_NPU_MEM_3 VDD_NPU_5

e
1uF 100nF

2
2

2
AK25 AL30 C0201 C0201 C0201 C0201 C0201 C0603 X5R 10V X5R 10V 10V 4V 4V 4V
1

1
VDD_NPU_MEM_4 VDD_NPU_6

2
X5R X5R AM30 C0603 C0603 C0201 C0201 C0201 C0201

r
4V 10V VDD_NPU_7 AN30

a
VDD_NPU_8
2

2
C0201 C0201 AP30
VDD_NPU_9

a nt i
RK3588S

w
BGA1253_17R00X17R00X1R10

o f t d e
s n f i
g
U1000U
U1000T G9 L3 U1000V U1000W U1000X U1000Y

o
A1 D22 G10 VSS_101 VSS_151 L5 P19 U41 AA10 AD11 AF34 AJ12

n
B A2 VSS_1 VSS_51 D26 G12 VSS_102 VSS_152 L6 P25 VSS_201 VSS_251 V3 AA11 VSS_301 VSS_351 AD12 AF37 VSS_401 VSS_451 AJ16 AN40 K34 U1000Z B
A42 VSS_2 VSS_52 D30 G20 VSS_103 VSS_153 L10 P26 VSS_202 VSS_252 V6 AA12 VSS_302 VSS_352 AD13 AF38 VSS_402 VSS_452 AJ26 AP2 VSS_501 AVSS_11 K35 AT22 AY4
VSS_3 VSS_53 VSS_104 VSS_154 VSS_203 VSS_253 VSS_303 VSS_353 VSS_403 VSS_453 VSS_502 AVSS_12 AVSS_54 AVSS_94

C
B3 D31 G21 L11 P27 V7 AA19 AD14 AF39 AJ27 AP5 K36 AT23 AY5

o
B5 VSS_4 VSS_54 D32 G22 VSS_105 VSS_155 L12 P28 VSS_204 VSS_254 V8 AA22 VSS_304 VSS_354 AD19 AF40 VSS_404 VSS_454 AJ28 AP6 VSS_503 AVSS_13 K37 AT29 AVSS_55 AVSS_95 AY7
VSS_5 VSS_55 VSS_106 VSS_156 VSS_205 VSS_255 VSS_305 VSS_355 VSS_405 VSS_455 VSS_504 AVSS_14 AVSS_56 AVSS_96

l
B8 E2 G25 L14 P29 V16 AA23 AD20 AF41 AJ29 AP25 K38 AU8 AY8
B10 VSS_6 VSS_56 E5 G26 VSS_107 VSS_157 L22 P30 VSS_206 VSS_256 V17 AA31 VSS_306 VSS_356 AD22 AG3 VSS_406 VSS_456 AJ30 AP27 VSS_505 AVSS_15 K39 AU16 AVSS_57 AVSS_97 AY9
B11 VSS_7 VSS_57 E6 G29 VSS_108 VSS_158 L23 P31 VSS_207 VSS_257 V19 AA37 VSS_307 VSS_357 AD23 AG4 VSS_407 VSS_457 AJ35 AP33 VSS_506 AVSS_16 K40 AU18 AVSS_58 AVSS_98 AY12
VSS_8 VSS_58 VSS_109 VSS_159 VSS_208 VSS_258 VSS_308 VSS_358 VSS_408 VSS_458 VSS_507 AVSS_17 AVSS_59 AVSS_99

n
B14 E8 H3 L24 P32 V23 AA38 AD24 AG5 AJ38 AP34 L34 AU19 AY14
B17 VSS_9 VSS_59 E9 H4 VSS_110 VSS_160 L32 P33 VSS_209 VSS_259 V24 AA39 VSS_309 VSS_359 AD25 AG6 VSS_409 VSS_459 AJ39 AP35 VSS_508 AVSS_18 L35 AU21 AVSS_60 AVSS_100 AY16
B19 VSS_10 VSS_60 E10 H5 VSS_111 VSS_161 L33 P34 VSS_210 VSS_260 V25 AA40 VSS_310 VSS_360 AE6 AG7 VSS_410 VSS_460 AJ40 AP37 VSS_509 AVSS_19 L41 AU24 AVSS_61 AVSS_101 AY17
VSS_11 VSS_61 VSS_112 VSS_162 VSS_211 VSS_261 VSS_311 VSS_361 VSS_411 VSS_461 VSS_510 AVSS_20 AVSS_62 AVSS_102

u
B21 E12 H6 L36 R3 V30 AB2 AE7 AG8 AJ41 AP38 M33 AU25 AY18
B23 VSS_12 VSS_62 E16 H11 VSS_113 VSS_163 M2 R4 VSS_212 VSS_262 V31 AB6 VSS_312 VSS_362 AE8 AG15 VSS_412 VSS_462 AK2 AP39 VSS_511 AVSS_21 M34 AU27 AVSS_63 AVSS_103 AY21
B26 VSS_13 VSS_63 E18 H12 VSS_114 VSS_164 M5 R8 VSS_213 VSS_263 V32 AB9 VSS_313 VSS_363 AE9 AG16 VSS_413 VSS_463 AK6 AP40 VSS_512 AVSS_22 N33 AU28 AVSS_64 AVSS_104 AY22
VSS_14 VSS_64 VSS_115 VSS_165 VSS_214 VSS_264 VSS_314 VSS_364 VSS_414 VSS_464 VSS_513 AVSS_23 AVSS_65 AVSS_105

X
B27 E19 H22 M8 R16 V33 AB10 AE10 AG17 AK7 AR3 AL15 AU29 AY23
B29 VSS_15 VSS_65 E21 H25 VSS_116 VSS_166 M9 R20 VSS_215 VSS_265 V34 AB11 VSS_315 VSS_365 AE11 AG18 VSS_415 VSS_465 AK16 AR4 VSS_514 AVSS_24 AM14 AU31 AVSS_66 AVSS_106 AY25
B31 VSS_16 VSS_66 E23 H29 VSS_117 VSS_167 M10 R21 VSS_216 VSS_266 V38 AB12 VSS_316 VSS_366 AE12 AG19 VSS_416 VSS_466 AK22 AR40 VSS_515 AVSS_25 AM15 AV8 AVSS_67 AVSS_107 AY28
B34 VSS_17 VSS_67 E25 J2 VSS_118 VSS_168 M12 R25 VSS_217 VSS_267 V39 AB19 VSS_317 VSS_367 AE13 AG20 VSS_417 VSS_467 AK26 AR41 VSS_516 AVSS_26 AN11 AV9 AVSS_68 AVSS_108 AY29
B35 VSS_18 VSS_68 E27 J6 VSS_119 VSS_169 M14 R35 VSS_218 VSS_268 V40 AB20 VSS_318 VSS_368 AE14 AG21 VSS_418 VSS_468 AK30 AT2 VSS_517 AVSS_27 AN13 AV12 AVSS_69 AVSS_109 AY32
B36 VSS_19 VSS_69 E30 J7 VSS_120 VSS_170 M17 T2 VSS_219 VSS_269 W2 AB21 VSS_319 VSS_369 AE15 AG22 VSS_419 VSS_469 AK40 AT5 VSS_518 AVSS_28 AN14 AV14 AVSS_70 AVSS_110 AY33
B38 VSS_20 VSS_70 E31 J8 VSS_121 VSS_171 M19 T3 VSS_220 VSS_270 W5 AB22 VSS_320 VSS_370 AE16 AG23 VSS_420 VSS_470 AL3 AT6 VSS_519 AVSS_29 AN15 AV15 AVSS_71 AVSS_111 AY36
B40 VSS_21 VSS_71 E33 J9 VSS_122 VSS_172 M21 T4 VSS_221 VSS_271 W7 AB23 VSS_321 VSS_371 AE19 AG24 VSS_421 VSS_471 AL4 AT36 VSS_520 AVSS_30 AN18 AV16 AVSS_72 AVSS_112 AY37
B42 VSS_22 VSS_72 E34 J10 VSS_123 VSS_173 M22 T7 VSS_222 VSS_272 W8 AB24 VSS_322 VSS_372 AE20 AG25 VSS_422 VSS_472 AL5 AU2 VSS_521 AVSS_31 AP7 AV21 AVSS_73 AVSS_113 AY39
C2 VSS_23 VSS_73 E37 J12 VSS_124 VSS_174 M23 T16 VSS_223 VSS_273 W9 AB32 VSS_323 VSS_373 AE22 AG28 VSS_423 VSS_473 AL16 AU3 VSS_522 AVSS_32 AP8 AV25 AVSS_74 AVSS_114 AY41
C6 VSS_24 VSS_74 E38 J14 VSS_125 VSS_175 M35 T17 VSS_224 VSS_274 W18 AB33 VSS_324 VSS_374 AE23 AG29 VSS_424 VSS_474 AL22 AU4 VSS_523 AVSS_33 AP9 AV29 AVSS_75 AVSS_115 BA3
C7 VSS_25 VSS_75 E39 J15 VSS_126 VSS_176 M36 T18 VSS_225 VSS_275 W19 AB34 VSS_325 VSS_375 AE24 AG31 VSS_425 VSS_475 AL35 AU35 VSS_524 AVSS_34 AP10 AV32 AVSS_76 AVSS_116 BA6
C9 VSS_26 VSS_76 F2 J16 VSS_127 VSS_177 N3 T20 VSS_226 VSS_276 W22 AB36 VSS_326 VSS_376 AE25 AG32 VSS_426 VSS_476 AM4 AU38 VSS_525 AVSS_35 AP11 AV33 AVSS_77 AVSS_117 BA9
C11 VSS_27 VSS_77 F3 J22 VSS_128 VSS_178 N7 T21 VSS_227 VSS_277 W23 AB37 VSS_327 VSS_377 AE26 AG33 VSS_427 VSS_477 AM5 AU39 VSS_526 AVSS_36 AP16 AW8 AVSS_78 AVSS_118 BA12
C12 VSS_28 VSS_78 F4 J24 VSS_129 VSS_179 N9 T24 VSS_228 VSS_278 W24 AB38 VSS_328 VSS_378 AE38 AG34 VSS_428 VSS_478 AM16 AU40 VSS_527 AVSS_37 AP22 AW9 AVSS_79 AVSS_119 BA15
C14 VSS_29 VSS_79 F8 J26 VSS_130 VSS_180 N11 T25 VSS_229 VSS_279 W26 AB39 VSS_329 VSS_379 AE39 AG35 VSS_429 VSS_479 AM17 AV5 VSS_528 AVSS_38 AP31 AW12 AVSS_80 AVSS_120 BA18
C15 VSS_30 VSS_80 F9 J29 VSS_131 VSS_181 N12 T35 VSS_230 VSS_280 Y3 AB40 VSS_330 VSS_380 AE40 AG40 VSS_430 VSS_480 AM23 AV36 VSS_529 AVSS_39 AP32 AW14 AVSS_81 AVSS_121 BA21
C18 VSS_31 VSS_81 F10 J30 VSS_132 VSS_182 N16 T36 VSS_231 VSS_281 Y4 AC3 VSS_331 VSS_381 AF2 AH2 VSS_431 VSS_481 AM25 AV41 VSS_530 AVSS_40 AR9 AW16 AVSS_82 AVSS_122 BA24
C19 VSS_32 VSS_82 F13 J31 VSS_133 VSS_183 N17 T37 VSS_232 VSS_282 Y5 AC4 VSS_332 VSS_382 AF6 AH3 VSS_432 VSS_482 AM27 AW3 VSS_531 AVSS_41 AR16 AW17 AVSS_83 AVSS_123 BA27
C20 VSS_33 VSS_83 F14 K3 VSS_134 VSS_184 N18 T38 VSS_233 VSS_283 Y6 AC5 VSS_333 VSS_383 AF7 AH4 VSS_433 VSS_483 AM31 AW4 VSS_532 AVSS_42 AR18 AW21 AVSS_84 AVSS_124 BA30
C22 VSS_34 VSS_84 F15 K6 VSS_135 VSS_185 N21 T39 VSS_234 VSS_284 Y11 AC6 VSS_334 VSS_384 AF8 AH5 VSS_434 VSS_484 AM32 C41 VSS_533 AVSS_43 AR20 AW25 AVSS_85 AVSS_125 BA33
C24 VSS_35 VSS_85 F16 K7 VSS_136 VSS_186 N22 T40 VSS_235 VSS_285 Y18 AC17 VSS_335 VSS_385 AF9 AH7 VSS_435 VSS_485 AM41 E40 AVSS_1 AVSS_44 AR21 AW28 AVSS_86 AVSS_126 BA36
C26 VSS_36 VSS_86 F19 K10 VSS_137 VSS_187 N34 U6 VSS_236 VSS_286 Y19 AC18 VSS_336 VSS_386 AF10 AH8 VSS_436 VSS_486 AN3 F40 AVSS_2 AVSS_45 AR22 AW29 AVSS_87 AVSS_127 BB1
C28 VSS_37 VSS_87 F21 K11 VSS_138 VSS_188 N38 U7 VSS_237 VSS_287 Y22 AC22 VSS_337 VSS_387 AF16 AH9 VSS_437 VSS_487 AN6 G36 AVSS_3 AVSS_46 AR25 AW32 AVSS_88 AVSS_128 BB42
C30 VSS_38 VSS_88 F23 K12 VSS_139 VSS_189 N39 U8 VSS_238 VSS_288 Y23 AC23 VSS_338 VSS_388 AF17 AH10 VSS_438 VSS_488 AN7 G41 AVSS_4 AVSS_47 AT7 AW33 AVSS_89 AVSS_129
C35 VSS_39 VSS_89 F29 K14 VSS_140 VSS_190 N40 U16 VSS_239 VSS_289 Y24 AC24 VSS_339 VSS_389 AF19 AH16 VSS_439 VSS_489 AN17 H37 AVSS_5 AVSS_48 AT8 AW36 AVSS_90
C37 VSS_40 VSS_90 F31 K17 VSS_141 VSS_191 P2 U17 VSS_240 VSS_290 Y28 AC25 VSS_340 VSS_390 AF20 AH17 VSS_440 VSS_490 AN23 H40 AVSS_6 AVSS_49 AT16 AW40 AVSS_91
C39 VSS_41 VSS_91 F33 K22 VSS_142 VSS_192 P6 U18 VSS_241 VSS_291 Y29 AC26 VSS_341 VSS_391 AF21 AH28 VSS_441 VSS_491 AN25 J38 AVSS_7 AVSS_50 AT19 AY2 AVSS_92
A D3 VSS_42 VSS_92 F34 K23 VSS_143 VSS_193 P7 U20 VSS_242 VSS_292 Y30 AC41 VSS_342 VSS_392 AF26 AH29 VSS_442 VSS_492 AN31 J39 AVSS_8 AVSS_51 AT20 AVSS_93 A
D4 VSS_43 VSS_93 F35 K25 VSS_144 VSS_194 P8 U21 VSS_243 VSS_293 Y31 AD2 VSS_343 VSS_393 AF27 AH36 VSS_443 VSS_493 AN32 J40 AVSS_9 AVSS_52 AT21
D7 VSS_44 VSS_94 F36 K26 VSS_145 VSS_195 P9 U22 VSS_244 VSS_294 Y32 AD3 VSS_344 VSS_394 AF28 AJ5 VSS_444 VSS_494 AN33 AVSS_10 AVSS_53 RK3588S
D11 VSS_45 VSS_95 F38 K31 VSS_146 VSS_196 P12 U23 VSS_245 VSS_295 AA3 AD5 VSS_345 VSS_395 AF29 AJ7 VSS_445 VSS_495 AN34
VSS_46 VSS_96 VSS_147 VSS_197 VSS_246 VSS_296 VSS_346 VSS_396 VSS_446 VSS_496 BGA1253_17R00X17R00X1R10
D14 F39 K32 P16 U24 AA6 AD6 AF30 AJ8 AN35
D15 VSS_47 VSS_97 G3 K33 VSS_148 VSS_198 P17 U25 VSS_247 VSS_297 AA7 AD8 VSS_347 VSS_397 AF31 AJ9 VSS_447 VSS_497 AN37 RK3588S
D18 VSS_48 VSS_98 G6 L2 VSS_149 VSS_199 P18 U39 VSS_248 VSS_298 AA8 AD9 VSS_348 VSS_398 AF32 AJ10 VSS_448 VSS_498 AN38
VSS_49 VSS_99 VSS_150 VSS_200 VSS_249 VSS_299 VSS_349 VSS_399 VSS_449 VSS_499 BGA1253_17R00X17R00X1R10
D19 G8 U40 AA9 AD10 AF33 AJ11 AN39
VSS_50 VSS_100 VSS_250 VSS_300 VSS_350 VSS_400 VSS_450 VSS_500
RK3588S RK3588S
RK3588S RK3588S BGA1253_17R00X17R00X1R10 BGA1253_17R00X17R00X1R10 RK3588S
BGA1253_17R00X17R00X1R10 BGA1253_17R00X17R00X1R10 BGA1253_17R00X17R00X1R10
Xunlong Co.,Limited
Design Name
ORANGEPI 5
Size Page Name Rev
A2 RK3588S_Power/GND 1.2

Date: Tuesday, November 08, 2022 Sheet 10 of 36


5 4 3 2 1
5 4 3 2 1

RK3588S(OSC/PLL/PMUIO1)
U1000E RK3588S

OSC PMUIO1 Domain


R1100
22R 5%
1 2 XOUT T42
XOUT_24M Operating Voltage=1.8V Only V42
NPOR PMIC_RESET_L
R0201 C1110

1
R1102 100nF

1
X9
510K X5R 1 2 TSADC_SHUT
TSX-2016 1% 10V R1104 0R 5% R0201

2
C1111 3 2 R0201 V41 C0201
12pF XOUT GND TVSS

2
4 1 XIN T41

1
C0G GND XIN C1112 XIN_24M
D D
25V 24MHz 12pF W38

1
REFCLK_OUT / GPIO0_A0_d TSADC_SHUT HOST_WAKE_WIFI_H

2
C0201 C0G AC39
25V TSADC_SHUT_ORG / TSADC_SHUT_M0 / GPIO0_A1_z W41
VCCA_1V8_S0 PMIC_SLEEP1 / GPIO0_A2_d SLEEP1_RESET1_DEVOFF1_VSEL1

2
C0201 AD39
PMIC_SLEEP2 / GPIO0_A3_d AC38 VSEL2
10mA N35
SDMMC_DET / GPIO0_A4_u Y39 SPI2_CLK_M2 R1115 1 2 22R 5% R0201 SDMMC_DET_L
PMIC_SPI_CLK

n
OSC_1V8_1 PMU_DEBUG / SDMMC_PWREN / SPI2_CLK_M2 / GPIO0_A5_d
C1100 N36 W39 SPI2_MOSI_M2 R1116 1 2 22R 5% R0201
100nF OSC_1V8_2 I2C0_SDA_M0 / SPI2_MOSI_M2 / GPIO0_A6_z W42 PMIC_SPI_MOSI

1
PMIC_INT_L / GPIO0_A7_u PMIC_INT_L

o
X5R

i
10V AC37
UART0_RX_M1 / I2C1_SCL_M1 / SPI2_CS1_M2 / GPIO0_B0_z RTC_INT_L

2
t
C0201 W40
PWM5_M0 / UART0_TX_M1 / I2C1_SDA_M1 / SPI2_CS0_M2 / GPIO0_B1_z AD38 PMIC_SPI_CS
32KOUT_WIFI
PLL
CLK32K_OUT0 CLK32K_IN / GPIO0_B2_u

a
Y38
VDDA_0V75_S0 I2C0_SCL_M0 / SPI2_MISO_M2 / GPIO0_B3_z
VCC1V8_PMU_DDR_S3
20mA

m sB
Y26
C1113 C1103 PLL_DVDD0V75 N37

r
1uF 100nF PMUIO1_1V8_1 R36

1
C0201 X5R PMUIO1_1V8_2 C1101

o
X5R 10V 100nF

1
2
f
2
6.3V C0201 X5R

a
10V
VCCA_1V8_S0

2
l
C0201

n
i :C
40mA AB25
PLL_AVDD1V8

l
C1114 C1104
VDD_0V75_S3
1uF 100nF
PMUIO1/2 Domain Logic Power
1

1
a
C0201 X5R

l
C 2 X5R 10V Operating Voltage=0.75V PMU_0V75_1
AJ36 C

2 n e
4V C0201 AJ37 C1105 C1125
PMU_0V75_2 100nF 1uF

1
r v
AA26 X5R X5R
PLL_AVSS 10V 4V

e e

2
C0201 C0201

t l
BGA1253_17R00X17R00X1R10

i n y
RK3588S

RK3588S(PMUIO2)
U1000F

t
PMUIO2 Domain

e l i
Operating Voltage=1.8V/3.3V

/ PCIE20X1_1_CLKREQN_M0 / / I2S1_MCLK_M1 /

r
a nt
I2C1_SCL_M0

i a / / UART2_TX_M0 / JTAG_TCK_M2 / GPIO0_B5_d


AH39 UART2_TX_M0/JTAG_TCK_M2

w
AH40 UART2_RX_M0/JTAG_TMS_M2
/ PCIE20X1_1_WAKEN_M0 / / I2S1_SCLK_M1 / I2C1_SDA_M0 / / UART2_RX_M0 / JTAG_TMS_M2 / GPIO0_B6_d

f t e
AK39
/ PCIE20X1_1_PERSTN_M0 / SPI0_CS1_M0 / I2S1_LRCK_M1 / I2C2_SCL_M0 / / CAN0_TX_M0 / PWM0_M0 / GPIO0_B7_d I2C2_SCL_M0
AM40

o d
/ / SPI0_MOSI_M0 / / I2C2_SDA_M0 / PDM0_CLK0_M1 / CAN0_RX_M0 / PWM1_M0 / GPIO0_C0_d I2C2_SDA_M0

s i
AM38

f
/ / / / / / / PMIC_SLEEP3 / GPIO0_C1_d VSEL3
AG36 VSEL4

n
/ / / / / / / PMIC_SLEEP4 / GPIO0_C2_d

g
AH38
/ PMIC_SLEEP5 VSEL5

o
B / / / / / / / GPIO0_C3_d B

n
AL38
DP0_HPDIN_M1 / / / / I2C4_SDA_M2 / PDM0_CLK1_M1 / UART0_RX_M0 / PWM2_M0 / GPIO0_C4_d LCD_MIPI_BL_PWM2_M0

o C
AG38
PCIE_PWREN_H

l
/ / / I2S1_SDI0_M1 / I2C4_SCL_M2 / PWM4_M0 / UART0_TX_M0 / GPU_AVS / GPIO0_C5_u
VCC1V8_PMU_DDR_S3 VCC1V8_PMU_DDR_S3
AH42 VCC1V8_PMU_DDR_S3
SATA_CP_POD HOST_WAKE_BT_H

n
/ / SPI0_CLK_M0 / I2S1_SDI1_M1 / / PWM5_M1 / UART0_RTSN / NPU_AVS / GPIO0_C6_u
AL40
/ SPI0_MISO_M0 / I2S1_SDI2_M1 I2C6_SDA_M0 / PDM0_SDI0_M1 / UART1_RTSN_M2 / PWM6_M0 / GPIO0_C7_d LCD_MIPI_BL_PWM6_M0

u
/ /

1
AG39
/ / SPI3_MISO_M2 / I2S1_SDI3_M1 / I2C6_SCL_M0 / PDM0_SDI1_M1 / UART1_CTSN_M2 / PWM7_IR_M0 / GPIO0_D0_d WIFI_REG_ON_H R90658 R1113 R1114 R1111 R1112

X
2.2K 2.2K 2.2K 2.2K 2.2K
AH41
/ HDMI_TX0_CEC_M1 / SPI0_CS0_M0 / I2S1_SDO0_M1 / I2C0_SCL_M2 / UART0_CTSN / UART1_TX_M2 / CPU_BIG0_AVS / GPIO0_D1_u I2C0_SCL_M2 5% 5% 5% 5% 5%
R0201 R0201 R0201 R0201 R0201
AG41
I2C0_SDA_M2

2
/ / SPI3_MOSI_M2 / I2S1_SDO1_M1 / I2C0_SDA_M2 / / UART1_RX_M2 / / GPIO0_D2_u
CC_INT0_L I2C2_SCL_M0 I2C0_SCL_M2
AG37
/ / SPI3_CLK_M2 / / / / / LITCPU_AVS / GPIO0_D3_u CC_INT0_L
I2C2_SDA_M0 I2C0_SDA_M2
AL39
SATA_CPDET / HDMI_TX0_SDA_M1 / SPI3_CS0_M2 / I2S1_SDO2_M1 / I2C1_SCL_M2 / PDM0_SDI2_M1 / CAN2_RX_M1 / PWM3_IR_M0 / GPIO0_D4_u CAN2_RX/GPIO0_D4
AM39
SATA_MP_SWITCH / HDMI_TX0_SCL_M1 / SPI3_CS1_M2 / I2S1_SDO3_M1 / I2C1_SDA_M2 / / CAN2_TX_M1 / CPU_BIG1_AVS / GPIO0_D5_u CAN2_TX/GPIO0_D5
AG42
/ / / / PDM0_SDI3_M1 / / PMIC_SLEEP6 / GPIO0_D6_d VSEL6
VCC1V8_PMU_DDR_S3
V37
PMUIO2_1V8_1 Y37
PMUIO2_1V8_2 C1106
100nF
1

X5R
A A
10V
2

C0201
VCC1V8_PMU_DDR_S3
PMUIO2_1
PMUIO2_2
V35
V36 Xunlong Co.,Limited
Design Name
C1107
100nF
ORANGEPI 5
1

X5R Size Page Name Rev


10V A3 RK3588S_OSC/PLL/PMUIO 1.2
2

C0201
BGA1253_17R00X17R00X1R10 Date: Tuesday, November 08, 2022 Sheet 11 of 36
5 4 3 2 1
5 4 3 2 1

RK3588S(DDR PHY)
U1000A RK3588S U1000B RK3588S

DDR_CH0_DQ0_A AJ2 U3 DDR_CH1_DQ0_C B20 A24


DDR_CH0_DQ0_A DDR_CH0_DQ0_B DDR_CH0_DQ0_B DDR_CH1_DQ0_C DDR_CH1_DQ0_D DDR_CH1_DQ0_D
DDR_CH0_DQ1_A AB4 AA5 DDR_CH1_DQ1_C E20 C25
DDR_CH0_DQ1_A DDR_CH0_DQ1_B DDR_CH0_DQ1_B DDR_CH1_DQ1_C DDR_CH1_DQ1_D DDR_CH1_DQ1_D
DDR_CH0_DQ2_A AJ1 N1 DDR_CH1_DQ2_C A20 B24
DDR_CH0_DQ2_A DDR_CH0_DQ2_B DDR_CH0_DQ2_B DDR_CH1_DQ2_C DDR_CH1_DQ2_D DDR_CH1_DQ2_D
DDR_CH0_DQ3_A AB3 U5 DDR_CH1_DQ3_C F20 A28
DDR_CH0_DQ3_A DDR_CH0_DQ3_B DDR_CH0_DQ3_B DDR_CH1_DQ3_C DDR_CH1_DQ3_D DDR_CH1_DQ3_D
DDR_CH0_DQ4_A AB5 P4 DDR_CH1_DQ4_C C17 D25
DDR_CH0_DQ4_A DDR_CH0_DQ4_B DDR_CH0_DQ4_B DDR_CH1_DQ4_C DDR_CH1_DQ4_D DDR_CH1_DQ4_D
DDR_CH0_DQ5_A AE5 P3 DDR_CH1_DQ5_C C16 B28
DDR_CH0_DQ5_A DDR_CH0_DQ5_B DDR_CH0_DQ5_B DDR_CH1_DQ5_C DDR_CH1_DQ5_D DDR_CH1_DQ5_D
DDR_CH0_DQ6_A AE2 U4 DDR_CH1_DQ6_C D17 C27
DDR_CH0_DQ6_A DDR_CH0_DQ6_B DDR_CH0_DQ6_B DDR_CH1_DQ6_C DDR_CH1_DQ6_D DDR_CH1_DQ6_D
DDR_CH0_DQ7_A AF3 P5 DDR_CH1_DQ7_C D16 C29
D DDR_CH0_DQ7_A DDR_CH0_DQ7_B DDR_CH0_DQ7_B DDR_CH1_DQ7_C DDR_CH1_DQ7_D DDR_CH1_DQ7_D D
DDR_CH0_DQ8_A AK5 G5 DDR_CH1_DQ8_C D10 D34
DDR_CH0_DQ8_A DDR_CH0_DQ8_B DDR_CH0_DQ8_B DDR_CH1_DQ8_C DDR_CH1_DQ8_D DDR_CH1_DQ8_D
DDR_CH0_DQ9_A AN5 J3 DDR_CH1_DQ9_C B12 D29
DDR_CH0_DQ9_A DDR_CH0_DQ9_B DDR_CH0_DQ9_B DDR_CH1_DQ9_C DDR_CH1_DQ9_D DDR_CH1_DQ9_D
DDR_CH0_DQ10_A AN4 G4 DDR_CH1_DQ10_C A12 E29
DDR_CH0_DQ10_A DDR_CH0_DQ10_B DDR_CH0_DQ10_B DDR_CH1_DQ10_C DDR_CH1_DQ10_D DDR_CH1_DQ10_D
DDR_CH0_DQ11_A AJ6 J4 DDR_CH1_DQ11_C C10 E32
DDR_CH0_DQ11_A DDR_CH0_DQ11_B DDR_CH0_DQ11_B DDR_CH1_DQ11_C DDR_CH1_DQ11_D DDR_CH1_DQ11_D
DDR_CH0_DQ12_A AJ3 N5 DDR_CH1_DQ12_C C13 B32
DDR_CH0_DQ12_A DDR_CH0_DQ12_B DDR_CH0_DQ12_B DDR_CH1_DQ12_C DDR_CH1_DQ12_D DDR_CH1_DQ12_D
DDR_CH0_DQ13_A AK3 N2 DDR_CH1_DQ13_C E13 C34
DDR_CH0_DQ13_B DDR_CH1_DQ13_D

n
AF4 DDR_CH0_DQ13_A DDR_CH0_DQ13_B J5 A16 DDR_CH1_DQ13_C DDR_CH1_DQ13_D C32
DDR_CH0_DQ14_A DDR_CH0_DQ14_A DDR_CH0_DQ14_B DDR_CH0_DQ14_B DDR_CH1_DQ14_C DDR_CH1_DQ14_C DDR_CH1_DQ14_D DDR_CH1_DQ14_D
DDR_CH0_DQ15_A AF5 N6 DDR_CH1_DQ15_C B16 A32
DDR_CH0_DQ15_A DDR_CH0_DQ15_B DDR_CH0_DQ15_B DDR_CH1_DQ15_C DDR_CH1_DQ15_D DDR_CH1_DQ15_D

i o
AE1 V5 DDR_CH0_DM0_B E17 D27 DDR_CH1_DM0_D
DDR_CH0_DM0_A DDR_CH0_DM0_A DDR_CH0_DM0_B DDR_CH1_DM0_C DDR_CH1_DM0_C DDR_CH1_DM0_D

t
AK4 G2 DDR_CH0_DM1_B D13 C33 DDR_CH1_DM1_D
DDR_CH0_DM1_A DDR_CH0_DM1_A DDR_CH0_DM1_B DDR_CH1_DM1_C DDR_CH1_DM1_C DDR_CH1_DM1_D

a
DDR_CH0_DQS0P_A AN1 B2 DDR_CH1_DQS0P_C A9 B41
DDR_CH0_DQS0P_A DDR_CH0_DQS0P_B DDR_CH0_DQS0P_B DDR_CH1_DQS0P_C DDR_CH1_DQS0P_D DDR_CH1_DQS0P_D
DDR_CH0_DQS0N_A AN2 B1 DDR_CH1_DQS0N_C B9 A41
DDR_CH0_DQS0N_A DDR_CH0_DQS0N_B DDR_CH0_DQS0N_B DDR_CH1_DQS0N_C DDR_CH1_DQS0N_D DDR_CH1_DQS0N_D
DDR_CH0_DQS1P_A AV4 K1 DDR_CH1_DQS1P_C A3 D36
DDR_CH0_DQS1P_A DDR_CH0_DQS1P_B DDR_CH0_DQS1P_B DDR_CH1_DQS1P_C DDR_CH1_DQS1P_D DDR_CH1_DQS1P_D

m sB
DDR_CH0_DQS1N_A AV3 K2 DDR_CH1_DQS1N_C A4 C36
DDR_CH0_DQS1N_A DDR_CH0_DQS1N_B DDR_CH0_DQS1N_B DDR_CH1_DQS1N_C DDR_CH1_DQS1N_D DDR_CH1_DQS1N_D

r
AR6 C4 C8 B39
AR5 DDR_CH0_WCK0P_A DDR_CH0_WCK0P_B C3 D8 DDR_CH1_WCK0P_C DDR_CH1_WCK0P_D A39
DDR_CH0_WCK0N_A DDR_CH0_WCK0N_B DDR_CH1_WCK0N_C DDR_CH1_WCK0N_D

o
AT4 E3 B6 A37

s
DDR_CH0_WCK1P_A DDR_CH0_WCK1P_B DDR_CH1_WCK1P_C DDR_CH1_WCK1P_D

f
AT3 E4 A6 B37
DDR_CH0_WCK1N_A DDR_CH0_WCK1N_B DDR_CH1_WCK1N_C DDR_CH1_WCK1N_D

n l a
AA2 V2 DDR_CH0_CLKP_B C21 C23 DDR_CH1_CLKP_D
DDR_CH0_CLKP_A DDR_CH0_CK_A DDR_CH0_CK_B DDR_CH1_CLKP_C DDR_CH1_CK_C DDR_CH1_CK_D

i :C
AA1 V1 DDR_CH0_CLKN_B D21 D23 DDR_CH1_CLKN_D
DDR_CH0_CLKN_A DDR_CH0_CKB_A DDR_CH0_CKB_B DDR_CH1_CLKN_C DDR_CH1_CKB_C DDR_CH1_CKB_D

l
U1 U2 DDR_CH0_A0_B B18 A26 DDR_CH1_A0_D
DDR_CH0_A0_A DDR_CH0_A0_A DDR_CH0_A0_B DDR_CH1_A0_C DDR_CH1_A0_C DDR_CH1_A0_D
AC2 R2 DDR_CH0_A1_B A21 A27 DDR_CH1_A1_D
DDR_CH0_A1_A DDR_CH0_A1_A DDR_CH0_A1_B DDR_CH1_A1_C DDR_CH1_A1_C DDR_CH1_A1_D

a l
AF1 R1 DDR_CH0_A2_B B22 A30 DDR_CH1_A2_D
C
DDR_CH0_A2_A AL2 DDR_CH0_A2_A DDR_CH0_A2_B D2 DDR_CH1_A2_C A7 DDR_CH1_A2_C DDR_CH1_A2_D A36 C
DDR_CH0_A3_A DDR_CH0_A3_A DDR_CH0_A3_B DDR_CH0_A3_B DDR_CH1_A3_C DDR_CH1_A3_C DDR_CH1_A3_D DDR_CH1_A3_D

n e
Y1 E1 DDR_CH0_A4_B A10 B33 DDR_CH1_A4_D
DDR_CH0_A4_A AG2 DDR_CH0_A4_A DDR_CH0_A4_B L1 DDR_CH1_A4_C A15 DDR_CH1_A4_C DDR_CH1_A4_D A38

r
DDR_CH0_A5_A DDR_CH0_A5_A DDR_CH0_A5_B DDR_CH0_A5_B DDR_CH1_A5_C DDR_CH1_A5_C DDR_CH1_A5_D DDR_CH1_A5_D

v
AM2 H1 B7 A33
DDR_CH0_A6_A DDR_CH0_A6_B DDR_CH1_A6_C DDR_CH1_A6_D

e e
DDR_CH0_LP4/4X_CKE0_A AK1 H2 DDR_CH0_LP4/4X_CKE0_B DDR_CH1_LP4/4X_CKE0_C A18 A35 DDR_CH1_LP4/4X_CKE0_D

t
DDR_CH0_LP4/4X_CKE0/LP5_CS0_A DDR_CH0_LP4/4X_CKE0/LP5_CS0_B DDR_CH1_LP4/4X_CKE0/LP5_CS0_C DDR_CH1_LP4/4X_CKE0/LP5_CS0_D

l
DDR_CH0_LP4/4X_CKE1_A AD1 F1 DDR_CH0_LP4/4X_CKE1_B DDR_CH1_LP4/4X_CKE1_C A13 A31 DDR_CH1_LP4/4X_CKE1_D
DDR_CH0_LP4/4X_CKE1/LP5_CS1_A DDR_CH0_LP4/4X_CKE1/LP5_CS1_B DDR_CH1_LP4/4X_CKE1/LP5_CS1_C DDR_CH1_LP4/4X_CKE1/LP5_CS1_D

n
Y2 J1 DDR_CH0_LP4/4X_CS0_B B15 B30 DDR_CH1_LP4/4X_CS0_D
DDR_CH0_LP4/4X_CS0_A DDR_CH1_LP4/4X_CS0_C

i y
AC1 DDR_CH0_LP4/4X_CS0_A DDR_CH0_LP4/4X_CS0_B M1 A19 DDR_CH1_LP4/4X_CS0_C DDR_CH1_LP4/4X_CS0_D A23
DDR_CH0_LP4/4X_CS1_A DDR_CH0_LP4/4X_CS1_A DDR_CH0_LP4/4X_CS1_B DDR_CH0_LP4/4X_CS1_B DDR_CH1_LP4/4X_CS1_C DDR_CH1_LP4/4X_CS1_C DDR_CH1_LP4/4X_CS1_D DDR_CH1_LP4/4X_CS1_D

e l i t
AG1 P1 B13 B25
DDR_RESET DDR_CH0_RESET_A DDR_CH0_RESET_B DDR_CH1_RESET_C DDR_CH1_RESET_D

r
a nt i a
VDDQ_DDR_S0 2 1 AM1 C1 1 2 VDDQ_DDR_S0 VDDQ_DDR_S0 2 1 A5 A40 1 2 VDDQ_DDR_S0
R1200 240R DDR_CH0_ZQ_A DDR_CH0_ZQ_B R1202 240R DDR_CH1_ZQ_C DDR_CH1_ZQ_D R1203 240R
R0201 240R R1201 R0201 R0201 1%

w
1% R0201 1% 1%

t
DDR_PLL Power LP4/4x CKE&LP5 CS Power&Reset DDR_PLL Power LP4/4x CKE&LP5 CS Power&Reset
20mA

f e
AB14 M6 M16 G24
VDDA_DDR_PLL_S0 DDR_CH0_PLL_DVDD 0.75-0.85V DDR_CH0_VDDQ_CKE_1 M7 VDDQ_DDR_CKE_S3 VDDA_DDR_PLL_S0 DDR_CH1_PLL_DVDD 0.75-0.85V DDR_CH1_VDDQ_CKE VDDQ_DDR_CKE_S3
30mA Y14 DDR_CH0_VDDQ_CKE_2

o d
AVDD1V8_DDR_PLL_S0 DDR_CH0_PLL_AVDD1V8 1.8V
LPDDR4/4x =1.1V L15

i
AVDD1V8_DDR_PLL_S0 DDR_CH1_PLL_AVDD1V8 1.8V

s
AA14 LPDDR5 =1.05V LPDDR4/4x =1.1V

f
DDR_CH0_PLL_AVSS LPDDR5 =1.05V
N15

n
Memory Interface Power CK Power K9 DDR_CH1_PLL_AVSS

g
DDR_CH0_VDDQ_CK_1 VDDQ_DDR_CK_S0
VDD_DDR_S0 V12 L9

o
B V13 DDR_CH0_VDD_MIF_1 DDR_CH0_VDDQ_CK_2 Memory Interface Power CK Power H24 B

n
DDR_CH0_VDD_MIF_2 0.75-0.85V DDR_CH1_VDDQ_CK VDDQ_DDR_CK_S0
V14 LPDDR4/4x =0.6V J20
DDR_CH0_VDD_MIF_3 VDD_DDR_S0 DDR_CH1_VDD_MIF_1

C
LPDDR5 =0.5V K20

o
L20 DDR_CH1_VDD_MIF_2 0.75-0.85V LPDDR4/4x =0.6V

l
DDR_CH1_VDD_MIF_3 LPDDR5 =0.5V
Digital Core Power DDR IO Power P10 VDDQ_DDR_S0

n
T12 (Except for CK, DDR_CH0_VDDQ_1 R10 H14
DDR_CH0_VDD_1 CKE and Reset) DDR_CH0_VDDQ_2 DDR_CH1_VDDQ_1 VDDQ_DDR_S0
T13 T10 Digital Core Power DDR IO Power H15
DDR_CH0_VDD_2 DDR_CH0_VDDQ_3 DDR_CH1_VDDQ_2

u
U12 0.75-0.85V LPDDR4/4x =0.6V V10 J18 (Except for CK, H16
U13 DDR_CH0_VDD_3 LPDDR5 =0.5V DDR_CH0_VDDQ_4 W10 K18 DDR_CH1_VDD_1 CKE and Reset) DDR_CH1_VDDQ_3 H18
DDR_CH0_VDD_4 DDR_CH0_VDDQ_5 DDR_CH1_VDD_2 DDR_CH1_VDDQ_4

X
Y10 L18 0.75-0.85V LPDDR4/4x =0.6V H20
DDR_CH0_VDDQ_6 DDR_CH1_VDD_3 LPDDR5 =0.5V DDR_CH1_VDDQ_5

BGA1253_17R00X17R00X1R10 BGA1253_17R00X17R00X1R10

DDR FILTER VDDQ_DDR_S0 VDD_DDR_S0 VDD_DDR_S0 VDDQ_DDR_S0

VDDQ_DDR_S0
VDD_DDR_S0 VDD_DDR_S0
C1205 C1206 C1207 C1208 C1221 C1222 C1223 C1224 C1250 C1251 C1252 C1253
10uF 100nF 100nF 100nF 1uF 100nF 10uF 100nF 100nF 100nF 100nF 100nF
1

1
C1200 C1202 C1203 C1204 C1217 C1218 C1219 C1220 C0402 X5R X5R X5R C0201 X5R C0402 X5R X5R X5R X5R X5R
10uF 100nF 100nF 100nF 10uF 100nF 1uF 100nF X5R 10V 10V 10V X5R 10V X5R 10V 10V 10V 10V 10V
1

2
C0402 X5R X5R X5R C0402 X5R C0201 X5R 4V C0201 C0201 C0201 4V C0201 4V C0201 C0201 C0201 C0201 C0201
X5R 10V 10V 10V X5R 10V X5R 10V
2

4V C0201 C0201 C0201 4V C0201 4V C0201


A A

AVDD1V8_DDR_PLL_S0 VDDA_DDR_PLL_S0 VDDQ_DDR_CKE_S3 VDDQ_DDR_CK_S0


AVDD1V8_DDR_PLL_S0 VDDA_DDR_PLL_S0 VDDQ_DDR_CK_S0 VDDQ_DDR_CKE_S3

C1209 C1210 C1213 C1212 C1214 C1215 C1211 C1216 Xunlong Co.,Limited
1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF Design Name
1

C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201


X5R X5R X5R X5R X5R X5R X5R X5R ORANGEPI 5
2

4V 4V 4V 4V 4V 4V 4V 4V Size Page Name Rev


A3 RK3588S DDR Controler 1.2

Date: Tuesday, November 08, 2022 Sheet 12 of 36


5 4 3 2 1
5 4 3 2 1

RK3588S(EMMCIO Domain)

D U1000C D
RK3588S

EMMCIO Domain
Operating Voltage=1.8V Only eMMC_D0/FSPI_D0
FSPI_D0

n
Y41 eMMC_D0/FSPI_D0
FSPI_D0_M0 / EMMC_D0 / GPIO2_D0_u eMMC_D1/FSPI_D1 eMMC_D1/FSPI_D1
Y40
FSPI_D1_M0 / EMMC_D1 / GPIO2_D1_u FSPI_D1

o
AA41 eMMC_D2/FSPI_D2
FSPI_D2_M0 / EMMC_D2 / GPIO2_D2_u

i
AA42 eMMC_D3/FSPI_D3 eMMC_D2/FSPI_D2
FSPI_D3_M0 / EMMC_D3 / GPIO2_D3_u FSPI_D2

t
AB42
UART5_RX_M2 / I2C1_SCL_M3 / EMMC_D4 / GPIO2_D4_u GPIO2_D4
AD42 eMMC_D3/FSPI_D3
UART5_TX_M2 / I2C1_SDA_M3 / EMMC_D5 / GPIO2_D5_u FSPI_D3
eMMC_D6/FSPI_CS0

a
AD41
FSPI_CS0N_M0 / EMMC_D6 / GPIO2_D6_u eMMC_D6/FSPI_CS0
AE41 FSPI_CS0
FSPI_CS1N_M0 / EMMC_D7 / GPIO2_D7_u

m sB
AE42 eMMC_CMD/FSPI_CLK eMMC_CMD/FSPI_CLK FSPI_CLK
FSPI_CLK_M0 / EMMC_CMD / GPIO2_A0_u AB41

r
/ EMMC_CLKOUT / GPIO2_A1_d AC40
UART5_CTSN_M1 / I2C2_SDA_M2 / EMMC_DATA_STROBE / GPIO2_A2_d AD40
UART5_RTSN_M1 / I2C2_SCL_M2 / EMMC_RSTN / GPIO2_A3_d

o s
VCCIO_FLASH

n f l a
AB35
EMMCIO_1V8_1

i :C
AC35 C1300
EMMCIO_1V8_2 1uF

1
l
X5R
6.3V

2
C0201

l
C C

n e
BGA1253_17R00X17R00X1R10

t e r l e v
i n i t y
RK3588S(VCCIO2 Domain) r
a nte i a l
f t w e
so f i d
n
U1000D

g
RK3588S

o
B B

n
VCCIO2 Domain

o C
Operating Voltage=1.8V/3.3V

l
AV2 SDMMC0_D0 SDMMC0_D0

n
PWM8_M1 / I2C3_SCL_M4 / PDM1_SDI3_M0 / JTAG_TCK_M1 / UART2_TX_M1 / SDMMC_D0 / GPIO4_D0_u SDMMC0_D1
AR2 SDMMC0_D1
PWM9_M1 / I2C3_SDA_M4 / PDM1_SDI2_M0 / JTAG_TMS_M1 / UART2_RX_M1 / SDMMC_D1 / GPIO4_D1_u SDMMC0_D2
AV1 SDMMC0_D2
/ I2C8_SCL_M0 / PDM1_SDI1_M0 JTAG_TCK_M0 UART5_CTSN_M0 SDMMC_D2 / GPIO4_D2_u

u
/ / / AT1 SDMMC0_D3
PWM10_M1 / I2C8_SDA_M0 / PDM1_SDI0_M0 / JTAG_TMS_M0 / UART5_RTSN_M0 / SDMMC_D3 / GPIO4_D3_u SDMMC0_D3
AU1 SDMMC0_CMD
PWM7_IR_M1 / CAN0_TX_M1 / PDM1_CLK1_M0 / MCU_JTAG_TCK_M0 / UART5_RX_M0 / SDMMC_CMD / GPIO4_D4_u SD_CLK

X
AR1 SDMMC0_CMD
TEST_CLKOUT_M0 / CAN0_RX_M1 / PDM1_CLK0_M0 / MCU_JTAG_TMS_M0 / UART5_TX_M0 / SDMMC_CLK / GPIO4_D5_d
VCC_1V8_S0
SD_CLK
AK11
VCCIO2_1V8 C1302
100nF
1 X5R
10V
2
C0201

VCCIO_SD_S0

AK10
VCCIO2 C1301
100nF
1

X5R
10V
A A
2

BGA1253_17R00X17R00X1R10 C0201

Xunlong Co.,Limited
Design Name
ORANGEPI 5
Size Page Name Rev
A3 RK3588S Flash/SD Controller 1.2

Date: Tuesday, November 08, 2022 Sheet 13 of 36


5 4 3 2 1
5 4 3 2 1

U1000L RK3588S

RK3588S(USB3.0/DP1.4) USB 3.0 OTG of TYPEC0


/DP1.4 ALT TYPEC0_SBU1/DP0_AUXP
BA8 TYPEC0_SBU1
BB8 TYPEC0_SBU2
TYPEC0_SBU2/DP0_AUXN
USB:U3/Gen1 BB10
DP:RBR/HBR/HBR2/HBR3 TYPEC0_SSRX1P/DP0_TX0P TYPEC0_SSRX1P
BA10 TYPEC0_SSRX1N
TYPEC0_SSRX1N/DP0_TX0N
BB11 TYPEC0_SSTX1P
TYPEC0_SSTX1P/DP0_TX1P BA11
TYPEC0_SSTX1N/DP0_TX1N TYPEC0_SSTX1N
D D

BB13
TYPEC0_SSRX2P/DP0_TX2P TYPEC0_SSRX2P
BA13
TYPEC0_SSRX2N/DP0_TX2N TYPEC0_SSRX2N

BB14 TYPEC0_SSTX2P

n
TYPEC0_SSTX2P/DP0_TX3P BA14
TYPEC0_SSTX2N/DP0_TX3N TYPEC0_SSTX2N

i o
R1400 8.2K 1% R0201
TYPEC0_DP0_REXT 1

t
AW11 2
TYPEC0_DP0_REXT
VDDA_0V85_S0

a
40mA
POWER TYPEC0_DP0_VDD_0V85
AT18

m sB
C1400

1
r
100nF
X5R

2
10V
300mA

f s
AP18 C0201
TYPEC0_DP0_VDDA_0V85_1

a
AR19
TYPEC0_DP0_VDDA_0V85_2

n
i :C l
C1401 C1402

1
100nF 1uF

l
X5R X5R

2
10V 4V

a
C0201 C0201

l
C VCCA_1V8_S0 C
60mA

n e
AR23

r
TYPEC0_DP0_VDDH_1V8

e e v
C1403 C1404

1
t l
100nF 1uF
X5R X5R

2
BGA1253_17R00X17R00X1R10 10V 4V

i y
C0201 C0201

RK3588S(USB2.0)
re l i t
a
U1000K RK3588S

USB Detection
a i
USB2.0 OTG of TYPEC0

t
VCC_3V3_S0

w en
HS/FS/LS

t
Download Port

f
AY11

1
TYPEC0_USB20_OTG_DP TYPEC0_OTG_DP
AY10 R2601
TYPEC0_USB20_OTG_DM TYPEC0_OTG_DM
4.7K

o fid
AW10 4.7K R90641 1 2 R0201 5% R0201
TYPEC0_USB20_OTG_ID

s
5%
TYPEC0_OTG_VBUSDET

2
40K AV10
TYPEC0_USB20_VBUSDET

n
AU7 OTG0_REXT 1 2

g
TYPEC0_USB20_OTG0_REXT R1404 200R R0201 1%

o
B B

n
USB2.0 HOST0

C
AW6
USB20_HOST0_DP

o
USB20_HOST0_DP AV6
USB20_HOST0_DM

l
USB20_HOST0_DM
HS/FS/LS

n
AW5 HOST0_REXT 1 2
USB20_HOST0_REXT R1405 200R R0201 1%

X u USB2.0 HOST1
HS/FS/LS
USB20_HOST1_DP
USB20_HOST1_DM

USB20_HOST1_REXT
AV7
AW7

AU6 HOST1_REXT 1
USB20_HOST1_DP
USB20_HOST1_DM

R1406 200R
2
VDDA_0V75_S0 1% R0201

30mA
USB2.0 POWER USB20_DVDD_0V75_1
AT11
AT12 C1407
USB20_DVDD_0V75_2 100nF
1

X5R
10V
C0201 USB_AVDD_1V8 VCC_1V8_S0
2

AT13 65mA
USB20_AVDD_1V8_1 AT14 C1406
A USB20_AVDD_1V8_2 100nF
A
1

X5R
10V
VCCA_3V3_S0
2

C0201

USB20_AVDD_3V3
AT1045mA Xunlong Co.,Limited
Design Name
C1405
100nF
ORANGEPI 5
1

X5R Size Page Name Rev


BGA1253_17R00X17R00X1R10 10V A3 RK3588S_USB20/USB30/DP PHY 1.2
2

C0201
Date: Tuesday, November 08, 2022 Sheet 14 of 36
5 4 3 2 1
5 4 3 2 1

RK3588S(SARADC/OTP/TSADC)
BOOT MODE CONFIG
SARADC_VIN2_LCD_ID

E
SARADC_VIN4_LCD_ID VCCA_1V8_S0 Item Rup Rdown ADC BOOT MODE(saradc_in5) E
SARADC_VIN3_HP_HOOK
LEVEL1 DNP 100K 0 USB (Maskrom mode)

1
MASKROM KEY R1501
Rup 100K
5%
RECOVERY KEY LEVEL2 100K 20K 682 SD Card-USB
U1000R RK3588S R0201

2
SARADC C1500 1 2 1nF X5R 25V C0201 SARADC_VIN0_BOOT LEVEL3 100K 51K 1365 EMMC-USB

n
12-bit 1MS/s

1
o
AW15 SARADC_VIN0_BOOT R1500 1 10K 2 5% R0201
VCCA_1V8_S0
R1502 LEVEL4 100K 100K 2047 FSPI M0-USB
SARADC_IN0_BOOT

i
DNP
SARADC_VIN1_KEY/RECOVERY 2 1nF X5R 25V C0201 Rdown

t
AY13 C1501 1 R0201
Recovery / SARADC_IN1
LEVEL5 100K 200K 2730 FSPI M1-USB
SARADC_VIN2_LCD_ID 2 1nF X5R 25V C0201

2
AV11 C1502 1
SARADC_IN2
AV13 SARADC_VIN3_HP_HOOK C1503 1 2 1nF X5R 50V C0201 LEVEL6 100K 499K 3412 FSPI M2-USB
SARADC_IN3

m sB
AY15 SARADC_VIN4_LCD_ID C1504 1 2 1nF X5R 25V C0201 FSPI_M2-FSPI_M0-EMMC

r
SARADC_IN4
LEVEL7 100K DNP 4095 -SD Card-USB
AW13
SARADC_IN5

o s
D D
VCCA_1V8_S0

f
R28 1 10K 2 5% R0201
VCCA_1V8_S0

n l a
AP23
SARADC_AVDD_1V8 R31 1 10K 2 5% R0201

i :C
C1506
100nF

l
X5R
10V

a
2
C0201

l
OTP

n e
AK9
Must floating

r
NC

v
AN8

e
OTP_VDDOTP_0V75 VDDA_0V75_S0

t l e
C1507
100nF
1

TSADC

n
X5R

i y
10V

t
2

C0201

e l i
AH37
TSADC_TEST_OUT_TS

r i a
C C

a nt
BGA1253_17R00X17R00X1R10

f t w e
so f i d
RK3588S(VCCIO1 Domain)

ng o n
o C
VCC_1V8_S0

l
U1000G RK3588S

n
VCCIO1 Domain

u
Operating Voltage=1.8V Only

1
B B
R90653 R90652
2.2K 2.2K

X
R38
SPI4_MISO_M0 / UART3_RX_M0/ / I2C3_SDA_M0 / / / GPIO1_C0_z SPI4_MISO/UART3_RX/GPIO1_C0
N41 5% 5%
SPI4_MOSI_M0 / UART3_TX_M0/ / I2C3_SCL_M0 / / / GPIO1_C1_z SPI4_MOSI/UART3_TX/GPIO1_C1
U36 R0201 R0201
SPI4_CLK_M0 / UART3_RTSN / PWM3_IR_M2 / I2C6_SDA_M1 / / I2S0_MCLK / GPIO1_C2_d SPI4_CLK/GPIO1_C2

2
M42
SPI4_CS0_M0 / UART3_CTSN / PWM7_IR_M2 / I2C6_SCL_M1 / / I2S0_SCLK / GPIO1_C3_d I2C7_SDA_M0
U35
SPI4_CS1_M0 / / PWM11_IR_M2 / I2C2_SDA_M3 / PDM0_CLK1_M0 / / GPIO1_C4_d SPI4_CS1/GPIO1_C4
P39
/ UART4_RTSN / / I2C2_SCL_M3 / / I2S0_LRCK / GPIO1_C5_d I2C7_SCL_M0
M41
/ / PWM15_IR_M2 / I2C4_SDA_M4 / PDM0_CLK0_M0 / / GPIO1_C6_d PWM15_IR/GPIO1_C6
P41
/ UART4_CTSN / / I2C4_SCL_M4 / / I2S0_SDO0 / GPIO1_C7_d
U37
SPI1_MISO_M2 / UART6_TX_M2 / / I2C7_SCL_M0 / / I2S0_SDO1 / GPIO1_D0_d U38 I2C7_SCL_M0
SPI1_MOSI_M2 / UART6_RX_M2 / / I2C7_SDA_M0 / PDM0_SDI1_M0 / I2S0_SDO2/I2S0_SDI3 / GPIO1_D1_d I2C7_SDA_M0
P40
SPI1_CLK_M2 UART4_TX_M0 PWM0_M1 I2C1_SCL_M4 PDM0_SDI2_M0 I2S0_SDO3/I2S0_SDI2 / GPIO1_D2_d R39 I2C1_SCL/UART4_TX/GPIO1_D2
SPI1_CS0_M2 / UART4_RX_M0 / PWM1_M1 / I2C1_SDA_M4 / PDM0_SDI3_M0 / I2S0_SDI1 / GPIO1_D3_d I2C1_SDA/UART4_RX/GPIO1_D3
N42
/ / / / / I2S0_SDI0 / GPIO1_D4_d P38
SPI1_CS1_M2 / / / / PDM0_SDI0_M0 / / GPIO1_D5_d HP_DET_L
VCC_1V8_S0

H31 5mA
VCCIO1_1V8 C1508
100nF
1

A X5R A
10V
2

C0201
Xunlong Co.,Limited
BGA1253_17R00X17R00X1R10 Design Name
ORANGEPI 5
Size Page Name Rev
A3 RK3588S_SARADC/1.8V GPIO 1.2

Date: Tuesday, November 08, 2022 Sheet 15 of 36


5 4 3 2 1
5 4 3 2 1

U1000N

RK3588S(MIPI_CSI) MIPI DPHY CSI_RX Port0


MIPI_CSI0_CLK0P
AN42
AN41
MIPI_CSI0_RX_CLK0P
MIPI_CSI_RX_D0-3
MIPI V1.2
MIPI_CSI0_CLK0N MIPI_CSI0_RX_CLK0N MIPI CSI_RX: Option1 Sensor1 x4Lane
2.5Gbps MIPI_CSI0_D0P
AL42
AL41
MIPI_CSI0_RX_D0P 100 Ohm ±10% MIPI_CSI_RX_CLK0
MIPI_CSI0_D0N MIPI_CSI0_RX_D0N
AK41
MIPI_CSI0_D1P MIPI_CSI0_RX_D1P
AK42
MIPI_CSI0_D1N MIPI_CSI0_RX_D1N
MIPI_CSI_RX_D0-1
D Sensor1 x2Lane D
MIPI_CSI0_CLK1P
AU41 MIPI_CSI_RX_CLK0
AU42
MIPI_CSI0_CLK1N
Option2 +
AT41
MIPI_CSI0_D2P MIPI_CSI0_RX_D2P
MIPI_CSI0_D2N
AT42
MIPI_CSI0_RX_D2N MIPI_CSI_RX_D2-3
Sensor2 x2Lane

n
MIPI_CSI0_D3P
AP42
MIPI_CSI0_RX_D3P MIPI_CSI_RX_CLK1
AP41
MIPI_CSI0_D3N MIPI_CSI0_RX_D3N

o
VDDA_0V75_S0

t i
AM37
MIPI_CSI0_AVCC0V75

a
C1602 C1603
100nF 1uF

1
X5R X5R

m sB
10V 4V

2
C0201 C0201

r
VCCA_1V8_S0

o
AM35

s
MIPI_CSI0_AVCC1V8

f
C1600 C1601
1uF 100nF

1
l
X5R X5R

n
i :C
4V 10V
RK3588S

2
C0201 C0201

RK3588S(MIPI_D/C PHY)
l
BGA1253_17R00X17R00X1R10
U1000P

a l
MIPI DPHY:
C
MIPI D/C-PHY DSI_TX Port1 C
100 Ohm ±10%

n e
U1000O BB19

r
MIPI_DPHY1_TX_CLKP/MIPI_CPHY1_TX_TRIO1_C MIPI_DPHY1_TX_CLKP

v
MIPI CPHY: D-PHY:V2.0 BA19 MIPI_DPHY1_TX_CLKN
MIPI D/C-PHY DSI_TX Port0
MIPI_DPHY1_TX_CLKN/MIPI_CPHY1_TX_TRIO1_B

e
50 Ohm ±10% 4.5Gbps/Lane

e
BB16 MIPI_DPHY1_TX_D0P

t
MIPI_DPHY1_TX_D0P/MIPI_CPHY1_TX_TRIO0_B

l
BA16 MIPI_DPHY1_TX_D0N
MIPI_DPHY1_TX_D0N/MIPI_CPHY1_TX_TRIO0_A
D-PHY:V2.0 MIPI_DPHY0_TX_CLKP/MIPI_CPHY0_TX_TRIO1_C
BB34 MIPI_DPHY0_TX_CLKP C-PHY:V1.1

n
BA34 MIPI_DPHY0_TX_CLKN BA17 MIPI_DPHY1_TX_D1P
4.5Gbps/Lane 5.7Gbps/Trio

i y
MIPI_DPHY0_TX_CLKN/MIPI_CPHY0_TX_TRIO1_B MIPI_DPHY1_TX_D1P/MIPI_CPHY1_TX_TRIO1_A BB17
MIPI_DPHY1_TX_D1N/MIPI_CPHY1_TX_TRIO0_C MIPI_DPHY1_TX_D1N

t
BB31 MIPI_DPHY0_TX_D0P
MIPI_DPHY0_TX_D0P/MIPI_CPHY0_TX_TRIO0_B

i
BA31 BA20
C-PHY:V1.1 MIPI_DPHY0_TX_D0N MIPI_DPHY1_TX_D2P

e
MIPI_DPHY0_TX_D0N/MIPI_CPHY0_TX_TRIO0_A MIPI_DPHY1_TX_D2P/MIPI_CPHY1_TX_TRIO2_B

l
BB20 MIPI_DPHY1_TX_D2N
5.7Gbps/Trio MIPI_DPHY1_TX_D2N/MIPI_CPHY1_TX_TRIO2_A

r
BA32 MIPI_DPHY0_TX_D1P

a
MIPI_DPHY0_TX_D1P/MIPI_CPHY0_TX_TRIO1_A BB32 BB22
MIPI_DPHY0_TX_D1N MIPI_DPHY1_TX_D3P

i
MIPI_DPHY0_TX_D1N/MIPI_CPHY0_TX_TRIO0_C MIPI_DPHY1_TX_D3P/NO_USE

a nt
BA22 MIPI_DPHY1_TX_D3N
BA35 MIPI_DPHY1_TX_D3N/MIPI_CPHY1_TX_TRIO2_C
MIPI_DPHY0_TX_D2P/MIPI_CPHY0_TX_TRIO2_B MIPI_DPHY0_TX_D2P
BB35 MIPI_DPHY0_TX_D2N

w
MIPI_DPHY0_TX_D2N/MIPI_CPHY0_TX_TRIO2_A

MIPI D/C-PHY CSI_RX Port1

t
BB37 MIPI_DPHY0_TX_D3P
MIPI_DPHY0_TX_D3P/NO_USE

f e
BA37 MIPI_DPHY0_TX_D3N
MIPI_DPHY0_TX_D3N/MIPI_CPHY0_TX_TRIO2_C BA26
MIPI_DPHY1_RX_CLKP/MIPI_CPHY1_RX_TRIO1_C MIPI_DPHY1_RX_CLKP
D-PHY:V2.0 BB26

o d
MIPI_DPHY1_RX_CLKN/MIPI_CPHY1_RX_TRIO1_B MIPI_DPHY1_RX_CLKN

i
4.5Gbps/Lane
MIPI D/C-PHY CSI_RX Port0

s
BA23 MIPI_DPHY1_RX_D0P

f
MIPI_DPHY1_RX_D0P/MIPI_CPHY1_RX_TRIO0_B BB23
MIPI_DPHY1_RX_D0N/MIPI_CPHY1_RX_TRIO0_A MIPI_DPHY1_RX_D0N
BB41 MIPI_DPHY0_RX_CLKP C-PHY:V1.1

n
MIPI_DPHY0_RX_CLKP/MIPI_CPHY0_RX_TRIO1_C
D-PHY:V2.0 BA41 BB25

g
MIPI_DPHY0_RX_CLKN MIPI_DPHY1_RX_D1P
MIPI_DPHY0_RX_CLKN/MIPI_CPHY0_RX_TRIO1_B 5.7Gbps/Trio MIPI_DPHY1_RX_D1P/MIPI_CPHY1_RX_TRIO1_A BA25 MIPI_DPHY1_RX_D1N
4.5Gbps/Lane

o
B BA38 MIPI_DPHY1_RX_D1N/MIPI_CPHY1_RX_TRIO0_C B

n
MIPI_DPHY0_RX_D0P/MIPI_CPHY0_RX_TRIO0_B MIPI_DPHY0_RX_D0P
BB38 MIPI_DPHY0_RX_D0N BB28 MIPI_DPHY1_RX_D2P
MIPI_DPHY0_RX_D0N/MIPI_CPHY0_RX_TRIO0_A MIPI_DPHY1_RX_D2P/MIPI_CPHY1_RX_TRIO2_B

C
BA28
C-PHY:V1.1 MIPI_DPHY1_RX_D2N

o
BA40 MIPI_DPHY1_RX_D2N/MIPI_CPHY1_RX_TRIO2_A
MIPI_DPHY0_RX_D1P

l
5.7Gbps/Trio MIPI_DPHY0_RX_D1P/MIPI_CPHY0_RX_TRIO1_A
MIPI_DPHY0_RX_D1N/MIPI_CPHY0_RX_TRIO0_C
AY40 MIPI_DPHY0_RX_D1N MIPI_DPHY1_RX_D3P/NO_USE
BA29 MIPI_DPHY1_RX_D3P
BB29 MIPI_DPHY1_RX_D3N

n
AY42 MIPI_DPHY1_RX_D3N/MIPI_CPHY1_RX_TRIO2_C
MIPI_DPHY0_RX_D2P/MIPI_CPHY0_RX_TRIO2_B MIPI_DPHY0_RX_D2P
BA42 MIPI_DPHY0_RX_D2N
C1612 1uF
MIPI_DPHY0_RX_D2N/MIPI_CPHY0_RX_TRIO2_A

u
X5R 4V C0201
AW41 MIPI_DPHY0_RX_D3P AT27 MIPI_D/C_PHY1_VREG 1 2
Power
MIPI_DPHY0_RX_D3P/NO_USE MIPI_D/C_PHY1_VREG

X
AW42 MIPI_DPHY0_RX_D3N
MIPI_DPHY0_RX_D3N/MIPI_CPHY0_RX_TRIO2_C
C1604 1uF VDDA_0V75_S0
X5R 4V C0201 130mA
Power MIPI_D/C_PHY0_VREG
AT33 MIPI_D/C_PHY0_VREG 1 2
MIPI_D/C_PHY1_VDD
AR27

VDDA_0V75_S0 C1613 C1614

1
VDDA_1V2_S0 1uF 100nF
AR33 X5R X5R
MIPI_D/C_PHY0_VDD

2
C1605 C1611 4mA 4V 10V
1uF 100nF AR35 C0201 C0201
1

X5R X5R MIPI_D/C_PHY_VDD_1V2_2 C1608


4V 10V 100nF

1
2

C0201 C0201 X5R


VDDA_1V2_S0 10V
VCCA_1V8_S0

2
C0201
C1610
AR34
MIPI_D/C_PHY_VDD_1V2_1 C1607 AT30 35mA 1 2
A
100nF MIPI_D/C_PHY_VDD_1V8_2 100nF X5R
A
1

X5R C0201 10V


10V
VCCA_1V8_S0
2

C0201

MIPI_D/C_PHY_VDD_1V8_1
AR30 RK3588S Xunlong Co.,Limited
C1609 BGA1253_17R00X17R00X1R10 Design Name
100nF
ORANGEPI 5
1

X5R
10V Size Page Name Rev
2

C0201 A3 RK3588S_MIPI Interface 1.2


RK3588S
BGA1253_17R00X17R00X1R10 Date: Tuesday, November 08, 2022 Sheet 16 of 36
5 4 3 2 1
5 4 3 2 1

RK3588S(HDMI2.1 TX/eDP1.3 TX)


D
Note: D

The HDMI2.1 trace length is less than 100mm. HDMI TX eDP TX HDMI TX
The HDMI2.1 differential trace impedance is 100 OHM.
100 Ohm ±10% 100 Ohm ±10% 100 Ohm ±10%
U1000Q

i o n
HDMI TX/eDP1.3 MUX Port0 Option2:HDMI_TX0
a t
m sB
HDMI:V2.1 12Gbps

r
BB4 EDP_TX0_D0P/HDMI0_TX0P HDMI0_TX0P
eDP:V1.3 5.4Gbps HDMI_TX0_D0P/EDP_TX0_D0P BA4 EDP_TX0_D0N/HDMI0_TX0N HDMI0_TX0N

o s
HDMI_TX0_D0N/EDP_TX0_D0N

f
EDP_TX0_D1P/HDMI0_TX1P

a
BA5 HDMI0_TX1P

l
HDMI_TX0_D1P/EDP_TX0_D1P

n
BB5 EDP_TX0_D1N/HDMI0_TX1N HDMI0_TX1N

i :C
HDMI_TX0_D1N/EDP_TX0_D1N

l
BB7 EDP_TX0_D2P/HDMI0_TX2P HDMI0_TX2P
HDMI_TX0_D2P/EDP_TX0_D2P EDP_TX0_D2N/HDMI0_TX2N

a
BA7

l
HDMI_TX0_D2N/EDP_TX0_D2N HDMI0_TX2N
C C

n e
BA2 EDP_TX0_D3P/HDMI0_TX3P HDMI0_TX3P

r
HDMI_TX0_D3P/EDP_TX0_D3P

v
BB2 EDP_TX0_D3N/HDMI0_TX3N HDMI0_TX3N
HDMI_TX0_D3N/EDP_TX0_D3N

t e l e
BA1 EDP_TX0_AUXP/HDMI0_TX_SBDP
HDMI_TX0_SBDP/EDP_TX0_AUXP HDMI0_TX_SBDP
AY1 EDP_TX0_AUXN/HDMI0_TX_SBDN

n
HDMI_TX0_SBDN/EDP_TX0_AUXN HDMI0_TX_SBDN

HDMI/eDP_TX0_REXT

e i
AY3

i t y
HDMI/eDP_TX0_REXT R1708 1

l
2 8.2K 1%
VDDA_0V75_S0

r
R0201

a nt i a
AM13 440mA
POWER
HDMI/EDP_TX0_VDD_0V75_1 AN12 C1710 C1711

w
HDMI/EDP_TX0_VDD_0V75_2 100nF 4.7uF

t
1

1
f e
X5R X5R
10V 6.3V

o d
2

2
C0201 C0402

s n f i 1mA

g
AN10
HDMI/EDP_TX0_AVDD_0V75

o
C1725

n
B C1712 B
1uF
1

1
100nF

o C
X5R
X5R

l
4V
10V
2

C0201

n
C0201

u
VCCA_1V8_S0

X
AK12 200mA
HDMI/EDP_TX0_VDD_IO_1V8 AL14 C1713 C1714
HDMI/EDP_TX0_VDD_CMN_1V8 100nF 4.7uF
1

X5R X5R
10V 6.3V
2

C0201 C0402

RK3588S
BGA1253_17R00X17R00X1R10

A A
Xunlong Co.,Limited
Design Name
ORANGEPI 5
Size Page Name Rev
A4 RK3588S_HDMI/eDP Interface 1.2

Date: Tuesday, November 08, 2022 Sheet 17 of 36


5 4 3 2 1
5 4 3 2 1

RK3588S(PCIE20/SATA30/USB30)
U1000M

D PCIE20/SATA30 Mux0 D

PCIE20:Gen1/Gen2 L42
SATA30:Gen1/Gen2/Gen3 PCIE20_0_REFCLKP PCIE20_0_REFCLKP
K41 PCIE20_0_REFCLKN
PCIE20_0_REFCLKN
CLK Differential Pair:
100 Ohm±10%

n
H41 DATA Differential Pair:
PCIe20x1_2 PCIE20_0_TXP/SATA30_0_TXP H42
PCIE20_0_TXP
PCIE20: 85 Ohm ±10%
PCIE20_0_TXN
1Lane(RC)--4(1L2) PCIE20_0_TXN/SATA30_0_TXN

o
SATA30: 100 Ohm ±10%

i
USB30: 90ohm ±10%

t
J42

MUX
SATA30 HOST PCIE20_0_RXP/SATA30_0_RXP PCIE20_0_RXP

a
J41 PCIE20_0_RXN
Controller0 PCIE20_0_RXN/SATA30_0_RXN

PCIE20/SATA30/USB30 HOST Mux2

r m sB
f o s
PCIE20:Gen1/Gen2

a
F41
SATA30:Gen1/Gen2/Gen3 PCIE20_2_REFCLKP

n l
F42
PCIE20_2_REFCLKN
USB 30:Gen1

PCIe20x1_1

l i :C
PCIE20_2_TXP/SATA30_2_TXP/USB30_2_SSTXP
E41 USB30_2_SSTXP

a l
D41 USB30_2_SSTXN
C 1Lane(RC)--3(1L1) PCIE20_2_TXN/SATA30_2_TXN/USB30_2_SSTXN C

r n ve
SATA30 HOST D42

e
USB30_2_SSRXP
Controller2 PCIE20_2_RXP/SATA30_2_RXP/USB30_2_SSRXP

e
C42 USB30_2_SSRXN
MUX

t
PCIE20_2_RXN/SATA30_2_RXN/USB30_2_SSRXN

USB30 HOST

i n y l
t
Controller2

e l i
VDDA_0V85_S0

r a
140mA

a nt i
H36
Power
PCIE20_SATA30_0_AVDD_0V85 J36
PCIE20_SATA30_USB30_2_AVDD_0V85 C1800 C1801

w
100nF 1uF

1
t
X5R X5R

e
10V 4V

f
2

2
C0201 C0201

so f i d
VCCA_1V8_S0
G34 270mA

n
PCIE20_SATA30_0_AVDD_1V8 H34

g
PCIE20_SATA30_USB30_2_AVDD_1V8 C1802 C1803

o
B 100nF 1uF B

n 1

1
X5R X5R

PHY C
10V 4V

o 2

2
C0201 C0201

l
RK3588S
BGA1253_17R00X17R00X1R10

n
PCIe2.0
u
X Controller Data & Clk Lane Configure
Name Control GPIO
CLK LANE DATA LANE

PCIE20_2_REFCLKP PCIE20_2_TX PCIE20X1_1_CLKREQ_M*


PCIE20X1_1 PCIE20_2_REFCLKN PCIE20_2_RX PCIE20X1_1_WAKEN_M*
RC PCIE20X1_1_PERSTN_M*
PCIE20X1_1_BUTTON_RSTN

PCIE20X1_2_CLKREQ_M*
PCIE20X1_2 PCIE20_0_REFCLKP PCIE20_0_TX PCIE20X1_2_WAKEN_M*
A RC PCIE20_0_REFCLKN PCIE20_0_RX PCIE20X1_2_PERSTN_M* A
PCIE20X1_2_BUTTON_RSTN

Xunlong Co.,Limited
Design Name
ORANGEPI 5
Size Page Name Rev
A3 RK3588S PCIE2/SATA3/USB3 PHY 1.2
Date: Tuesday, November 08, 2022 Sheet 18 of 36
5 4 3 2 1
5 4 3 2 1

RK3588S(VCCIO4 Domain)
RK3588S(VCCIO6 Domain)
U1000H

VCCIO4 Domain U1000J

Operating Voltage=1.8V/3.3V VCCIO6 Domain


/ PCIE20X1_1_CLKREQN_M2 / DP0_HPDIN_M2 / UART6_RX_M1 / SPI4_MISO_M2 / I2C2_SDA_M4 / GPIO1_A0_d
G40 LCD_MIPI_PWREN_H Operating Voltage=1.8V/3.3V
L40 LCD_MIPI_PWREN_H_1 / AV19 I2S1_MCLK
/ PCIE20X1_1_WAKEN_M2 / / UART6_TX_M1 / SPI4_MOSI_M2 / I2C2_SCL_M4 / GPIO1_A1_d BT1120_D0 / CIF_D0 / I2S1_MCLK_M0 / UART9_RTSN_M1 / SPI0_MISO_M1 / / PCIE20X1_1_CLKREQN_M1 / GPIO4_A0_d
D38 AW18 I2S1_SCLK_TX
PWM0_M2 / / VOP_POST_EMPTY / UART6_RTSN_M1 / SPI4_CLK_M2 / I2C4_SDA_M3 / GPIO1_A2_d PWM0_LED I2C4_SDA_M3_TP BT1120_D1 / CIF_D1 / / I2S1_SCLK_M0 / UART9_CTSN_M1 / SPI0_MOSI_M1 / / PCIE20X1_1_WAKEN_M1 / GPIO4_A1_d
D PWM1_M2 / / / UART6_CTSN_M1 / SPI4_CS0_M2 / I2C4_SCL_M3 / GPIO1_A3_d
L39 PWM1/GPIO1_A3 I2C4_SCL_M3_TP BT1120_D2 / CIF_D2 / / I2S1_LRCK_M0 / / SPI0_CLK_M1 / / PCIE20X1_1_PERSTN_M1 / GPIO4_A2_d
AV26 I2S1_LRCK_TX D

G37 TP1_RST_L AY19


/ / / / SPI2_MISO_M0 / / GPIO1_A4_d BT1120_D3 / CIF_D3 / / / UART0_TX_M2 / / / / GPIO4_A3_d UART0_TX_M2/GPIO4_A3
M40 HDMI_TX0_HPD_M0 / AW19 UART0_RX_M2/GPIO4_A4
/ / HDMI_TX0_HPD_M0 / / SPI2_MOSI_M0 / / GPIO1_A5_d BT1120_D4 / CIF_D4 / / UART0_RX_M2 / SPI2_MISO_M1 / I2C3_SCL_M2 / / GPIO4_A4_d
D39 MIPI_CAM2_RST_L / AU15 TYPEC0_SBU1_DC
/ / / / SPI2_CLK_M0 / / GPIO1_A6_d BT1120_D5 / CIF_D5 / I2S1_SDI0_M0 / UART3_TX_M2 / SPI2_MOSI_M1 / I2C3_SDA_M2 / / GPIO4_A5_d
H38 TP1_INT_L / AV18 I2S1_SDI1
PWM3_IR_M3 / PCIE20X1_1_PERSTN_M2 / / / SPI2_CS0_M0 / PDM1_SDI0_M1 / GPIO1_A7_u BT1120_D6 / CIF_D6 / I2S1_SDI1_M0 / UART3_RX_M2 / SPI2_CLK_M1 / I2C5_SCL_M2 / / GPIO4_A6_d

n
H39 MIPI_TE1 / AW26 TYPEC0_SBU2_DC
/ / / / SPI2_CS1_M0 / PDM1_SDI1_M1 / GPIO1_B0_u BT1120_D7 / CIF_D7 / I2S1_SDI2_M0 / / SPI2_CS0_M1 / I2C5_SDA_M2 / / GPIO4_A7_d
G39 AW27

o
/ / / / SPI0_MISO_M2 / PDM1_SDI2_M1 / GPIO1_B1_d LCD_MIPI_RESET_0 BT1120_CLKOUT / CIF_CLKIN / / I2S1_SDI3_M0 / UART8_TX_M0 / SPI2_CS1_M1 / I2C6_SDA_M3 / / GPIO4_B0_d I2C6_SDA_M3

i
M38 MIPI_CAM1_RST_L AU22 I2C6_SCL_M3
/ / / UART4_RX_M2 / SPI0_MOSI_M2 / PDM1_SDI3_M1 / GPIO1_B2_d SPDIF1_TX_M1 / MIPI_CAMERA0_CLK_M0 / SATA2_ACT_LED_M0 / I2S1_SDO0_M0 / UART8_RX_M0 / SPI0_CS1_M1 / I2C6_SCL_M3 / / GPIO4_B1_u

t
M37 AT15 CAN1_RX_M1/GPIO4_B2
/ / SATA0_ACT_LED_M1 / UART4_TX_M2 / SPI0_CLK_M2 / PDM1_CLK1_M1 / GPIO1_B3_d LCD_MIPI_RESET_1 CAN1_RX_M1 / BT1120_D8 / CIF_HREF / PWM14_M1 / I2S1_SDO1_M0 / UART8_RTSN_M0 / SPI0_CS0_M1 / I2C7_SCL_M3 / PCIE20X1_1_BUTTON_RSTN/ GPIO4_B2_u

a
M39 TP_RST_L / PWM15_IR_M1 AV23 CAN1_TX_M1/GPIO4_B3
/ / / UART7_RX_M2 / SPI0_CS0_M2 / PDM1_CLK0_M1 / GPIO1_B4_u CAN1_TX_M1 / BT1120_D9 / CIF_VSYNC / I2S1_SDO2_M0 / UART8_CTSN_M0 / / I2C7_SDA_M3 / PCIE20X1_2_BUTTON_RSTN/ GPIO4_B3_u
D40 TP_INT_L / PWM11_IR_M1 AV27 I2S1_SDO3
/ / / UART7_TX_M2 / SPI0_CS1_M2 / / GPIO1_B5_u BT1120_D10 / CIF_CLKOUT / I2S1_SDO3_M0 / UART9_TX_M1 / / DP0_HPDIN_M0 / SPDIF0_TX_M1 / GPIO4_B4_u
L38 AU23

m sB
/ / MIPI_CAMERA1_CLK_M0 / UART1_TX_M1 / SPDIF0_TX_M0 / I2C5_SCL_M3 / GPIO1_B6_u I2C5_SCL/UART1_TX/GPIO1_B6 BT1120_D11 / / PWM12_M1 / / UART9_RX_M1 / SPI3_MISO_M1 / / / GPIO4_B5_d SDMMC_PWREN
F37 I2C5_SDA/UART1_RX/GPIO1_B7 AW22 HDMI0_TX_ON_H

r
PWM13_M2 / SATA2_ACT_LED_M1 / MIPI_CAMERA2_CLK_M0 / UART1_RX_M1 / SPDIF1_TX_M0 / I2C5_SDA_M3 / GPIO1_B7_u BT1120_D12 / / PWM13_M1 / / / SPI3_MOSI_M1 / I2C5_SCL_M1 / SATA0_ACT_LED_M0 / GPIO4_B6_d
L37 MIPI_CAM3_CLKOUT / AV22 HDMI_TX0_SCL_M0
PWM14_M2 / / MIPI_CAMERA3_CLK_M0 / UART1_RTSN_M1 / / I2C8_SCL_M2 / GPIO1_D6_u BT1120_D13 / / HDMI_TX0_SCL_M0 / / SPI3_CLK_M1 / I2C5_SDA_M1 / PCIE20X1_2_CLKREQN_M1 / GPIO4_B7_u

o s
G38 MIPI_CAM4_CLKOUT / AW23 HDMI_TX0_SDA_M0
PWM15_IR_M3 / MIPI_CAMERA4_CLK_M0 / UART1_CTSN_M1 / / I2C8_SDA_M2 / GPIO1_D7_u BT1120_D14 / / HDMI_TX0_SDA_M0 / / SPI3_CS0_M1 / I2C8_SCL_M3 / PCIE20X1_2_WAKEN_M1 / GPIO4_C0_u

f
VCC_1V8_S0 AY26
BT1120_D15 / SPDIF1_TX_M2 / PWM6_M1 / HDMI_TX0_CEC_M0 / / SPI3_CS1_M1 / I2C8_SDA_M3 / PCIE20X1_2_PERSTN_M1 / GPIO4_C1_d HDMI_TX0_CEC_M0

a
VCC_1V8_S0

l
G27

n
Note:
VCCIO4_1V8_1 G28 C1902

i :C
VCCIO4_1V8_2 100nF AJ34
BT1120 Only Support Output

1
X5R VCCIO6_1V8 C1906
10V 100nF

1
VCC_1V8_S0 VCC_3V3_S0

2
C0201 X5R
10V

2
G31 AL33 C0201

l
VCCIO4 C1903 VCCIO6_1 AM33 C1907
100nF VCCIO6_2 100nF

1
C C

n e
X5R X5R
10V 10V

r
2

2
C0201 C0201

v
RK3588S RK3588S
BGA1253_17R00X17R00X1R10 BGA1253_17R00X17R00X1R10

t e l e
VCC_3V3_S0

RK3588S(VCCIO5 Domain)

i n i t y

1
e l
U1000I R1914 R1915
2.2K 2.2K

r
VCCIO5 Domain
5% 5%

a
R0201 R0201

2
Operating Voltage=1.8V/3.3V

a nt
I2C6_SCL_M3

AR38 I2C6_SDA_M3
/ PWM10_M0 / SPI4_MISO_M1 / I2C6_SDA_M4 / GMAC1_TXD2 / I2S3_MCLK / FSPI_D0_M2 / SDIO_D0_M1 / GPIO3_A0_u GMAC0_TXD2

w
AR37 GMAC0_TXD3
AUDDSM_LN / PWM11_IR_M0 / SPI4_MOSI_M1 / I2C6_SCL_M4 / GMAC1_TXD3 / I2S3_SCLK / FSPI_D1_M2 / SDIO_D1_M1 / GPIO3_A1_u

t
AT38 GMAC0_RXD2

f e
AUDDSM_LP / UART8_TX_M1 / SPI4_CLK_M1 / / GMAC1_RXD2 / I2S3_LRCK / FSPI_D2_M2 / SDIO_D2_M1 / GPIO3_A2_u
AT40 GMAC0_RXD3
AUDDSM_RN / UART8_RX_M1 / SPI4_CS0_M1 / / GMAC1_RXD3 / I2S3_SDO / FSPI_D3_M2 / SDIO_D3_M1 / GPIO3_A3_u

o d
AT39 GMAC0_TXCLK
AUDDSM_RP / UART8_RTSN_M1 / SPI4_CS1_M1 / / GMAC1_TXCLK / I2S3_SDI / / SDIO_CMD_M1 / GPIO3_A4_d

s i
AV38 GMAC0_RXCLK

f
/ UART8_CTSN_M1 / / I2C4_SDA_M0 / GMAC1_RXCLK / FSPI_CLK_M2 / MIPI_CAMERA0_CLK_M1 / SDIO_CLK_M1 / GPIO3_A5_d
AV37 BT_REG_ON_H
/ / / I2C4_SCL_M0 / ETH1_REFCLKO_25M / / MIPI_CAMERA1_CLK_M1 / / GPIO3_A6_d GPIO3_A6

n
AT37
GMAC0_RXD0

g
/ / / / GMAC1_RXD0 / / MIPI_CAMERA2_CLK_M1 / PWM8_M0 / GPIO3_A7_u
AR39
GMAC0_RXD1

o
/ / / / GMAC1_RXD1 / / MIPI_CAMERA3_CLK_M1 / PWM9_M0 / GPIO3_B0_u

n
B AV39 B
/ UART2_TX_M2 / / / GMAC1_RXDV_CRS / / MIPI_CAMERA4_CLK_M1 / PWM2_M1 / GPIO3_B1_d GMAC0_RXDV_CRS

C
AW34 GMAC0_RSTn_L

o
/ UART2_RX_M2 / / / GMAC1_TXER / I2S2_SDI_M1 / / PWM3_IR_M1 / GPIO3_B2_d

l
AW35 GMAC0_TXD0
/ UART2_RTSN / / / GMAC1_TXD0 / I2S2_SDO_M1 / / / GPIO3_B3_u
AV35
/ UART2_CTSN / / / GMAC1_TXD1 / I2S2_MCLK_M1 / / / GPIO3_B4_u GMAC0_TXD1

n
AY35
/ UART3_TX_M1 / / CAN1_RX_M0 / GMAC1_TXEN / I2S2_SCLK_M1 / / PWM12_M0 / GPIO3_B5_u GMAC0_TXEN

u
AW37
/ UART3_RX_M1 / / CAN1_TX_M0 / GMAC1_MCLKINOUT / I2S2_LRCK_M1 / / PWM13_M0 / GPIO3_B6_d GMAC0_MCLKINOUT
AY34 MIPI_TE0
/ / SPI1_MOSI_M1 / I2C3_SCL_M1 / GMAC1_PTP_REF_CLK / / / / GPIO3_B7_d

X
/ UART7_TX_M1 / SPI1_MISO_M1 / I2C3_SDA_M1 / GMAC1_PPSTRIG / / / / GPIO3_C0_d
AR36 TYPEC_EN MAC_INTB
AW38 MIPI_CAM1_PDN_L
/ UART7_RX_M1 / SPI1_CLK_M1 / / GMAC1_PPSCLK / / / / GPIO3_C1_d
AV40
/ UART7_RTSN_M1 / SPI1_CS0_M1 / I2C8_SCL_M4 / GMAC1_MDC / / MIPI_TE0 / PWM14_M0 / GPIO3_C2_d GMAC0_MDC
AW39
/ UART7_CTSN_M1 / SPI1_CS1_M1 / I2C8_SDA_M4 / GMAC1_MDIO / / MIPI_TE1 / PWM15_IR_M0 / GPIO3_C3_d GMAC0_MDIO
AU34 MIPI_CAM3_RST_L
/ UART5_TX_M1 / SPI3_CS0_M3 / CAN2_RX_M0 / CIF_D8 / / FSPI_CS0N_M2 / / GPIO3_C4_u
AV34 MIPI_CAM2_PDN_L
/ UART5_RX_M1 / SPI3_CS1_M3 / CAN2_TX_M0 / CIF_D9 / / FSPI_CS1N_M2 / / GPIO3_C5_u
AV30
/ / SPI3_MISO_M3 / / CIF_D10 / / / / GPIO3_C6_u MIPI_CAM3_PDN_L
AU30
/ / SPI3_MOSI_M3 / I2C5_SCL_M0 / CIF_D11 / PCIE20X1_2_CLKREQN_M0 / HDMI_TX0_SCL_M2 / / GPIO3_C7_u PCIE20x1_2_CLKREQn_M0
AW31
/ UART4_RX_M1 / SPI3_CLK_M3 / I2C5_SDA_M0 / CIF_D12 / PCIE20X1_2_WAKEN_M0 / HDMI_TX0_SDA_M2 / PWM8_M2 / GPIO3_D0_u PCIE20x1_2_WAKEn_M0
AY27
/ UART4_TX_M1 / SPI0_MISO_M3 / / CIF_D13 / PCIE20X1_2_PERSTN_M0 / / PWM9_M2 / GPIO3_D1_d PCIE20x1_2_PERSTn_M0
AY30
/ UART9_RTSN_M2 / SPI0_MOSI_M3 / I2C7_SCL_M2 / CIF_D14 / / / / GPIO3_D2_d UART9_RTSN_M2_BT
AY31
/ UART9_CTSN_M2 / SPI0_CLK_M3 / I2C7_SDA_M2 / CIF_D15 / / / PWM10_M2 / GPIO3_D3_d UART9_CTSN_M2_BT
AV31
/ UART9_RX_M2 / SPI0_CS0_M3 / / MCU_JTAG_TCK_M1 / / HDMI_TX0_HPD_M1 / / GPIO3_D4_d UART9_RX_M2_BT
AW30
A / UART9_TX_M2 / SPI0_CS1_M3 / / MCU_JTAG_TMS_M1 / / / PWM11_IR_M3 / GPIO3_D5_d UART9_TX_M2_BT A

AF35 VCC_1V8_S0
RESERVED
AF36
VCCIO5_1V8 C1904
100nF
1

X5R
10V
VCC_1V8_S0
2

C0201
AC33
VCCIO5_1
VCCIO5_2
AC34
C1905 Xunlong Co.,Limited
100nF Design Name
1

X5R
10V ORANGEPI 5
2

C0201 Size Page Name Rev


RK3588S A2 RK3588S GPIO 1.2
BGA1253_17R00X17R00X1R10
Date: Tuesday, November 08, 2022 Sheet 19 of 36
5 4 3 2 1
5 4 3 2 1

USB Type-C Port J11


TYPEC0_SSTX1P
C2604 1 2 100nF X5R 10V C0201 TYPEC_SSTX1P A2 B11 TYPEC_SSRX1P TYPEC0_SSRX1P
C2603 1 2 100nF X5R 10V C0201 TYPEC_SSTX1N A3 SSTXP1 SSRXP1 B10 TYPEC_SSRX1N
TYPEC0_SSTX1N SSTXN1 SSRXN1 TYPEC0_SSRX1N
R2600 1 100K 2 R0201 5%
TYPEC0_SBU1_DC
A6 B7 TYPEC0_OTG_DM
TYPEC0_OTG_DP A7 DP1 DN2 B6
TYPEC0_OTG_DM DN1 DP2 TYPEC0_OTG_DP

TYPEC0_SBU1
C2600 1 2 100nF X5R 10V C0201 TYPEC_SBU1 TYPEC0_SSRX2N TYPEC_SSRX2N A10 B2 TYPEC_SSTX2P C0201 10V X5R 100nF 2 1 C2606 TYPEC0_SSTX2P
C2601 1 2 100nF X5R 10V C0201 TYPEC_SBU2 TYPEC_SSRX2P A11 SSRXN2 SSTXP2 B3 TYPEC_SSTX2N C0201 10V X5R 100nF 2 1 C2605
TYPEC0_SBU2 TYPEC0_SSRX2P SSRXP2 SSTXN2 TYPEC0_SSTX2N
TYPEC_CC1 A5 B5 TYPEC_CC2

1
R2602 R2603 TYPEC_SBU1 A8 CC1 CC2 B8 TYPEC_SBU2
D SBU1 SBU2 D
R2604 1 100K 2 R0201 5% 2M 2M
TYPEC0_SBU2_DC
R0201 R0201 A4 B4
VBUS_TYPEC VBUS#1 VBUS#3 VBUS_TYPEC
5% 5% A9 B9
VBUS#2 VBUS#4

2
DNP DNP C9923
22uF A1 B1

1
GND#1 GND#8 U2

1
C0603 A12 B12 ED8 SY6280AAC

n
25V 1 GND#2 GND#9 VCC5V0_SYS VBUS_TYPEC

USB Type-C CC CTRL


GND#3 AZ5825-01F SOT_23_5

2
X5R 2
GND#4 ESD0402 5 1

o
3 C6 IN VOUT
GND#5

i
4 C9
GND#6 10uF 2 C7

1
100nF

t
5 6 GND

1
47uF

2
U2600 GND#7 GND#14 C0402

1
X5R
X5R 4 3 C0603
UT12113-11601-7H

a
EN OCB 10V

2
10V X5R
TYPEC_CC1

2
10 2 UT12113-11601-7H C0201

1
VBUS_TYPEC

2
CC1_10 VBUS R9 10V
11 R10

2
CC1_11 100K

m sB
12 C26170 C0201 4.7K
VCONN_12 VCC5V0_SYS R0201
TYPEC_CC2 1 13 100nF X5R 5%

r
CC2_1 VCONN_13 R2615 0R VCC5V0_SYS TYPEC_EN

1
14 16V R0201
CC2_14

2
3 5% R0201
VDD_3

o
C2612 C2613 4 1 2

s
VDD_4 VCC_3V3_S3
220pF 220pF

f
C2616 C2615
1

C0201 C0201 100nF 100nF

a
1

1
l
C0G C0G X5R X5R

n
VCC5V0_SYS VCC_SYSIN VCC_5V0
2

i :C
50V 50V 2 10V 10V

2
C0201 C0201

l
8 6 I2C6_SCL_M3
9 GND_8 SCL 7
GND_9 SDA I2C6_SDA_M3

a l
15 5 CC_INT0_L
C
ePAD INT# C

r n e
FUSB302MPX

v
MLP14_2R50X2R50X0R80

n t e l e
DCIN-5V/4A

e i l i t y RTC IC

r
a nt i a
TPYE-C POWER IN
f t w e
RTC1
VCC_RTC B5819WS
sod-323-1N5819 R1 4.7K

o d
2 1 1 2

i
VCC5V0_SYS

s
RTC BAT

f
D1 R0201
10K VCC_1V8_S3
R21 1 2
GND1

n
R0201
10K

g
R2 1 2 R0201

o
B 10K B

n
J2 R3 1 2 R0201
C1 2 1 12pF C0G 50V
A2 B11

C
SSTXP1 SSRXP1 C0201

o
A3 B10 U1
SSTXN1 SSRXN1

2
l
Y1 1 8 C2 1 2 10uF X5R
A6 B7 OSCI VDD C0402 6.3V
DP1 DN2 32.768KHz

n
A7 B6 SX-3215
DN1 DP2 2 7
OSCO CLKOUT 32KOUT_WIFI
1 DNP

1
C3 2
A10 B2

u
SSRXN2 SSTXP2 C0201 3 6
A11 B3 RTC_INT_L INT SCL I2C6_SCL_M3
SSRXP2 SSTXN2
5.1k

X
RP1 RP2 4 5
A5 B5 VSS SDA I2C6_SDA_M3
GND CC1 CC2 GND
R0402 A8 B8 5.1kR0402
SBU1 SBU2 HYM8563TS
TSSOP8_3R10X3R10X1R10
VCC5V0_SYS A4 B4 VCC5V0_SYS
A9 VBUS#1 VBUS#3 B9 Address:Read A3H,Write A2H
VBUS#2 VBUS#4
1

ED7
A1 B1
CP1 CP2 AZ5825-01F GND#1 GND#8 CP3 CP4
10uF A12 B12
100nF ESD0402 GND#2 GND#9 10uF 100nF
C0603 1
C0402 GND#3 C0603 C0402
2
3 GND#4
2

4 GND#5
GND#6 GND
GND GND 5 6 GND
GND#7 GND#14
UT12113-11601-7H

A A

Xunlong Co.,Limited
Design Name
ORANGEPI 5
Size Page Name Rev
A3 Power_Type-C 1.2

Date: Tuesday, November 08, 2022 Sheet 20 of 36


5 4 3 2 1
5 4 3 2 1
U2200A

PMIC1 RK806-1 PMIC RK806-1 BUCK C2200 22uF


VCC_SYSIN VCC_SYSIN
C2201 22uF

峰 值 电 流 2 . 5 A X5R
2
C0603
1 44 52 1
X5R C0603
2
T85 峰 值 电 流 6 A
VDD_DDR_S0 VCC5 VCC1_1 VDD_GPU_S0
0.80V VCC1_2
53
SLEEP1_RESET1_DEVOFF1_VSEL1
PMIC_SW5 PMIC_SW1
0.85V
VSEL4
45 50 0.55 0.75 0.95
BUCK5 BUCK1
R2200 L2200 SW5 SW1_1 51 L2201
VSEL5 SW1_2
Default:0.85V C2202 C2203 100R C9922 0.47uH 0.22uH C2209 R2208 C2210 C2205 C2280
2.5A 6.5A

1
47uF 22uF 5% 1uF IND_201610 46 IND_404020 1uF 100R 22uF 47uF 47uF
Low frequency:

1
PMIC_INT_L VOUT5
X5R 10V X5R 10V R0201 X5R 49 PMIC_VOUT1 X5R 5% X5R 10V X5R 10V X5R 10V
0.85V-->0.75V VOUT1

2
C0603 C0603 6.3V 6.3V R0201 C0603 C0603 C0603
PMIC_RESET_L

2
0.675 0.85 0.935 C0201 C0201

2
47 VDD_GPU_S0
VDD_DDR_S0 FB5 (FB=0.5V)
Feedback from RK3588S Feedback from RK3588S
PMIC_SPI_CLK
PMIC_SPI_CS 48
D (FB=0.5V)FB1 D
PMIC_SPI_MOSI

VCC_SYSIN VCC_SYSIN
峰 值 电 流 1 . T110 A C2213 22uF
X5R C0603
峰 值 电 流 3 A
IF TVS UNMOUNTED,
VCC_SYSIN 28 33 1 2 T95
VCC_1V1_NLDO_S3 VDD2_DDR_S3 VCC6 VCC2_1 VDD_CPU_LIT_S0
600mA 1.10V 658mA 34
ESD OR SURGE SHOULD BE

n
VCC2_2
PMIC_SW6 29 35 PMIC_SW2 0.95V
1

DAMAGE THE PMIC!!! 0.55 0.75 0.95


ED2200 L2202 SW6 SW2_1 36 L2203

o
BUCK6 BUCK2
AZ5825-01F 0.47uH SW2_2 0.24uH
1.045 1.1 1.155 C2214 C2215 C2216 C2221 R2219 C2217 C2218 C2281

1
i
ESD0402-6 This device must be mounted.Replacing TVS mode is not 47uF 22uF 100pF IND_201610 PMIC_VOUT6 30 IND_252012 1uF 100R 22uF 22uF 22uF
2.5A 5A

1
VOUT6 PMIC_VOUT2

t
recommended, if must, please choose the same specifications X5R 10V X5R 10V C0G R2218 37 X5R 5% X5R 10V X5R 10V X5R 10V
120K VOUT2

2
Operating Supply Vltage :5.5V(5.25-6V) C0603 C0603 25V 6.3V R0201 C0603 C0603 C0603
2

2
PeakPulse Current:>10A(tp=8/20uS) C0201 1% C0201

a
PMIC_FB6

2
Surge Clamping Voltage:<6.5V R0201 31 VDD_CPU_LIT_S0
FB6 (FB=0.5V)
DO NOT DELETE IT! Feedback from RK3588S

1
m sB
R2227
100K 38
(FB=0.5V) FB2
LPDDR4/4x=1.1V

r
120K 1%
R0201
LPDDR5=1.05V 110K

2
VCC_SYSIN VCC_SYSIN

o
C2225 22uF C2226 22uF

s
X5R C0603 X5R C0603

f
T60
2 1 1 54 1 2
峰 值 电 流 2 A

a
VDDQ_DDR_S0 VCC9 VCC3 T75
232.60mA

n l
VDD_LOGIC_S0
0.60V 0.75V

i :C
0.57 0.6 0.63 PMIC_SW9 68
VSEL5 PMIC_PWR_CTRL2 SW9 PMIC_SW3
1 2
0.475 0.5 0.525
L2204 55 0.675 0.75 0.825
BUCK9 BUCK3
R2242 0R R0201 5% C2229 0.47uH SW3 L2205

1
R2244 C2228 C2227 100pF IND_201610 PMIC_VOUT9 67 0.24uH C2230 R2238 C2231 C2232 C2282
2.5A 5A
1

1
DNP 47uF 22uF C0G R2236 VOUT9 IND_252012 1uF 100R 22uF 47uF 47uF

1
a l
120K X5R 10V X5R 10V 25V 20K X5R 5% X5R 10V X5R 10V X5R 10V

2
R0201 C0603 C0603 C0201 1% 6.3V R0201 C0603 C0603 C0603
PMIC_FB9

2
R0201 66 C0201

n e
FB9 (FB=0.5V)
2

2
56 VDD_LOGIC_S0
VOUT3

1
C C

v
R2241 Feedback from RK3588S
100K

e
PMIC_PWR_CTRL3

e
VSEL4 1 2 1%
LPDDR4/4x=0.6V

t
0R 20K 100K

l
R2290 R0201 5% R0201

2
R2291 VCC_SYSIN VCC_SYSIN
1

DNP LPDDR5=0.5V 0R DNP C2235 22uF C2236 22uF

n
120K X5R C0603 X5R C0603

y
2 . 5 A 2 A

i
R0201 2 1 7 22 1 2
峰 值 电 流 VCC8 VCC4 T77 峰 值 电 流

t
VCC_3V3_S3 T33 VDD_VDENC_S0
2

i
0.775V

e l
PMIC_SW8 6
SW8 BUCK8 BUCK4 SW4
23 PMIC_SW4 0.675 0.75 0.825

r
L2206 L2207
2.5A 5A

a
0.47uH 0.24uH C2291 C2240 C2237 C2283

1
1uF 22uF 22uF 47uF

i
C2238 C2239 IND_201610 IND_252012 R2209

a nt
1

1
47uF 22uF PMIC_VOUT8 5 24 X5R 100R X5R 10V X5R 10V X5R 10V
VOUT8 VOUT4

2
X5R 10V X5R 10V 6.3V 5% C0603 C0603 C0603
2

2
C0603 C0603 C0201 R0201

2
VDD_VDENC_S0

t
Feedback from RK3588

f e
VCC_SYSIN VCC_SYSIN
C2241 22uF

峰 值 电 流 1 A X5R C0603
0 . 5 A

o d
2 1 27 43 峰 值 电 流0.35A

i
VCC10 VCC7 T20
T18

s
VCC1V8_PMU_DDR_S3 VCC_1V8_S3 VCC_2V0_PLDO_S3
2.0V

f
Default:1.8V
PMIC_SW10 26 BUCK10 BUCK7 42 PMIC_SW7
2.5A 2.5A

n
L2208 SW10 SW7 L2209

g
0.47uH 0.47uH C2244 C2245

1
C2242 C2243 IND_201610 IND_201610 22uF 47uF

o
1

47uF 22uF PMIC_VOUT10 PMIC_VOUT7

n
25 41 X5R 10V X5R 10V
VOUT10 VOUT7

2
X5R 10V X5R 10V C0603 C0603
2

C
C0603 C0603

l o
B RK806-1 B
QFN68_7R00X7R00X0R80_T

n
PMIC RK806-1 Managerment PMIC RK806-1 LDO

X u
VCC_1V8_S3_PLDO6 U2200C VCC_2V0_PLDO_S3 U2200B VCC_1V8_S0
200mA
VCCIO 59 0.5A 60 C2246 1uF 1 2 6.3VC0201 X5R Default:1.8V
C2248 1uF 2 1 20 18 PMIC_SPI_CS VCC11 PLDO1 2.7 3.3 3.6
VCCIO (IIC/SPI)CS VCCA_1V8_S0
6.3VX5R C0201 C2247 150mA 1.65 1.8 1.95
1

15 PMIC_SPI_MOSI 1uF
1

(SDA)MOSI 0.3A 1uF 1


R2258 X5R 6.3V
PLDO2
58 C2249 2 6.3VC0201 X5R Default:1.8V
PMIC_SPI_CLK 100K
2

17 C0201
(SCL)CLK VDDA_1V2_S0
2mA
300mA
PLDO6

5%
16 PMIC_PWR_CTRL3 R0201
VCC_SYSIN (PWRCTRL3)SO 0.3A 1uF 1
2

VCC_1V8_S3 PLDO3
57 C2250 2 6.3VC0201 X5R Default:1.2V
61 PMIC_PWR_CTRL2 VCC_SYSIN
20220929 21 PWRCTRL2 VCCA_3V3_S0
200mA
VCCA 62 SLEEP1_RESET1_DEVOFF1_VSEL1 VCCA_1V8_S0 VCC_1V8_S0
PWRCTRL1 0.5A 1uF 1 AVDD1V8_DDR_PLL_S0
C2254 64 63 C2251 2 6.3VC0201 X5R Default:3.3V
1

10uF VCC12 PLDO4


VCC_SYSIN
1

VCCIO_SD_S0
C0402
VCCA
R2261 R2263 C2252 1mA
1

X5R
10K 10K 10uF
2

C2290
3 39 5% 5% X5R 10V 0.3A 65 C2253 1uF 1 2 6.3VC0201 X5R Default:3.3V 1uF

1
C4 SYNC_CLK (M/S)EXT_EN PLDO5
1

R0201 R0201 C0402 X5R


10uF
PMIC_INT_L
PLDO
2

2 19 6.3V
C0402 SYNC INT

2
X5R C0201
VCC_1V1_NLDO_S3 VDD_0V75_S3
2

R2264
1 2 PMIC_VDC 32 40 PMIC_RESET_L
10mA
45K

VDC RESETB
510K
0.3A
2

C2260 4 69 13 14 C2255 2.2uF 1 2 6.3VC0402 X5R Default:0.75V


2

R0201 PWRON ePAD T1 VCC13 NLDO1


D6 R2265 1nF C2262
1

VDDA_DDR_PLL_S0
B5819WS 510K C0201 100nF C2257 126mA
1

sod-323-1N5819 R0201 X5R RESET X5R 10V 1uF Default:0.85V;


RK806-1 0.3A C2258 2.2uF 1
2

25V C2261 C0201 X5R 6.3V 12 2 6.3VC0402 X5R


Low frequency:0.85V-->0.75V
1
1

100nF NLDO2
1

A QFN68_7R00X7R00X0R80_T C0201 A
VDDA_0V75_S0
X5R 10V 500mA
2

C0201
POWER KEY 0.5A 11 C2259 2.2uF 1 2 6.3VC0402 X5R Default:0.75V
Note:
NLDO3
RK3588S VCC_1V1_NLDO_S3 VDDA_0V85_S0
nPOR 500mA
Reset Key Control Path 9 0.5A 10 C2263 2.2uF 1 2 6.3VC0402 X5R Default:0.85V
VCC14 NLDO4
TSADC_SHUT C2264
Xunlong Co.,Limited
1

TSADC_SHUT Control Path 1uF


0.3A
set Key

X5R 6.3V 8 Design Name


NLDO5
2

C0201
5 4 3 2 1

VDD_CPU_BIG0 VDD_CPU_BIG1
VCC_SYSIN
T96 峰 值 电 流 3 . 5 A
VCC_SYSIN
峰 值 电 流 3 . 5 A
VDD_CPU_BIG0_S0 T97 VDD_CPU_BIG1_S0
C2300 C2301 U2300 0.95V 0.95V
1

22uF 22uF D1 D3 0.55 0.75 1.05 C2308 C2309 U2301 0.55 0.75 1.05

1
D VIN_1 SW_1 D
X5R X5R D2 D4 L2300 22uF 22uF D1 D3
VIN_2 SW_2 0.24uH VIN_1 SW_1
2

10V 10V E1 E3 X5R X5R D2 D4 L2301


VIN_3 SW_3 VIN_2 SW_2 0.24uH

2
C0603 C0603 E2 E4 IND_252012 R2301 C2302 C2303 C2304 C2306 C2307 10V 10V E1 E3
VIN_4 SW_4 A4 100R 1uF 22uF 47uF 22uF 47uF C0603 C0603 E2 VIN_3 SW_3 E4 IND_252012 R2305 C2310 C2311 C2312 C2314 C2315

1
BIG/NPU_EN A2 VOUT 5% X5R X5R X5R X5R X5R VIN_4 SW_4 A4 100R 1uF 22uF 22uF 47uF 47uF

1
EN B2 R0201 6.3V 6.3V 6.3V 6.3V 6.3V BIG/NPU_EN A2 VOUT 5% X5R X5R X5R X5R X5R

n
VCC_SYSIN GND1 EN

2
VSEL2 A1 B3 C0201 C0603 C0603 C0603 C0603 B2 R0201 6.3V 6.3V 6.3V 6.3V 6.3V
I2C0_SDA_M2 VSEL GND2 GND1

2
B1 C1 VSEL6 A1 B3 C0201 C0603 C0603 C0603 C0603
SDA GND3 VSEL GND2

o
I2C0_SCL_M2 I2C0_SDA_M2

2
A3 C2 VCC_SYSIN B1 C1
SCL GND4 SDA GND3

i
I2C0_SCL_M2

2
C25 C26 C3 A3 C2
2.2uF 2.2uF GND5 SCL GND4

t
B4 C4 C3
1

X5R X5R AGND GND6 VDD_CPU_BIG0_S0 B4 GND5 C4


RK860-2 AGND GND6 VDD_CPU_BIG1_S0
Feedback from RK3588S

a
10V 10V C5
2.2uF
C16
2.2uF RK860-3
Feedback from RK3588S
2

C0201 C0201 WLCSP20_1R65X2R05X0R63

1
X5R X5R WLCSP20_1R65X2R05X0R63

m sB
10V 10V
VCC_3V3_S3

2
C0201 C0201

r
BIG/NPU_EN
VDD
1 2 OUT

o
R2302

s
100K

f
1

R0201 R2303

a
120K

l
5%

n
RK3588S

i :C
5%

100R
R0201 FB

l
2

DCDC

a l
C C

e r n ve
e
VDD_NPU

i n t y l
t
VCC_SYSIN
峰 值 电 流 4 A

e l i
T90 VDD_NPU_S0

r a
0.90V

a nt i
C2317 C2316 U2302 0.55 0.75 0.95
1

22uF 22uF D1 D3
X5R X5R D2 VIN_1 SW_1 D4 L2302

w
VIN_2 SW_2 0.24uH
2

10V 10V E1 E3
VIN_3 SW_3

t
C0603 C0603 E2 E4 IND_252012 R2309 C2318 C2319 C2320 C2322 C2323
VIN_4 SW_4 100R 1uF 22uF 22uF 47uF 22uF

f e
A4
1

1
BIG/NPU_EN A2 VOUT 5% X5R X5R X5R X5R X5R
EN B2 R0201 6.3V 6.3V 6.3V 6.3V 6.3V

o d
GND1
2

VSEL3 A1 B3 C0201 C0603 C0603 C06032 C0603

i
I2C2_SDA_M0 VSEL GND2

s
B1 C1

f
I2C2_SCL_M0 SDA GND3
2

A3 C2
SCL GND4 C3

n
B4 GND5 C4

g
AGND GND6 VDD_NPU_S0 Feedback from RK3588S

o
B RK860-2 B

n
WLCSP20_1R65X2R05X0R63

l o C
un
X
I2C0_SCL_M2
I2C0_SDA_M2

I2C2_SCL_M0
I2C2_SDA_M0
A A
VSEL2
VSEL3
VSEL6

Xunlong Co.,Limited
Design Name
ORANGEPI 5
Size Page Name Rev
A3 Power_Ext Discrete 1.2

Date: Tuesday, November 08, 2022 Sheet 22 of 36


5 4 3 2 1
5 4 3 2 1

D D

USB2.0 Type-A Port


usb-af-04-004c02

n
USB-A-H

o
7

i
6 Shield3

t
VCC5V0_SYS 5 Shield2
Shield1

a
4
R26 1 2.2R 2 R0201 TYPEC0_OTG0DM 3 VBUS
TYPEC0_OTG_DM D-
TYPEC0_OTG_DP R27 1 2.2R 2 R0201 TYPEC0_OTG0DP 2

m sB
1 D+
GND

r
P1

o s

1
f
ED9
AZ5825-01F

l a
ESD0402

l n
i :C

2
a l
C C

e r n ve
n t l e
i y
USB20_HOST0_DP

t
USB20_HOST0_DM
USB3.0 HOST

re l i
USB20_HOST1_DP

a
USB20_HOST1_DM

i
VCC5V0_USB_HOST

a nt
USB30_2_SSTXP

1
USB30_2_SSTXN

w
ED10

t
USB30_2_SSRXP AZ5825-01F
ESD0402 VCC5V0_USB_HOST

f e
USB30_2_SSRXN VCC5V0_USB_HOST
DOWN5
22 19

o d
GND7 GND1

2
s i
10 1

f
VCC_5V0 USB20_HOST1_DM 11 VCC1 VCC 2
VCC5V0_USB_HOST D1- D- USB20_HOST0_DM
USB20_HOST1_DP 12 3

USB3.0
USB20_HOST0_DP

n
C2504 U2501 D1+ D+
13 4

g
2 1 1uF 5 1 USB30_2_SSRXN USB30_HOST2_SSRXN GND4 GND8
R2512 1 2 0R R0201 5% 14 5

USB2.0
X5R 10V IN VOUT

o
B RX1- RX- B

n
C0402 R36 2 C2505
GND USB30_2_SSRXP R2513 1 2 0R R0201 5% USB30_HOST2_SSRXP 15 6
100K 22uF C2503 RX1+ RX+
1

C
16 7
100nF

o
R0201 4 3 X5R GND5 GND2
EN OCB USB30_2_SSTXN C2506 1 2 100nF X5R C0201 10V USB30_HOST2_SSTXN 17 8

l
2.4V 10V X5R SSTX1- SSTX-
USB30_2_SSTXP C2507 1 2 100nF X5R C0201 10V USB30_HOST2_SSTXP 18 9
SY6280AAC/TCS9163
2

C0603 16V SSTX1+ SSTX+


1

SOT_23_5 R2514 C0201 21 20

n
GND6 GND3
6.8K ESD61 JEU03SC
R0201 USB30_HOST2_SSRXN 1 10 USB30_HOST2_SSRXN

u
USB30_HOST2_SSRXP 2 IN1 NC1 9 USB30_HOST2_SSRXP
IN2 NC2 USB3-A Device
2

3 8

X
USB30_HOST2_SSTXN 4 GND1 GND2 7 USB30_HOST2_SSTXN USB3_0_DIPX22X25X30X1031
USB30_HOST2_SSTXP IN3 NC3 USB30_HOST2_SSTXP
Ilim(A)=6800/Rset(ohm) 5
IN4 NC4
6

DFN2510P10E

Cj<=0.3pF

A A

Xunlong Co.,Limited
Design Name
ORANGEPI 5
Size Page Name Rev
A3 USB20/USB30 HOST Port 1.2

Date: Tuesday, November 08, 2022 Sheet 23 of 36


5 4 3 2 1
5 4 3 2 1

VCC1V8_PMU_DDR_S3 U3800B

F1 A3
F12 VDD1_1 VSS_1 A10
G4 VDD1_2 VSS_2 C1
G9 VDD1_3 VSS_3 C5
U3800A VDD1_4 VSS_4

LPDDR4/4X
T4 C8
CH A CH B T9 VDD1_5 VSS_5 C12

VDD1: 1.8V
U1 VDD1_6 VSS_6 D2
VDD1_7 VSS_7 VDDQ_DDR
DDR_CH0_DQ0_A B2
DQ0_a DQ0_b
AA2 DDR_CH0_DQ0_B
U12
VDD1_8 VSS_8
D4 Sequence:VDD1-VDD2-VDDQ
DDR_CH0_DQ1_A C2 Y2 VDD2_DDR_S3 D9
DQ1_a DQ1_b DDR_CH0_DQ1_B VSS_9
DDR_CH0_DQ2_A E2 V2 D11
DQ2_a DQ2_b DDR_CH0_DQ2_B VSS_10
DDR_CH0_DQ3_A F2 U2 A4 E1 C3807 C3808 C3809 C3810 C3811 C3812 C3813 C3814 C3815 C3816 C3817 C3818 C3819 C3820 C3821 C3822 C3823 C3824 C3825
DQ3_a DQ3_b DDR_CH0_DQ3_B VDD2_1 VSS_11
F4 U4 A9 E5 47uF 47uF 47uF 1uF 1uF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF

1
DDR_CH0_DQ4_A DQ4_a DQ4_b DDR_CH0_DQ4_B VDD2_2 VSS_12
DDR_CH0_DQ5_A E4 V4 F5 E8 X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
DQ5_a DQ5_b DDR_CH0_DQ5_B VDD2_3 VSS_13
DDR_CH0_DQ6_A C4 Y4 F8 E12 10V 25V 25V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V
DQ6_a DQ6_b DDR_CH0_DQ6_B VDD2_4 VSS_14

2
DDR_CH0_DQ7_A B4 AA4 H1 G1 C0603 C0603 C0603 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201
DQ7_a DQ7_b DDR_CH0_DQ7_B VDD2_5 VSS_15
H5 G3
D3 W3 H8 VDD2_6 VSS_16 G5
D DDR_CH0_DQS0P_A DQS0_t_a DQS0_t_b DDR_CH0_DQS0P_B VDD2_7 VSS_17 D
E3 V3 DDR_CH0_DQS0N_B
H12 G8
DDR_CH0_DQS0N_A DQS0_c_a DQS0_c_b VDD2_8 VSS_18 VDD2_DDR_S3
K1 G10
C3 Y3 K3 VDD2_9 VSS_19 G12
DDR_CH0_DM0_A DMI0_a DMI0_b DDR_CH0_DM0_B VDD2_10 VSS_20

LPDDR4 LPDDR4X
K10 J1
B11 AA11 K12 VDD2_11 VSS_21 J3 C3826 C3827 C3828 C3829 C3830 C3831 C3832 C3833 C3834 C3835 C3836 C3837 C3838 C3839 C3840
DDR_CH0_DQ8_A DDR_CH0_DQ8_B

n
DQ8_a DQ8_b VDD2_12 VSS_22 47uF 47uF 1uF 1uF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF
C11 Y11 N1 J10 For U3800

1
DDR_CH0_DQ9_A DQ9_a DQ9_b DDR_CH0_DQ9_B VDD2_13 VSS_23

VDD2: 1.1V 1.1V


DDR_CH0_DQ10_A E11 V11 N3 J12 X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
DQ10_a DQ10_b DDR_CH0_DQ10_B VDD2_14 VSS_24
F11 U11 N10 K2 25V 25V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V

o
DDR_CH0_DQ11_A DQ11_a DQ11_b DDR_CH0_DQ11_B VDD2_15 VSS_25

2
F9 U9 N12 K4 C0603 C0603 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201

i
DDR_CH0_DQ12_A DQ12_a DQ12_b DDR_CH0_DQ12_B VDD2_16 VSS_26
DDR_CH0_DQ13_A E9 V9 R1 K9
DQ13_a DQ13_b DDR_CH0_DQ13_B VDD2_17 VSS_27

t
DDR_CH0_DQ14_A C9 Y9 R5 K11
DQ14_a DQ14_b DDR_CH0_DQ14_B VDD2_18 VSS_28
DDR_CH0_DQ15_A B9 AA9 DDR_CH0_DQ15_B
R8 N2
DQ15_a DQ15_b VDD2_19 VSS_29 VCC1V8_PMU_DDR_S3

a
R12 N4
D10 W10 U5 VDD2_20 VSS_30 N9
DDR_CH0_DQS1P_A DQS1_t_a DQS1_t_b DDR_CH0_DQS1P_B VDD2_21 VSS_31
E10 V10 U8 N11
DDR_CH0_DQS1N_A DQS1_c_a DQS1_c_b DDR_CH0_DQS1N_B VDD2_22 VSS_32 C3841
AB4 P1 C3842 C3843 C3844 C3845 C3846 C3847 C3848

m sB
VDD2_23 VSS_33 47uF 100nF 100nF 100nF 100nF 100nF 100nF 100nF
C10 Y10 AB9 P3 LPDDR4 LPDDR4X

1
DDR_CH0_DM1_A DMI1_a DMI1_b DDR_CH0_DM1_B VDD2_24 VSS_34
VDDQ_DDR P10 X5R X5R X5R X5R X5R X5R X5R X5R
VDD1: 1.70-1.95 1.70-1.95

r
H2 R2 VSS_35 P12 25V 10V 10V 10V 10V 10V 10V 10V
DDR_CH0_A0_A DDR_CH0_A0_B
CA0_a CA0_b VSS_36 VDD2: 1.06-1.17 1.06-1.17

2
DDR_CH0_A1_A J2 P2 B3 T1 C0603 C0201 C0201 C0201 C0201 C0201 C0201 C0201
CA1_a CA1_b DDR_CH0_A1_B VDDQ_1 VSS_37
H9 R9 B5 T3 VDDQ: 1.06-1.17 0.57-0.65

o
DDR_CH0_A2_A DDR_CH0_A2_B

s
H10 CA2_a CA2_b R10 B8 VDDQ_2 VSS_38 T5
DDR_CH0_A3_A DDR_CH0_A3_B

f
H11 CA3_a CA3_b R11 B10 VDDQ_3 VSS_39 T8
DDR_CH0_A4_A CA4_a CA4_b DDR_CH0_A4_B VDDQ_4 VSS_40

a
DDR_CH0_A5_A J11 P11 D1 T10
CA5_a CA5_B DDR_CH0_A5_B VDDQ_5 VSS_41

n l
D5 T12
J8 P8 D8 VDDQ_6 VSS_42 V1

i :C
DDR_CH0_CLKP_A CK_t_a CK_t_b DDR_CH0_CLKP_B VDDQ_7 VSS_43
J9 P9 D12 V5
DDR_CH0_CLKN_A CK_c_a CK_c_b DDR_CH0_CLKN_B VDDQ_8 VSS_44
F3 V8 R3820 0R 1% R0402

l
1 2 J4 P4 1 2 F10 VDDQ_9 VSS_45 V12 1 2
DDR_CH0_LP4/4X_CKE0_A CKE0_a CKE0_b DDR_CH0_LP4/4X_CKE0_B VDDQ_10 VSS_46 VDDQ_DDR_CKE_S3 VDD2_DDR_S3
R3810 1 49.9R 2 R0201 J5 P5 R3812 1 49.9R 2 R0201 U3 W2
DDR_CH0_LP4/4X_CKE1_A CKE1_a CKE1_b DDR_CH0_LP4/4X_CKE1_B VDDQ_11 VSS_47

LPDDR4 LPDDR4X
a
49.9R 49.9R

l
R3811 R0201 K8 N8 R3813 R0201 U10 W4
CKE2_a_NC CKE2_b_NC W1 VDDQ_12 VSS_48 W9 R3821 0R 1% R0402
VDDQ_13 VSS_49

VDDQ: 1.1V 0.6V


W5 W11 1 2 VDDQ_DDR_S0

n e
VDDQ_14 VSS_50 VDDQ_DDR_CK_S0
H4 R4 W8 Y1
DDR_CH0_LP4/4X_CS0_A CS0_a CS0_b DDR_CH0_LP4/4X_CS0_B VDDQ_15 VSS_51

r
H3 R3 W12 Y5
DDR_CH0_LP4/4X_CS1_A DDR_CH0_LP4/4X_CS1_B

v
K5 CS1_a CS1_b N5 AA3 VDDQ_16 VSS_52 Y8
R3800 CS2_a_NC CS2_b_NC AA5 VDDQ_17 VSS_53 Y12

e
VDDQ_18 VSS_54

e
10K 1 2 G2 T2 1 2 VDD2_DDR_S3 AA8 AB3
VDD2_DDR_S3 ODT_CA_a ODT_CA_b VDDQ_19 VSS_55

t
0R

l
C R0201 1% R3801 AA10 AB5 R3808 1% R0402 C
R3804 240R 10K VDDQ_20 VSS_56 AB8 1 2
1% R0201 R0201 VSS_57 AB10
VDDQ_DDR_S0 0.6V

n
1 2 A5 1% VSS_58

i y
VDDQ_DDR ZQ0
1 2 A8 1 2
ZQ1 VDDQ_DDR VDD2_DDR_S3 1.1V

t
G11 T11 DDR_RESET R3809 0R.NC 1%R0402
R3806 240R ZQ2_NC RESET_n

i
A1 AA1
DNU_1 DNU_7

e
1% R0201 C3899

l
A2 AA12
1

1nF DNP DNU_2 DNU_8


A11 AB1 LPDDR4x 0R DNP

r
LPDDR4_200P X5R 50V A12 DNU_3 DNU_9 AB2

a
DNU_4 DNU_10
LPDDR4 DNP 0R
2

BGA200_15R00X10R00X0R90 C0201 B1 AB11

i
DNU_5 DNU_11

a nt
B12 AB12
DNU_6 DNU_12

LPDDR4_200P

w
BGA200_15R00X10R00X0R90

t
H9HCNNNCPMMLXR-NEE 200FBGA LPDDR4X 4266Mbps 4GB

o f i d e
s
VCC1V8_PMU_DDR_S3 U3801B

f
F1 A3

n
F12 VDD1_1 VSS_1 A10

g
U3801A G4 VDD1_2 VSS_2 C1 VDDQ_DDR

CH A CH B G9 VDD1_3 VSS_3 C5

o
VDD1_4 VSS_4

n
T4 C8
B2 AA2 T9 VDD1_5 VSS_5 C12 C3849 C3850 C3851 C3852 C3853 C3854 C3855 C3856 C3857 C3858 C3859 C3860 C3861 C3862 C3863 C3864 C3865 C3866 C3867
DDR_CH1_DQ0_C DQ0_a DQ0_b DDR_CH1_DQ0_D VDD1_6
VDD1: 1.8V VSS_6 47uF 47uF 47uF 1uF 1uF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF

C
C2 Y2 U1 D2

1
DDR_CH1_DQ1_C DDR_CH1_DQ1_D

o
E2 DQ1_a DQ1_b V2 U12 VDD1_7 VSS_7 D4 X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
DDR_CH1_DQ2_C DDR_CH1_DQ2_D

l
F2 DQ2_a DQ2_b U2 VDD2_DDR_S3 VDD1_8 VSS_8 D9 10V 25V 25V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V
DDR_CH1_DQ3_C DQ3_a DQ3_b DDR_CH1_DQ3_D VSS_9

2
DDR_CH1_DQ4_C F4 U4 D11 C0603 C0603 C0603 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201
DQ4_a DQ4_b DDR_CH1_DQ4_D VSS_10
E4 V4 A4 E1

n
DDR_CH1_DQ5_C DQ5_a DQ5_b DDR_CH1_DQ5_D VDD2_1 VSS_11
DDR_CH1_DQ6_C C4 Y4 A9 E5
DQ6_a DQ6_b DDR_CH1_DQ6_D VDD2_2 VSS_12
DDR_CH1_DQ7_C B4 AA4 F5 E8
DDR_CH1_DQ7_D

u
DQ7_a DQ7_b F8 VDD2_3 VSS_13 E12 VDD2_DDR_S3
D3 W3 H1 VDD2_4 VSS_14 G1
DDR_CH1_DQS0P_C DQS0_t_a DQS0_t_b DDR_CH1_DQS0P_D VDD2_5 VSS_15
B E3 V3 H5 G3 B

X
DDR_CH1_DQS0N_C DQS0_c_a DQS0_c_b DDR_CH1_DQS0N_D VDD2_6 VSS_16
H8 G5 C3868 C3869 C3870 C3871 C3872 C3873 C3874 C3875 C3876 C3877 C3878 C3879 C3880 C3881 C3882
VDD2_7 VSS_17 47uF 47uF 1uF 1uF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF
C3 Y3 H12 G8 For U3801

1
DDR_CH1_DM0_C DMI0_a DMI0_b DDR_CH1_DM0_D VDD2_8 VSS_18
K1 G10 X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
B11 AA11 K3 VDD2_9 VSS_19 G12 25V 25V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V
DDR_CH1_DQ8_C DQ8_a DQ8_b DDR_CH1_DQ8_D VDD2_10 VSS_20
LPDDR4 LPDDR4X

2
DDR_CH1_DQ9_C C11 Y11 K10 J1 C0603 C0603 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201
DQ9_a DQ9_b DDR_CH1_DQ9_D VDD2_11 VSS_21
DDR_CH1_DQ10_C E11 V11 K12 J3
DQ10_a DQ10_b DDR_CH1_DQ10_D VDD2_12 VSS_22
DDR_CH1_DQ11_C F11 U11 N1 J10
DQ11_a DQ11_b DDR_CH1_DQ11_D VDD2_13 VSS_23
VDD2: 1.1V 1.1V

DDR_CH1_DQ12_C F9 U9 DDR_CH1_DQ12_D
N3 J12
E9 DQ12_a DQ12_b V9 N10 VDD2_14 VSS_24 K2 VCC1V8_PMU_DDR_S3
DDR_CH1_DQ13_C DQ13_a DQ13_b DDR_CH1_DQ13_D VDD2_15 VSS_25
DDR_CH1_DQ14_C C9 Y9 N12 K4
DQ14_a DQ14_b DDR_CH1_DQ14_D VDD2_16 VSS_26
DDR_CH1_DQ15_C B9 AA9 R1 K9
DQ15_a DQ15_b DDR_CH1_DQ15_D VDD2_17 VSS_27
R5 K11
D10 W10 R8 VDD2_18 VSS_28 N2 C3883 C3884 C3885 C3886 C3887 C3888 C3889 C3890
DDR_CH1_DQS1P_C DQS1_t_a DQS1_t_b DDR_CH1_DQS1P_D VDD2_19 VSS_29
E10 V10 R12 N4 47uF 100nF 100nF 100nF 100nF 100nF 100nF 100nF

1
DDR_CH1_DQS1N_C DQS1_c_a DQS1_c_b DDR_CH1_DQS1N_D VDD2_20 VSS_30
U5 N9 X5R X5R X5R X5R X5R X5R X5R X5R
C10 Y10 U8 VDD2_21 VSS_31 N11 25V 10V 10V 10V 10V 10V 10V 10V
DDR_CH1_DM1_C DMI1_a DMI1_b DDR_CH1_DM1_D VDD2_22 VSS_32 2

2
AB4 P1 C0603 C0201 C0201 C0201 C0201 C0201 C0201 C0201
H2 R2 AB9 VDD2_23 VSS_33 P3
DDR_CH1_A0_C CA0_a CA0_b DDR_CH1_A0_D VDD2_24 VSS_34
J2 P2 VDDQ_DDR P10
DDR_CH1_A1_C CA1_a CA1_b DDR_CH1_A1_D VSS_35
DDR_CH1_A2_C H9 R9 P12
CA2_a CA2_b DDR_CH1_A2_D VSS_36
DDR_CH1_A3_C H10 R10 B3 T1
CA3_a CA3_b DDR_CH1_A3_D VDDQ_1 VSS_37
DDR_CH1_A4_C H11 R11 B5 T3
CA4_a CA4_b DDR_CH1_A4_D VDDQ_2 VSS_38
DDR_CH1_A5_C J11 P11 DDR_CH1_A5_D
B8 T5
CA5_a CA5_B B10 VDDQ_3 VSS_39 T8
J8 P8 D1 VDDQ_4 VSS_40 T10
DDR_CH1_CLKP_C CK_t_a CK_t_b DDR_CH1_CLKP_D VDDQ_5 VSS_41
J9 P9 D5 T12
DDR_CH1_CLKN_C CK_c_a CK_c_b DDR_CH1_CLKN_D VDDQ_6 VSS_42
D8 V1
1 2 J4 P4 1 2 D12 VDDQ_7 VSS_43 V5
DDR_CH1_LP4/4X_CKE0_C CKE0_a CKE0_b DDR_CH1_LP4/4X_CKE0_D VDDQ_8 VSS_44
DDR_CH1_LP4/4X_CKE1_C R3814 1 49.9R 2 R0201 J5 P5 R3816 1 49.9R 2 R0201 F3 V8
CKE1_a CKE1_b DDR_CH1_LP4/4X_CKE1_D VDDQ_9 VSS_45
R3815 49.9R R0201 K8 N8 R3817 49.9R R0201 F10 V12
CKE2_a_NC CKE2_b_NC U3 VDDQ_10 VSS_46 W2
VDDQ_11 VSS_47
LPDDR4 LPDDR4X

U10 W4
H4 R4 W1 VDDQ_12 VSS_48 W9
DDR_CH1_LP4/4X_CS0_C CS0_a CS0_b DDR_CH1_LP4/4X_CS0_D VDDQ_13 VSS_49
VDDQ: 1.1V 0.6V

H3 R3 DDR_CH1_LP4/4X_CS1_D
W5 W11
DDR_CH1_LP4/4X_CS1_C K5 CS1_a CS1_b N5 W8 VDDQ_14 VSS_50 Y1
CS2_a_NC CS2_b_NC W12 VDDQ_15 VSS_51 Y5
1 2 G2 T2 1 2 AA3 VDDQ_16 VSS_52 Y8
VDD2_DDR_S3 ODT_CA_a ODT_CA_b VDD2_DDR_S3 VDDQ_17 VSS_53
R3802 10K 1% R0201 R3803 AA5 Y12
A 10K AA8 VDDQ_18 VSS_54 AB3 A
R3805 240R 1% R0201 R0201 AA10 VDDQ_19 VSS_55 AB5
1 2 A5 1% VDDQ_20 VSS_56 AB8
5 4 3 2 1

TF CARD
VCC_3V3_S3 VCC3V3_SD_S0

R4200 1 DNP 2 0R 5%
R0402
D D
SDMMC0_D0 2 3
SDMMC0_D1
SDMMC0_D2 C4200
100nF Q4200

n
SDMMC0_D3

1
WPM2015-3/TR

1
X5R D4200 R4202

1
o
SDMMC0_CMD 16V SOT-23 ESD5451N 10K.NC

2
C0201 ESD0402-6 R0201

t
For discharge
SD_CLK SDMMC_PWREN 1 2 5%

a
SDMMC_DET_L R4201 DNP
10K

2
m sB
SDMMC_PWREN R0201

r
5%

n f o l a s
l i :C
a l
C C

e r n ve
t l e

13

12
n

G4

G3
y
SDMMC0_D2 2 R4204 22R 5% SD_D2

i
1 R0402 1
VCC3V3_SD_S0 DATA2

t
SDMMC0_D3 1 2 R4205 22R 5% R0402 SD_D3 2

i
SDMMC0_CMD 2 R4206 22R 5% SD_CMD CD/DATA3

e
R0402

l
1 3
CMD

r
4

a
SD_CLK VDD

i
5

a nt
6 CLK
SDMMC0_D0 1 2 R4207 22R 5% R0402 SD_D0 7 VSS

w
SDMMC0_D1 2 R4208 22R 5% R0402 SD_D1 DATA0

t
1 8
DATA1

e
SDMMC_DET_L 2 R4209 22R 5% SD_DET

f
1 R0402 9
CD

o i d

G1

G2
s f
J4200
1

1
TFP09-2-12B

10

11
C4201 C4202 D4201 D4202 D4203 D4204 D4205 D4206 D4207

g n
10uF 100nF ESD5341N ESD5341N ESD5341N ESD5341N ESD5341N ESD5341N ESD5341N MICROSD-9P-A
1

o
X5R X5R ESD0402-6 ESD0402-6 ESD0402-6 ESD0402-6 ESD0402-6 ESD0402-6 ESD0402-6

n
B B
10V 10V

o C
2

C0603 C0201

l
2

2
Close to MicroSD Card

un
X
MicroSD Card

A A
Xunlong Co.,Limited
Design Name
ORANGEPI 5
Size Page Name Rev
Flash-TF Card
Rockchip Confidential
A4 1.2

Date: Tuesday, November 08, 2022 Sheet 26 of 36


5 4 3 2 1
5 4 3 2 1

MIPI-CSI0_RX
MIPI_CSI0_RX_D0P
MIPI_CSI0_RX_D0N

MIPI_CSI0_RX_D1P
MIPI_CSI0_RX_D1N

MIPI_CSI0_RX_D2P
MIPI_CSI0_RX_D2N
Cam1
OK-10F030-04 VCC_3V3_S3
D MIPI_CSI0_RX_D3P D
CON_SMD_OK-10F030-04
MIPI_CSI0_RX_D3N
30 1
MIPI_CSI0_RX_CLK0P 30 1
MIPI_CSI0_RX_D3P 29 2 C4618
MIPI_CSI0_RX_CLK0N 29 2
MIPI_CSI0_RX_D3N 28 3 1uF

1
27 28 3 4 I2C7_SCL_M0 X5R

n
MIPI_CSI0_RX_D2P 26 27 4 5 I2C7_SDA_M0 10V
MIPI_CAM3_CLKOUT 26 5
MIPI_CSI0_RX_D2N

2
25 6 C0201
25 6

o
24 7
24 7

i
MIPI_CSI0_RX_CLK0P 23 8 MIPI_CAM3_RST_L
MIPI_CSI0_RX_CLK0N 23 8 MIPI_CAM3_PDN_L

t
22 9
MIPI_CAM3_RST_L 22 9
21 10
MIPI_CSI0_RX_D1P 21 10 MIPI_CAM3_CLKOUT

a
20 11
MIPI_CSI0_RX_D1N 19 20 11 12
18 19 12 13
MIPI_CAM3_PDN_L 18 13 VCC_3V3_S3

m sB
MIPI_CSI0_RX_D0N 17 14
MIPI_CSI0_RX_D0P 16 17 14 15

r
16 15

o s
I2C7_SCL_M0

33 G_34
32 G_33
31 G_32
G_31
f
I2C7_SDA_M0

34
l n
i :C l
a l
C C

e r n ve
n t l e
e i l i t y
r
a nt i a
f t w e
so f i d
g o n
B B

l o n C
un
X
A A

Xunlong Co.,Limited
Design Name
ORANGEPI 5
Size Page Name Rev
A3 VI-Camera MIPI CSI0-RX / Debug 1.2

Date: Tuesday, November 08, 2022 Sheet 27 of 36


5 4 3 2 1
5 4 3 2 1

VI-Camera DPHY_RX MIPI D-PHY0


Cam2
OK-10F030-04
CON_SMD_OK-10F030-04
MIPI_DPHY0_RX_CLKP
MIPI_DPHY0_RX_CLKN
30 1
MIPI_DPHY0_RX_D3P 29 30 1 2
MIPI_DPHY0_RX_D0P 29 2
D MIPI_DPHY0_RX_D0N MIPI_DPHY0_RX_D3N 28 3 D
27 28 3 4 I2C7_SCL_M0
MIPI_DPHY0_RX_D2P 26 27 4 5 I2C7_SDA_M0
MIPI_DPHY0_RX_D1P 26 5
MIPI_DPHY0_RX_D1N MIPI_DPHY0_RX_D2N 25 6
24 25 6 7
MIPI_DPHY0_RX_CLKP 23 24 7 8 MIPI_CAM1_RST_L
MIPI_DPHY0_RX_D2P 23 8
MIPI_DPHY0_RX_D2N MIPI_DPHY0_RX_CLKN 22 9 MIPI_CAM1_PDN_L

n
21 22 9 10
MIPI_DPHY0_RX_D1P 20 21 10 11 MIPI_CAM4_CLKOUT
MIPI_DPHY0_RX_D3P 20 11

o
MIPI_DPHY0_RX_D3N MIPI_DPHY0_RX_D1N 19 12
19 12 VCC_3V3_S3

i
18 13 VCC_3V3_S3
MIPI_DPHY0_RX_D0N 18 13

t
17 14
MIPI_DPHY0_RX_D0P 16 17 14 15
16 15

a
C4716
MIPI_CAM4_CLKOUT
1uF

1
33 G_34
32 G_33
31 G_32
G_31
m sB
X5R
10V

34

2
C0201
MIPI_CAM1_PDN_L

MIPI_CAM1_RST_L

n f o l a s
l i :C
a
I2C7_SCL_M0

l
C I2C7_SDA_M0 C

e r n ve
n t l e
VI-Camera DPHY_RX
e i l i t y
r
MIPI D-PHY1
MIPI_DPHY1_RX_CLKP

a nt i a Cam3

w
MIPI_DPHY1_RX_CLKN

t
OK-10F030-04

e
CON_SMD_OK-10F030-04

f
MIPI_DPHY1_RX_D0P
MIPI_DPHY1_RX_D0N
30 1

o d
MIPI_DPHY1_RX_D3P 29 30 1 2

i
MIPI_DPHY1_RX_D1P 29 2
MIPI_DPHY1_RX_D3N

s
MIPI_DPHY1_RX_D1N 28 3

f
27 28 3 4 I2C2_SCL_M0
MIPI_DPHY1_RX_D2P 26 27 4 5 I2C2_SDA_M0
MIPI_DPHY1_RX_D2P

n
MIPI_DPHY1_RX_D2N 25 26 5 6

g
MIPI_DPHY1_RX_D2N 25 6
24 7

o
B MIPI_DPHY1_RX_CLKP 23 24 7 8 MIPI_CAM2_RST_L B

n
MIPI_DPHY1_RX_D3P 23 8
MIPI_DPHY1_RX_D3N MIPI_DPHY1_RX_CLKN 22 9 MIPI_CAM2_PDN_L
22 9

C
21 10

o
MIPI_DPHY1_RX_D1P 20 21 10 11 MIPI_CAM4_CLKOUT

l
MIPI_DPHY1_RX_D1N 19 20 11 12
18 19 12 13 VCC_3V3_S3
MIPI_CAM2_PDN_L VCC_3V3_S3

n
MIPI_DPHY1_RX_D0N 17 18 13 14
MIPI_CAM2_RST_L 17 14
MIPI_DPHY1_RX_D0P 16 15
16 15

u
C4727
1uF

1
33 G_34
32 G_33
31 G_32
G_31

X5R
10V
34

2
C0201
I2C2_SDA_M0
I2C2_SCL_M0

A A

Xunlong Co.,Limited
Design Name
ORANGEPI 5
Size Page Name Rev
A3 VI-Camera_MIPI-DPHY-RX 1.2

Date: Tuesday, November 08, 2022 Sheet 28 of 36


5 4 3 2 1
5 4 3 2 1

HDMI2.1 TX0
HDMI0_TX0P
HDMI0_TX0N
HDMI0_TX1P
HDMI0_TX1N

23
22
HDMI0_TX2P
HDMI0_TX2N

G4
G3
HDMI0_TX3P
HDMI0_TX3N
U5000 JEU03SC
DFN2510P10E Cj<=0.2pF
HDMI0_TX2P C5000 1 2 220nF X5R 10V C0201 HDMI0_TX2P_PORT 1 10 HDMI0_TX2P_PORT 1
D HDMI0_TX_SBDP IO1 NC_10 D2P D
HDMI0_TX2N C5001 1 2 220nF X5R 10V C0201 HDMI0_TX2N_PORT 2 9 HDMI0_TX2N_PORT 2
HDMI0_TX_SBDN IO2 NC_9 D2_G
3 8 3
HDMI0_TX1P C5002 1 2 220nF X5R 10V C0201 HDMI0_TX1P_PORT 4 GND GND 7 HDMI0_TX1P_PORT 4 D2N
HDMI_TX0_SCL_M0 IO3 NC_7 D1P
HDMI_TX0_SDA_M0 HDMI0_TX1N C5003 1 2 220nF X5R 10V C0201 HDMI0_TX1N_PORT 5 6 HDMI0_TX1N_PORT 5
IO4 NC_6 6 D1_G
HDMI_TX0_CEC_M0 D1N
HDMI0_TX0P C5004 1 2 220nF X5R 10V C0201 HDMI0_TX0P_PORT 1 10 HDMI0_TX0P_PORT 7
HDMI_TX0_HPD_M0

n
HDMI0_TX0N C5005 1 2 220nF X5R 10V C0201 HDMI0_TX0N_PORT 2 IO1 NC_10 9 HDMI0_TX0N_PORT 8 D0P
3 IO2 NC_9 8 9 D0_G
HDMI0_TX_ON_H GND GND D0N

o
HDMI0_TX3P C5006 1 2 220nF X5R 10V C0201 HDMI0_TX3P_PORT 4 7 HDMI0_TX3P_PORT 10
IO3 NC_7 CLKP

i
HDMI0_TX3N C5007 1 2 220nF X5R 10V C0201 HDMI0_TX3N_PORT 5 6 HDMI0_TX3N_PORT 11

Type A
IO4 NC_6 CLK_G

t
12
U5001 JEU03SC 13 CLKN
HDMI0_TX_CEC_PORT HDMI0_SBDP CEC

a
DFN2510P10E 14
HDMI0_TX_SCL_PORT 15 Utility
HDMI0_TX_SDA_PORT 16 SCL
SDA

m sB
17
18 GND
VCC5V_HDMI_TX0

r
HDMI0_SBDN 19 +5V
HPD

f o s

1
HDMI TX DDC

a
C5008
VCC_5V0 VCC_5V0 VCC5V_HDMI_TX0 10uF

l
ED5000 ED5001 ED5002 ED5003 ED5004

G1
G2
1
ESD5341N ESD5341N ESD5341N ESD5341N ESD5341N

i :C
X5R J5000
2 B5819WS HDMI_TYPE_A

20
21
D5000 1 ESD0402-6 ESD0402-6 ESD0402-6 ESD0402-6 ESD0402-6 10V
VCC_3V3_S0

2
sod-323-1N5819 C0402 hdmi-type-a
1

2
D5001

a
B5819WS

l
C sod-323-1N5819 C

n e
2

r v
1

R5000

e
1

e
10K Q5000 R5001 HDMI0_TX0P_PORT

t l
5% 2SK3018 1.8K HDMI0_TX0N_PORT
R0201 SOT_323 5%
1

n
HDMI0_TX1P_PORT
2

R0201

i y
HDMI_TX0_SCL_M0 HDMI0_TX_SCL_PORT HDMI0_TX1N_PORT
2

2 3

i t
HDMI0_TX2P_PORT

e
VCC_3V3_S0

l
HDMI0_TX2N_PORT

r a
HDMI0_TX3P_PORT HDMI0_TX_SBDP C5009 1 2 1uF X5R 10V C0402 HDMI0_SBDP

a nt i
HDMI0_TX3N_PORT
1

R5002 R5003 HDMI0_TX_SBDN C5010 1 2 1uF X5R 10V C0402 HDMI0_SBDN

w
10K 1K

1
t
5% 5% R5004 R5005 R5006 R5007 R5008 R5009 R5010 R5011
499R 499R 499R 499R 499R 499R 499R 499R

e
R0201 R0201

f
1

VCC_1V8_S0
2

R5012 1% 1% 1% 1% 1% 1% 1% 1%
C5011 1.8K R0201 R0201 R0201 R0201 R0201 R0201 R0201 R0201

o d
100pF
2

2
Q5001 5%

i
1

s
C0G 2SK3018 R0201

f
2

50V SOT_323
1
2

C0201 R5013 R5014

2
n
HDMI_TX0_SDA_M0 2 3 HDMI0_TX_SDA_PORT 47K 47K

g
Q5002 Q5003 Q5004 Q5005 R0402 R0402
3

3
o
B WNM6002-3/TR WNM6002-3/TR WNM6002-3/TR WNM6002-3/TR 5% 5% B

n
HDMI0_TX_ON_H 1 SOT_323 1 SOT_323 1 SOT_323 1 SOT_323
HDMI_TX0_HPD_M0

1
o C
2

2
l

3
HDMI TX CEC

n
1
Rds=1.7ohm/2.6V Q5006 Q5007

u
2SK3018 2SK3018

2
Coss=7.33pf

3
SOT_323 SOT_323 2.4-5.3V

X
1 1 2
VCC_3V3_S0 VCC_5V0 R5015
Note: 1K

2
R5016
R0201
47K 5%
The controller only support AC coupled R0402
1

R5017 Q5008 link In order to backward compatibility 5%


27K 2SK3018

1
5% SOT_323
or to meet HDMI2.0 (1.4b) DC common
1

R0201 mode spec and Voff, need do R based


HDMI_TX0_CEC_M0 HDMI0_TX_CEC_PORT level-shift.
2

2 3

Switch on in HDMI2.0(TMDS) mode


Switch off in HDMI2.1(FRL) mode.

A A

Xunlong Co.,Limited
Design Name
ORANGEPI 5
Size Page Name Rev
A3 VO-HDMI2.1 TX 1.2

Date: Tuesday, November 08, 2022 Sheet 29 of 36


5 4 3 2 1
5 4 3 2 1

MIPI DPHY TX MIPI DPHY0 TX LCD1

32
FPC Pin List

GND_32
CNN30_1R00_FP05SL_V
SARADC_VIN4_LCD_ID
FPC30-05PH-BOT
SARADC_VIN2_LCD_ID
Pin1 :GND
Pin2 :D0N
TP_RST_L Pin3 :D0P
TP1_RST_L 1 Pin4 :GND
D 1 D
2 Pin5 :D1N
LCD_MIPI_PWREN_H 2 MIPI_DPHY0_TX_D0N
3 Pin6 :D1P
LCD_MIPI_PWREN_H_1 MIPI_DPHY0_TX_D0P 3 4 Pin7 :GND
5 4 Pin8 :CLKN/AUXN
LCD_MIPI_BL_PWM2_M0 MIPI_DPHY0_TX_D1N 5 6 Pin9 :CLKP/AUXP
LCD_MIPI_BL_PWM6_M0 6 MIPI_DPHY0_TX_D1P
7 Pin10:GND

n
7 8 Pin11:D2N
MIPI_TE0 8 MIPI_DPHY0_TX_CLKN
9 Pin12:D2P
MIPI_TE1 MIPI_DPHY0_TX_CLKP 9

o
10 Pin13:GND
10

i
11 Pin14:D3N
I2C7_SCL_M0 MIPI_DPHY0_TX_D2N 11

t
12 Pin15:D3P
I2C7_SDA_M0 12 MIPI_DPHY0_TX_D2P
13 Pin16:GND
13

a
14 Pin17:LCD_PWM_BL
I2C2_SDA_M0 14 MIPI_DPHY0_TX_D3N
15 Pin18:LCD_TE
I2C2_SCL_M0 MIPI_DPHY0_TX_D3P 15 16 Pin19:VCC3V3_LCD
16

m sB
LCD_MIPI_BL_PWM2_M0 17 Pin20:LCD_RST
17 18 MIPI_TE0 Pin21:LCD_ID
LCD_MIPI_RESET_0

r
19 18 Pin22:LCD_PWREN
LCD_MIPI_RESET_1 VCC3V3_LCD_MIPI 19 20 LCD_MIPI_RESET_0 Pin23:TP_I2C_SCL
20

o
SARADC_VIN2_LCD_ID 21 Pin24:TP_I2C_SDA

s
TP_INT_L 21 LCD_MIPI_PWREN_H

f
22 Pin25:TP_INT
TP1_INT_L I2C7_SCL_M0 22

a
23 Pin26:TP_RST
23 I2C7_SDA_M0

l
Pin27:GND

n
24
TP_INT_L 24

i :C
25 Pin28:5V0
25 26 TP_RST_L Pin29:5V0
26

l
27 Pin30:5V0
VCC3V3_LCD_MIPI 27 28
28

a l
VCC5V0_SYS 29
C
29 30 C
30 VCC5V0_SYS

n e
C5500 C5501
10uF 100nF

1
r
VCC_5V0

v
X5R X5R C5502 C5503
10V 16V 100nF 22uF

1
2
e
2
C0603 C0201 X5R X5R

t l
16V 10V

GND_31

2
C0201 C0603

i n y

31
e
MIPI DPHY1 rTX l i t
a nt i a
w
LCD2

f t e

32
o i d
FPC Pin List

GND_32
s
CNN30_1R00_FP05SL_V

f
FPC30-05PH-BOT
Pin1 :GND

n
Pin2 :D0N

g
Pin3 :D0P

o
B 1 Pin4 :GND B

n
1 2 Pin5 :D1N
2 MIPI_DPHY1_TX_D0N

C
3 Pin6 :D1P
MIPI_DPHY1_TX_D0P

o
3 4 Pin7 :GND

l
5 4 Pin8 :CLKN/AUXN
MIPI_DPHY1_TX_D1N 5 6 Pin9 :CLKP/AUXP
MIPI_DPHY1_TX_D1P

n
7 6 Pin10:GND
7 8 Pin11:D2N
8 MIPI_DPHY1_TX_CLKN

u
9 Pin12:D2P
MIPI_DPHY1_TX_CLKP 9 10 Pin13:GND
10

X
11 Pin14:D3N
MIPI_DPHY1_TX_D2N 11 12 Pin15:D3P
12 MIPI_DPHY1_TX_D2P
13 Pin16:GND
13 14 Pin17:LCD_PWM_BL
14 MIPI_DPHY1_TX_D3N
15 Pin18:LCD_TE
MIPI_DPHY1_TX_D3P 15 16 Pin19:VCC3V3_LCD
LCD_MIPI_BL_PWM6_M0 17 16 Pin20:LCD_RST
17 18 MIPI_TE1 Pin21:LCD_ID
19 18 Pin22:LCD_PWREN
VCC3V3_LCD_MIPI_1 19 20 LCD_MIPI_RESET_1 Pin23:TP_I2C_SCL
SARADC_VIN4_LCD_ID 21 20 Pin24:TP_I2C_SDA
21 22 LCD_MIPI_PWREN_H_1 Pin25:TP_INT
I2C2_SCL_M0 23 22 Pin26:TP_RST
23 24 I2C2_SDA_M0 Pin27:GND
TP1_INT_L 25 24 Pin28:5V0
25 26 TP1_RST_L Pin29:5V0
27 26 Pin30:5V0
27 28
VCC3V3_LCD_MIPI 29 28
A VCC5V0_SYS 29 A
30 VCC5V0_SYS
30
C5507 C5508
10uF 100nF C5509 C5510
1

100nF 22uF
X5R X5R
Xunlong Co.,Limited
1

1
10V 16V X5R X5R
2

C0603 C0201 16V 10V Design Name


GND_31

2
C0201 C0603
ORANGEPI 5
31

Size Page Name Rev


A3 VO-MIPI DPHY0/1-TX 1.2

Date: Tuesday, November 08, 2022 Sheet 30 of 36


5 4 3 2 1
5 4 3 2 1

10M/100M/1000M ETH R247 R0201

GMAC0_MCLKINOUT
GMAC0_MCLKINOUT R6710 1 2 100R 5% CLK125
1 2 GND PHY addr = 1
C6704 R6712
R0201 3.3Vpp 2.49K 1%
RXCTL PHYAD2 R231 1 R0201 2 4.7K

1
DNP 120R MAC <----- PHY 0_DVDD33
C0201 5% DVDDRG0 RXCLK PHYAD1 R233 1 R0201 2 4.7K

2
R0201 R90486 R0201
4.7k Internal 1.8V R234 1 2 4.7K RXD3 PHYAD0 R235 1 R0201 2 NC

0_LED0/CFG_EXT
2

0_LED2/CFG1
0_LED1/CFG0
R0201

XTAL_OUT0
0_AVDD33
0_AVDD10
XTAL_IN0
CLK125
RSET0
R0201 Pull up to stop PLL
D VCCIO_PHY0=3.3V DNP 22R MAX:1A R236 1 2 NC RXD2 PLLOFF R237 1 R0201 2
Pull up to add 2ns delay to TXC for TXD latching
4.7K D

R238 1 R0201 2 NC 4.7K


VCCIO_PHY0=1.8V 120R 100R TXDLY R239 1 R0201 2

40
39
38
37
36
35
34
33
32
31
RXD1
Pull up to add 2ns delay to RXC for RXD latching

AVDD33 40
RSET
AVDD10 38
XTAL_IN
CLKOUT
XTAL_OUT/EXT_CLK
LED2/CFG_LDO1
LED1/CFG_LDO0
LED0/CFG_EXT
INTB/PMEB
R240 1 R0201 2 4.7K RXD0 RXDLY R241 1 R0201 2 NC
GND
41

n
EGND#1

VCC_PHY0_IO Voltage Config

o
1 2 DVDDRG0
GMAC0_MDIO

i
R225 1.5K GND 0_LED0/CFG_EXT 1 R0201 2 VCC_3V3_S3
4.7K

t
MDI0+ 1 30 REGOUT0 R449
GMAC0_MDC R0201 MDI[0]+ REG_OUT
MDI0- 2 29 0_DVDD33 0_LED1/CFG0 1 R0201 2
靠近YT8531C MDI[0]- DVDD33 29 GND
4.7K

a
2.2R
0_AVDD10 3
AVDD10 3 DVDD_RG
28 DVDDRG0 External 1.8V R90490
R8 1 2 R0201 RXCLK MDI1+ 4 27 RXCLK 0_LED2/CFG1 1 R0201 2
GMAC0_RXCLK MDI[1]+ RXC/PHYAD1 VCC_3V3_S3
GMAC0_RXDV_CRS
RXCTL MDI1- 5
MDI[1]- U54 RXCTL/PHYAD2
26 RXCTL R90633 4.7K

m sB
RXD0 MDI2+ 6 25 RXD0
GMAC0_RXD0 MDI[2]+ RXD0/RXDLY
RXD1 MDI2- 7 24 RXD1
GMAC0_RXD1

r
RXD2 0_AVDD10 8 MDI[2]- RXD1/TXDLY 23 RXD2
GMAC0_RXD2 AVDD10 8 RXD2/PLLOFF RGMII Power Source CFG_EXT CFG_LDO[1:0]
RXD3 MDI3+ 9 22 RXD3
GMAC0_RXD3 MDI[3]+ RXD3/PHYAD0

o
10 21 0_DVDD10 External 3.3V 1'b1 2'b00 CFG_EXT:

s
MDI3-
MDI[3]- DVDD10 21

f
1:External Power Source for IO pad.
YT8531C 1'b1 0:Integrated LDO for IO pad

a
2'b10
靠近RK3588S External 1.8V (default)

n l
2.2R CFG_LDO(1:0)

i :C
R228 1 2 R0201 TXCLK
GMAC0_TXCLK 10:1.8V
TXCTL Internal 1.8V 1'b0 2'b10 00:3.3V
GMAC0_TXEN

l
TXD0
GMAC0_TXD0
TXD1

a
GMAC0_TXD1

AVDD33 11
TXD2
GMAC0_TXD2

PHYRSTB
C C

TXCTL
TXD3

MDIO
TXD3
TXD2
TXD1
TXD0
GMAC0_TXD3 rj45_gmac_led-xy

MDC

TXC
e
CN3 HRJA-E22C02H79NL

r v
R0201 510R

11
12
13
14
15
16
17
18
19
20
QFN40_5X5_0_4_L0_8 0_LED1/CFG0 R408 11
12 YELLOW LED+

e
GND YELLOW LED-

t l e
MDI0+ 1
TD0+

n
MDI0-

GMAC0_MDIO
2

GMAC0_MDC
i y
TD0-

0_AVDD33
RHYRSTB

TXCLK
TXCTL
t
TXD3
TXD2
TXD1
TXD0
MDI1+ 3
TD1+

e l i
X8 25MHz MDI1- 4
C0201 100nF TD1-

r
4 1 XTAL_IN0

a
C90203 2 1 NC XTAL_OUT0 GND XIN C347 Differential pairs GND 1 2 5

i
TXCLK 3 2 5

a nt
GND C2617 X5R 16V 6
C0201 C346
XOUT GND
12pF
Z0= 100 ohm 6
TSX-2016 VCC_1V8_S3 MDI2+ 7

w
RXCLK C90198 2 1 NC 12pF C0201 7
GND 0_DVDD33

t
C0201 C0201 MDI2- 8
8

f e
接RTL8211F/FI

1
GND R13 MDI3+ 9
10K R246 TD3+

o d
GND Q6
10K 10

i
R0201 MDI3-
2SK3018 TD3-
3.3V

s
R0201

f
SOT_323

1
2
VCC_3V3_S3 13
RHYRSTB

n
GMAC0_RSTn_L 2 3 GREEN LED+
close to pin 21 0_LED2/CFG1 R357 510R 14

g
0_DVDD10 R0201 GREEN LED-

1
B B

n
1

C90196
C90194 R46 15
1 2 100NF SHIELD1

C
100nF 16

2
o
GND SHIELD2
0R.NC
2

C0201 C0201

l
close to pin 30 GND R0201
GND

n
L19 WPN252012H2R2MT 2.6A
REGOUT0 1 2 0_AVDD10 close to pin 3 & 8 & 38

u
2

L2520 C90201 C90200 C90197 C90195 C90202


4.7uF

X
100NF 100NF 100NF 100NF
1

C0402 C0201 C0201 C0201 C0201


GND GND GND GND GND

ESD59 JEU03SC
ESD60 JEU03SC MDI1- 1 10 MDI1-
VCC_3V3_S3 MDI3- 1 10 MDI3- MDI1+ 2 IN1 NC1 9 MDI1+
MDI3+ IN1 NC1 MDI3+ IN2 NC2
close to pin 29 2
IN2 NC2
9 3
GND1 GND2
8
0_DVDD33 3 8 MDI0- 4 7 MDI0-
MDI2- 4 GND1 GND2 7 MDI2- MDI0+ 5 IN3 NC3 6 MDI0+
1

MDI2+ IN3 NC3 MDI2+ IN4 NC4


C90204 C226
VCC_1V8_S3
close to pin 28 5
IN4 NC4
6
100nF 4.7uF SLP2510P8-ESD
2

C0201 C0402 2 1 SLP2510P8-ESD


1 2 DVDDRG0 C90199 100nF
GND
A
0_AVDD33
close to pin 11 & 40 R29 0R
C228
2 C0201
1
4.7uF
A
R0402
1

C0402
C229 C230
100nF 100nF
Xunlong Co.,Limited
2

C0201 C0201
Design Name
ORANGEPI 5
Size Page Name Rev
A3 1000M PHY ETH 1.2

Date: Tuesday, November 08, 2022 Sheet 31 of 36

5 4 3 2 1
5 4 3 2 1

J1

VCC3V3_PCIE30
M.2_PCIe_SATA/WIFIBT_ Interface
77
77

1 2
GND14 3V3#9
3 4
GND13 3V3#8
5 6
PETn3 NC1/LED1
7 8
PETp3 NC2/LED2
9 10 HOST_WAKE_BT 1 R24 2
D GND12 DAS/LED1# HOST_WAKE_BT_H D
100R R0201
11 12
PERn3 3V3#7
13 14
PERp3 3V3#6
15 16

n
GND11 3V3#5
17 18
PETn2 3V3#4

i o
19 20
PETp2 NC3

t
21 22 WL_DIS_N 1 R11 2
GND10 NC4 WIFI_REG_ON_H
100R R0201

a
23 24 BT_DIS_N 1 R12 2
PERn2 NC5 BT_REG_ON_H
100R R0201

m sB
25 26
PERp2 NC6

r
27 28
GND9 NC7
VCC_1V8_S0

o
29 30 UART_RX 1 R4 2 VCC3V3_PCIE30

s
PETn1 NC8/UART TX UART9_RX_M2_BT
100R R0201

f
UART_TX R5

a
31 32 1 2
PETp1 NC9/UART RX UART9_TX_M2_BT
100R R0201

n l
UART_CTS

i :C
33 34 1 R6 2
GND8 NC10/UART RTS UART9_CTSN_M2_BT

1
100R R0201
R32

1
UART_RTS

l
35 36 1 R7 2
PERn1 NC11/UART CTS UART9_RTSN_M2_BT R33 Q2 10K
100R R0201
1.8K 2SK3018 5%

a
HOST_WAKE_WL 1 R25

l
37 38 2
PERp1 DEVSLP HOST_WAKE_WIFI_H 5% SOT_323 R0201

1
C 100R R0201 C

2
R0201

n e
39 40 PCIE_PERSTn

2
GND7 SMB_CLK 3 2
PCIE20x1_2_PERSTn_M0

r v
41 42
PCIE20_0_RXN PETn0 SMB_DATA

e e
43 44
PCIE20_0_RXP

t
PETP0 ALERT VCC_1V8_S0

l
VCC3V3_PCIE30
45 46
GND6 NC13

n
C0201 X5R 10V

i y
C10 1 2 220nF 47 48
PCIE20_0_TXN PERn0 NC14

1
i
C11 1 2 220nF 49 50 PCIE_PERSTn
PCIE20_0_TXP R34

e
PERP0 PERSTn

1
C0201 X5R 10V
R38 Q3 10K
PCIE_CLKREQn

r
51 52
1.8K 2SK3018 5%

a
GND5 CLKREQn
5% SOT_323 R0201

1
a nt
PCIE20_0_REFCLKN 53 54 PCIE_WAKEn

2
REFCLKN WAKEn R0201
PCIE_CLKREQn

2
3 2
PCIE20_0_REFCLKP 55 56 PCIE20x1_2_CLKREQn_M0

w
REFCLKP NC15

t
57 58
GND4 NC16

f e
VCC3V3_PCIE30 VCC_1V8_S0
PCIE M.2 NGFF

o i d
M-KEY SOCKET

s f

1
n
R39

1
67 VCC3V3_PCIE30 R41 Q4 10K
PIN69:

o
B NC17 1.8K 2SK3018 5% B

n
69 NC ----PCIe 68 5% SOT_323 R0201

1
COFIG_1 SUSCLK 32KOUT_WIFI

2
C
GND ---SATA R0201

o
PCIE_WAKEn

2
71 70 3 2

l
GND3 3V3#3 PCIE20x1_2_WAKEn_M0
73 72

n
GND2 3V3#2
75 74
GND1 3V3#1

u
76 H6
76

X
H5 VCC3V3_PCIE30 VCC3V3_PCIE30
HOLE_3R20 VCC3V3_PCIE30
HOLE_3R20
HOLE_500CIR270D
HOLE_500CIR270D

1
1
Socket 2(B key——ngff)和Socket 3(M key——nvme)
C12 C13 C14 C15
C17 C18
22uF 100nF 22uF 100nF

1
22uF 100nF

1
X5R X5R X5R X5R
X5R X5R
6.3V 10V 6.3V 10V
6.3V 10V

2
VCC_SYSIN C0603 C0201 C0603 C0201

2
C0603 C0201
VCC3V3_PCIE30
U3
Default 3.39V MAX1A
4 3 L1
VIN LX 2.2uH
C19 C20 2 IND_252012
10uF 100nF GND C21 R37
1

X5R X5R R35 1 2 H有效 1 5 22pF 232K


1

10K 5% EN FB/OUT
A
25V 25V H>1.5V C0G 1%
A
ETA3409/SY8089AAC
2

C0402 C0201 R0201 50V R0201 C22 C23


22uF 10uF
2

C24 SOT_23_5 C0201


1

100nF
2

FB=0.6V X5R X5R


1

X5R 6.3V 6.3V


PCIE_PWREN_H Xunlong Co.,Limited
2

10V R40 C0603 C0402


1

49.9K
2

C0201
1% Design Name
R0201 ORANGEPI Tablet
Size Page Name Rev
2

A3 M.2_PCIe_SATA 1.2

Date: Tuesday, November 08, 2022 Sheet 32 of 36

5 4 3 2 1
5 4 3 2 1

VCCA3V3_CODEC

CODEC ES8388 DVDD_CODEC


1 R7000 2
C7001 C7002 4.7R
C7000 4.7uF 100nF C7003 C7004

1
R0402
100nF C0402 X5R 100nF 4.7uF

1
X5R X5R 16V 5% X5R X5R
VCCA3V3_CODEC

2
16V U7000 10V C0201 16V 10V
ES8388 VCCA_1V8_S0 DVDD_CODEC

2
C0201 C0201 C0402
QFN28_4R00X4R00X0R90_T
C7005 17
I2C6_SCL_M3 100nF 2 AVDD 16

1
I2C6_SDA_M3 DVDD HPVDD
X5R 3 24 C7006 1 2 1uF X5R C0402 10V INP_PHONE_MIC C7008
PVDD LIN1 2 1uF X5R C0402 10V HP_GND 10uF
16V IO LEVEL 23 C7007 1

1
D I2S1_MCLK RIN1 D

2
C0201 4 C0603
I2S1_SCLK_TX DGND
I2S1_LRCK_TX 22 C7009 1 2 1uF X5R C0402 10V MIC2P X5R
LIN2 2 1uF

2
21 C7010 1 X5R C0402 10V MIC2N 10V
I2S1_SDI1 RIN2
I2S1_SDO3 I2S1_MCLK R7002 1 2 0R 5% R0402 1
I2S1_SCLK_TX R7003 1 2 0R 5% R0402 5 MCLK 20 C7011 1 2 10uF X5R C0603 10V
I2S1_SDO3 R7004 1 2 0R 5% R0402 6 SCLK VMID 19 C7012 1 2 10uF X5R C0603 10V VCCA_3V3_S0 VCCA3V3_CODEC

n
I2S1_LRCK_TX R7005 1 2 0R 5% R0402 7 DSDIN ADCVREF 10 C7013 1 2 10uF X5R C0603 10V
SARADC_VIN3_HP_HOOK LRCK VREF
I2S1_SDI1 R7006 1 2 0R 5% R0402 8
HP_DET_L ASDOUT

o
18 C7014
AGND

i
29 13 100nF

1
E-pad HPGND

t
X5R
I2C6_SCL_M3 R7007 1 2 0R R0402 5% 28 16V
I2C6_SDA_M3 2 0R CCLK

2
R7008 1 R0402 5% 27 15 C0201
2 1 I2C_ADDR_CE 26 CDATA LOUT2 14
R7009 CE ROUT2

m sB
10K 5%

9 NC_25
12 ROUT1
LOUT1
NC_9
R0201

25
11
f o s
LOUT1

a
ROUT1

l n
i :C l
a l
C

EARPHONE
VCCA3V3_CODEC
Analog MIC C

n e
C7015 1 2 4.7uF R7010 1 2 2.2K

r v
C0402 X5R 6.3V R0201 5%

e
VCCA3V3_CODEC

e
SARADC_VIN3_HP_HOOK 1 2 INP_PHONE_MIC

t l
C7016 R7012 R7011 100K 1 2

1
n
100nF 100K 5% R0201

i y
X5R 5% R7013 C7017

CTIA(L,R.G,M)

t
100R 4.7uF
2
16V R0201

1
i
C0201 R0201 6.3V R7015

e l
1K

2
5% X5R 1%
C7018 47uF R7016 10R

2
C0402 R0201

a
C0603 X5R 6.3V 5%R0201 J7103

a nt i
HP_GND

2
ROUT1 1 2 1 2 PJ-3536
PJ7_PJ3536 MIC2P 1 2
R7019 100K 2 C7020

w
C7019 47uF R7018 10R 1 2 HP_DET_L 5 2 100pF R7017 0R MIC1

1
VCCA_1V8_S0 5

t
C0603 X5R 6.3V 5%R0201 3 C0201 5% R0201 1
LOUT1 3 +

e
5% R0201 C0G

f
1 2 1 2 6 2
6 -

2
4 50V
7 4 MIC2N 1 2 Micphone

o d
1 7 MIC_4522D

i
1

s
R7020
1

1
f
R7021 R7022 0R 5% ED7004 ED7005
1

1
470R 470R C7021 R0201 R7024 ESD5451N ESD5451N

n
5% 5% ED7003 100nF ED7000 ED7001 ED7002 1K ESD0402-6 ESD0402-6

g
1

R0402 R0402 ESD5451N X5R ESD5451N ESD5451N ESD5451N 1%

o
2

B ESD0402-6 16V ESD0402-6 ESD0402-6 ESD0402-6 R0201 B

n
2
2

2
C0201 R7014
0R
2

o C
5%

l
R0402

n 1

X u

A A

Xunlong Co.,Limited
Design Name
ORANGEPI 5
Size Page Name Rev
A3 Audio Codec(ES8388) 1.2

Date: Tuesday, November 08, 2022 Sheet 33 of 36


5 4 3 2 1
5 4 3 2 1

EXT I/O
VCC_1V8_S3 VCC_3V3_S3
C90222
UU8
C0201 1 2 8 1 C0201 1 2 C90223
100nF X5R 16V VCCA VCCB 100nF X5R 16V
7 2
I2C5_SDA/UART1_RX/GPIO1_B7 A1 B1
6 3
D I2C5_SCL/UART1_TX/GPIO1_B6 A2 B2 D

SGM4553
sot-23-8
5 4
GND OE

n
VCC_1V8_S3 VCC_3V3_S3
C90220

o
UU7

i
C0201 1 2 8 1 C0201 1 2 C90221
100nF VCCA VCCB 100nF

t
X5R 16V X5R 16V
7 2
PWM15_IR/GPIO1_C6 A1 B1

a
PWM1/GPIO1_A3 6 3 PWM1/GPIO1_A3_J
A2 B2

SGM4553
sot-23-8
m sB
5 4
GND OE

r
VCC_5V0
VCC_3V3_S3

f o s
5% R0201 22R 2 1 R90660

a
CAN1_RX_M1/GPIO4_B2 1 2
I2C5_SDA/UART1_RX/GPIO1_B7_J 3.3V1 5.0V1

n l
3 4
5% R0201 22R 2 I2C5_SCL/UART1_TX/GPIO1_B6_J SDA 5.0V2

i :C
1 R90661 5 6
CAN1_TX_M1/GPIO4_B3 SCL GND3
PWM15_IR/GPIO1_C6_J 7 8 UART0_TX_M2/GPIO4_A3_J
IO-GCLK TXD0 UART0_RX_M2/GPIO4_A4_J

l
9 10
CAN1_RX_M1/GPIO4_B2_J 11 GND1 RXD0 12 CAN2_TX/GPIO0_D5_J
IO-0 IO-1

a
CAN1_TX_M1/GPIO4_B3_J

l
13 14
C CAN2_RX/GPIO0_D4_J 15 IO-2 GND4 16 I2C1_SDA/UART4_RX/GPIO1_D3_J C
IO-3 IO-4 I2C1_SCL/UART4_TX/GPIO1_D2_J

n e
17 18
VCC_1V8_S3 VCC_3V3_S3 SPI4_MOSI/UART3_TX/GPIO1_C1_J 19 3.3V2 IO-5 20

r
SPI-MOSI GND5

v
SPI4_MISO/UART3_RX/GPIO1_C0_J 21 22 GPIO2_D4_P
C90224 SPI-MISO IO-6
C0201 UU9 SPI4_CLK/GPIO1_C2_J 23 24 SPI4_CS1/GPIO1_C4_J

e
SPI-CLK SPI-CE0

e
1 2 8 1 C0201 1 2 C90225 25 26 PWM1/GPIO1_A3_J

t
VCCA VCCB GND2 SPI-CE1

l
100nF X5R 16V 100nF X5R 16V
7 2
SPI4_MOSI/UART3_TX/GPIO1_C1 A1 B1 CON4

i n y
DIP26-254
6 3
SPI4_MISO/UART3_RX/GPIO1_C0 A2 B2

t
SGM4553
sot-23-8

i
5 4

e
GND OE

C0201
C90218
VCC_1V8_S3

r
a nt i a l UU6
VCC_3V3_S3

w
1 2 8 1 C0201 1 2 C90219
VCCA VCCB

t
100nF X5R 16V 100nF X5R 16V

f e
7 2
SPI4_CLK/GPIO1_C2 A1 B1 R90664 2 1 NC R0402
POWER KEY
6 3 5%

o d
SPI4_CS1/GPIO1_C4 A2 B2
SGM4553
sot-23-8

s i
5 4 R90666 1 2 100RR0201 5%

f
GND OE UART0_RX_M2/GPIO4_A4
R90665 1 2 100RR0201 5%
UART0_TX_M2/GPIO4_A3

g o n
B B

1
1

1
C
ED9303 ED9304

o
VCC_1V8_S3 VCC_3V3_S3 ESD5341N ESD5341N ESD5341N

l
C90216 ESD0402-6 ESD0402-6 ESD0402-6
C0201 UU5 ED9302

n
1 2 8 1 C0201 1 2 C90217
100nF VCCA VCCB 100nF

2
2

2
X5R 16V X5R 16V

u
7 2 CAN2_RX/GPIO0_D4_J
CAN2_RX/GPIO0_D4 A1 B1
VCC_1V8_S3 VCC_3V3_S3
CAN2_TX/GPIO0_D5_J

X
6 3
CAN2_TX/GPIO0_D5 A2 B2
SGM4553
sot-23-8

5 4
GND OE

1
R42

1
10K Q5 R45
5% 2SK3018 10K
R0201 SOT_323 5%

1
2
R0201 H4 H3 H2 H1
GPIO2_D4_P

2
2 3
GPIO2_D4
VCC_1V8_S3 VCC_3V3_S3
C90226
C0201 UU10
1 2 8 1 C0201 1 2 C90227
100nF X5R 16V VCCA VCCB 100nF X5R 16V
7 2 I2C1_SDA/UART4_RX/GPIO1_D3_J
I2C1_SDA/UART4_RX/GPIO1_D3 A1 B1
A A
6 3 I2C1_SCL/UART4_TX/GPIO1_D2_J
I2C1_SCL/UART4_TX/GPIO1_D2 A2 B2
SGM4553
sot-23-8

5 4
GND OE

Xunlong Co.,Limited
Design Name
ORANGEPI 5
Size Page Name Rev
A3 EXT I/O 1.2

Date: Tuesday, November 08, 2022 Sheet 34 of 36


5 4 3 2 1
5 4 3 2 1

1
R18
2
MASKROM
MASKROM KEY
22R R0201

2
MASKROM KEY

2
1
MASKROM
D D2 D
T2Key
ESD5451N

1
ESD0402-6

1
2
i o n
SW2
t
R19

a
RECOVERY
2 1
POWER KEY
100R R0201

m B
R20
1 2 5%

r
RECOVERY KEY
POWER_Key 22R R0201

s
TS-026-3

1
RECOVERY KEY o s
CC1 3

f
TS-026-3

2
a
100nF

n l

2
i
C0201 RECOVERY

l l: C
D4

2
ESD5341N T2Key

a
ESD0402-6

1
C C

n e

1
t e r l e v
i n ity
UART Debug re
a nt i a l VCC_5V0 VCC_3V3_S3

LED
f t w e LED PWR
o fid
R22 R23

s
VCC1V8_PMU_DDR_S3 VCC_3V3_S3 VCC1V8_PMU_DDR_S3 VCC_3V3_S3

RUN
1K 1K

n
R0201 R0201

ng o
B

C UART
1

o
1

R14 LED-G LED-R

l
1V8 R15 R16
1

10K LED-G LED-R


10K Q7 R17 10K

n
5% LED0603 LED0603
5% 2SK3018 10K 5%
3V3

u
5% Q8 R0201 NC/SIP1X3
R0201 SOT_323 R0201
1

2SK3018 SIP1X3
2

X
R0201
DEBUG_UART_TX
2

UART2_TX_M0/JTAG_TCK_M2 2 3 SOT_323 3
1

3
UART2_RX_M0/JTAG_TMS_M2 2 3 DEBUG_UART_RX 2 Q1
2 2SK3018
1 1 SOT_323
1

1
1 PWM0_LED
ED1 ED2
ESD5341N ESD5341N

2
ESD0402-6 ESD0402-6
2

A A
Xunlong Co.,Limited
Design Name
ORANGEPI 5
Size Page Name Rev
A4 KEY 1.2

Date: Tuesday, November 08, 2022 Sheet 35 of 36


5 4 3 2 1

SPI FLASH
E E

FSPI_D0
FSPI_D1
FSPI_D2 VCC_1V8_S3 VCCIO_FLASH
FSPI_D3

n
FSPI_CLK

o
FSPI_CS0

U9

a t i
m sB
W25Q256JWPIQ VCCIO_FLASH

r
wson-6x5-mm
FSPI_CS0 1 8

o s
CS VCC

f
D D
FSPI_D1 FSPI_D3 C28

a
2 7 C27

l
DO(D1) HOLD(D3)

n
100nF 1uF

1
i :C
FSPI_D2 3 6 FSPI_CLK X5R X5R
WP(D2) CLK

l
16V 6.3V
FSPI_D0

2
C0402 C0402

a
4 5

l
VSS DI(D0)

EPAD
r n ve

9
t e l e
SPI Nor:1.8V

i n i t y
C

r
a nte i a l C

f t w e
so i d
VCCIO_FLASH VCCIO_FLASH

g n f
n o
Note:
1

1
o C
R43 R44

l
10K.nc 10K.nc When using SPI FLASH with only
5% 5%

n
R0402 R0402 1 bit, it needs to be stuffed.

u
2

2
B DNP DNP B
FSPI_D2 FSPI_D3

A
Xunlong Co.,Limited A
Design Name
ORANGEPI 5
Size Page Name Rev
A4 KEY 1.2

Date: Tuesday, November 08, 2022 Sheet 36 of 36


5 4 3 2 1

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