DESIGN AND CHARACTERIZATION OF SEQUENTIAL CIRCUITS AND SYSTEMS

LAB REPORT 5 & 6

MARCH 7, 2024
DEBASHISH KALITA
2101EE95
Aim:

1. To design and analyse the sequential circuits and systems using

Cadence VLSI EDA software.
2. Understand sequential circuits via designing D-latch and D-flip-flop,
utilizing advanced elements such as transmission gates and self-built
in library cells.
3. To Estimate the power and performance for both configurations and
their dependence on supply voltage and sizing of MOSFETs.

Tool Used: Cadence Software

Procedure:

1. Design D-Latch and D-Flipflop as per the circuit diagram.

2. For observations set Vdd=1.8V, square Vpulse clock signal and
D(data) I/P signal with desired period, pulse width and voltage
range of [0 to 1.8] V.
3. Perform and plot the transient analysis of Latch and Flipflop.
4. Estimate the output (Q: memory signal) propagation delay, rise
time and fall time for both the configurations.

Theory:
D-latch: D-latch, or data latch, is a fundamental building block
in digital circuitry is used
for storing and capturing data. The latch stores and outputs the
value of the data input (D) when the control clock input is
level triggered or active.
A Sequential logic circuit with two inputs: a data input (D)
and a control
input (usually labelled as "Enable" or "Clock").

D flip-flop:
Data flip-flop is a type of digital storage element used in
sequential logic circuits. It stores
the single bit of data and is sensitive to the rising or falling
edge of a clock signal. The key
characteristic of a D flip-flop is its ability to capture and hold
the value of the D (data)
input when the clock signal transitions.
D (Data Input): The input bit that is to be stored.
CLK (Clock Input): The clock signal, either rising or falling
edge-triggered, depending
on the specific D flip-flop design.

D flip-flop and D latch are fundamental building blocks in

digital VLSI (Very Large Scale Integration) design. They both
serve similar functions in storing binary data, but they have
different characteristics and use cases, making them suitable
for different applications within VLSI design.

D Flip-Flop:

A D flip-flop is a sequential logic device that stores one bit of

data. It has a data input (D), a clock input (CLK), and two
outputs - Q and Q'.
The D flip-flop captures the input (D) value and stores it at the
rising (or falling) edge of the clock signal.
D flip-flops are commonly used in applications where data
needs to be synchronized with a clock signal. They are crucial
in designing sequential circuits such as counters, registers, and
memory elements.

D Latch:

A D latch, also known as transparent latch, is another

sequential logic device that stores one bit of data.
Unlike a D flip-flop, a D latch is level-sensitive, meaning it
captures and stores the input (D) value whenever the enable
signal (often denoted as E or EN) is asserted.
D latches are commonly used in asynchronous designs where
the timing of the clock signal is not strictly enforced or when
there is a need for faster operation compared to flip-flops.
They are used in level-sensitive designs and as building
blocks for more complex asynchronous circuits.
Relation to VLSI Design:

Timing Considerations: In VLSI design, timing is critical.

Both D flip-flops and D latches play essential roles in
managing timing constraints. Flip-flops are typically used in
synchronous designs where timing synchronization is crucial,
while latches are used in asynchronous designs or in cases
where timing requirements are less stringent.

Power Consumption: D flip-flops generally consume more

power compared to D latches because flip-flops are edge-
triggered and have more complex internal circuitry. In low-
power VLSI design, designers often opt for latches where
possible to reduce power consumption.

Area Efficiency: D flip-flops are typically larger in size

compared to D latches due to their internal circuitry. In VLSI
design, where area efficiency is crucial, designers may choose
latches over flip-flops to conserve silicon real estate,
especially in high-density designs.

Clock Distribution: Flip-flops are often used at the inputs

of large combinational logic blocks to synchronize their
outputs to a common clock signal. This helps in maintaining
proper timing and avoiding issues such as clock skew.
Latches, on the other hand, might be preferred in local areas
where strict timing synchronization is not required.

In summary, both D flip-flops and D latches are integral

components of VLSI design, each offering distinct advantages
and trade-offs in terms of timing, power consumption, area
efficiency, and clock distribution. The choice between them
depends on the specific requirements of the design and the
constraints of the target application.

Circuit Diagram:
D-Latch
TRUTH TABLE OF D-LATCH:

D-latch Schematic Layout

 D-FlipFlop

D-FlipFlop Schematic Layout

D-FLIP FLOP TRUTH TABLE

Observation Tables:
D-Latch (Level Triggering)
Clock D Q Output Output Rise Output Output
Signal Data (o/p) Fall Time Propagation Propagation
Signal Latched Time (tR) delay time delay time
Signal (tF) from high to from low to
low high

1 0 0 - - - -
1 1 1 - 68Ps - 97Ps
0 1 1(hold) - - -
0 0 1(hold) - - - -
1 0 0 60Ps - 135Ps -
[Clock and Input d are given with Delay]
[Clock: Rise Time is 40Ps and Fall Time is 40Ps]
[Input D: Rise Time is 40Ps and Fall Time is 40Ps]

D-Flip Flop (Positive Edge Triggering)

Clock D Q Q! Output Output Output Output

Signal Data (o/p) Signal Fall Rise Propagation Propagation
Signal Latched Time Time delay time delay time
Signal (tF) (tR) from high to from low to
low high

1 0 0 1 - - - -
1 1 0 1 - - - -
0 1 0 1 - - - -
1 1 1 0 - 68.1Ps - 104.2Ps
1 0 1 0 - - - -
0 0 1 0 - - - -
1 0 0 1 57.8Ps - 121.6Ps -
[Clock: Rise Time is 80Ps and Fall Time is 80Ps]
[Input D: Rise Time is 160Ps and Fall Time is 160Ps]
Graphical Observations:
D-Latch Transient Analysis:
 D-FlipFlop Transient Analysis:

Question 2:

Design a circuit with one binary input X which produces a 3-

bit output pattern (A, B, C).
As external source feeds X one bit per clock cycle, when input
X= 0 the output pattern
remain unchanged otherwise, the output repeats the binary
sequency/pattern: 0,1,3,7,6
4, one at a time.
Truth Table:
[A,B,C are input signals and X is the control signal]
A(present) B(present) C(present) X A(next) B(next) C(next) Da Db Dc
0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 1 0 0 1
0 0 1 0 0 0 1 0 0 1
0 0 1 1 0 1 1 0 1 1
0 1 1 0 0 1 1 0 1 1
0 1 1 1 1 1 1 1 1 1
1 0 0 0 1 0 0 1 0 0
1 0 0 1 0 0 0 0 0 0
1 1 0 0 1 1 0 1 1 0
1 1 0 1 1 0 0 1 0 0
 1 1 1 0 1 1 1 1 1 1
1 1 1 1 1 1 0 1 1 0
[2:(010), 5:(101) are don’t care values]
(Da, Db ,Dc are calculated using present state of inputs)
 Da= AX!+B(A+X)
 Db=CX+BX!
 Dc =CX!+A!X

Circuit Diagram:
Transient Analysis:

Conclusion:
1. We have successfully verified the working of D-Latch and D-Flipflop, and learnt why
they are used for memory storage.
2. The disadvantage of D Flipflop as observed is its circuit size, which is about twice as
large as that of a D latch. And the propagation delay and power consumption in D Flip
flop is more as compared to D latch.
3. We observed that D-latch is a level triggering device while D Flip Flop is an Edge
triggering device.
4. Average Power Consumption in D-Flipflop is 262.9 uW.
5. Average Power Consumption in D-latch is 131.2 uW.