A Theoretical Framework for the Design of Low

Noise Analog PLLs

Chembiyan T

Circuit Design
Specifications
VCO, XO and buffer design (High Frequency analog)
Jitter/Phase noise/Spurs/Settling time Chargepump and LPF design (low frequency analog)
PFD and divider design (Custom digital)
Jrms (φrms) or Sφf0,tot(foff) or τ
Σ∆ M and other digital control (Synthesizable digital)

Sφf0,tot(f) VCO noise

Qcp Iup
Ref noise Vdd

Iup φe
Idn
fr
f ref UP f0
f0-fugb 0 f0+fugb fdiv Sφf0,tot(f)
div DN Fractional spur
Vref Z(s)
Idn VCO Reference spur

N+n[k] f0-fr
0.f Σ∆
f0 f0+fr
MOD
f0-ffr f0+ffr
System Design Top level simulations
Optimum Loop dynamics for low noise Functionality checks
PLL loop design from dynamics Bandwidth switching/DSM operation etc.,
Behavioral simulations for spurs/noise Linearity and Spurs

Fig. 1. Figure showing the design considerations in a PLL

As technology is accelerating at an unprecedented pace with an explosive growth in AI and related

technologies, we are at a point in time where we are pushing the boundaries of what we can achieve in
terms of performance of all the analog and RF systems and PLLs are no exception to this trend. Integrated
circuit PLLs have been existing for more than four decades now and our understanding of them have
evolved and many new architectures of PLLs have been invented to achieve ultra low jitter levels. In
spite of the large body of literature on the different types of PLLs and their design approaches, a single
unifying theory of PLL design and performance limits and trade-off is still lacking. Especially as we are
reaching the technological limits of what can be achieved in terms of jitter, there is a pressing need to
have a deeper understanding of the PLL design and the fundamental limits on what is achievable and
what do these fundamental limits depend on. If theory can answer these questions on limits of what can
be achieved and give some insights and guidelines in designing these systems to achieve those limits,
then may be it is worth looking into. This chapter is an honest attempt towards that goal.
The design of a PLL involves many design milestones involving several design variables as shown in
Fig.1. Broadly however, the design procedure can be consolidated into few major steps. PLL designs
generally start with a noise specification that is mentioned in terms of integrated phase noise in radians
or as rms jitter that includes both the random and deterministic noise. The design of the PLL focuses on
arriving at the suitable loop architecture and block level specifications (including the reference oscillator
and the VCO) for the PLL that can achieve the desired noise levels. It should be noted that there are
other important specifications of a PLL that are not dependent on noise. For example, settling time is one
such specifications that is independent of noise and should be preferably as low as possible. However the
loop dynamics that minimizes settling time need not be the one that minimizes noise. This problem is
normally resolved in PLLs by noting that settling time and noise are orthogonal specifications. One is a
time domain and a transient specification. While the other one is a frequency domain and a steady state
specification. So it is a common practice to use bandwidth switching (or gear shifting), where the PLL
bandwidth is set to a much higher value during the initial transient settling to achieve faster locking and
then switched to a bandwidth that minimizes noise, once steady state is reached or the PLL is locked.
So the main focus of most PLL designs is to arrive at the loop parameters of the PLL that minimize the

Sφ0(f)
Sφr(f)
Functionality checks
f J (φ ) f
Jrms (φrms) or Sφf0,tot(foff) Verify top level specs rms rms
Jitter/settling time/Noise

Derive optimum PLL loop dynamics L(s) VCO and XO design

(based on first cut VCO and XO design) (with LDOs and loop in place) k3//s3

|L(jω)|
k2//s2

PLL Loop Design (CP & LPF deisgn) Optimize for Spurs ωu/s ωp1 ωp2
L(s) { Icp, Z(s), Kv, N } (circuit and system level)
ωz2 ωz1 ωu ω

Fig. 2. Flowchart showing the design steps involved in an Analog PLL

overall PLL noise. Once the loop parameters and specifications of the critical blocks like the reference
oscillator and VCO are known, the circuit design of the individual blocks of the PLL loop are carried out
to meet the noise specifications. This is then followed by the verification stage. Simulations are carried
out at the top level by integrating these blocks to check if the specifications are met at the top level, before
signing it off for design closure. All the major steps involved in the PLL design can be summarized as
shown in the Flowchart in Fig.2.
From Fig.2, the first major step of the PLL design is to arrive at the optimum loop dynamics and
specifications for the VCO and reference clocks from the jitter specifications of the PLL. The fundamental
questions that a designer needs to understand before starting the PLL design at a system level are 1) For
a given reference and VCO noise level, what is the minimum achievable jitter and the desired PLL loop
dynamics or conversely 2) For a given jitter and a given PLL dynamics, what are the required reference
and VCO noise levels to achieve the jitter. This step is extremely important as it defines the specifications
of the critical blocks like the VCO and the reference oscillator circuits and the associated loop dynamics.
A detailed design procedure and jitter and power trade offs in integer-N PLL design is discussed in the
literature for Type-II PLLs in [1], [2]. This work extends the analysis to a more generalized PLL loop
dynamics of arbitrary type and order for both integer-N and Fractional-N PLLs. The analysis is rigorous
and at the same time very intuitive. The analysis also presents the dependence of jitter on the input and
output frequencies of the PLL in great detail, which helps the designer understand the impact of frequency
planning on desired loop dynamics and minimum achievable jitter. From the analysis, the power and noise
requirements of the VCO and reference clocks are derived in a systematic manner.
Deriving the specifications of the blocks in a PLL from jitter requirements is one thing, but knowing if
the design is the most optimal 1 is a very important aspect of PLL design. Put in simple words, how
does one know if the design is good enough. To that end, the second half of the chapter discusses the
figure-of-merit (FOM) of the PLL and derives closed-form expressions for theoretical minimum achievable
PLL FOM. Then the design methods and conditions required to achieve the minimum PLL FOM are also
1 The word ’optimal’ in analog and RF design generally refers to a design that is power optimized. An optimal design is one in which, the specifications
are met with the least amount of effort (power in this case).
discussed. A graphical visualization procedure of the PLL design is developed, where the specifications
and parameters of the PLL are viewed on ’design planes’. Finally a FOM centric design approach of
PLLs is proposed which takes all the noise sources including the loop noise of the PLL into account and
arrive at an optimal PLL design.
Section I discusses the noise sources and how they can be classified based on their dependence on the
PLL loop parameters. Section II talks about the generalized transfer function of PLLs of any type and
order and the basic design procedure for the noise optimized PLL loop design. Section III discusses the
refined models of quantifying noise of the VCO and reference clocks which then help in understanding the
optimum jitter and UGB equations in a more intuitive manner. Sections IV and V presents the mathematical
analysis and closed form expressions for the optimum UGB and jitter for integer-N and Fractional-N PLLs.
Sections VI and VII presented a detailed discussion of the dependence of the optimum UGB and jitter on
the reference and PLL output frequencies in both integer-N and Fractional-N PLLs. Section VIII discusses
the effect of frequency planning of the PLL on the optimum jitter and UGB. Section IX discusses the
systematic procedure of deriving the VCO and reference source specifications starting from the Jitter
requirements. Section X discusses the design planes that are very useful graphic tools in visualizing the
reference and VCO clocks power and quality for a desired jitter. Section XI presents a rigorous derivations
for the FOM and the Quality of the entire PLL in terms of the FOM and the quality of the reference and
VCO clocks. Expressions for the minimum achievable PLL FOM is also discussed in the same section.
Section XII discusses the power required in the VCO and reference clocks and the approaches to scale
the power to achieve a PLL jitter in the order of 10’s of femtoseconds. The optimum dynamics and the
minimum achievable jitter and PLL FOM in the presence of the noise of the PLL loop is discussed in
detail in Section XIII. Section XIV discusses the power scaling approaches to achieve low jitter levels in
the presence of the PLL loop noise. Section XV proposes the modified design planes and power scaling
laws for PLLs that employ external reference clocks. Section XVI proposes the design planes, guidelines
to achieve best FOM and power scaling laws for Fractional-N PLLs that do not employ quantization noise
cancellation. Finally Section XVII discusses the design equations and the minimum achievable FOM of
PLLs for some special cases (like Injection locked PLLs and Sub-sampling PLLs) where one of the two
clocks (typically the reference clock) is much less noisier compared to the other. Section XVIII presents
a summary of the salient results and design guidelines presented in the chapter. Section XIX discusses
the conclusions of the results discussed in the chapter.

I. E XTRINSIC AND INTRINSIC NOISE SOURCES IN A PLL

From the analysis carried out in the previous chapter as shown in Fig.3, the total noise of a Fractional-N
PLL at the PLL output is given by
Z ∞
"  2 #
2π
Ntot = 2 KL + SΣ−∆ ( f ) + Sicpn ( f ) (N. f )2 |Hl p ( f )|2 d f (1)
0 Icp
Z ∞
"  2 #
KH Kv
+2 2
+ SR ( f ) |Hhp ( f )|2 d f (2)
0 f f
In most PLL designs, the frequency planning, which involves deciding the choice of the reference and
VCO frequencies, is done independent of the loop design2 . Thus the divide value of the PLL (N. f ) is
fixed first and there isn’t much freedom in the choice of the divider value from a PLL noise optimization
standpoint at least in integer-N PLLs. Keeping this in mind, it can be seen from Eq.(1) that the noise
sources of the PLL can be broadly split into two types.
Extrinsic noise sources: The noise sources that are independent of the loop parameters like the charge
pump current, or the loop filter impedance values or the VCO gain sensitivity. These noise sources are
referred to as the Extrinsic noise sources. The VCO noise, the reference noise and the Σ − ∆ quantization
2 In wireless transceivers for example the frequency planning is done keeping phenomenon like power amplifier PA pulling [3] in mind
noise (in Fractional-N PLLs) as shown in Fig.3, are examples of extrinsic noise sources. It should be noted
that these noise sources and their contributions to the PLL output depend upon the overall loop dynamics
of the PLL but not on the individual loop parameters.
Z ∞ Z ∞
2 2 KH
Next = 2 [KL + SΣ−∆ ( f )] (N. f ) |Hl p ( f )| d f + 2 2
|Hhp ( f )|2 d f (3)
0 0 f
Intrinsic noise sources: The noise contributed by the loop components like the chargepump and the loop
filter resistors are classified as Intrinsic noise sources. The noise contributions from these sources are a
strong function of the values of the loop parameters like the chargepump current, loop filter impedance
values and the VCO gain.
Z ∞  2 Z ∞  2
2π 2 2 Kv
Nint = 2 Sicpn ( f )(N. f ) |Hl p ( f )| d f + 2 SR ( f ) |Hhp ( f )|2 d f (4)
0 Icp 0 f
By classifying the noise sources into these two categories, the design of the PLL can be broken down
into two main design steps.

SR(f) 2πKv
Sφr(f) Sicpn(f) Sφ0(f)
s
∆φr + Icp + + + + ∆φ0
2πKv
2π Z(s)
- s
∆φdiv +
1/N.f
SΣ∆(f) +
SQ(f)=1/12fr
2π 1
NTF(z)
N.f 1-z-1
Extrinsic noise sources Intrinsic noise sources

Sφr(f) Sφ0(f) 2πKv

Sicpn(f) SR(f)
∆φr + Icp + + ∆φ0 s
2πKv ∆φr +
2π Z(s)
s
Icp + + 2πKv + + ∆φ0
- Z(s)
∆φdiv - 2π s
+
1/N.f ∆φdiv
SΣ∆(f) + 1/N.f
2π 1 SQ(f)=1/12fr
NTF(z)
N.f 1-z-1

Fig. 3. Splitting the noise sources in the PLL as Internal and External noise sources

• The first step is to determine the optimized loop dynamics or the desired transfer function which
includes the location of the poles, zeroes and the phase margin of the PLL loop.
• The second step is deriving the individual loop parameters from the knowledge of the loop dynamics.
In this chapter, starting from the jitter specification, we develop an analytical design procedure that arrives
at the optimum PLL loop dynamics and its dependence on the extrinsic noise sources. From the analysis
we arrive at the noise requirements of the VCO and the reference signals to achieve the desired integrated
jitter at the PLL output.

II. O PTIMUM LOOP DYNAMICS OF THE PLL

The generalized loop gain L(s) of a PLL with m integrators in the forward path (m poles at dc) and l
additional higher frequency poles can be expressed as
 
!
m
ki  l 1 
L(s) = ∑ i ·  ∏ s  (5)
i=1 s j=1 (1 + )
ωp j
 φn,l φn,h k3/s3
φr + φ0

|L(jω)|
NL(s) k2/s2
-
φdiv k1/s
ωu ωp1 ωp2
1/N ωz2 ωz1
ω
(a) (b)

Fig. 4. a) Control loop representation of a PLL with noise sources shown and b) Illustrative plot of the loop gain magnitude for M = 3 and l = 2

The high frequency poles normally occur after the unity gain bandwidth 3 ωu ( fu ) of the PLL as shown in
Fig.4.(b). The m-integrators in the forward path contributed to m − 1 zeroes in the loop. Thus the transfer
function is also commonly expressed in terms of the zeroes and poles as follows
m−1 m−1
ωu ωz1 ωz2 · · · ωzm−1 ∏i=1 (1 + s/ωzi ) km ∏i=1 (1 + s/ωzi )
L(s) = m l
= m l (6)
s ∏i=1 (1 + s/ω pi ) s ∏i=1 (1 + s/ω pi )
where km = ωu ωz1 ωz2 · · · ωzm−1 is a constant of the loop filter that depends upon the zeroes and the UGB
of the loop filter.
Now to estimate the overall noise at the PLL output, the noise sources can be divided into two groups.
The sources that see a low-pass transfer function φn,l and the sources that see the high pass transfer
function φn,h as shown in Fig.4.(a). In a CPPLL, the low pass noise sources include the reference noise,
Σ − ∆ quantization noise, feedback divider noise and PFD and CP current noise. The VCO noise and the
loop filter noise (when referred at the VCO output) sees a high pass transfer function. The low pass noise
sources and the high pass noise sources are modeled as φn,l and φn,h as shown in Fig.4.(a). The transfer
function seen by the low pass noise sources is given by
Φ0 (s) L(s) Φ0 (s) 1
=N = NHl p (s) & = = Hhp (s) (7)
Φn,l (s) 1 + L(s) Φn,h (s) 1 + L(s)
Let Sφ,l p ( f ) and Sφ,hp ( f ) represent the total phase noise 4 due to the low pass and high pass noise sources
referred at the input and the output respectively, then the total phase noise at the PLL output is given by
2
Sφ0,tot ( f ) = Sφ,l p ( f )N 2 |Hl p ( f )| + Sφ,hp ( f )|Hhp ( f )|2 (8)
Let Nint denote the integrated rms phase noise power at the PLL output given by
Z ∞ Z ∞ Z ∞
2
Nint = 2 Sφ0,tot ( f ) d f = 2 2
Sφ,l p ( f )N |Hl p ( f )| d f + 2 Sφ,hp ( f )|Hhp ( f )|2 d f (9)
0 0 0
The integrated jitter at the PLL output Jrms and the output phase noise Nint are related as
rZ
T0 ∞ T0 √
Jrms = 2·Sφ0,tot ( f ) d f = Nint (10)
2π 0 2π
where T0 is the time period of the PLL output. The optimum loop gain L(s) of the PLL is obtained by
minimizing Eq.(10). The loop gain of the PLL L(s) depends on many variables (ki and ω pi ). To simplify
the design process and arrive at an optimum solution, all the parameters of the loop gain can be expressed
3 The poles, zeroes and the UGB are expressed as ω p , ωz and ωu in rad/sec units or as f p , fz and fu in Hz interchangeably throughout this work.
4 In all instances in this chapter, the phase noise represents the base band phase noise of the signal of interest.
 k3/s3

|L(jω)|
k2/s2

k1/s
ωu β1 ωu β2 ωu
ωu ωu ω
α2 α1

Fig. 5. Illustrative plot of the loop gain magnitude for M = 3 and l = 2 showing the poles and zeroes in terms of the UGB ωu .

in terms of the unity gain bandwidth ωu . As explained in the previous chapter, a Type-m PLL has m poles
at dc and to stabilize the loop gain, m − 1 zeroes are added by adding the integrator outputs in parallel.
For stable PLLs, the zeroes occur before the UGB and the high frequency poles occur after the UGB.
Thus the poles and zeroes can be expressed as
ωu
ωzi = & ω pi = βi ωu (11)
αi
where αi and βi are fixed real numbers greater than 1. Thus the loop gain can now be expressed in terms
of the poles and zeroes as
  l
km m−1 sαi 1
L(s) = m ∏ 1 + ·∏   (12)
s i=1 ωu j=1 1 + s
β j ωu

A. Choosing the values of αi and βi

Once the transfer function is expressed in terms of the UGB ωu ( fu ), the problem of finding the
optimum loop dynamics in a PLL design is reduced to finding a single variable fu that minimizes the
noise. But from Eq.(12), it can be seen that the loop gain has additional parameters αi and βi . How does
one choose the optimum values of those parameters such that the noise is minimized. This part of the
section deals with arriving at a systematic approach to find the best values of αi and βi .
A PLL characterized by the loop gain in Eq.(12) has m poles at dc, m − 1 zeroes before the UGB and l
poles after the UGB. Let the ith zero of the m − 1 zeroes be denoted as fzi and the ith pole be denoted by
f pi (the poles and zeroes are expressed in Hz units here). The phase response for the reduced loop gain
L(s) given in Eq.(12) can be easily shown to be
   
π m−1 −1 f l
−1 f
φ( f ) = −m + ∑ tan − ∑ tan (13)
2 i=1 fzi j=1 f pi
The first term in Eq.(13) is due to the m poles at dc, each pole at dc creates a phase shift of −π/2 and
thus the total phase shift due to the m poles at dc is −mπ/2. The zeroes decrease the overall phase shift
and bring it to a value lower than −π at the UGB. The high frequency poles that occur after the UGB
then decrease the phase after the UGB. The phase margin of the PLL loop is given by
   
π m−1 −1 fu l
−1 fu
φPM = π − m + ∑ tan − ∑ tan (14)
2 i=1 fzi j=1 f pi
The phase margin can also be expressed in terms of the variables αi and βi as
 
π m−1 −1 l
−1 1
φPM = π − m + ∑ tan (αi ) − ∑ tan (15)
2 i=1 i=1 βi
It should be noted that in a PLL design, the UGB determines the important characteristis of the PLL like
low pass and high pass filter bandwidths for different noise sources and also time domain specifications
like settling time. The zeroes and poles in the loop before and after the UGB, determine the loop’s
stability. The poles in addition to stability also provide filtering for reference spurs and quantization noise
in Fractional-N PLLs. Thus we choose the unknown variables αi and βi keeping loop stability (phase
margin) and the filtering properties in mind.
A higher phase margin for a given UGB ωu leads to a lower phase noise. To understand this intuitively,
one can consider the power integrated in a second order lowpass and bandpass pass transfer functions
with a finite filter Q. The integrated power at the filter outputs is directly proportional to the Q of the
filter (proof given in Appendix C). A poor or lower phase margin leads to a higher Q or peaking in
the transfer function Hl p ( f ) and Hhp ( f ) and thus an increased integrated phase noise. Fig.6 shows the
variation of the integrated jitter vs phase margin for a fixed UGB for a Type-II 4th order PLL.
The goal of the PLL loop design is to see if there is an optimum choice of the location of the poles

260
240
220
200
30 40 50 60 70 80 90

Fig. 6. Variation of the PLL optimum Jitter with the loop Phase margin

and zeros ( values of αi and βi ) that maximizes the phase margin and also minimizes the variations of
the phase margin across corners. Since αi and βi are positive real numbers, the maximum possible value
of the phase margin in Eq.(15) is π/2 and the trivial solutions that achieve this maximum is given by
π
φPM,max = =⇒ αi = ∞ & βi = ∞ (16)
2
This is the condition where all the zeroes are pushed to zero and the poles pushed to ∞. However in
practice, the desired phase margin is not always π/2 and the values of αi and βi are finite and decided
by the area and noise filtering requirements. So we look at the problem in a different manner, for a given
phase margin is there a choice of αi and βi that minimizes the variations of phase margin across process
corners.
To better understand this problem and gain an intuitive understanding, the phase response and phase
margin of the loop gain can be expressed in terms of UGB, poles and zeroes.
   
π m −1 f l
−1 f
φ( f ) = −m + ∑ tan − ∑ tan (17)
2 i=1 fzi i=1 f pi
   
π m −1 fu l
−1 fu
φPM = π − m + ∑ tan − ∑ tan (18)
2 i=1 fzi i=1 f pi
We will first do away with the simplest case of the loop gain, That is a Type-I 2nd order PLL as its design

(a) (b)
|L(f)| |L(f)|

fp1 > 10fu fu fp1 < 10fu

fu

φ(f)
-π/2 φ(f) -π/2
dφ(f) ≠ 0
dφ(f) =0 -3π/2 df -3π/2
df φPM f=fu φPM
-π -π
f=fu

fu fp1 f fu fp1 f

Fig. 7. Illustrative shape of the phase response of a Type-I 2nd order PLL a) when f p1 > 10 fu and b) f p1 < 10 fu

is very different from the PLLs of higher Type (≥ 2). A Type-I 2nd order PLL loop has no stabilizing
zeroes and has one pole at dc and a pole after the UGB. From a design viewpoint it is the simplest
transfer function. The loop gain, phase response and the phase margin of a Type-I PLL are given by
   
ωu 1 −π −1 f π −1 fu
L(s) = & φ( f ) = + tan & φPM = − tan (19)
s 1 + s/ω p1 2 f p1 2 f p1
The phase response of a Type-I PLL is flat all the way from dc till a decade away from the first pole and
it is a monotonically decreasing function after that reaching −π at infinite frequencies. Thus the system is
unconditionally stable as the phase never reaches −π for any finite frequency. In addition to that, the first
pole always occurs after the UGB and hence the phase margin is always greater than π/4. Placing the
pole f p1 a decade away from the UGB ensures that the phase response is flat (|dφ( f )/d f | = 0) near the
UGB as shown in Fig.7.(a) and thus the variations in phase margin across corners will also be minimized.
However it may not be always be possible from a spur rejection point of view since placing the pole as
close to the UGB maximizes the spur rejection. The former case however is still feasible in very low
bandwidth PLLs where the UGB is much smaller than the reference frequency. This allows the designer
to place the pole a decade away from the UGB and still provide good spur rejection. In fact multiple
poles can be added a decade after the UGB, without affecting the phase margin and hence PLL stability
for filtering the spurs.
PLLs of Type ≥ 2 on the hand have a concave phase response shape and thus the UGB can be chosen to
be at the point of maximum phase margin. The most commonly employed PLL in many applications is
the Type II 3rd order PLL. A Type-II 3rd order PLL (m = 2 and l = 1) has two poles at dc, one stabilizing
zero and one high frequency pole after the UGB with the illustrative shape of the phase response and
loop gain shown in Fig.8.(a). The phase response and the phase margin are given by
       
−1 f −1 f −1 fu −1 fu
φ( f ) = −π + tan − tan & φPM = tan − tan (20)
fz1 f p1 fz1 f p1
As we move along the frequency axis from dc, the phase starts at −π due to the two poles at dc and it

|L(f)| (a) |L(f)| (b)

fu = fz1fp1 fu ≠ fz1fp1

fu fp1 fp1
fz1 fz1 fu

φ(f) φ(f)
dφ(f) =0
df dφ(f)
φPM f=fu φPM ≠0
df
-π f=fu
-π

fz1 fu fp1 f fz1 fu fp1 f

Fig. 8. Illustrative shape of the phase response of a Type-II 3rd order PLL a) when UGB is at the maximum phase margin point and b) When UGB is away
from the maximum phase margin point

starts to increase as we reach the zero fz1 and then the phase reaches a peak before it starts to decrease
due to high frequency pole f p1 . Since phase margin is measured at the UGB, for given choice of the pole
and the zero, the phase margin is maximized if the UGB occurs at the peak of the phase response. Also,
the slope of the phase response is positive after the zero and then it becomes negative before the pole
and thus it becomes zero at the maximum point. If the UGB also occurs at the same frequency where
the phase response peaks or the point of zero slope |dφ( f )/d f | = 0, then not only the phase margin is
maximized but the variations in the phase margin due to process variations will also be minimized as
shown in Fig.8.(a). If the UGB occurs at any other frequency away from the peak or the point of zero
slope |dφ( f )/d f | = 0, then the phase variations at that point will not be minimum. This can happen if the
pole is pushed closer to the zero. The phase response in that case will peak before the UGB as shown in
Fig.8.(b). In conclusion, to achieve maximum phase margin and minimize phase variations across corners,
the UGB should be at the point of maximum phase. This can be easily achieved by ensuring that the
slope of the phase response given in Eq.(20) is zero at the UGB [4].
dφ( f ) p
= 0 =⇒ fu = fz f p1 (21)
d f f = fu
Thus the UGB should be chosen such that its value is the geometric mean of the zero fz1 and the pole
f p1 . By expressing Eq.(21) on a log frequency axis, one can readily show that log( fu ) is an arithmetic
mean or the average value of log( fz ) and log( f p1 )
p 1
fu = fz1 f p1 =⇒ log( fu ) = [log( fz1 ) + log( f p1 )] (22)
2
In the expressions for the loop gain, the poles and zeroes were expressed in terms of the UGB. By
substituting fz1 = fu /α1 and f p1 = β1 fu in Eq.(21), we get
r
fu
fu = β1 fu =⇒ α1 = β1 (23)
α1
On a log frequency axis, the zero and pole can be expressed in terms of the UGB as
fu
fz1 = & f p1 = α1 fu =⇒ log( fz1 ) = log( fu ) − log(α1 ) & log( f p1 ) = log( fu ) + log(α1 ) (24)
α1
Thus the UGB is equidistant from the pole and the zero on a log frequency axis. Eq.(21) should look
intuitive when one thinks of the phase response on log frequency scale. The phase response due to a zero
increases at the rate of 450 per decade and decreases at the rate of −450 per decade due to a pole. If the
UGB is placed such that it is equidistant from the zero and pole on a log scale, the slopes of the phase
responses cancel each other and the phase response remains flat at the UGB.
The phase margin of the PLL for the Type-II 3rd order PLL can now be expressed as
   
−1 −1 1 −1 −1 1
φPM = tan (α1 ) − tan = tan (α1 ) − tan (25)
β1 α1
Thus there is a unique solution (a single design equation for the loop gain) for a Type-II 3rd order PLL

φ(f) fu = fz1fp1 Increasing φPM

φPM

-π

0 fz1=fu/α1 fu fp1=fuα1 ∞
Fig. 9. Figure showing the increase in the Phase margin as the zero and pole are pushed apart (increasing α1 )

that relates the zero and the pole to the UGB, that maximize the phase margin and also minimizes phase
variations. From Eq.(25), one can see that for higher phase margin, the value of α1 should be increased or
the zero and pole should be pushed farther away from each other. Satisfying Eq.(21) ensures the UGB is
at the maximum phase point, and keeping the pole and zero farther apart (larger α1 ) increases the absolute
value of phase margin as shown in Fig.9.
The same procedure can be extended to higher Type (and order) PLLs, but the design equations are not
as simple as Eq.(21). For PLLs of higher type where the number of zeroes and the high frequency poles
are the same (m − 1 = l), we can use some intuitions to gain an understanding about the distribution of
the zeroes and the high frequency poles to maximize the phase margin. Consider a Type-m PLL of order
2m − 1 (m − 1 poles and m − 1 zeroes), the phase response of the PLL loop gain is given by
  m−1  
mπ m−1 −1 f −1 f
φ( f ) = − + ∑ tan − ∑ tan (26)
2 i=1 fzi j=1 f pi
Differentiating the phase response in the above equation and setting it to zero at the UGB, we arrive at
the condition
l l
dφ( f ) αi βi
= 0 =⇒ ∑ 2
= ∑ 2
(27)
d f f = fu i=1 1 + αi i=1 1 + βi
A trivial solution for this problem is αi = βi . Every zero has a corresponding pole that form a pair whose
geometric mean is the UGB of the PLL loop
p
αi = βi =⇒ fu = fzi f pi (28)
Satisfying the above expression, the slopes of the phase change due to the each zero fzi is canceled out
by the slope of the phase change due to the corresponding pole f pi . The condition of symmetric phase
response around the UGB is possible only when the number of zeroes in the loop gain equals the number
of high frequency poles m − 1 = l. For a On a log frequency scale, all the zeroes and the high frequency
poles are symmetrically placed around the UGB (log( fu ) on a log frequency scale). The UGB can be
expressed in both log and linear scale as follows
1
log( fu ) = [log( fz1 ) + log( fz2 ) + · · · log( fzm−1 ) + log( f p1 ) + log( f p2 ) + · · · log( f pm−1 )] (29)
2m − 2
fu = ( fz1 fz2 · · · fzm−1 f p1 f p2 · · · f pm−1 )1/(2m−2) =⇒ α1 α2 · · ·αm−1 = β1 β2 · · ·βm−1 =⇒ αi = βi (30)
The maximum phase margin of the PLL loop of Type m and order 2m − 1 is then given by
(m − 2)π m−1 −1
φPM = − + ∑ tan (αi ) − tan−1 (1/αi ) (31)
2 i=1
Unlike a Type-II PLL, the value of phase margin uniquely defines the positions of the zero and the pole (as
it depends only on a single variable). For PLLs of Type greater than 2, there are more than two unknowns.
For example in a Type-III 5th order PLL, the UGB and the poles and zeroes are related as follows
1
log( fu ) = [log( fz1 ) + log( fz2 ) + log( f p1 ) + log( f p2 )] =⇒ α1 = β1 & α2 = β2 (32)
4
Meeting this condition will ensure that the phase margin is maximized. An illustrative shape of the

log(fz2)+log(fz1)+log(fp1)+log(fp2)
|L(f)| log(fu) =
4

fu = fz1fp1 = fz2fp2
fu fp1 fp2
fz2 fz1

dφ(f) =0
df
φ(f) f=fu
φPM
-π

-3π/2 -3π/2

fz2 fz1 fu fp1 fp2 log(f)

Fig. 10. Illustrative magnitude and phase response of a Type-III 5th order PLL with a symmetric phase response
magnitude and phase response of the Type-III 5th order PLL is shown in Fig.10. The phase margin of the
Type-III 5th order PLL that is designed to maximize the phase margin is given by
 π 
φPM = − + tan−1 (α2 ) − tan−1 (1/α2 ) + tan−1 (α1 ) − tan−1 (1/α1 ) (33)
2
The phase response is symmetric around the UGB on a log frequency scale and the phase margin is
determined by two variables α1 and α2 , which determine the distribution of the two zeroes and two poles
around the UGB. If the high frequency pole f p2 and the low frequency zero fz2 are chosen to be far
away (more than a decade away) from the UGB (zero pushed away to dc and pole to higher frequencies
by choosing α2 >> 10), then they do not impact the phase margin of the PLL and the phase margin is
similar to that of a Type-II 3rd order PLL.
φPM ≈ tan−1 (α1 ) − tan−1 (1/α1 ) (∵ α2 >> 10) (34)
Thus a Type-III 5th order PLL design problem is reduced to a Type-II 3rd order PLL by choosing the
second zero and pole to be more than a decade away from the UGB. In most practical PLLs however,
the Type rarely exceeds 2. Even in Type-III PLLs the high frequency poles (other than the first pole) are
chosen to provide further filtering for reference spurs and thus choosing the poles to maximize phase
margin may not be most optimal from a spur rejection point of view. Furthermore with three poles at
dc, the zero fz2 is usually chosen much smaller than the zero fz1 and is normally a decade away from
the UGB 5 . Thus near the UGB, even in higher ’Type’ PLLs, all the low frequency zeroes cancel out the
poles at dc and the loop gain appears like that of a Type-II PLL as shown in Fig.11. The figure shows
the illustrative shape of the loop gain of the Type-III and Type-II PLL overlaid on top of each other. The
zero fz2 occurs much before fz1 and the loop gain of the Type-III PLL merges with that of the Type-II
PLL after fz2 . Thus both the responses look the same near the UGB which is what determines the phase
margin and thus the integrated jitter value. The loop gain of a higher Type PLL can thus be approximated
to a Type-II PLL with the same high frequency poles as follows
  l   l
km m−1 sαi 1 ωu 2 sα1 1
L(s) = m ∏ 1 + ·∏  ≈ 2
1+ ·∏   (35)
s i=1 ωu j=1 1 + s α1 s ωu j=1 1 + s
β j ωu β j ωu
The low frequency zeroes can be set in a decreasing order and the values of those zeroes will not impact
the phase margin values as all those zeroes will be more than decade away from the UGB. Eq.(35) shows
the loop gain of a reduced system and now the problem of the loop design reduces to finding the optimized
values of zero closest to the UGB and the high frequency poles. That is to find the values of α1 and
βi that maximize the phase margin. However even for a reduced system given by Eq.(35), finding the
optimum values of α1 and βi using a mathematical analysis is not as simple for PLL order greater than
3 (l + m ≥ 4). To better understand this, consider the phase response of a reduced loop gain in Eq.(35) for
a PLL of order l + m.    
l
−1 f −1 f
φ( f ) = −π + tan − ∑ tan (36)
fz1 i=1 f pi
In PLLs where the zeroes and poles are not the same, the phase response will have a maxima, but the
shape of the phase response will not be symmetric around the UGB on the log frequency axis. Since the
number of poles are greater than the zeroes, the phase response cannot be symmetric around the point of
maximum phase and the slope will be higher as one moves closer away from the UGB towards the first
pole. Assuming that the UGB of the PLL loop is chosen to be at the point of maximum phase (the point
5 Placing the zero f
z2 a decade before the UGB will ensure that there is no impact of the zero on the phase margin as the phase change due to the zero
fz2 would have flattened out (tan−1 ( fu / fz2 ) ≈ π/2) at the UGB. This ensures that the phase response looks the same near the UGB as that of a conventional
Type-II PLL ensuring the stability remains unaffected even as the Type of the PLL is changed.
 Type-III
3
k3/s

|L(jf)|
wu2/α1s2
Type-II
ωu/s
β1fu β2fu
fu fu fu f
fz2 <
10 α1

Fig. 11. Loop gain of a Type-III and Type-II PLL showing the merging of the loop gain after the zero fz2

where slope of the phase response is zero), we get

α1 β1 β2 βl
= 2
+ 2
+···+ (37)
1 + α1 2
1 + β1 1 + β2 1 + βl 2
The phase margin is given by  
l
−1 −1 1
φPM = tan (α1 ) − ∑ tan (38)
i=1 βi
For a given phase margin, it can be seen from Eq.(37) and Eq.(38) there are many unknowns (l + 1 = m
unknowns α1 , β1 , · · · βl ) and two equations. However most PLLs that are optimized for low noise demand
a phase margin greater than 600 and in such cases we can make some assumptions to simplify the problem
and arrive at an optimal solution (or distribution of poles and zeroes aournd the UGB). The condition in
Eq.(37) can also be expressed in a simpler way for cases where the values of α1 2 , β1 2 , · · · βl 2 are much
greater than 1 (using the condition tan−1 (x) ≈ x and a/(1 + a2 ) ≈ 1/a. The phase margin and the condition
for maximum phase reduces to
 
−1 1 1 1
φPM ≈ tan (α1 ) − + +···+ (39)
β1 β2 βl
1 1 1 1 1 1 1 1
≈ + +···+ =⇒ = + +···+ (40)
α1 β1 β2 βl α1 fu f p1 f p2 f pl
Substituting the above expression in Eq.(39), the phase margin can be reduced to
1
φPM ≈ tan−1 (α1 ) − (41)
α1
Now for a given phase margin there is only one positive solution for the above equation and the value of
α1 and thus the location of the zero fz1 is decided. The values βi are chosen such that the harmonic sum
of all the poles is equal to α1 fu . Since the poles f pi are in an increasing order, the high frequency poles
after the UGB which are more than a decade away from UGB will not contribute to the phase margin
and hence the stability of the loop. Keeping this in mind, we can ignore all the high frequency poles and
retain only those that are closer to the UGB. Assuming that only two poles are closer to the UGB (within
a decade of the UGB), the conditions in Eq.(39) and Eq.(40) reduces to
1 1 1 1
φPM ≈ tan−1 (α1 ) − & ≈ + (42)
α1 α1 β1 β2
Now we end up with two unknowns (α1 is known from Eq.(41)) and since β2 > β1 and the harmonic sum
of β1 & β2 is equal to α1 , these conditions further reduces the search space to a narrow range of values.
fr
β1 ∈ [α1 , 2α1 ] & β2 ∈ [2α1 , βm ] where βm = (43)
fu
A third condition can be introduced based on the desired spur rejection specification. Based on the spur
rejection the two values of β1 and β2 can be set. We discuss one such case of choosing the two values
β1 and β2 here. For a desired phase margin, the values of β1 should lie in the range [α1 , 2α1 ] and the
values of β2 should be between [2α1 , ∞]. The values of β2 is obtained such that the harmonic sum is
always equal to α1 . For example by choosing β1 = α1 , the value of β2 has to be ∞ since the harmonic
sum of two numbers is always smaller than the smallest of the two values. The harmonic sum is similar
to the equivalent resistance of two resistors connected in parallel. If the value of β1 = 2α1 , then we get
β2 = 2α1 . An interesting choice of values of β1 and β2 that satisfies Eq.(42) in the given range would be
n n
β1 = α1 & β2 = nα1 =⇒ f p1 = α1 fu & f p2 = nα1 fu (44)
n−1 n−1
where n is a positive integer (it can even be a real number) in the range 6 [2, βm /α1 ]. The closer the first
pole is to α1 fu , the farther away the second pole should be. To get the best spur rejection the product of
the two poles should be as small as possible and that occurs when
f p1 = f p2 = 2α1 fu
Choosing the two poles close to 2α1 fu results in the best spur rejection. However placing two poles at
the same location using a passive loop filter structure may not be a very easy task and on top of that,
having two repeated poles at the same location will result in the phase response rolling off at a higher
rate (double the rate as compared to a single pole) which might worsen the variations in phase margin
across corners. So another more pragmatic choice based on Eq.(44) is to choose the poles slightly apart,
for example f p1 = 1.5α1 fu & f p2 = 3α1 fu or f p1 = 1.33α1 fu & f p2 = 4α1 fu .
Based on the discussions above, we can summaries the design procedure to choose the right value of α1
and βi for any PLL order. The procedure is based on the idea that only the first pole and first zero are
closest to the UGB and hence has the maximum impact on the phase margin. The basic steps involved
in the design procedure is listed below
1) Find the desired phase margin from architecture level simulations. Add a margin to the target phase
margin φPM + ∆φ
2) Treat the PLL like a Type-II 3rd order PLL and choose the value of α1 by solving Eq.(25) with the
margin added. This step decides the location of the first zero fz1 = fu /α1 .
3) If the PLL is a Type-II 3rd order PLL, then the first pole is also decided uniquely f p1 = α1 fu .
6 Ideally one would expect the range of n to be [2, ∞]. The case n = ∞ corresponds to a Type-II 3rd order PLL as the second pole is pushed to infinity and
the first pole reaches α1 fu . A more practical maximum (nmax ) value of n would be to restrict its value such that the second pole occurs before the reference
frequency.
fr
f p2 < fr =⇒ nmax =
α1 f u
Thus the modified range can be expressed as    
fr βm
n ∈ [2, nmax ] = 2, = 2,
α1 f u α1
 4) If the PLL order is higher than 3, then first place the zero based on step 2 and then choose the two
poles such that their harmonic sum equals α1 fu . Choosing the poles closer ensures that the spur
rejection is maximized. Based on the spur rejection requirement, for stringent rejection requirement
choose them to be closer β1 = 1.33α1 & β2 = 4α1 and for less stringent rejection requirements, the
poles can be placed farther apart for example β1 = 1.142α1 & β2 = 8α1 . Placing the poles farther
apart helps in minimizing the phase margin variations across PVT corners
5) Similarly add additional high frequency poles as necessary which are much farther away from the
UGB and any small changes in the phase margin should be accounted for in the added margin ∆φ in
step 2. Every additional high frequency pole will be farther away from the UGB, their contribution
to the phase degradation near the UGB keeps diminishing. Poles that are more than a two or three
decades away from the UGB will not contribute to any degradation in phase margin. Such poles can
be added directly without worrying about the stability of the PLL.
6) Thus once the phase margin is set, the values of α1 and βi can be found using the steps 1 to 5.
Now in PLLs of Type greater than 2, the values of αi (i ≥ 2) or the zero locations can be chosen
such that the zeroes occur much before fz1 (the zero closest to the UGB) α2 >> α1 . These zeroes
should not impact the phase margin and thus have no effect on the integrated jitter.
The next problem to consider is how to decide the exact value of phase margin at a system level that
minimizes jitter. It can be seen from the Fig.6 that the improvement becomes marginal when the phase
margin is > 600 . A higher phase margin is achieved by pushing the zero to lower frequencies which
translates to a higher loop filter area for low noise analog PLLs or by pushing the high frequency poles
farther away from the UGB which translates to a poor rejection of reference spurs. So choosing a high
phase margin close to 900 is not going to be optimum from area or spur rejection view point as the returns
in terms of integrated jitter are not proportionate. It is a common practice to choose a phase margin of
600 to minimize peaking in the transfer function in closed loop amplifiers and PLLs. Thus we set the
phase margin to 600 in the foregoing analysis.

B. Basic noise optimization procedure

Once the phase margin is fixed, the parameters αi and βi are also fixed based on the procedure
described in the previous section. Once the loop parameters are set, the only unknown variable in the
loop gain and hence the integrated noise Nint or integrated Jitter Jint is the UGB ωu ( fu ).
  l r Z
km m−1 sαi 1 T0 ∞
L(s) = m ∏ 1 + ·∏   & Jint ( fu ) = 2 Sφ0 ( f ) d f (45)
s i=1 ωu j=1 1 + s 2π 0
β j ωu
With the knowledge of the optimum UGB ωopt ( fopt ) (which corresponds to the UGB where the jitter is
minimum) and the desired phase margin the loop dynamics of the PLL can be derived systematically.
Thus the first step is to find the optimum UGB that minimizes integrated jitter. To find the minimum
value of the jitter, we find the minimum value of the integrated output phase noise (or the rms phase noise
power) as the UGB is varied. The total integrated phase noise at the PLL output is given by
Z ∞
Nint ( fu ) = 2 Sφ0,tot ( f ) d f (46)
0
The optimum UGB and the optimum jitter can then be computed by finding the minima of the integrated
noise
dNint ( fu )
= 0 =⇒ fu = fopt (47)
d fu
T0 p
Nopt = Nint ( fopt ) & Jopt = Nopt (48)
2π
One can intuitively guess that at very low bandwidths, the noise of the PLL is dominated by the VCO
noise 7 as the reference noise is filtered out significantly and at very high bandwidths the noise is dominated
by the reference noise as the VCO noise gets filtered out significantly by the large cut-off frequency of the
high pass transfer function. Thus an optimized design is where the overall noise of the PLL is minimized.
The PLL designer has to solve Eq.46 numerically by sweeping the UGB and find the optimum UGB that
minimizes the integrated jitter at the PLL output. An illustrative plot of the jitter variation with the UGB
is shown in Fig.12. The jitter vs optimum UGB plot is a convex function with a minima at the optimum
UGB.

Jrms ≈ Jref
Jrms ≈ Jvco
Jrms(fu)

Jopt
fopt fu
Fig. 12. Illustrative plot of the variation of the optimum Jitter of an integer-N PLL with the UGB of the PLL.

C. Constant phase margin scaling (or Frequency scaling)

As explained previously, the optimum UGB is found by sweeping the UGB and finding the minimum
value of the jitter Jrms and the corresponding UGB fopt . One important consideration in the analysis is
how the loop parameters α1 and βi are varied as the UGB is swept to find the optimum jitter.
Since the phase margin is set to 600 , as the UGB is swept, it should be ensured that the phase margin
remains at the same value. As an increase or decrease of phase margin will lead to peaking or change
in the Q value of the transfer function and hence a change in the jitter value. So as the UGB is varied
the loop parameters (the integrator coefficients ki and the high frequency poles w pi ) of the PLL should
also change but by keeping the phase margin constant. This is achieved by maintaining the variables α1
and βi as constants (From Eq.(15), it can seen that the Phase margin is dependent only on the variables
α1 and βi .) as the UGB is varied. We refer to this approach as Constant phase margin scaling. Let the
UGB be increased by the factor x and the poles and zeroes are also increased by the same factor, then
the phase margin of the loop as the UGB is varied is given by
  l     l  
−1 x fu −1 x f u −1 fu −1 fu
φPMx = tan − ∑ tan = tan − ∑ tan = φPM (49)
x fz1 i=1 x f pi fz1 i=1 f pi
Intuitively the constant phase margin scaling can be seen as a frequency scaling of the transfer function.
As the UGB is swept, the poles and zeroes are also varied by the same proportion in which the UGB is
varied.
m−1 m−1
km xm ∏i=1 (1 + s/xωzi ) km ∏i=1 (1 + (s/x)/ωzi ) s
Lx (s) = m = = L (50)
s ∏li=1 (1 + s/xω pi ) (s/x)m ∏li=1 (1 + (s/x)/ω pi ) x
7 The VCO noise is sees a high pass transfer function with a very low cut-off frequency and thus most of the VCO noise comes unfiltered at the PLL output
Having discussed the procedure to find the optimum jitter, we now derive closed form expressions for the
optimum jitter and optimum UGB. By making some simple approximations on the closed loop transfer
functions and the reference and VCO noise models, closed form expressions can be derived for the
optimum UGB and jitter. The values estimated from the closed form expressions serves two purposes
1) It helps the designer gain an intuitive understanding of the dependence of jitter ad the optimum loop
dynamics on the VCO and reference noise levels and 2) it can also serve as an initial guess to the
numerical solver and reduce the computation overhead for PLLs of higher Type and order. The next few
sections of the chapter focuses on deriving closed form expressions for the rms jitter in case of integer-N
and Fractional-N PLLs and comparing them with the results obtained from numerical simulations.
III. P URITY OF CLOCK SIGNALS
Before we delve into the mathematical analysis of deriving the optimum loops dynamics of PLLs, we
take a small detour to look at a way of comparing the purity or quality of clocks of different frequencies.
This helps in better understanding the optimum jitter and loop dynamics that one derives from the
optimization procedure. As discussed in Chapter II, phase noise is a frequency dependent quantity but
integrated jitter and hence the jitter PSD is an absolute metric, which can be used for comparing clocks of
different frequencies. However an interesting metric would be to define a simpler parameter that provides
an indication of ’how good a clock is’. To do that, we quickly revisit the models for the reference and
VCO phase noise.
We assume models for the reference and VCO noise sources that are mathematically tractable and close

a) Sφr(f) b) Sφ0(f)

KL KH/f2

0 0
Fig. 13. Equivalent baseband phase noise models (two-sided) of a) Reference signal and b) Open loop VCO output

to what is seen in practical applications. The reference phase noise is assumed to be a white noise source,
while the VCO noise is assumed to be a Coloured noise with different frequency profiles. Let KL be the
equivalent two-sided base band (as explained in Chapter II) reference signal phase noise floor referred
at the input of the PLL and let KH / f 2 be the equivalent two sided base band phase noise of the VCO
measured at the PLL output as shown in Fig.13 (The frequency f here represents the frequency offset from
the carrier frequency.). Reference and VCO clocks of different frequencies but the same integrated jitter
are referred to frequencies of similar quality or purity. To eliminate the dependence of the absolute value
of reference frequency on the phase noise, we normalize the phase noise by 1/ fr 2 . To ensure that the
normalized phase noise has units of rad2 /Hz (or dBc/Hz on the decibel scale), we multiply it by (1 Hz)2 .
The new normalized phase noise is referred to as the Purity or Quality of the reference source Qre f given
by  
1 Hz 2 KL
Qre f = Sφr ( f ) = 2 (51)
fr fr
The quality is better understood when we consider the Jitter PSD of the reference clock. The jitter PSD
and the phase noise are related as SJr ( f ) = Sφr ( f )/(2π fr )2 . The Jitter PSD by definition normalizes the
phase noise by divinding it by the carrier frequency fr removing the clock frequency dependence
Sφr ( f ) KL Qre f
SJr ( f ) = 2
= 2
= (52)
(2π fr ) (2π fr ) 4π2
Thus two reference clocks of different reference frequencies fr1 and fr2 will have different phase noise
plots but the same Jitter PSD (and hence same integrated rms jitter) if the quality or purity of the two
clocks are the same.
 2
Qre f fr1
SJr1 ( f ) = = SJr2 ( f ) & Sφr1 ( f ) = Sφr2 ( f ) (53)
4π2 fr2
Similarly we define the purity or quality of the VCO clocks so that two different VCOs can be compared
without worrying about their oscillation frequency or the power consumption. To eliminate the frequency
dependence, we normalize the VCO phase noise by the VCO frequency. However, unlike the model of
phase noise of the reference source, the VCO phase noise is dependent on the frequency offset from the
carrier as well. The VCO phase noise normally has a 1/ f 3 roll-off when flicker noise is the dominating
source of noise and a 1/ f 2 roll-off where the thermal noise is the dominant source of noise. Thus to
eliminate the offset frequency dependence, we not only divide the phase noise by the VCO frequency but
also multiply it by the offset frequency 8 ( f / f0 )2 . The purity or the Quality of the VCO clock can be
defined as
f2 KH f 2 KH
Qvco = Sφ0 ( f ) · 2 = 2 · 2 = 2 (54)
f0 f f0 f0
It should be noted that this definition of purity ensures that the VCO purity has units of rad2 /Hz (or
dBc/Hz on the decibel scale).
Clocks of different frequencies will have different phase noise as PN is a frequency dependent metric
of clock purity. But if the quality or purity defined in Eq.(51) and Eq.(54) remains the same, then we
refer to such clocks as equally pure or signals of same ’quality’. Clocks of same quality will have same
integrated jitter and jitter PSD. A lower value of Qre f and Qvco indicates that the clocks are ’purer’ or of
better quality with low integrated jitter.
The phase noise of the reference and VCO signals can be expressed in terms of the ’purity’ of the reference
and VCO clocks as well. Starting from Eq.(51) and Eq.(54), the reference and VCO phase noise can be
rewritten in terms of purity as follows
KH f0 2
Sφr ( f ) = KL = Qre f · fr 2 & Sφ0 ( f ) = = Qvco 2 (55)
f2 f

A. Figure-of-merit (FOM) and Quality of clocks

Engineers are more used to terms like Figure-of-merit (FOM) which is not only a measure of the
quality or how good a system is but also the effort it takes to attain that quality. FOM normally contains
the information about the power dissipated (the effort) in the system as well. For an oscillator or clock
signal like the reference or the VCO, the FOM can be defined as [5]
 
Pclk
FOMclock = 10 log10 Qclk · = 10 log10 (Qclk ) + Pclk,dBm (56)
1 mW
The units of FOM is dBc/Hz which is the same as that of the purity of the clock signals. A smaller
FOM implies a better clock. Two clocks can be of the same purity but different FOMs if the power
spent to achieve that purity are very different. The clock with the lower FOM is superior as it consumes
less power to achieve the same levels of purity. In simple terms, quality and FOM can be interpreted as
follows. Quality is a measure of how pure/accurate the clock is and FOM is a measure of the effort 9 it
takes to achieve that purity. It should be noted that the clock quality Qclk should not be confused with the
quality factor of a resonator. The clock quality Qclk is more of a purity metric which tells us how good
8 It should be noted that this definition of VCO purity assumes that the VCO phase noise decreases as 1/ f 2 from the carrier frequency. In general the VCO
frequency has a 1/ f 3 roll off at low frequency offsets (which is usually in the order of few 100 kHz) and a flat phase noise shape at high frequencies. Thus
a more accurate definition of quality also mentions the offset frequency at which the quality is defined.
9 The effort here refers to the energy (or power) expended to achieve that level of purity.
a clock is (how spectrally pure a clock is) and it may have some dependency on the quality factor Q of
the resonator in resonator based oscillators like LC oscillators and crystal oscillators.
We now define the FOM for the VCO and the reference clocks in terms of clock quality and FOM,
following our definition of FOM in Eq.(56)
 
Pvco
FOMvco = 10 log10 Qvco = 10 log10 (Qvco ) + Pvco,dBm (57)
1 mW
 
Pre f
FOMre f = 10 log10 Qre f = 10 log10 (Qre f ) + Pre f ,dBm (58)
1 mW

IV. O PTIMUM JITTER AND UGB IN INTEGER -N PLL S

Sφr(f) Sφ0(f)
KL Vdd KH/f2

0
Iup Sφ0,tot(f)
0
fr ref UP f0 VCO noise
fdiv Ref noise
div DN
Z(s)
VCO
Idn
0 fu
N

Fig. 14. Integer-N PLL with different noise sources and their illustrative phase noise shapes (the reference noise (Sφr ( f )), the open loop VCO noise (Sφ0 ( f ))
and the total PLL phase noise (Sφ0,tot ( f ))).

We start with the noise optimization of the simplest case of integer-N PLLs. Understanding the noise
trade-offs in integer-N PLLs is crucial as they help provide engineers with a lower limit on the minimum
achievable jitter levels in many PLLs like Fractional-N PLLs and Fractional-N PLLs with quantization
noise cancellation.
The noise analysis of the integer-N PLL can be performed by splitting the noise sources into low pass
and high pass noise as discussed earlier. The integrator phase noise power at the PLL output is given by
Z ∞ Z ∞ Z ∞
2
Nint = 2 Sφ0,tot ( f ) d f = 2 2
Sφ,l p ( f )N |Hl p ( f )| d f + 2 Sφ,hp ( f )|Hhp ( f )|2 d f (59)
0 0 0
The low pass noise sources are grouped together as a noise floor Sφ,l p ( f ) and the high pass noise sources
referred to the PLL output are accounted for as a pink noise model with a second order roll-off Sφ,hp ( f ).
Assuming that the source of noise is only the extrinsic noise sources, the low pass noise sources KL
represents the reference noise floor measured at the reference frequency fr and Sφ,hp ( f ) = KH / f 2 is the
VCO noise measured at the PLL output frequency f0 as shown in Fig.14. The integrated phase noise
power at the PLL output can be reduced to10
Z ∞ Z ∞
KH
Nint = 2KL N 2 |Hl p ( f )|2 d f + 2 2 |Hhp ( f )|2 d f (60)
0 0 f
Fig.14 shows the illustrative shapes of the phase noise of the reference clock, the VCO clock and the
total PLL output phase noise. To derive an exact expression for the integrated noise power as a function
10 The factor 2 in the expression accounts for the lower side band of the phase noise. Since f represents the frequency offset from the carrier the integration
limits go from 0 → ∞.
of the UGB, we need to evaluate the two definite integrals. The low pass integral ILP and the high pass
integral IHP given by
Z ∞ Z ∞
2 Hhp ( f ) 2
ILP = |Hl p ( f )| d f & IHP = df (61)
0 0 f
The transfer functions Hl p ( f ) and Hhp ( f ) are functions of the loop gain of the PLL and an exact analysis
involves a great deal of arithmetic complexity. We can however make some simple approximations to the
loop gain and derive expressions for the integrals and get an intuitive understanding of the value of the
integrals and hence their dependence on the UGB. For a simple Type-I PLL with no high frequency poles
the loop gain is given by L(s) = ωu /s and the low pass and high pass filter transfer functions are first
order high pass and low pass filters. The filter transfer functions and the value of the integral for a Type-I
1st order PLL are given by
L(s) 1 1 s/ωu
Hl p (s) = = & Hhp (s) = = (62)
1 + L(s) 1 + s/ωu 1 + L(s) 1 + s/ωu
Z ∞ Z ∞ H (f) 2
2 π hp 1π
ILP = |Hl p ( f )| d f = fu & IHP = df = (63)
0 2 0 f fu 2
For any PLL order greater than 2 the closed form expressions of the integrals in Eq.(61) becomes compli-
cated. However a Type-II 3rd order PLL is the most popularly used PLL architecture and understanding
the Type-II 3rd order PLL is the gateway to understanding higher order PLLs. To resolve this problem of
arithmetic complexity with 3rd order PLL, we consider two ’reduced’ loop gains of a Type-II 3rd order
PLL and evaluate the integrals of these reduced transfer functions. A Type-II 3rd order PLL has two poles
at dc, a zero before the UGB and a pole after the UGB. To study the impact of the zero and the pole on
the final integral values, we consider two loop gains of order 2. In the first case, the loop gain L1 (s) is
that of a Type-II 2nd order PLL with two poles at dc and one zero (the high frequency pole is pushed to
infinity). In the second case, the loop gain L2 (s) is that of a Type-I 2nd order PLL with one pole at dc and
one high frequency pole. The zero is pushed to very low frequencies and for all practical purposes can be
assumed that it canceled out one of the poles at dc. The loop gains of the two cases can be expressed as
ωu ωz1 ωu 1
L1 (s) = 2
(1 + s/ωz1 ) & L2 (s) = (64)
s s (1 + s/ω p1 )
For the first case (Type-II 2nd order PLL), the high pass and the low pass transfer functions and the
corresponding low pass and high pass integral values are given by
L1 (s) 1 + s/ωz1 1 s2 /(ωu ωz1 )
Hl p (s) = = 2 & Hhp (s) = = 2 (65)
1 + L1 (s) (s /ωu ωz1 ) + s/ωz1 + 1 1 + L1 (s) (s /ωu ωz1 ) + s/ωz1 + 1
Z ∞   Z ∞
2 π fz1 Hhp ( f ) 2 1π
ILP = |Hl p ( f )| d f = fu 1 + & IHP = df = (66)
0 2 fu 0 f fu 2
The low pass transfer function has a peaking in the magnitude response near the UGB and the peaking
increases as the zero approaches the UGB. From a stability point of view the zero moving closer to the
UGB reduces the phase margin and thus the poles move closer to the jw axis on the s-plane, leading to
peaking in the transfer function. This leads to a higher integration value for the low pass integral compared
to the case of first order loop in Type-I PLL. The high pass transfer function however does not see the
peaking and thus it integrates to the same value as that of the conventional Type-I PLL. Thus the presence
of zero impacts the integration of the low pass noise sources.
For the second case (Type-I 2nd order PLL), the high pass and the low pass transfer functions and the
corresponding low pass and high pass integral values are given by
L2 (s) 1 1 (1 + s/ω p1 )s/ωu
Hl p (s) = = 2 & Hhp (s) = = 2 (67)
1 + L2 (s) (s /ωu ω p1 ) + s/ωu + 1 1 + L2 (s) (s /ωu ω p1 ) + s/ωu + 1
 Z ∞ Z ∞  
2 π Hhp ( f ) 2 1π fu
ILP = |Hl p ( f )| d f = fu & IHP = df = 1+ (68)
0 2 0 f fu 2 f p1
In this case the high pass transfer function has a zero at the ω = ω p1 and thus the high pass transfer
function sees a peaking and the low pass transfer function does not see the peaking in the frequency
response. This leads to the low pass integral being the same as that of the a first order PLL and the high
pass integral value is higher by the factor (1 + fu / f p1 ).
One observation to be made from the preceding analysis is that, the low pass integrals are proportional
to the UGB and the high pass integrals are inversely proportional to the UGB.
Z ∞ Z ∞
2 Hhp ( f ) 2 a2
ILP = |Hl p ( f )| d f = a1 fu & IHP = df = (69)
0 0 f fu
where a1 and a2 are constants of proportionality that depend on the high pass and low pass filter transfer
functions (or the Type and order of the PLL). The phase noise power at the PLL output in Eq.(60) can
be expressed as
a2
Nint ( fu ) = 2KL N 2 a1 fu + 2KH (70)
fu
The optimum UGB and jitter of the PLL can be derived by finding the minima of Eq.(70)
r
dNint ( fu ) a2 KH (a1 a2 KL KH )1/4
= 0 =⇒ fopt = & Jopt = √ T (71)
d fu a1 N 2 KL π N
The constants a1 and a2 determine appear both in the expressions of the optimum UGB and jitter of the
PLL. The goal of the PLL design is to minimize jitter and hence to minimize the product a1 a2 .

A. The Symmetric phase condition

In some specific cases the proportionality constants will be equal a1 = a2 when the low pass and
the high pass filters with the same cut-off frequency fu obey the following condition, where the high
pass and low pass filter transfer functions can be transformed into one another by applying frequency
transformation and scaling s → ωu 2 /s or f → fu 2 / f .
 2  2
fu fu
|Hhp ( f )| = Hl p ⇐⇒ |Hl p ( f )| = Hhp =⇒ a1 = a2 (72)
f f
The above equation can be easily proved and the value of the integrals can be expressed as 11
Z ∞ Z ∞
2 2 Hhp ( f ) 2 C0 2
ILP = |Hl p ( f )| d f = C0 fu & IHP = df = (73)
0 0 f fu
2
where C0 is a constant that depends on the order of the low pass and high pass filters a1 = a2 = Cp
0 . From
st
Eq.(63) it can be seen that a Type-I 1 order PLL obeys this property and the value of C0 is π/2. A
11 Since the low pass integral is proportional to the UGB, it can be expressed as follows
Z ∞
ILP = |Hl p ( f )|2 d f = C0 2 fu
0

Since the high pass filter is related to the low pass filter by the relation
 
fu 2
|Hhp ( f )| = Hl p
f
The high pass integral can be solved by expressing in terms of the low pass filter response and by making the substitution f1 = fu 2 / f , the integral reduces to
Z ∞ Z ∞ 2 Z ∞ Z ∞
Hhp ( f ) 2 Hl p ( fu 2 / f ) 2 df 1 2 C0 2
IHP = df = df = Hl p ( fu 2 / f ) = 2 Hl p ( f1 ) d f1 =
0 f 0 f 0 f2 fu 0 fu

Thus the constant of proportionality is the same for both the lowpass and highpass integrals.
more general expression for the C0 can be derived by multiplying the low pass and the high pass integrals
in Eq.(63)
Z ∞ Z ∞
!1/4
2
Hhp ( f )
C0 = (ILP ·IHP )1/4 = |Hl p ( f )|2 d f · df (74)
0 0 f
In fact any PLL with equal number of poles and zeroes that are symmetrically placed around the UGB
√
on a log scale ωu = ωzi ω pi =⇒ αi = βi will have the phase margin maximized and symmetric phase
response around the UGB on a log scale. Assuming the PLL has m − 1 poles and m − 1 zeroes, then PLL
is a Type-m PLL with an order of 2m − 1. The loop gain of such a PLL can be expressed as
    m−1  
ωu ωz1 · · ·ωzm−1 m−1 1 + s/ωzi ωu m 1 1 + αi s/ωu
L(s) =
sm ∏ 1 + s/ω pi = s αiα2· · ·αm−1 ∏ 1 + s/αiωu (75)
i=1 i=1
It can be readily shown that PLLs with loop gain of the form in Eq.(76) obey Eq.(72)
 2   m m−1  
ωu s 1 + s/αi ωu 1
L = αi α2 · · ·αm−1 ∏ = (76)
s ωu i=1 1 + αi s/ωu L(s)
 2
ωu L(ωu 2 /s) 1
=⇒ Hl p = 2
= = Hhp (s) (77)
s 1 + L(ωu /s) 1 + L(s)
For the lowpass and highpass filters to obey Eq.(72), the loop gain of the PLL should obey Eq.(76)
 2  2  2
fu fu ωu 1
|Hhp ( f )| = Hl p ⇐⇒ |Hl p ( f )| = Hhp =⇒ L = (78)
f f s L(s)
The most commonly used Type-II 3rd order PLL with a loop gain given by ωu ωz1 (1 + s/ωz1 )/(s2 (1 +
√
s/ω p1 )), that is designed to maximize the phase margin satisfying the condition ωu = ωz1 ω p1 will also
obey the same relation. Assuming that ωz1 = ωu /α1 and ω p1 = α1 ωu the corresponding lowpass and
highpass transfer functions of the PLL can be expressed as follows
1 + s/ωz1 1 + α1 s/ωu
Hl p (s) = = (79)
(s /ωu ωz1 ω p1 ) + (s2 /ωu ωz1 ) + (s/ωz1 ) + 1
3
(s/ωu ) + α1 (s/ωu )2 + α1 (s/ωu ) + 1
3

(1 + s/ω p1 )s2 /ωu ωz1 (1 + s/α1 ωu )α1 (s/ωu )2

Hhp (s) = 3 = (80)
(s /ωu ωz1 ω p1 ) + (s2 /ωu ωz1 ) + (s/ωz1 ) + 1 (s/ωu )3 + α1 (s/ωu )2 + α1 (s/ωu ) + 1
It can be easily verified by making the substitution s → ωu 2 /s in the lowpass transfer function, we arrive
at the highpass transfer 12
√ function and vice versa . In addition to that since the phase margin is maximized
by choosing fu = fu fz1 , the jitter which depends upon the product of the two integrals is minimized.
Stated otherwise, to minimize the jitter, the values of a1 and a2 should be equal a1 = a2 = C0 2 or the
PLL loop should be designed to maximize its phase margin.

The phase noise power and the rms jitter of the PLL with lowpass and highpass filters obeying the
condition in Eq.(72) in Eq.(60) can be expressed as
  s 
2KH 2 2 C0 2KH 2
Nint ( fu ) = + 2KL N fu ·C0 =⇒ Jrms ( fu ) = + 2KL N fu (81)
fu 2π f0 fu
12 Substituting s = ωu 2 /s in the lowpass transfer function, we get
 2
ωu 1 + ωu 2 /sωz1 (1 + s/ω p1 )s2 /ωu ωz1
Hl p = 3
= 3
= Hhp (s)
s 2 2 2
(ωu /s) + (ωu /s ωu ωz1 ) + (ωu /sωz1 ) + 1 (s/ωu ) + (s2 /ωu ωz1 ) + (s/ωz1 ) + 1
Similarly it can be easily shown that Hhp (ωu 2 /s) = Hl p (s).
The optimum UGB and jitter of the PLL that is designed to maximise the phase margin can be derived
by finding the minima of Eq.(81)
r
dNint ( fu ) KH
= 0 =⇒ fopt = (82)
d fu N 2 KL
The optimum jitter is obtained by substituting Eq.(82) in Eq.(81)
Z ∞ Z ∞
!1/4
2
(KL KH )1/4 C0 Hhp ( f )
Jopt = Jrms ( fopt ) = √ T & C0 = |Hl p ( f )|2 d f · df (83)
N π 0 0 f

The exact value of the constant C0 for the Type-II 3rd order PLL is not easily solved like the second
order systems. To arrive at closed form expressions that are intuitive, we use some simple models for the
low pass and high pass transfer functions as shown in Fig.15 that have the same low pass and high pass
integral constants and obey Eq.(72). We use four different filter models 1) Ideal brick-wall, 2) First order
filter model, 3) Second order filter with finite Q and 4) Mth order Butterworth filter. We then derive the
expressions for optimum UGB and jitter in each case and draw conclusions from these results.
Ideal brick-wall filter: Assuming that the low pass and high pass filters to be ideal brick-wall filters with

Hlp(f) Hhp(f)
1 1
a)

fu f fu f

1 jf/fu
1 (1+jf/fu) 1 (1+jf/fu)
b)

fu f fu f

Q 1 Q
(jf/fu)2
1 2
1-(f/fu) +jf/Qfu 1 1-(f/fu)2+jf/Qfu
c)

fu f fu f

1 |Hhp(f)|= (f/fu)2M
|Hlp(f)|=
1 1 1+(f/fu)2M
(1+(f/fu)2M)
d)

fu f fu f

Fig. 15. Low pass and high pass filter models a) Ideal brick wall filter, b) First order filter, c) Second order filter with a finite Q and d) Mth order Butterworth
filter.
cut-off frequencies at fu as shown in Fig.15.(a). In the pass band, the gain of both the filters is assumed
to be 1 (or 0 dB). The integrated noise power at the PLL output is given by
Z fu Z ∞
2 KH KH
Nint ( fu ) = 2KL N d f + 2 d f = 2KL N 2 fu + 2 (84)
0 fu f2 fu
To find the optimum UGB, we find the minima of Eq.(84)
r
dNint ( fu ) KH KH
= 2KL N 2 − 2 2 = 0 =⇒ fopt = (85)
d fu fu N 2 KL
Substituting Eq.(85) into Eq.(84), we get the optimum phase noise power and jitter to be
4KH p
2
T0 p (KL KH )1/4
Nopt = = 4 KL KH N =⇒ Jopt = Nopt = √ T (86)
fopt 2π π N
The ideal brick wall filter model integrates the least amount of noise as it completely eliminates the noise
outside the band of interest and so the results obtained using this model will be more optimistic.
First order filter: The low pass and high pass transfer functions are assumed to be 1st order filters with
frequency responses as shown in Fig.15.(b). The transfer functions of PLLs of Type-I or Type-II PLLs
with phase margin close to 900 can be approximated to first order responses 13 given by
1 ( f / fu )2
|Hl p ( f )|2 = & |Hhp ( f )|2 = (87)
1 + ( f / fu )2 1 + ( f / fu )2
Substituting the filter responses in Eq.(87) in the expression for the rms phase noise in Eq.(60), the
integrated phase noise power is given by
Z ∞ Z ∞
N2 2KH 1
2KL 2
df + 2 df
0 1 + ( f / fu ) fu 0 1 + ( f / fu )2
The above expression can be reduced to (Proof of the integration is given in Appendix ??)
π 2KH π
Nint ( fu ) = 2KL fu N 2 + (88)
2 fu 2
The optimum UGB can then be found by finding the minimum value of the above function
r
KH
fopt = (89)
N 2 KL
The optimum integrated phase noise power (Nopt ) and rms jitter (Jopt ) at the PLL output is given by
4KH π p
2
π T0 p (KL KH )1/4
Nopt = = 4 KL KH N =⇒ Jopt = Nopt = √ T (90)
fopt 2 2 2π 2πN
Second order filter with finite Q: A more accurate representation of the Type-II PLL is to model the
low pass and high pass filter as a second order filter with a finite Q. The illustrative shapes of low pass
and high pass transfer functions and their frequency responses showing a peaking in the transfer functions
are shown in Fig.15.(c) and they can be mathematically represented as
1 ( j f / fu )
Hl p ( f ) = & Hhp ( f ) = (91)
1 − ( f / fu )2 + j f /Q fu 1 − ( f / fu )2 + j f /Q fu
13 A Type-I PLL with the high frequency pole shifted to infinity or a Type-II PLL with the zero pushed to very low frequencies ( f < f /100) and the high
u
frequency pole pushed to very high frequencies ( f > 100 fu )
ωu ωu ωu ωz1 (1 + s/ωz1 ) ωu
lim ≈ & lim ≈
ω p1 →∞ s(1 + s/ω p1 ) s ωz1 →0,ω p1 →∞ s2 (1 + s/ω p1 ) s
Substituting the filter responses in Eq.(91) in the noise expression in Eq.(60), the integrated phase noise
power is given by
Z ∞ Z ∞
N2 2KH 1
2KL 2
df + 2 2
df
0 (1 − ( f / fu )2 ) + ( f /Q fu )2 (1 − ( f / fu )2 ) + ( f /Q fu )2
fu 0

The above expression can be reduced to (Proof of the integration is given in Appendix ??)
π 2KH π
Nint ( fu ) = 2KL fu N 2 Q + Q (92)
2 fu 2
The optimum UGB can then be found by finding the minima of the above function
r
KH
fopt = (93)
N 2 KL
The optimum integrated phase noise power and rms jitter at the PLL output is given by
4KH π p Qπ T0 p (KL KH )1/4 p
Nopt = Q = 4 KL KH N 2 =⇒ Jopt = Nopt = √ T Q (94)
fopt 2 2 2π 2πN
Mth order Butterworth filter: Finally we consider the case where the low pass and high pass transfer
functions are Mth order Butterworth filters with monotonic frequency responses as shown in Fig.15.(d).
The transfer functions can be represented as follows
1 ( f / fu )2M
|Hl p ( f )|2 = & |Hhp ( f )|2 = (95)
1 + ( f / fu )2M 1 + ( f / fu )2M
Substituting Eq.(95) in Eq.(60), the integrated phase noise is given by
Z ∞ Z ∞
N2 2KH ( f / fu )2M−2
2KL 2M
df + 2 df
0 1 + ( f / fu ) fu 0 1 + ( f / fu )2M
π/2M 2KH π/2M
Nint ( fu ) = 2KL fu N 2 + (96)
sin(π/2M) fu sin(π/2M)
The optimum UGB can then be found by finding the minima of the above function
r
KH
fopt = (97)
N 2 KL
Substituting Eq.(97) in Eq.(96), the optimum integrated phase noise power (Nopt ) and integrated jitter (Jopt )
at the PLL output can be obtained as
s
1/4
p π/2M (KL K H ) 1
Nopt = 4 KL KH N 2 =⇒ Jopt = √ T (98)
sin(π/2M) 2πN M sin(π/2M)

B. Inference from the analysis

One interesting observations to be made from the above analysis is that the optimum UGB is inde-
pendent of the filter model (or the value of C0 ) as it can be seen from equations Eq.(85), Eq.(89), Eq.(93)
and Eq.(97). r
KH
fopt = (99)
N 2 KL
This hold true even for Type-II 3rd order PLLs which are designed to maximize the phase margin as it
can be seen from simulated results in Fig.16. The optimum jitter can be expressed as
(KL KH )1/4
Jopt = √ T ·C0 (100)
π N
 p
where C0 is a constant dependent
p on the filter model. 1) C0 = 1 for brick-wall filter,
p 2) C0 = π/2 for a
first order filter, 3) C0 = Qπ/2 for second order filter with finite Q and 4) C0 = π/(2M sin(π/2M))
for an Mth order Butterworth filter model. Unlike the UGB, the integrated jitter or the phase noise power
however depend on the value of C0 (on the lowpass and highpass filter characteristics).
Fig.16 shows the simulated Jitter vs UGB plot overlaid with the analytical results from Eq.(81). A 20 MHz

600
Simulated
500 Brick Wall
First Order
400 Second Order
Butterworth

300

200 J opt 210.2 fs

J opt 145.2 fs

fopt 850 kHz

100
105 106 4 106

Fig. 16. Jitter vs UGB plot with different filter models overlaid on the simulated results

reference clock with a phase noise of -160 dBc/Hz and a 2.4 GHz VCO with a phase noise of -120 dBc/Hz
at 1 MHz offset is used for the simulations. Throughout the entire chapter unless stated otherwise, the
same noise model is assumed for the reference and the VCO clocks. The second order filter model was
assumed 14 to have a Q of 1.5 and the Butterworth filter model assumes a filter order of 2. It can be seen
from the figure that the optimum UGB of ≈ 850 kHZ is same for all the filter models and it matches with
the simulated results of a Type-II 3rd order PLL 0
p designed to achieve a phase margin of 60 . The optimum
2
UGB from analytical expressions is fopt = KH /N KL = 833.33 kHz, which matches very closely with
the simulated results 15 .
Unlike√the optimum UGB, the analytical value of the optimum jitter given by Jopt = (KL KH )1/4 T ·
C0 /(π N) depends on the value of C0 . The value of Cp 0 (derived towards the end of the section) for
a Type-II 3rd order PLL with a 600 phase margin is ≈ 2π/3. Using this value of C0 , the optimum
jitter value predicted by the analysis is Jopt ≈ 210 fs. From the simulated jitter vs UGB plot in Fig.16,
the optimum jitter value is 210.2 fs, which matches very closely with the analysis. Another interesting
14 The second order filter Q is chosen so that the jitter vs UGB curve matches the simulated results. The actual peaking in the PLL lowpass and highpass
transfer functions is lower than Q=1.5. But the PLL filter responses are flat for a larger frequency range around the cut-off frequency and thus integrates to
the same value as the second order filter which rolls off faster than the Type-II PLL response
15 It should be noted that the optimum UGB and jitter are found by sweeping the sweeping the UGB values in the interval ( f /1000, f /5) by taking
r r
logarithmically spaced points in each decade. This results in the jitter and UGB being computed only at some points in the interval and thus may not exactly
match the result in Eq.(99 to all decimals. By increasing the frequency points in the UGB sweep interval, one can arrive at results that will closely match
Eq.(99).
observation to make is that the optimum jitter values for the PLL closely matches the optimum jitter value
for the second order filter model. The results of the simulated PLL is that of a Type-II 3rd order PLL
and yet it matches the second order filter model. Even though both these filters are of different orders,
the integrated noise powers are very close to each other. That is, the value of C0 is not unique for every
filter response.
The brick-wall filter predicts the lowest optimum jitter value of 145.2 fs as it integrates the lowest noise
among all the filter models. The jitter curve for the Butterworth filter model is very close to the brick-wall
filter model as the frequency response of the two filters match very closely in the frequency domain 16 .
The first order filter model approximates the responses of a Type-I PLL with no poles and integrates to a
lower phase noise compared to a Type-II PLL as expected due to better phase margin. Type-I PLLs can
have close to 900 phase margin.
Another interesting observation to be made is the distribution of noise between the reference and VCO
clocks at the optimum point. At the optimum UGB point, the phase noise power of the VCO can be
shown to be
2KH p Nopt
Nvco = ·C0 2 = 2 KL KH N 2 ·C0 2 = (101)
fopt 2
Similarly the noise contribution from the reference source at the PLL output can be shown to
p Nopt
Nre f = 2KL fopt ·C0 2 = 2 KL KH N 2 ·C0 2 = (102)
2
Thus both the VCO and the reference noise contributions at the optimum point are equal
Nopt Jopt
Nre f = Nvco = & Jre f = Jvco = √ (103)
2 2
A final point to note In a PLL with a very low reference noise (KL → 0), the optimum UGB will tend to
infinity theoretically and a PLL with very low VCO noise (KH → 0), the theoretical optimum UGB tends
to zero. r r
KH KH
fopt = lim → ∞ & f opt = lim →0 (104)
KL →0 N 2 KL KH →0 N 2 KL
However the maximum UGB is usually limited by the reference frequency of the PLL and the minimum
UGB is limited by the loop filter area and loop noise in the PLL. A typical range of the loop bandwidth
that is common in literature and practice in chargepump PLLs is
fr fr
< fu < (105)
1000 10

C. Optimum loop dynamics in Integer-N PLLs with low noise reference source
A special case to consider when dealing with Integer-N PLLs is PLLs with very low reference noise.
In PLLs with ring oscillators or very low noise reference sources, the noise of the reference signal can
16 The integrated noise power at the PLL output for a brick-wall filter model is given by
 
2KH
NBW ( fu ) = 2KL fu N 2 +
fu
The integrated noise power at the PLL output for a butterworth filter model is given by
 
π/2M 2KH π/2M 2KH π/2M
Nbwth ( fu ) = 2KL fu N 2 + = 2KL fu N 2 +
sin(π/2M) fu sin(π/2M) fu sin(π/2M)
In the limiting case when M → ∞, we get
π/2M
lim =1
M→∞ sin(π/2M)
2KH
∴ Nbwth ( fu ) = 2KL fu N 2 + = NBW ( fu )
fu
Thus the noise using the butter worth filter model approximates the brick-wall filter in the limiting case when M → ∞.
be ignored when compared to the VCO noise. By setting KL = 0 in Eq.(81), the integrated noise power
at the PLL output is reduced to
2KH 2
Nint ( fu ) = C0 (106)
fu
From Eq.(106), it can be seen that the total noise power at the PLL output is inversely proportional to
the UGB. Thus the theoretical minimum value of the phase noise power occurs at fu = ∞. Since analog
PLLs have an upper limit on the maximum allowable bandwidth, there is a limit on the maximum value
of fu . Let fu,max represent the maximum achievable PLL bandwidth, then the optimum noise power and
minimum achievable jitter are given by
s
2KH 2 KH C0
Nopt = C0 & Jopt = · (107)
fu,max 2 fu,max π f0
In general, the maximum UGB is a fraction of the reference frequency. In most traditional chargepump
PLLs the UGB is at least ten times smaller than the reference frequency. In Injection locked PLLs, the
maximum UGB can be very close to the reference frequency. Let the maximum UGB be expressed as
fu,max = a0 fr , where a0 is usually lower than 0.1 for chargepump PLLs, then the optimum jitter can be
reduced further to r r r
KH fr −3/2 KH C0 1 Qvco C0
Jopt = · C0 = · √ = √ (108)
2a0 Nπ 2a0 π f0 fr 2a0 π fr
√
Thus the optimum jitter in case of PLLs with low reference noise scales inversely as 1/ fr with an
increasing reference frequency (keeping the PLL output frequency f0 constant). This should be intuitive
as the higher reference frequency translates to a higher bandwidth which then leads to an hyperbolic
decrease (1/ fu ) in the phase noise power contributed from the VCO.

D. Optimum loop dynamics in Integer-N PLLs with low noise VCOs

Generally the reference clocks are much less noisier than the on chip VCOs but in some specific
applications like Jitter cleaning PLLs, the reference source is much more noisier than the VCO clock and
thus requires extensive filtering 17 . Such cases can be treated as a problem where KH → 0 in comparison to
the reference source. Since there is only the reference noise and no VCO noise, the UGB that minimizes
noise is zero. fopt = 0. Analog PLLs have a limitation on the minimum bandwidth due to loop filter area
constraints (A lower bandwidth requires a lower Icp Z(s) product in CPPLLs and the preferred option is
to decrease the impedance which results in large loop filter area.) (and even in case of digital PLLs the
minimum bandwidth cannot be zero in practice as it leads to an infinite loop settling time). Let fu,min
denote the minimum PLL bandwidth, then the total noise power at the PLL output is given by
p C0
Nopt = 2KL N 2 fu,minC0 2 & Jopt = 0.5KL fu,min · (109)
π fr
The optimum jitter can also be expressed in terms of the reference clock quality as follows
p C0 p C0
Jopt = 0.5KL fu,min · = 0.5Qre f fu,min · (110)
π fr π

E. Comments on the integration constant C0

The constant C0 figures in the expressions of optimum jitter and integrated phase noise of the PLL.
So estimating its value very accurately is of interest as it helps in estimating the jitter of the PLL
accurately (closer to the actual value) and also as it will be clearer in the latter half of the chapter, it helps
in estimating the theoretical minimum value of the PLL FOM. In the analysis so far, the value of C0 is
derived based on some approximations to the filter models. In this section we look at the intuitive ways
17 The PLLs in such application serve as ’phase filters’ or ’jitter cleaners’ of the incoming clock.
 (a) α1=1 (b) α1= ∞

|L(f)|=(fu/f)2 fz1= fp1=fu |L(f)|=fu/f fz1= 0 , fp1= ∞

fu fu

φ(f)
φ(f) -π/2
φPM=0 φPM=π/2
-π -π

fu f fu f
|Hlp(f)| 1 1
Hlp(f) = |Hlp(f)| Hlp(f) =
1-(f/fu)2 (1+jf/fu)
1 1
C0 = ∞ C0 = √π/2

fu f fu f

Fig. 17. Illustrative shapes of the magnitude and phase response of the loop gain and the corresponding low pass filter frequency response |Hl p ( f )| for a)
the unstable loop when α1 = 1 and 2) the stable Type-I loop when α1 = ∞

of arriving at the range of values of C0 and also its exact values for Type-II 3rd order PLL and study its
dependence on the phase margin of the PLL.
C0 is defined as the constant of proportionality of the lowpass and highpass integrals while calculating
the jitter and UGB of the PLL. A general expression for C0 is given by the relation
Z ∞ Z ∞
!1/4
2
Hhp ( f )
C0 = |Hl p ( f )|2 d f · df (111)
0 0 f

For the lowpass and the highpass filters that obey the condition Hhp ( f ) = Hl p ( fu 2 / f ), the value of C0 can
also be found by solving one of the integrals using the relation
s s
Z Z ∞
1 ∞ Hhp 2
C0 = |Hl p |2 d f = fu df (112)
fu 0 0 f
For a Type-II 3rd order PLL that is designed to maximize the phase margin ωz1 = ωu /α1 and ω p1 = α1 ωu ,
the loop gain and filter transfer functions can be expressed as follows
ωu ωz1 1 + s/ωz1 ωu 2 1 + α1 s/ωu
L(s) = = (113)
s2 1 + s/ω p1 α1 s2 1 + s/α1 ωu
L(s) 1 + α1 s/ωu
Hl p (s) = = (114)
1 + L(s) (s/ωu ) + α1 (s/ωu )2 + α1 (s/ωu ) + 1
3

1 (1 + s/α1 ωu )α1 (s/ωu )2

=
Hhp (s) = (115)
1 + L(s) (s/ωu )3 + α1 (s/ωu )2 + α1 (s/ωu ) + 1
The value of C0 is independent of fu and can be found using Eq.(112)
Z ∞ Z ∞
2 1 2 1 1 + (α1 f / fu )2
C0 = |Hl p | d f = 2 2
df (116)
fu 0 fu
(1 − α1 ( f / fu )2 ) + ((α1 f / fu ) − ( f / fu )3 )
0

Eq.(116) cannot be solved analytically and it has to be solved numerically. But using some simple
intuitions, we can still arrive at the limiting values of the integral. The phase margin of the Type-II
PLL that is optimally designed depends only on the value α1 . As the value of α1 is varied from 1 to ∞,
the phase margin varies from 00 to 900 .
 
−1 −1 1
φPM = tan (α1 ) − tan & α1 ∈ (1, ∞) =⇒ φPM ∈ (00 , 900 ) (117)
α1
When α1 = 1, the pole and zero fall exactly on top of the UGB (ωu = ωz1 = ω p1 ) and they cancel each
other and the loop now reduces to a cascade of two integrators without a stabilizing zero as shown in
Fig.17.(a). The loop now becomes a classic oscillator and it will oscillate at the unity gain frequency as
the phase margin is zero. A lower phase margin implies larger peaking in the lowpass transfer function,
which in turn leads to a larger integration value. The maximum value of C0 can be found by integrating
the lowpass transfer function of the PLL when its loop phase margin is zero. This is when the filter acts
like a second order lowpass filter with infinite Q as shown in Fig.17.(a). The loop gain and the lowpass
and the highpass transfer functions and the maximum value of C0 are given by 18
ωu 2 1 (s/ωu )2
L(s) = =⇒ H lp (s) = & H hp (s) = (118)
s2 1 + (s/ωu )2 1 + (s/ωu )2
v
u Z 2
u1 ∞ 1
C0,max = t df =∞ (119)
f u 0 1 − ( f / f u )2
When α1 = ∞, the zero and pole are pushed away from the UGB on either sides to zero and infinite

C0 = ∞ (Type-II unstable PLL)

C0

C0 ≈ √2π/3 (Type-II stable PLL)

C0 = √π/2 (Type-I PLL)

φPM
φPM=0 0
φPM=60 0
φPM=90 0

Fig. 18. Illustrative shape of the variation of C0 with the phase margin φPM of the PLL loop.

frequencies respectively. The zero cancels one pole at dc and the PLL reduces to a Type-I PLL with
no poles as shown in Fig.17.(b). The minimum value of C0 can be found by integrating the lowpass
transfer function of the PLL, which is a first order lowpass filter with a cut-off frequency fu as shown in
Fig.17.(b). The loop gain and the lowpass and the highpass transfer functions and the maximum value of
C0 are given by
ωu 2 1 + α1 s/ωu ωu 1 (s/ωu )
L(s) = lim 2
= =⇒ Hl p (s) = & Hhp (s) = (120)
α1 →∞ α1 s 1 + s/α1 ωu s 1 + (s/ωu ) 1 + (s/ωu )
s Z r
1 ∞ 1 π
C0,min = d f = (121)
f u 0 1 + ( f / f u )2 2
18 The PLL lowpass transfer function can be seen as a second order filter with an infinite Q. Thus the integral value of the second order lowpass filter with
an infinite Q is infinite πQ/2 → ∞.
Thus the value of C0 is inversely related to the phase margin of a Type-II 3rd order PLL. It blows up to
infinity C0 → ∞ as the phase margin approaches zero φPM → 00 and reaches a minimum value of C0 is
p
π/2 (for a Type-I PLL) as the phase margin reaches 900 as shown in Fig.18. A more useful value of
C0 is to find it at the desired phase margin of 600 , which can be computed by evaluating the integral in
Eq.(116) numerically by substituting the value of α1 ≈ 4. The integral can be evaluated at any value of
UGB as the value of the integral is independent of the absolute value of UGB. For convenience, we can
evaluate the integral for fu = 1 Hz 19 .
Z ∞ Z ∞
2 1 1 + (α1 f / fu )2 1 + (α1 f )2
C0 = 2 2
df = 2 2
d f (122)
fu (1 − α1 ( f / fu )2 ) + ((α1 f / fu ) − ( f / fu )3 )
0 0 (1 − α1 f 2 ) + ((α1 f ) − f 3 )

To get the value of the C0 at any phase margin, one can compute the corresponding α1 by solving
φPM = tan−1 (α1 ) − tan−1 (1/α1 ) and then solve the above equation numerically. p For a phase margin of
600 , the above integral converges to a value very close to 2π/3 and so C0 ≈ 2π/3.

V. O PTIMUM UGB AND JITTER IN FRACTIONAL -N PLL S

Sφ0(f)
Sφr(f) Vdd KH/f2
KL
Iup Sφ0,tot(f)
0
0 fr ref UP f0 VCO noise
fdiv Ref noise
div DN
Z(s)
SΣ∆(f) Idn VCO
0 fu
N+n[k] Σ∆ noise
0.f Σ∆
0 MOD

Fig. 19. Fractional-N PLL with the different noise sources and their illustrative phase noise shapes (the reference noise (Sφr ( f )), the Σ − ∆ quantization
noise (SΣ∆ ( f )), the open loop VCO noise (Sφ0 ( f )) and the total PLL phase noise (Sφ0,tot ( f ))).

In Fractional-N PLLs, in addition to the reference noise, there is also the Σ − ∆ quantization noise from
the feedback divider which goes through a lowpass transfer function as shown in Fig.19. The optimum
loop dynamics and minimum achievable jitter can be obtained by minimizing the noise at the PLL output
as it was done for integer-N PLLs.
Z ∞ Z ∞ Z ∞
2 2 2 2 KH
Nint = 2KL (N. f ) |Hl p ( f )| d f + 2 SΣ−∆ ( f )(N. f ) |Hl p ( f )| d f 2 2 |Hhp ( f )|2 d f (123)
0 0 0 f
where SΣ−∆ ( f ) is the PSD of the quantization noise from the feedback divider referred to the PLL input.
The shape of the PSD of the quantization noise depends on the manner in which the Σ − ∆ modulator
is implemented. For a Σ − ∆ modulator clocked at the reference frequency fr with a quantization noise
transfer function NT F(z), the noise PSD of the Σ − ∆ modulator referred to the PLL input is given by
 
2π 2 1 NT F(z) 2
SΣ−∆ ( f ) = (124)
N. f 12 fr 1 − z−1
19 The lowpass integral can be reduced by making the substitution f = f / fu =⇒ d f = d f / fu .
Z ∞ Z ∞
1 + (α1 f / fu )2 df 1 + (α1 f )2
C0 2 = = df
2 2 3 2 2 2
0 (1 − α1 ( f / fu ) ) + ((α1 f / fu ) − ( f / fu ) ) fu 0 (1 − α1 f 2 ) + ((α1 f ) − f 3 )
Thus the value of the integral is independent of the absolute value of the UGB.
Substituting Eq.(124) into Eq.(123), the integrated noise power at the PLL output is given by
Z ∞ Z ∞ Z ∞
2 2 (2π)2 NT F(z) 2 2 KH
Nint = 2KL (N. f ) |Hl p ( f )| d f + 2 |Hl p ( f )| d f 2 |Hhp ( f )|2 d f (125)
0 0 12 fr 1 − z−1 0 f2
The NTF of the Σ − ∆ modulator depends upon the modulator architecture. For an Lth order MASH Σ − ∆
modulator the NTF[6] is simply a Lth order high pass filter with L zeroes at dc given by
L L
|NT F( f )| = |1 − z−1 | = |1 − e− j2π f / fr | = |2 sin(π f / fr )|L (126)
Since the NTF is a non-linear function of f , when Eq.(126) is substituted in Eq.(125) as it is, the integral
can only be solved numerically and it is not as possible to derive closed form expressions for optimum
UGB and jitter as it was done for the integer-N PLLs. However, by making some approximations on the
NT F of the modulator and for some special case of the low pass and high pass filter characteristics, the
analysis becomes mathematically tractable.
Using the fact that the UGB is generally much smaller than the reference frequency fu << fr , the NTF
in the region of integration can be approximated to
2π f L L
|NT F( f )| = |2 sin(π f / fr )| ≈ (127)
fr
Substituting Eq.(127) into Eq.(124), the Σ − ∆ noise at the input of the PLL from Eq.(124) can be
approximated to
   
2π 2 1 2L−2 2π 2 1 2π f 2L−2
SΣ−∆ ( f ) = |2 sin(π f / fr )| ≈ (128)
N. f 12 fr N. f 12 fr fr
Now with the NT F of the modulator given in Eq.(127), the low pass filter model should be chosen such
that the order of the filter should be at least greater than 2L − 2. Otherwise the noise integral in Eq.(125)
will diverge 20 to ∞. The second simplification we make for the analysis to be tractable is to assume the
low pass and high pass filter models to be brick wall filters with the cut-off frequency of fu . As brick
wall filters can be seen as filters of infinite order, it eliminates the problem of choosing the right filter
order for Eq.(125) to converge. Using these two approximations, Eq.(125) reduces to
Z fu Z fu Z ∞
(2π)2 NT F(z) 2 2KH
Nint ( fu ) = 2 KL d f + 2 df + df (129)
0 12 fr 1 − z−10 fu f
2

Substituting Eq.(127) into Eq.(129) and evaluating the integral we get

 
2 fr 2π 2L fu 2L−1 2KH
Nint ( fu ) = 2KL fu + + (130)
12 fr 2L − 1 fu
In the presence of KL in Eq.(130), the analysis becomes more complicated and the closed form expressions
for the optimum jitter and UGB are not simple to derive as We end up with an Lth order polynomial
which does not have a general solution and has to be solved numerically. Thus we make the third and
final simplification in the analysis to arrive at simple closed form expression for the optimum jitter and
UGB. We ignore the reference noise in the analysis (KL = 0). The analysis holds true for the cases where
the VCO noise is much higher ( ring oscillator based Fractional-N PLLs) than the reference noise or when
the reference source is an extremely low noise source. Now the two main sources of noise in the PLL
are the Σ − ∆ noise and the VCO noise. The total phase noise power at the output of the PLL (by setting
KL = 0 in Eq.(130)) is given by
 
2 fr 2π 2L fu 2L−1 2KH
Nint ( fu ) = + (131)
12 fr 2L − 1 fu
20 The noise increases exponentially as f 2L−2 and thus for the integral of noise to converge the noise should be passed through a low pass filter of order
greater than 2L − 2. In the actual NTF without any approximations, the noise is a sinc function and thus does not have the problem of diverging noise PSD.
 104

103

Jopt 461.1 fs

Jopt 258.3 fs
Simulation
fopt 237.6 kHz fopt 381.8 kHz Calculated
100
4 104 105 106

Fig. 20. Simulated vs analytical plot of Jitter vs UGB in Fractional-N PLLs.

The optimum UGB is derived by finding the minimum value of Eq.(131) and it can be easily shown to
be
 1
fr 12KH 2L
fopt = (132)
2π fr
Substituting Eq.(132) in Eq.(131), the optimum phase noise power and optimum jitter at the PLL output
is given by
2KH 2L
Nopt = Nint ( fopt ) = (133)
fopt 2L − 1
s
2KH 2L 1
Jopt = · (134)
fopt 2L − 1 2π f0
Fig.20 shows the optimum jitter vs the UGB plot in a Fractional-N PLL with a 3rd order MASH 1-1-1
modulator and a VCO noise similar to that of the integer-N PLL. It can be seen from the plot that after
the optimum point, as the UGB is increased the jitter increases exponentially with a much higher rate
compared to the case of integer-N PLLs. At high UGB values, the low pass noise source dominates the
overall noise as the VCO noise is fully suppressed by the high UGB of the PLL loop. In an integer-N
PLL, the reference noise is modeled as a white noise source with a flat PSD but incase of Fractional-N
PLLs, the Σ − ∆ noise increases exponentially as the bandwidth of integration is increased. The simulated
jitter and the calculated jitter are overlaid in the plot and it can be seen that there is a deviation from
the actual simulation results. The reasons for this error in analytical results will be explained in Section
V-C. It should be noted that the brick wall filter case gives a lower bound on the jitter value at the PLL
output. As it integrated the least amount of power among all the filter models.

A. Fractional-N PLLs with prescaler embedded in the feedback path

In the previous analysis, it was assumed that the VCO output drives the multimodulus divider directly
and thus the quantization step size at the divider output is T0 = 1/ f0 . In case of Fractional-N PLLs with a
prescaler between the VCO and the multimodulus divider as shown in Fig.21. The high frequency clock
driving the divider is reduced to f0 /P and thus the quantization step size is increased to PT0 , which results
in the increase of the quantization noise PSD by P2 as shown in the figure. The integrated noise at the
PLL output using a brick-wall filter approximation for the low pass and high pass filter transfer functions
 Sφ0(f)
Sφr(f) Vdd KH/f2
KL
Iup Sφ0,tot(f)
0
0 fr ref UP f0 VCO noise
fdiv Ref noise
div DN
P2SΣ∆(f) Z(s)
Idn VCO
f0d 0 fu
N+n[k] P
0.f/P Σ∆ Σ∆ noise
0 MOD

Fig. 21. Fractional-N PLL with a feedback prescaler with the different noise sources and the illustrative phase noise shapes of the reference noise (Sφr ( f )),
the increased Σ − ∆ quantization noise (P2 SΣ∆ ( f )), the open loop VCO noise (Sφ0 ( f )) and the total PLL phase noise (Sφ0,tot ( f )).

can be derived similar to Eq.(129) to be

Z fu Z ∞
2 (2π)
2
NT F(z) 2 2KH
Nint ( fu ) = 2 P df + df (135)
0 12 fr 1 − z−1 fu f2
The optimum UGB and jitter can again be derived by finding the minima of the integrated noise power
Eq.(135) in a similar manner
 1  1
fr 12KH 2L fr 12KH 2L 1
fopt = = (136)
2π P2 fr 2π fr P1/L
Eq.(135) shows that the optimum UGB decreases in the case with the prescaler by a factor of P1/L . This

P=1
P=4

104

103

Jopt = 576.7 fs, fopt = 153.8 kHz

Jopt = 461.1 fs, fopt = 237.6 kHz

105 106

Fig. 22. Jitter vs UGB plot of a Fractional-N PLL with and without a prescaler.

is intuitive because the quantization noise power increases 21 by P2 times and thus the optimum UGB
point has to move to a lower value to minimize the jitter contribution from the Σ − ∆ modulator. The
21 The phase step size at the multi-modulus divider output before adding the prescaler is T = 1/ f . After adding the prescaler the input to the multi-modulus
0 0
divider is a lower frequency signal with a time period PT0 . Thus the phase step at the output of the multi-modulus divider increases by P times and the
quantization noise power increases by P .2
optimum jitter is then given by s
2KH 2L 1
Jopt = · (137)
fopt 2L − 1 2π f0

Since fopt is decreased by a factor of P1/L , Jrms is increased by a factor of P1/2L .

fopt
1/L
=⇒ Jopt → Jopt ·P1/2L
fopt → (138)
P
This is a direct result of an increase in the Σ − ∆ quantization noise step size of the Σ − ∆ modulator after
adding the prescaler. Fig.22 shows the jitter vs UGB plot of the Fractional-N PLL with a prescaler of value
P = 4 and without a prescaler P = 1 overlaid on top of each other. The order of the Σ−∆ modulator is L = 3.
As predicted by the analysis, the optimum UGB decreases from 237.6 kHz to (237.6)/41/3 ≈ 150 kHz by a
factor P1/L after adding the prescaler. The optimum jitter increased from 461.6 fs to (461.1)·41/6 = 581 fs
by a factor P1/2L very close to values predicted by the analysis in Eq.(137).

B. Inferences from the analysis

In case of integer-N PLLs, the noise contribution at the optimum point was equally divided between
the reference and the VCO noise. It is therefore of interest to see the noise contribution of the Σ − ∆
modulator and the VCO to the total noise Nopt at the optimum point in case of Fractional-N PLLs. The
noise power due to the VCO at the optimum UGB point is given by
2KH 2L − 1
Nvco = = Nopt (139)
fopt 2L
Similarly the noise of the Σ − ∆ modulator at the PLL output is given by
 
2 fr 2π 2L fopt 2L−1 2KH 1 1
NΣ−∆ = = = Nopt (140)
12 fr 2L − 1 fopt 2L − 1 2L − 1
Unlike integer-N PLLs, the noise at the PLL output in case of Fractional-N PLLs is not equally split
between the high pass noise sources (VCO) and the low pass noise sources (Σ − ∆ modulator noise). The
noise contribution is dependent on the order of the modulator.
1 2L − 1
NΣ−∆ = Nopt & Nvco = Nopt (141)
2L 2L
r r
1 2L − 1
JΣ−∆ = Jopt & Jvco = Jopt (142)
2L 2L
For first order modulator, the noise is equally split between the VCO and the Σ − ∆ modulator.
1
NΣ−∆ = Nvco = Nopt for L = 1 (143)
2
This result should sound intuitive as the Σ − ∆ modulator noise when referred to the PLL input behaves
like a white noise as it sees a first order integration when it is referred to the PLL input 22 . As the order
of the modulator increases the total noise is mostly dominated by the VCO
1 2L − 1
NΣ−∆ = Nopt → 0 & Nvco = Nopt → Nopt (L >> 1) (144)
2L 2L
22 The Σ − ∆ modulator noise after one integration behaves like the white noise of a Nyquist modulator with a PSD ∆2 /12 fr .
C. Optimum Σ − ∆ modulator order
An important factor to consider in the design of Fractional-N PLLs is the order of the Σ − ∆ modulator
for minimizing noise. An increased modulator order leads to a higher order noise shaping which pushes
most of the noise out of the PLL bandwidth. From Eq.(132), we can see that the optimum UGB reaches
a limiting value as the order is increased indefinitely.
 
fr 12KH 1/2L fr
lim fopt = lim = (145)
L→∞ L→∞ 2π fr 2π
Similarly the limiting value of the optimum jitter is given by
s s
2KH 2L 1 4πKH 1
lim Jrms = lim · = (146)
L→∞ L→∞ fopt 2L − 1 2π f0 fr 2π f0
These limiting results however do not hold in actual PLL designs and this is due to the limitations of
the model of the filter assumed for the optimum UGB and jitter calculations. In the analysis so far in
Fractional-N PLLs, the filter was assumed to be a brick wall filter as it gave simple closed form expressions
for the optimum UGB and jitter. Thus even as the order of the filter is increased any noise outside the
PLL bandwidth is completely rejected by the brick wall filter and is not accounted for in the calculation
of the noise power integral of Eq.(131). In most practical PLLs, the order of the low pass filter is finite
and the Σ − ∆ noise is a nonlinear function (sinc function) of frequency. Both these approximations lead
to an increase in the calculation error in the integrated noise as the order of the PLL is increased.
To better understand the error in the calculations, we look at the PSD of the Σ − ∆ modulator and how
the noise power is distributed and filtered by the PLL loop in different frequency bands. For a MASH
Σ − ∆ modulator of order L, the Σ − ∆ noise referred at the PLL input is given by
 
2π 2 1
SΣ−∆ ( f ) = |2 sin(π f / fr )|2L−2 (147)
N. f 12 fr
As the order of the modulator is increased, the PSD of noise is lower for higher order modulators at
lower frequencies and higher for higher frequencies. This implies that at some frequency the higher
order modulator noise will be equal to the modulator noise of lower noise. One can precisely calculate
the frequency at which the crossover takes place. As shown in Fig.23 all the noise PSD for different
modulator orders coincide at a single frequency and it can be easily shown to be
  2L−2
2L−2 πf fr
2 sin = 1 =⇒ fint = (148)
fr 6
As the order of the modulator is increased, the noise PSD in this frequency range [0, fr /6] is lower for
higher order modulators. It is only after this frequency the noise PSD peaks exponentially (∝ 22L−2 ) with
increasing modulator order. When this noise PSD is passed through the PLL transfer function, which is
a lowpass filter in this case, the high frequency noise outside the PLL bandwidth gets filtered. The noise
at the PLL output is given by
(2π)2
Sφ0,Σ−∆ ( f ) = |2 sin(π f / fr )|2L−2 |Hl p ( f )|2 (149)
12 fr
It is not possible to realize brick-wall filters in practical PLL applications. Adding many poles (even if
they are outside the PLL bandwidth) tend to decrease the phase margin and thus lead to instability. Most
practical PLLs have additional l poles (in addition to the poles at dc). These poles are placed after the
UGB and typically before the reference frequency. The high frequency poles do not play any role in
determining the PLL loop dynamics like UGB, settling time etc., They do however help in filtering noise
close to reference frequency. Thus they help in filtering the reference spurs and also Σ − ∆ noise after the
 -50
M Order=2
M Order=3
M Order=4

-100

(f) (dBc/Hz)
S

-150

fr /6 3.3MHz
-200
104 105 106 107
freq(Hz)

Fig. 23. Quantization noise from Σ − ∆ modulator for different modulator orders

UGB. Typically the number of poles do not exceed 2 or 3 as adding additional poles degrade stability23 .
As explained in the previous chapter, the PLL transfer function behaves like a first order filter near the
UGB excluding the poles. The roll-off order after the UGB in the PLL transfer function is always less
than l + 1.
So as the order of the modulator is increased, for most practical PLLs, the integrated power of the low pass
filtered σ − ∆ noise starts to increase as the order of the modulator is increased (keeping the PLL order
the same). Thus increasing the order of the modulator does not bring any returns and after a point, the
noise power starts to increase as the PLL order cannot be increased indefinitely due to stability reasons. In
addition to that a higher order modulator leads to an increase in noise of the quantization noise cancellation
circuitry and also cause other linearity related problems [7], [8].
An increased modulator order also leads to an increase in the quantization noise swing at the PFD input
leading to more problems of non-linearity (For every increase of the modulator order by 1, the range of
the phase error seen at the input of the PFD increases by a factor of two). An optimum choice of the
Σ − ∆ order should be chosen such the best noise shaping is achieved without compromising the linearity
and noise. Thus there is a sweet spot that minimizes noise or when an increase in the order does not reap
a proportional improvement in jitter. Generally the order of the Σ − ∆ modulator is restricted 24 to 2 or 3.
Fig.24 shows the plot of the optimum jitter vs UGB for different modulator orders for a Type-II PLL with
two additional poles after the UGB. It can be seen from the plot that after order 3, the returns in terms
of the optimum jitter are not significant. Thus an order of L = 3 is chosen for simulations in Fractional-N
PLLs throughout the thesis.
In summary, in spite of the errors incurred by the filter model, the optimum UGB and jitter results are not
very far off from the actual values for modulator orders lower than 3. In addition to that, as will become
clearer in the upcoming sections, the trends of the variation of jitter and the UGB with the reference and
VCO frequency can be very accurately predicted by the analysis.

D. Optimum loop dynamics in Fractional-N PLLs with noise cancellation

Fractional-N PLLs that employ quantization noise cancellation decrease the Σ − ∆ noise significantly.
Thus the design of a Fractional-N PLL reduces to that of an Integer-N PLL. The results in Section IV
23 A lower phase margin leads to a higher peaking in the transfer function which in turn leads to higher integrated noise at the PLL output.
24 First order modulators are always used in conjunction with quantization noise canellation for low noise PLLs.
 M Order=2
M Order=3
M Order=4
104

Jopt = 743.1 fs, fopt = 99.5 kHz

103

Jopt = 461.1 fs, fopt = 237.6 kHz Jopt = 422.7 fs, fopt = 289.5 kHz

105 106

Fig. 24. Optimum Jitter as a function of Σ − ∆ modulator order

will then apply for Fractional-N PLLs with quantization noise cancellation.
s
KH
fopt = (150)
(N. f )2 KL

(KL KH )1/4
Jopt = √ T ·C0 (151)
π N. f

VI. I MPACT OF REFERENCE FREQUENCY ON THE OPTIMUM UGB AND JITTER

One of the most important design aspects of the PLL is frequency planning, the process of arriving
at the right values of the reference and VCO frequencies. The question that is of interest to designers is
to see if there is a right choice of the reference and VCO frequencies that minimizes jitter and simplifies
the design. In this section we analyze the impact of the reference frequency on the optimum Jitter and
UGB in both Integer-N and Fractional-N PLLs.

A. Integer-N PLLs

Fig. 25. Optimum Jitter and UGB vs reference frequency in Integer-N PLLs

To analyze the impact of reference frequency on the optimum parameters of the integer-N PLL, the
reference frequency is varied keeping the VCO frequency as constant. As discussed earlier, the phase
noise is a function of the frequency of the clock. We refine the model of the reference phase noise taking
this into account as explained in Section III. From Eq.(51), the phase noise of the reference signal can
be expressed as
Sφr ( f ) = KL = Qre f fr 2 (152)
where Qre f is the quality of the reference signal and is a frequency independent quantity. From Eq.(99)
and Eq.(100) the optimum UGB and the optimum jitter can be rewritten as
s s
KH 1 KH
fopt = 2
= (153)
N 2 Qre f fr f0 Qre f
 1/4
Qre f KH ( fr )2

1/4
Qre f KH
Jopt = √ TC0 = √ C0 (154)
π N π f0
Eq.(153) and Eq.(154) shows that the optimum UGB and the optimum integrated jitter are independent
of the reference frequency as long as the quality Qre f of the reference signal is maintained the same even
as the frequency is varied. Fig.25 shows the simulated plots for Jrms as a function of UGB and reference
frequency. The reference frequency is varied keeping its ’purity’ (quality) constant and the VCO frequency
is unchanged (the divide value is changed to account for this) and the plot shows that the optimum UGB
and jitter remain the same and are the independent of the reference frequency, corroborating the analysis.
The reference source phase noise in practice however decreases with increasing reference frequency (explained

fr = 20 MHz
fr = 40 MHz
fr = 80 MHz
fr = 160 MHz

Jopt = 217.7 fs, fopt 850 kHz

102

Jopt = 76.9 fs, fopt 6.8 MHz

105 106 107

Fig. 26. Optimum Jitter and UGB vs reference frequency for practical reference clock (with improved Quality for higher reference frequencies) in Integer-N
PLLs

in Section XIII). That is the quality of the reference clock improves (Qre f decreases) as the reference
frequency is increased. The Quality of the reference clock decreases is related to the reference frequency
as Qre f ∝ 1/ fr 2 (proof shown in Section XIII). Using this result in Eq.(153) and Eq.(154), the optimum
UGB and the jitter are related to reference frequency as follows
1 1
Qre f ∝ 2 =⇒ fopt ∝ fr & Jopt ∝ √ (155)
fr fr
Fig.26 shows the Jitter vs UGB plot different values of the reference frequency as the quality of the
clock is varied as 1/ fr 2 . As expected the optimum UGB increases and the optimum jitter decreases with
increasing reference frequency. The optimum UGB increases from 850 kHz to 850·8 = 6.8 MHz as the
reference frequency is increased from√ 20 MHz to 160 MHz (an eight fold increased). The optimum jitter
decreases from 217.7 fs to 217.7/ 8 = 76.97 fs. Both the optimum UGB and jitter change in agreement
to the theoretical predictions in Eq.(155).
B. Integer-N PLLs with very low reference noise
The optimum jitter of integer-N PLLs with very low reference noise where the bandwidth is chosen
to be the highest permissible value is given by (Eq.(108))
r r
KH C0 1 Qvco C0
Jopt = · √ = √ (156)
2a0 π f0 fr 2a0 π fr
where a0 ≤ 0.1. If the quality of VCO is fixed, it doesn’t matter what the value of the VCO frequency
f0 is the jitter will decrease with increasing reference frequency as the maximum bandwidth of the PLL
can be increased proportional to the reference frequency.
r
Qvco C0 1
Jopt = √ =⇒ Jopt ∝ √ (157)
2a0 π fr fr
The optimum jitter is inversely proportional to the square-root of the reference frequency.

C. Fractional-N PLLs
In case of fractional-N PLLs, the reference frequency has a significant impact on the loop parameters.
An increase in the reference frequency results in a significant reduction of the quantization noise power
within a given integration bandwidth as the quantization noise PSD with in the PLL bandwidth decreases
exponentially with increasing reference frequency (as seen from Eq.(127)). Thus the optimum bandwidth
and the jitter will have a strong dependence on the reference frequency. Keeping the PLL output frequency
f0 constant and increasing the reference frequency alone, from Eq.(132), it can be seen that the optimum
UGB and the reference frequency are related as follows
 1
fr 12KH 2L
fopt = =⇒ fopt ∝ fr 1−1/2L (158)
2π fr
In a similar manner from Eq.(146), the relation between the optimum jitter and the reference frequency
can be shown to be
1 fr 1/4L
Jopt ∝ p ∝ √ (159)
fopt fr
The variation of the optimum UGB and the jitter with varying reference frequency can be seen in Fig.27.

104
fr = 20 MHz
fr = 40 MHz
fr = 80 MHz
fr = 160 MHz

103

Jopt 452.6 fs

Jopt 190.9 fs
fopt 241.1 kHz fopt 1.35 MHz
2
10
104 105 106 107

Fig. 27. Optimum Jitter and UGB vs reference frequency in Fractional-N PLLs

The reference frequency is varied from 20 MHz to 160 MHz. As the reference frequency is increased from
20 MHz to 160 MHz (an eight fold increase) the optimum UGB increases from 241.1 kHz to 241.1 ∗ 45/6 ≈
1.364 MHz. The optimum jitter reduces from 461 fs to 461/(85/12 ) ≈ 194 fs. The simulated values of the
optimum UGB and jitter at 160 MHz are 1.35 MHz and 191 fs, which are very close to the estimated
values based on the analysis from Eq.(158) and Eq.(159).
The mathematical analysis so far assumes that the reference noise is zero. In practice however, when the
reference noise is also taken into account, depending on the reference noise levels, the optimum jitter
and UGB will show nearly similar trends as predicted by Eq.(158) and Eq.(159). Fig.28 shows the Jitter
vs UGB plot for different reference frequencies. The simulated values of the optimum UGB and jitter
at 160 MHz are 1.025 MHz and 272.8 fs. As the reference frequency is increased, the noise contribution
from the Σ − ∆ modulator decreases significantly, and the reference noise remains the same (the quality
of the reference signal is maintained the same as the frequency is varied). This leads the optimizer to
converge to a UGB less than the previous value (UGB decreased from 1.364 MHz to 1.025 MHz) due to
the presence of the reference noise and the optimum jitter increases from the predicted value due to the
new added noise from the reference signal (Jitter increases from 191 fs to 272.8 fs).

104
fr = 20 MHz
fr = 40 MHz
fr = 80 MHz
fr = 160 MHz

103

Jopt 460.9 fs

Jopt 272.8 fs

fopt 241.1 kHz fopt 1.025 MHz

102
104 105 106 107

Fig. 28. Optimum Jitter and UGB vs reference frequency in Fractional-N PLLs

VII. I MPACT OF THE PLL OUTPUT FREQUENCY ON THE OPTIMUM UGB AND JITTER
Having considered the impact of choice of the reference frequency on the optimum parameters of the
PLLs, we now look at the effect of the choice of the output frequency on the PLL optimum dynamics
and jitter. To do that, we vary the output frequency by keeping the reference frequency fixed. To arrive
at a clearer picture and make the analysis more accurate, we refine the model of the VCO phase noise
to account for the dependence on the VCO frequencies as discussed in Section III. Using the frequency
dependent phase noise model of the VCO from Eq.(54)
KH Qvco
Sφ,0 ( f ) = 2 = 2 f0 2 =⇒ KH = Qvco f0 2 (160)
f f
where Qvco is the VCO signal quality and is a frequency independent measure of how pure the VCO
clock signal is.

A. Integer-N PLLs
The optimum UGB and the optimum jitter in the case of Integer-N PLLs can be rewritten as
r s r
KH Qvco f0 2 Qvco
fopt = 2
= 2
= · fr (161)
N KL N KL KL
  1/4
Qvco KL ( f0 )2 (KL Qvco )1/4
Jopt = √ TC0 = √ C0 (162)
π N π fr
Since the reference frequency is maintained constant Eq.(161) and Eq.(162), shows that the optimum
UGB and the optimum integrated jitter are independent of the VCO frequency as long as the purity of
the VCO signals are the same even as the frequency is varied. Fig.29 shows the simulated plots for Jrms

Fig. 29. Optimum Jitter and UGB vs VCO frequency in Integer-N PLLs

vs UGB as the VCO frequency is varied from 0.6 GHz to 9.6 GHz. The VCO frequency is varied keeping
its ’purity’ constant and the plot shows that the optimum UGB and jitter remain the same and are the
independent of the VCO frequency, corroborating the analysis.
In practice, as the VCO frequency is increased, the FOM of the VCO decreases with increasing fre-
quency [9] especially for frequencies in 10’s of GHz. That is for a given VCO power, the quality of the
VCO clock degrades (Qvco increases) with increasing VCO frequency. Assuming that the FOM of the
VCO degrades linearly with increasing VCO frequency, the quality of the VCO also degrades (increases)
linearly with the VCO frequency. Qvco ∝ f0 . Using this model for the quality degradation with VCO
frequency, from Eq.(161) and Eq.(162), the optimum UGB and jitter are related to the VCO quality and
frequency as follows p p
fopt ∝ Qvco ∝ f0 & Jopt ∝ (Qvco )1/4 ∝ f0 1/4 (163)
Fig.30 shows the optimum jitter vs UGB plot for different VCO frequencies with the quality of the
VCO increasing linearly
√ with the VCO frequency. As expected the UGB increases from 850 kHz at
f0 = 2.4 GHz to 850· 8 ≈ 2.4 MHz at f0 = 19.2 GHz. Similarly the optimum jitter increases from 217.7 fs
at f0 = 2.4GHz to 217.7·81/4 = 366.1 fs at f0 = 19.2 GHz. The simulated values of optimum jitter and
UGB increase by the same amount as predicted by Eq.(163).

B. Fractional-N PLLs
Similar to the integer-N PLLs, we analyze the case where the VCO frequency is varied and study the
impact on the optimum parameters of the Fractional-N PLL. We use the modified models of the VCO
phase noise to account for the changing VCO frequency as it was done in the previous section.
 1/2L  
fr 12Qvco f0 2 fr 12Qvco 1/2L 1/L
fopt = = · f0 (164)
2π fr 2π fr
From the above equation, it can seen that
fopt ∝ f0 1/L (165)
 f0 = 2.4 GHz
f0 = 4.8 GHz
f0 = 9.6 GHz
f0 = 19.2 GHz

103

Jopt = 366.1 fs, fopt 2.34 MHz

Jopt = 217.7 fs, fopt 850 kHz

102
104 105 106 107

Fig. 30. Optimum Jitter and UGB vs VCO frequency with degrading quality with frequency in Integer-N PLLs

Similarly the impact of the optimum jitter on the VCO frequency can be derived to be
s s
2Qvco f0 2 2L 1 2Qvco 2L 1
Jopt = · = · (166)
fopt 2L − 1 2π f0 fopt 2L − 1 2π
From Eq.(165) and Eq.(166), the dependence of the optimum UGB and jitter on the PLL output frequency

f0 = 2.4 GHz
f0 = 4.8 GHz
f0 = 9.6 GHz
104

103

Jopt = 461.1 fs, fopt = 237.6 kHz

Jopt = 373.8 fs, fopt = 381.8 kHz

105 106

Fig. 31. Optimum Jitter and UGB vs VCO frequency in Fractional-N PLLs

can be expressed as follows

1
fopt ∝ f0 1/L & Jrms ∝ p ∝ f0 −1/2L (167)
fopt
An increase in the VCO frequency results in a decrease in the quantization step size at the divider
output (assuming that there is no prescaler in the feedback path), which amounts to a reduced input
noise of the PLL. This in turn results in an increased UGB and reduced jitter due to decrease of noise
contributions from both the Σ − ∆ modulator (due to reduced quantization step size) and the VCO (due to
the increased optimum UGB).
Fig.31 shows the plot of Jitter vs UGB for three different VCO frequencies 2.4 GHz, 4.8 GHz and 9.6 GHz.
The quality of the VCO signal is kept constant. The optimum UGB increases from 236.7 kHz at the VCO
frequency of 2.4 GHz to 237.6 ∗ 41/3 ≈ 377.2 kHz as the VCO frequency is increased by four times
9.6 GHz. The simulated optimum UGB value at the VCO frequency of 9.6 GHz is 381.8 kHz (as shown
in the figure) which is very close to the estimated value of 377.2 kHz using the relation of UGB and the
output frequency in Eq.(167). Similarly, the optimum jitter decreases from 461.6 fs at VCO frequency
of 2.4 GHz to 461.1/(41/6 ) ≈ 366 fs at f0 = 9.6 GHz. The simulated jitter value of 373.8 fs at 9.6 GHz
matches very closely to the estimated value of 366 fs using the relationship between the optimum UGB
and the output frequency given in Eq.(167).

C. Impact of the output frequency on Fractional-N PLLs employing a prescaler in the feedback path
In PLLs with a prescaler in the feedback path, what matters in the noise analysis is the input frequency
of the feedback divider as it determines the quantization step size of the divider. There are two possibilities
in this case 1) One can change the PLL output frequency without changing the frequency f0d at which the
programmable divider operates (by increasing the prescaler value proportional to the output frequency).
2) The divider frequency changes in proportion to the output frequency and the prescaler value is fixed.
The second case is the same as the analysis that was carrier out in the previous section. In the first case
where the input to the multimodulus divider is kept the same even as the VCO frequency is varied, the
quantization noise of the modulator remains the same even and thus optimum dynamics and jitter should
also remain the same.
1 1
   
fr 12Qvco f0 2 2L fr 12Qvco f0d 2 2L
fopt = = (168)
2π P2 f r 2π fr
The optimum jitter can be expressed as
s s
2Qvco f0 2 2L 1 2Qvco 2L 1
Jopt = · = · (169)
fopt 2L − 1 2π f0 fopt 2L − 1 2π
Since f0d remains unchanged, from Eq.(168) the optimum UGB remains unchanged and is independent
of f0 . Similarly from Eq.(169), it can be seen that the optimum jitter is also independent of the output
frequency. This should be intuitive as the Σ − ∆ modulator noise and the VCO noise (assuming the purity
remains the same) remain unchanged, the optimum UGB and jitter should also remain unchanged.
VIII. D EPENDENCE OF THE OPTIMUM UGB AND JITTER ON THE FREQUENCY PLANNING OF THE PLL
The optimum UGB and jitter of an integer-N PLL were shown to be
r
KH (KL KH )1/4
fopt = & Jopt = √ T ·C0 (170)
N 2 KL π N
where C0 is a constant that depends on the filter model or the loop phase margin. In the pervious sections
as the dependence of frequency planning on the optimum dynamics and jitter were studied, the reference
and the VCO frequencies were varied keeping one of them constant. But what if both are varied and how
does the optimum UGB and jitter change with changing reference and VCO frequencies. The question is
better understood when framed in a different manner. Does the jitter of a PLL depend upon the choice
of the reference and VCO frequencies (or the frequency planning of the PLL) and if it does how does it
vary? To study the impact of the absolute values of the frequencies, we use the modified models of the
reference and VCO phase noise that captures the dependence of the phase noise of the clocks on their
frequencies as explained in Section III.
KH Qvco f0 2
Sφ, fr ( f ) = KL = Qre f fr 2 & Sφ, f0 ( f ) =
= (171)
f2 f2
Substituting the expressions for phase noise parameters KL and KH in terms of the quality or purity of
the signals into the Eq.(99) and Eq.(100) we get
s s
Qvco f0 2 Qvco
fopt = = (172)
N 2 Qre f fr 2 Qre f
  1/4
Qre f Qvco ( f0 fr )2

1/4
Qre f Qvco
Jopt = √ TC0 = C0 (173)
π N π
√
Eq.(170) show that the optimum UGB and integrated jitter are inversely proportional to N and N
respectively, that there is a strong dependence on the divide value or the absolute values of the reference
and VCO frequencies. This is not always true and thus the derived expressions can be misleading when
interpreted as it is. As it can be seen from Eq.(172) and Eq.(173), that the optimum parameters depend
upon the quality of the reference and VCO clocks and not on the absolute value of the frequencies or the
divide value. Thus the optimum UGB and jitter does not depend upon the divide value or the frequency
planning of the PLL, as long as the quality of the clocks are maintained the same even as the reference
and VCO frequencies are varied.
In case of Fractional-N PLLs on the other hand, the reference frequency and the VCO frequency have a
direct impact on the optimum UGB and jitter of the PLL as predicted by Eq.(167) and Eq.(159).

IX. A RRIVING AT THE VCO AND REFERENCE CLOCK SPECIFICATIONS FROM THE RMS JITTER OF THE PLL
In the analysis carried out so far, we started with a noisy reference and VCO clock signals and derived
the optimum UGB and the minimum jitter achievable. However in most PLLs designs, the design usually
starts with a jitter or rms phase error specification and then arriving at the requirements of the reference
and VCO clock noise levels to achieve the desired jitter. The rms phase error can be expressed in terms
of the reference and VCO phase noise as
 
2
p
2 2 2 φrms 4
Nopt = φrms = 4 KH KL N C0 =⇒ KH ·N KL = (174)
2C0
For a given φrms , the product of KH and N 2 KL is constant 25 and from Eq.(174), it can be seen that

KH

φrms1>φrms2>φrms3

φrms1
φrms2
φrms3

N2KL
Fig. 32. Constant φrms curves on a KH − KL plane or Noise plane

there an infinite number of solutions that satisfy the equation. In fact all the solutions of Eq.(174) can be
visualized graphically on a KH − NLK plane or the noise plane. The solutions of the equation fall on the
hyperbolic line on the ’noise plane’ as shown in Fig.32. Each curve represents the locus of the the values
of KH and N 2 KL that meet same the rms phase error specification and as the rms phase is increased the
25 The reference noise floor K is multiplied by N 2 so that both the noise sources can be compared at the same frequency, the PLL output frequency
L
f0 = N fr .
curves shift away from the origin. We refer to these curves as constant jitter (or φrms ) curves on a noise
plane. Another interesting point to note is that since the optimum phase error is dependent on the product
of the noise of the reference and VCO signals, it should be equal to zero if either the reference or VCO
phase noise is zero. If KH = 0 (a noiseless VCO), then from Eq.(174), the optimum rms phase error is zero
and to achieve this optimum jitter the bandwidth must be set to zero. This is because the reference noise is
still finite and to achieve zero rms phase error, the reference phase noise should be fully eliminated which
is achieved by choosing the optimum bandwidth to be zero. Similarly, if N 2 KL = 0 (a noiseless VCO), the
optimum phase error is zero and to achieve zero jitter the optimum UGB is infinite. This is because to
achieve zero rms phase error, the VCO phase noise has to completely eliminated, which is achieved by
setting the optimum UGB to infinite. However in practical analog PLLs, there are practical limitations to
the minimum and maximum values of the UGB. Typically the UGB cannot be very small (< fr /1000) or
greater than fr /10 for practical reasons like large loop filter area and PLL stability. Using these conditions
of maximum and minimum bandwidth, we can arrive at some upper and lower bound for the solutions
of Eq.(174).
From the analysis of the integer-N PLLs it was shown that for a noise optimized PLL, the reference
and VCO contribute equally at the PLL output. The noise of the VCO and the reference clocks can be
expressed in terms of the total phase noise power Nopt as
Nopt
Nvco = Nre f = (175)
2
Eq.(175) can also be expressed in terms of KH and KL as follows
Nopt φrms 2 2KH 2
= = 2KL N 2 fopt C0 2 = C0 (176)
2 2 fopt
The optimum UGB is lowest when the VCO noise is at its lowest value or the reference noise is at the
highest value. The optimum UGB should be minimum to attain low jitter in both cases. We can arrive at
the minimum and maximum values of the VCO and reference noise using this condition to be
φrms 2 2KH C0 2 φrms 2 fu,min φrms 2
= 2KL N 2 fu,minC0 2 = =⇒ N 2 KL,max = & KH,min = (177)
2 fu,min 4 fu,minC0 2 4C0 2
Similarly the optimum UGB is maximum when the VCO noise is very high or when the reference noise
is at its minimum value. Using this condition in Eq.(176), we can arrive at the minimum and maximum
values of the reference and the VCO noise levels to be
φrms 2 2 2 2KH C0 2 2 φrms 2 fu,max φrms 2
= 2KL N fu,maxC0 = =⇒ N KL,min = & KH,max = (178)
2 fu,max 4 fu,maxC0 2 4C0 2
For a given rms jitter (or rms phase error), the desired reference noise and VCO noise range can be
estimated using Eq.(178) and Eq.(177)
 
2 2 2 φrms 2 φrms 2
N KL ∈ [N KL,min , N KL,max ] = , (179)
4 fu,maxC0 2 4 fu,minC0 2
 
fu,min φrms 2 fu,max φrms 2
KH ∈ [KH,min , KH,max ] = , (180)
4C0 2 4C0 2
This reduces the range of values (from an infinite to a finite range) of the reference and VCO noise to
meet the desired jitter as shown in Fig.33.(a). If the reference noise N 2 KL,re f is given or known, then
one can graphically solve for the desired VCO phase noise parameter (KH,des ) by using Fig.33.(a) or by
solving Eq.(174) and vice versa. Another interesting point to note is that as the desired rms phase error is
decreased, the range of values of reference and VCO noise over which the rms phase error specification
will be met also decreases (as given by Eq.(177) and Eq.(178)) as shown in Fig.33.(b). Eventually to
theoretically achieve zero jitter, the plot converges to a [0, 0] point on the noise plane (and the permissible
range of KH and N 2 KL also shrinks to zero as φrms → 0).
 KH

KH,max fu,max
KH
Decreasing φrms
KH,max fu,max

constant φrms
fu,min
KH,des
fu,min
KH,min KH,min

N2KL,ref N2KL,max N 2K L N2KL,min N2KL,max N 2K L

N2KL,min

Fig. 33. a) Constant φrms curve with reduced range on the noise plane (KH − N 2 KL plane) and b) Constant φrms curves for decreasing jitter on the noise plane

A. Quality of clocks vs minimum Jitter

A more intuitive way of analyzing the clock requirements based on the jitter specifications is by using
the clock quality (Qre f , Qvco ) in place of the noise levels (KH , KL ). From Eq.(174), the rms phase error and
the reference and VCO noise levels are related as follows
φrms 4 π4 Jrms 4 f0 4
KH KL = =⇒ K H KL = (181)
16N 2C0 4 N 2C0 4
By rearranging the terms in Eq.(181), and using the result fr = f0 /N, we get
KH KL π4 Jrms 4
= (182)
f0 2 fr 2 C0 4
The quality of the reference and VCO signals are defined as Qvco = KH / f0 2 and Qre f = KL / fr 2 and
substituting these values in Eq.(182), we arrive at the relation between the Quality of the reference and
VCO clocks to the PLL jitter as derived in the previous section to be
 
πJrms 4 C0
1/4
Qvco Qre f = =⇒ Jrms = Qvco Qre f (183)
C0 π
By using the clock quality instead of noise levels, the jitter now depends only on two design variables,
the quality of the two clocks. For a given jitter specification the product of the quality of the two clocks
is a constant. Thus we will now have a plot of hyperbolic constant jitter curves on a Qvco − Qre f plane
very much like curves on the KH − KL plane. Fig.34.(a) shows an illustrative plot of the constant Jitter
curve on a Qvco − Qre f plane and Fig.34.(b) shows the constant Jitter curves shrink in size as the desired
jitter value decreases (reaching the theoretical [0, 0] point on the Qvco − Qre f plane. It should be noted that
though Eq.(183) shows that if either one of the clocks is ideal Qvco = 0 or Qre f = 0, then the minimum
jitter tends to zero. That however is not practical, as to achieve zero jitter the optimum bandwidth of
the PLL should either be zero or infinity. For example if the reference source is ideal with zero noise
Qre f = 0, then the optimum jitter reaches zero and optimum UGB to achieve that jitter value is ∞. This
is because the VCO noise has to be completely suppressed to achieve zero jitter. To completely suppress
or eliminate the VCO noise the theoretical bandwidth required is infinite. And the opposite holds true
for the case when the VCO is noiseless (Qvco → 0). The optimum jitter tends to zero and the optimum
bandwidth to achieve zero jitter is 0 (to completely eliminate the reference noise).
s
C0
1/4 Qvco
lim Jrms = Qvco Qre f → 0 & lim fopt = →∞ (184)
Qre f →0 π Qre f →0 Qre f
 Qvco
Qvco,max fu,max
Qvco Decreasing Jrms
Qvco,max fu,max

constant Jrms curve

fu,min
KH,des
Qvco,min fu,min Qvco,min

Qref,min Qref Qref,max Qref Qref,min Qref,max Qref

Fig. 34. a) Constant Jrms cuvre with reduced range on a Qvco − Qre f plane and b) Constant Jrms cuvres for decreasing jitter on a Qvco − Qre f plane

s
C0
1/4 Qvco
lim Jrms = Qvco Qre f →0 & lim fopt = →0 (185)
Qvco →0 π Qvco →0 Qre f
Thus one must exercise caution while using Eq.(183) and realize that it is not possible to achieve zero
jitter if one of the noise sources is made zero as implied by the equation. The equation is valid for finite
non-zero values of clock purity Qclk > 0. Also by restricting the minimum and maximum values of the
PLL bandwidth, we can limit the range of the values of Qvco and Qre f as it was done for the KH − KL
plane.
We start with the fact that both the VCO and the reference source contribute to jitter equally at the
optimum point.
   2
φrms 2 2KH C0 2 2 2 2 Qvco C0 2 C0
= = 2KL N fopt C0 =⇒ Jrms = = Qre f fopt (186)
2 fopt fopt π π
If the optimum UGB that minimizes the jitter is at its minimum value, it implies that the VCO noise is
very low (and the reference noise is at a maximum level since their product is constant for a given jitter).
   2
2 Qvco C0 2 C0
Jrms = = Qre f fu,min (187)
fu,min π π
Solving Eq.(187), we can arrive at the minimum VCO quality and the maximum reference quality levels.
   
Jrms π 2 Jrms π 2 1
=⇒ Qvco,min = fu,min & Qre f ,max = (188)
C0 C0 fu,min
Similarly if the UGB is maximum, it implies that VCO noise is at its maximum level (and the reference
noise is at a minimum since their product is constant for a given jitter).
   2
2 Qvco C0 2 C0
Jrms = = Qre f fu,max (189)
fu,max π π
Solving Eq.(189), we can arrive at the minimum VCO quality and the maximum reference quality levels.
   
Jrms π 2 Jrms π 2 1
=⇒ Qvco,max = fu,max & Qre f ,min = (190)
C0 C0 fu,max
Thus the range of Quality of the Reference and VCO clocks are given by
"    #
Jrms π 2 1 Jrms π 2 1
Qre f ∈ [Qre f ,min , Qre f ,max ] = , (191)
C0 fu,max C0 fu,min
 " 2  2 #
Jrms π Jrms π
Qvco ∈ [Qvco,min , Qvco,max ] = fu,min , fu,max (192)
C0 C0
using these results the constant jitter curves can also be reduced to a simplified or reduced version on a
Qvco − Qre f plane as shown in Fig.34.(a). It is more convenient to plot the jitter in the Qvco − Qre f plane
on a log scale as the relation between Qvco and Qre f reduces to a linear function. Taking logarithm on
both sides of Eq.(183) we get
 

πJrms
10 log10 (Qvco ) + 10 log10 Qre f = 40 log10 (193)
C0
A lower value of Jrms demands lower values of Qvco and Qre f or higher (or better) quality reference source
and VCO. If the quality of the reference sources Qre f is known, one can graphically solve from Fig.35.(a)
or solve Eq.(193) to find the desired VCO quality Qvco,des . Since it a log(Qvco ) − log(Qre f ) graph, as the
desired jitter specification decreases exponentially (say in multiples of 10) from Eq.(191) and Eq.(192)
it can be seen that the range also decreases exponentially on a linear scale and on a log scale it remain
the same (it becomes more negative). Thus the shrinking constant jitter curves becomes parallel constant
jitter lines moving towards [−∞, ∞] as the jitter tends to zero as shown in Fig.35.(b).

40log(Jrmsπ/C0)
10log(Qref) (0,0)
10log(Qref) Qref,min Qref Qref,max (0,0)

Qvco,max fu,max Decreasing Jrms

fopt=fu,max

fopt,des Qvco,des
fopt fu,min
Qvco,min
constant log(Jrms) line fopt=fu,min 40log(Jrmsπ/C0)

10log(Qvco) 10log(Qvco)

Fig. 35. Figure showing a) Constant log(Jrms (φrms )) line on a log(Qvco ) − log(Qre f ) plane and b) decreasing noise range with decreasing Jrms on a
log(Qvco ) − log(Qre f ) plane

X. T HE PLL DESIGN PLANES

Engineers are more comfortable with (or used to) terms like figure-of-merit and power dissipation than
the quality of the clocks. So a more useful goal for the analysis would be to derive a relationship between
figure-of-merti (FOM), power consumption in the clock sources and the minimum jitter. We start with the
relation between the figure-of-merit of a clock source, power and quality as discussed earlier
 
Pclk 10(FOMclk /10)
FOMclk = 10 log10 Qclk = 10 log10 (Qclk ) + Pclk,dBm =⇒ Qclk = (194)
1 mW 103 Pclk
Substituting the expression for figure-of-merit in Eq.(183) or Eq.(193), the expression relating the jitter
and power and FOM of the reference and VCO clocks can be derived to be
   
10(FOMvco +FOMre f )/10 πJrms 4 C0 4 10(FOMvco +FOMre f )/10
= =⇒ Pre f Pvco = (195)
106 Pre f Pvco C0 πJrms 106
 1/4 FOMvco + FOMre f
C0 10−6
∴ Jrms = · 10 40 (196)
π Pvco Pre f
In a similar manner, the optimum UGB of the PLL can also be expressed in terms of FOM and power
of the VCO and reference sources.
s r FOMvco − FOMre f
Qvco Pre f
fopt = = · 10 20 (197)
Qre f Pvco
The power-jitter relation in Eq.(195) can also be expressed on a dB scale (log scale) as follows
 
πJrms
Pvco,dBm + Pre f ,dBm = −40 log10 + FOMvco + FOMre f (198)
C0
Eq.(198) has four unknowns (the two FOMs and Power numbers). In practice a designer may have an
upper limit on the power that can be spent on the PLL or some reference FOMs for the VCO and reference
clocks available to them. So what is of interest is to see the desired FOMs of the clock sources for a
given power limit. And similarly, for a given FOM what is the range of values of power of the clocks
that are required to achieve the jitter specification.
In the first case, we fix the FOM 26 and then get an estimate of the power numbers that can achieve the
desired jitter. The optimum jitter and the UGB in Eq.(198) can then be expressed as
 
πJrms
Pvco,dBm + Pre f ,dBm = −40 log10 + FOMvco + FOMre f (199)
C0
Since the FOM of the two clocks are known prior, the only variables in this equation are the VCO and

Pvco,dBm FOMref FOMref,min FOMref,max (0,0)

fopt=fu,min
Pvco,dBm,max fopt=fu,max FOMvco,max
constant log(Jrms) line
fopt

fopt
Pvco,dBm,min fopt=fu,max constant log(Jrms) line FOMvco,min
fopt=fu,min

(0,0) Pref,dBm,min Pref,dBm,max Pref,dBm

(a) (b) FOMvco

Fig. 36. Figure showing Constant log(Jrms (φrms )) line on a) the power plane (Pvco,dBm − Pre f ,dBm plane) and b) the FOM plane (FOMvco − FOMre f plane).

reference clock powers. For a given rms jitter, we can visualize the VCO and reference clock powers as
straight line on a power plane as shown in Fig.36.(a). Similar to the Q-plane, we can derive the minimum
and maximum values of the reference clock power Pre f ,dBm ∈ [Pre f ,min,dBm , Pre f ,max,dBm ] and VCO clock
power Pvco,dBm ∈ [Pvco,min,dBm , Pvco,max,dBm ] based on the minimum and maximum possible UGB.
 
πJrms
Pre f ,dBm,min = 10 log10 ( fu,min ) + FOMre f − 20 log10 (200)
C0
 
πJrms
Pre f ,dBm,max = 10 log10 ( fu,max ) + FOMre f − 20 log10 (201)
C0
 
πJrms
Pvco,dBm,min = −10 log10 ( fu,max ) + FOMvco − 20 log10 (202)
C0
 
πJrms
Pvco,dBm,max = −10 log10 ( fu,min ) + FOMvco − 20 log10 (203)
C0
26 That is the clocks with a fixed FOM are available to the engineers, may be from their previous generations of PLL design or taken from the research
literature.
Now if the powers of the two clocks are fixed based on an upper limit on the total power consumption
in each block, then the desired values of the FOM to achieve the jitter specification can be derived from
Eq.(199) to be  
πJrms
FOMvco + FOMre f = 40 log10 + Pvco,dBm + Pre f ,dBm (204)
C0
Since the powers of the reference and VCO clocks are constants, the FOMs of the two clocks are the only
variables in Eq.(204). For a given rms jitter specification, the desired range of FOM values that satisfy
Eq.(204) can be visualized as straight line on a FOM plane as shown in Fig.36. The range of permissible
values of FOM of the reference and the VCO clocks (based on the minimum and maximum UGB values)
can also be derived similar to the Power-plane and the Q-plane to be
 
πJrms
FOMre f ,min = −10 log10 ( fu,max ) + 20 log10 + Pre f ,dBm (205)
C0
 
πJrms
FOMre f ,max = −10 log10 ( fu,min ) + 20 log10 + Pre f ,dBm (206)
C0
 
πJrms
FOMvco,min = 10 log10 ( fu,min ) + 20 log10 + Pvco,dBm (207)
C0
 
πJrms
FOMvco,max = 10 log10 ( fu,max ) + 20 log10 + Pvco,dBm (208)
C0
The effect of the FOMs can also be visualized on a power plane by plotting the constant jitter lines on a
power plane for different FOM values. Increasing the FOM values (poorly designed clocks) will push the
constant jitter line away from the origin as shown

A. Quality plane, Power plane and FOM plane

10log(Qref) (0,0) FOMref (0,0)

Pvco,dBm

fu,max Decreasing Jrms fu,min fu,max Decreasing Jrms

fu,min fu,min

Decreasing Jrms fu,max

Pref,dBm
10log(Qvco) FOMvco
(a) (b) (c)

Fig. 37. Figure showing Constant log(Jrms (φrms )) lines on a) the Quality plane (log(Qvco ) − log(Qre f ) plane) and b) the power plane (Pvco,dBm − Pre f ,dBm
plane) and c) the FOM plane (FOMvco − FOMre f plane).

To summarize the discussions in this section so far, there are three design relations for a PLL that
relate jitter and the specifications of the VCO and reference clocks like quality, power and FOM given
by Eq.(193), Eq.(199) and Eq.(204). The locus of the variables of these three equations can be visualized
as constant jitter lines on a quality plane or power plane or FOM plane as shown in Fig.37.
The first result in Eq.(193) is the Quality equation. The jitter and the optimum UGB (and thus the PLL
loop dynamics) are uniquely determined by the quality of the reference and the VCO clocks given by the
relation   s

πJrms Qvco
10 log10 (Qvco ) + 10 log10 Qre f = 40 log10 & fopt = (209)
C0 Qre f
Once the jitter specification of the PLL is known, Eq.(429) gives the range of values of the reference
and VCO clock quality that can achieve the desired Jrms . It can be visualized more conveniently on the
Quality plane or Purity plane as shown in Fig.37.(a). The plot shows constant jitter lines which are locus
of all the points where the jitter is constant even as the quality of the two clocks are varied. The UGB of
the PLL varies with the quality of the clocks in accordance to Eq.(429). It can be seen from the plot as
the jitter is reduced the desired quality of the clocks also decreases (it becomes more negative). A lower
value of the quality implies a purer clock and it is achieved by increasing the power or improving the
FOM of the clock.
The second design equation is the Power relation. From the knowledge of the FOM of the clocks one
can then also derive the relation between the jitter and PLL loop dynamics (UGB) to power of the VCO
and reference clocks as
  r
πJrms Pre f
Pvco,dBm + Pre f ,dBm = −40 log10 + λ0 & fopt = · 10λ1 /20 (210)
C0 Pvco
where λ0 = FOMvco + FOMre f and λ1 = FOMvco − FOMre f are constants. Eq.(430) can be visualized
on a power plane as shown in Fig.37.(b). The locus of all the points where the jitter is constant is a
straight line as shown in the figure and constant jitter line on the power plane gives the range of values
of the VCO and reference clock powers to achieve the desired jitter Jrms . A decreasing Jrms results in
an increased power consumption in the clocks and the constant jitter lines move away from the origin
as shown in the figure (indicating an increase in the power consumption). The constant jitter lines tend
towards ∞ as the jitter tends to zero.
Finally the third design equation is the FOM equation. If there is an upper bound on the total power
consumption on each block that is if Pre f and Pvco are fixed, then starting from the quality of the clocks
one can arrive at equations relating the jitter and optimum UGB to VCO and reference clock FOM as
follows.
 
πJrms
FOMvco + FOMre f = 40 log10 + λ2 & fopt = λ3 · 10(FOMvco −FOMre f )/20 (211)
C0
p
where λ2 = Pvco,dBm + Pre f ,dBm and λ3 = Pre f /Pvco are constants as the powers of the VCO and reference
clocks are fixed. On an FOM plane shown in Fig.37.(c), constant jitter lines shows the locus of points
which are the different reference and VCO FOM values that achieve the desired jitter. As the desired
jitter values decreases, the desired FOM of the clocks also decreases (they become more negative) and
the constant jitter line moves towards −∞ as shown in the figure.
It is useful to have these planes as a starting point for the PLL design as it relates the specifications
of the PLL (Jitter and optimum loop dynamics) to the specifications of the VCO and reference clocks
like FOM and power. Fig.38 shows the constant jitter lines on the design planes of a PLL with a VCO
and reference clock FOMs of -190 dBc/Hz and -300 dBc/Hz for the power plane √ and power limit of
Ptot = Pre f + Pvco = 20 mW for the FOM plane for jitter levels of 100 fs, 100/ 10 = 31.62 fs and 10 fs.
As expected for a fixed clock FOM, the power of the clocks increases with decreasing jitter on the power
plane. Similarly, the desired FOM of the clocks decreases with decreasing jitter on the FOM plane.

XI. FOM AND Q UALITY OF THE PLL

The previous sections developed relations between jitter and the specifications of the reference and
the VCO clocks like power, quality and FOM. The next logical step is to derive the relation between
the FOM of the overall PLL and its relation to the reference and VCO clock specifications. Unlike the
definitions of the clock FOM so far, the PLL FOM is defined from a time domain specification (Jrms ) as
follows [5]   !
Jrms 2 PPLL
FOMPLL = 10 log10 (212)
1s 1 mW
 45 -180

40 -185

35 -190

30 -195
Pvco,dBm

25 -200

FOMvco
20 -205

15 -210

10 -215
Jrms = 10 fs Jrms = 10 fs
5 Jrms = 31.62 fs -220 Jrms = 31.62 fs
Jrms = 100 fs Jrms = 100 fs
0 -225
-10 0 10 20 30 40 -330 -320 -310 -300 -290 -280
Pref,dBm FOMref

Fig. 38. Figure showing simulated constant log(Jrms ) lines on a) The power plane and b) the FOM plane.

By substituting Eq.(183) in Eq.(212) we get

 2 !
C0 p PPLL
FOMPLL = 10 log10 Qre f Qvco · (213)
π 1 mW
Thus the FOM of the PLL can be related to the quality of the VCO and reference clocks as follows
10 log10 (Qvco ) + 10 log10 (Qre f )
FOMPLL = + PPLL,dBm +C (214)
2
where C = 20 log10 (C0 /π) is a constant depending on the PLL filter characteristics.
Replacing the quality of the clocks in Eq.(229) with their FOMs from Eq.(194) we get
 2 !
C0 P PLL
FOMPLL = 10 log10 10(FOMvco +FOMre f )/20 p (215)
π Pvco Pre f
Further simplifying the above equation leads to an expression of FOM of the PLL in terms of the FOM
of the reference and VCO clocks given by
FOMvco + FOMre f Pvco,dBm + Pre f ,dBm
FOMPLL = + PPLL,dBm − +C (216)
2 2

A. Minimum achievable FOM in PLLs

A question of interest as we keep pushing the limits in designing better quality clocks and PLLs is, Is
there a theoretical lower limit on the minimum achievable FOM of the PLL? That is does Eq.(216) have
a minimum value. Using the result PPLL = Pvco + Pre f , Eq.(215) can be reduced to
s r !
FOMvco + FOMre f Pvco Pre f
FOMPLL = + 10 log10 + +C (217)
2 Pre f Pvco
The above equation shows that given the reference and VCO clocks with fixed FOMs, the FOM of the
PLL is dependent on ratio of the VCO and reference powers. The expression for the PLL FOM can also
be written in terms of the VCO and reference powers in dBm units as follows.
FOMvco + FOMre f P∆  
FOMPLL = + + 10 log10 1 + 10−P∆ /10 +C (218)
2 2
 FOMPLL

-0.5 0.5

FOMPLL,min

0
Pvco,dBm = Pref,dBm P∆ (Pvco,dBm - Pref,dBm)

Fig. 39. Illustrative plot of PLL FOM vs P∆ = Pvco,dBm−Pre f ,dBm showing the minimum PLL FOM condition.

where P∆ = 10 log10 (Pvco /Pre f ) = Pvco,dBm −Pre f ,dBm . As the VCO power is increased keeping the reference
power constant, P∆ increases (becomes more positive) and vice versa. For values of |P∆ | > 10 dB, the FOM
of the PLL can be expressed as
FOMvco + FOMre f P∆
FOMPLL ≈ + +C (219)
2 2
The above expression shows that the FOM is an increasing function of P∆ , that is the FOM of the PLL
increases if the either the VCO power or the reference power is higher than the other one
Pvco,dBm > Pre f ,dBm or Pre f ,dBm > Pvco,dBm =⇒ FOMPLL ↑
So naturally one should expect the FOM of the PLL to have a minima at P∆ = 0 or when Pre f = Pvco as
shown illustratively in Fig.39.
d(FOMPLL )
= 0 =⇒ Pvco,dBm = Pre f ,dBm or Pvco = Pre f (220)
dP∆
The minimum FOM condition can also derived by directly finding the minimum value 27 of Eq.(217).
Substituting Pre f = Pvco in Eq.(217), the minimum value of the FOM is given by
FOMvco + FOMre f FOMvco + FOMre f
FOMPLL,min = + 10 log10 (2) +C = + 3 +C (221)
2 2
The exact value of the power of the individual clocks can be found by substituting Eq.(220) in Eq.(199)
 
πJrms FOMvco + FOMre f
Pre f ,dBm = Pvco,dBm = −20 log10 + (222)
C0 2
The minimum achievable FOM can be visualized on a power plane by plotting the equal power line
Pvco,dBm = Pre f ,dBm on a power plane as shown in Fig.40. The points where the line intersects the constant
jitter lines is where the FOM is minimum. The optimum UGB of the PLL corresponding to the minimum
27 The
p p
theoretical minimum of the function Pvco /Pre f + Pre f /Pvco can be found by assuming x = Pre f /Pvco and finding the minima of a simpler function
√ 1
x+ √
x
The minima of the above function occurs at x = 1
x = 1 =⇒ Pre f = Pvco
 45

40

35

30
Pvco,dBm

25

20

15

10 Jrms = 10 fs
Jrms = 31.62 fs
5 Jrms = 100 fs
Pvco = Pref
0
-5 0 5 10 15 20 25 30 35 40
Pref,dBm

Fig. 40. Figure showing the minimum FOM line Pre f = Pvco intersecting the simulated constant log(Jrms ) lines on a power plane

FOM can be derived by substituting Pre f = Pvco in Eq.(197) to be

FOMvco − FOMre f
FOMvco − FOMre f
fopt = 10 20 or 10 log10 ( fopt ) = (223)
2
An interesting observation to be made here is that with the knowledge of FOMs of the reference and the
VCO clocks, starting from the desired jitter specification, all the important design specifications of the
PLL are uniquely defined. The three important design equations of a PLL can be expressed in terms of
the reference and VCO FOMs and jitter specifications as follows
λ0 λ0 λ1
FOMPLL,min = + 3 +C & Pre f ,dBm = Pvco,dBm = −Jrms,dBs + +C & 10 log10 ( fopt ) = (224)
2 2 2
where Jrms,dBs = 20 log10 (Jrms /1 s) is the rms jitter expressed in dBs (decibel second) units, λ0 = FOMvco +
FOMre f and λ1 = FOMvco − FOMre f are constants that depend on the FOM of the reference and VCO
clocks. C = 20 log10 (C0 /π) is a constant that depends on the PLL phase margin 28 . The value of C0 is
minimized by increasing the PLL p phase margin and the minimum value of C0 is that of a Type-I PLL
0
with a 90 phase margin C0 = π/2. Thus the theoretical minimum value of the FOM of the PLL is
given by
p !
FOMvco + FOMre f π/2 FOMvco + FOMre f
FOMPLL,min = + 20 log10 +3 ≈ −5 (225)
2 π 2
A well designed PLL should be able to achieve this theoretical minimum within a dB or two of margin.
The FOM expression in Eq.(225) is still very useful for PLL designers as it is independent of the
PLL architecture. Whether the PLL is analog Chargepump PLL (CPPLL) or an analog Subsampling
PLL (SSPLL) or an all digital PLL (ADPLL), the FOM can never be lower than the theoretical minimum
value in Eq.(225). Any PLL with lower phase margin will result in the degradation of the FOM . For
28 The constant C is dependent on the filter model assumed for the low pass and high pass transfer functions. The general value of the constant C can be
0 0
expressed in terms of the PLL transfer functions in more general terms as described previously
Z ∞ Z ∞
!1/4
L( f ) 2 1/ f 2
C0 = (a1 a2 )1/4 = d f· df
0 1 + L( f ) 0 1 + L( f )
 p
example, for a Type-II PLL with a phase margin of φPM = 600 , the value of C0 ≈ 2π/3 and the theoretical
minimum value of the FOM can be derived to be
FOMvco + FOMre f
FOMPLL,min = − 3.73 (226)
2
In fact once we take the loop noise into consideration, the FOM of the PLL will increase depending on
the PLL loop architecture and the amount by which the FOM degrades is dependent on the FOM of the
PLL loop. The effect of the PLL loop on the FOM of the PLL will be discussed towards the end of the
chapter. Any PLL architecture that is able to approach the theoretical minimum FOM within a few dBs
of margin should be considered a well designed PLL.

B. PLL Quality
In similar fashion to the reference and VCO clocks, we define the Quality of a PLL which is a
measure of how spectrally pure the PLL output clock is. Since the PLL FOM is defined from a time
domain specification, the Quality of the PLL29 is also defined in this work in a similar manner as
 
Jrms 2
QPLL = & 10 log10 (QPLL ) = Jrms,dBs (227)
1s
On a log scale the quality of the PLL is simply the rms jitter in dBs units. PLLs of same Quality will
have the same output rms jitter irrespective of the output frequency. Like it was defined for the reference
and VCO clocks, the quality of the PLL is also a frequency independent performance metric. The FOM
of the PLL and its quality can be related 30 to the PLL Quality and the PLL power from Eq.(212) as
follows
FOMPLL = 10 log10 (QPLL ) + PPLL,dBm (228)
Substituting Eq.(228) in Eq.(229), we get
10 log10 (Qvco ) + 10 log10 (Qre f )
10 log10 (QPLL ) = Jrms,dBs = +C (229)
2
Eq.(229) shows that having either a good quality VCO or a reference source, one can design a PLL with
a good quality. One can choose a very high bandwidth and suppress the VCO noise to the maximum
levels if we have a good quality reference source and vice versa. Eq.(229) can also be expressed as in a
linear form as follows  2
p C0
QPLL = Qvco Qre f (230)
π

C. Quality of the reference and VCO clocks for the minimum FOM PLL
For the PLL with minimum FOM, we were able to derive expressions for the reference and VCO
clock powers in terms of the FOM of the clocks. Similarly, the quality of the clocks can also be derived
for the minimum FOM PLL in terms of FOM of the clocks. Since Pre f = Pvco for the minimum FOM
PLL, the quality of the reference and VCO clocks are not independent and are related as
FOMvco − FOMre f
Qvco
Pre f = Pvco =⇒ = 10 10 (231)
Qre f
29 It should be noted that when defining Quality for clocks, it was derived from frequency domain specifications (similar to FOM) and when defining for
PLLs, it was defined from time domain specifications. In case of PLLs defining quality based on frequency domain is not prudent as there are different
regions with different phase noise shapes and most importantly unlike the reference and the VCO clocks, the integrated jitter at the PLL output is always
a bounded quantity. The open loop VCO noise is not integrable due to the 1/ f 3 region extending all the way to zero frequency offsets. But the PLL high
pass filtering action ensures that the integrated jitter at the PLL output is finite. Similarly the integrated jitter of the reference clock can be quiet high (as it
extends all the way to fr /2 and the low pass filtering action of the PLL produces a finite value at the PLL output. So when defining quality of open loop
clocks a frequency domain approach is used and when defining quality for a PLL (a closed loop system), a time domain approach is preferred. However both
definitions signify how pure the clock output signal is. A lower value of Quality implies it is a very good clock source. In time domain it translates to lower
jitter and in frequency domain it translated to lower phase noise
30 On a log scale it can be defined as the sum to the quality and power of the PLL. On a linear scale the FOM is the product of quality and power.
Using this condition and the result Jrms,dBs = 10 log10 (QPLL ), the quality of the reference and VCO clocks
can be found by solving Eq.(230) and Eq.(231) and expressed in terms of the PLL jitter for the PLL with
the minimum FOM as
FOMvco − FOMre f
10 log10 (Qvco ) = + Jrms,dBs −C (232)
2

FOMre f − FOMvco
10 log10 Qre f = + Jrms,dBs −C (233)
2
XII. P OWER AND FOM REQUIREMENTS IN VERY LOW JITTER PLL S
In the last two decades as both the wireless and wireline communications saw an exponential rise in
the data rates and performance, the jitter requirements of the PLLs also decreased orders in magnitude.
For example the jitter requirements of the WiFi PLLs were in the order of 100’s of femtoseconds (WiFi-3
and WiFi-4) in the last decade and now in the order of 10’s of femtoseconds (for WiFi 7 MCS 13 signal).
The performance of high speed ADCs used in RF sampling applications also require clocks with very low
jitter levels. Once a VCO design or the reference clock design is optimized for performance to achieve
the best FOM possible, the only way to improve its quality is to increase the power. So it is natural to
expect low jitter PLLs to be very power hungry. It is therefore of great importance for PLL designers to
understand how the power of the VCO and reference clocks scales to achieve very low jitter levels and if
there is some optimal way of scaling the powers of the clocks. This section discusses the different ways
in which the power of the clocks can be varied to achieve low jitter levels and then arrive at the most
optimal power scaling approaches that minimizes the overall PLL FOM.
The power of the VCO and reference clocks and jitter of the overall PLL are related by
 
πJrms
Pvco,dBm + Pre f ,dBm = −40 log10 + FOMvco + FOMre f (234)
C0
Eq.(234) shows that for a given FOM of the reference and VCO clocks, the jitter can be lowered by
increasing the power consumption of the VCO and reference blocks (thus improving the quality of both
the clocks). There are two ways in which the power of the clocks can be varied to achieve low jitter.
1) By increasing the power of one of the clocks (either VCO or the reference clock) or 2) by increasing
or scaling the power of both the clocks together. Both these approaches lead to very different trade-offs
between the clock power dissipation and the achievable jitter.

A. Asymmetric power scaling

In many applications, the designer has control over changing the power of either one of the clocks.
In that case, we can treat the other power to be a constant. This approach of power scaling to achieve
low jitter levels in PLLs is refered in this work as Assymetric power scaling. Assuming the VCO power
is varied keeping the reference power contant, Eq.(234) reduces to
 
πJrms 1
Pvco,dBm = −40 log10 + γ0 =⇒ Pvco ∝ (235)
C0 (Jrms )4
where γ0 = FOMre f + FOMvco − Pre f ,dBm is a constant. In a similar manner by keeping the power of the
VCO clock constant, if the power of the reference clock is varied, we get a similar relation between the
reference power and the jitter.
 
πJrms 1
Pre f ,dBm = −40 log10 + γ1 =⇒ Pre f ∝ (236)
C0 (Jrms )4
where γ1 = FOMre f + FOMvco − Pvco,dBm is a constant. Eq.(235) and Eq.(236) show that in this approach,
the power of the clocks raises exponentially with a linear decrease in the jitter specifications. For a ten
fold decrease in the jitter, the power of the clocks should be increased by 10,000 times!
Another important point to node in this approach is the variation of the UGB of the PLL as the powers
are varied. The optimum UGB of the PLL is related to the clock powers and jitter as follows
r r
Pre f (FOMvco −FOMre f )/20 Pre f
fopt = · 10 =⇒ fopt ∝ (237)
Pvco Pvco
r
1 1 1 p 1
Pvco ∝ 4
=⇒ fopt ∝ ∝ (Jrms )2 & Pre f ∝ 4
=⇒ fopt ∝ Pre f ∝ (238)
(Jrms ) Pvco (Jrms ) (Jrms )2
An increase in the VCO power results in a decrease in the optimum UGB and an increase in the reference

60 108
Ptot,dBm
Pvco,dBm
50

40 107

30

106
Ptot/vco (dBm)

fopt (Hz)
20

fopt 200 kHz

10
105
0

-10
104

-20
fopt 2 kHz
-30 103
10-2 10-1 100 10-2 10-1 100
Jrms (ps) Jrms (ps)

Fig. 41. Figure showing the variation of the VCO power, total power and the optimum UGB with the PLL jitter in the asymmetric power scaling method

power results in an increase of the optimum UGB. This result should sound intuitive, as to achieve low
jitter levels, it is theoretically sufficient to have one of the clocks to be very pure (low Qvco or Qre f ).
The bandwidth of the PLL can then be increased or decreased to suppress the noise of the ’more noisy’
clock. Possessing a very high purity VCO (by increasing the VCO power) can help in drastically reduce
the jitter if the bandwidth is chosen to be very low to suppress the noise from the reference clock and
vice versa. For example to achieve a ten fold reduction in jitter, the VCO or the reference clock power
should be increased by 104 times and the UGB should be decreased or increased by one hundred times.
Fig.41 shows the variation of the VCO power with the PLL jitter. As the PLL jitter is reduced from 100 fs
to 10 fs, the VCO power (and even the total power) increases from 10 dBm to 50 dBm and the optimum
UGB decreases from 200 kHz to 2 kHz as expected.

B. Symmetric power Scaling

The other method of achieving low jitter levels is to increase both the powers of the VCO and
reference clocks in same proportion (the total power of the PLL also increases by the same proportion).
This approach is refered to as Symmetric power scaling. To derive the relation between the power of the
clocks and the PLL jitter, we start with the result in Eq.(186) to arrive at
 
πJrms 1
Pre f ,dBm = −20 log10 + FOMre f + 10 log10 ( fopt ) =⇒ Pre f ∝ (239)
C0 (Jrms )2
 
πJrms 1
Pvco,dBm = −20 log10 + FOMvco − 10 log10 ( fopt ) =⇒ Pvco ∝ (240)
C0 (Jrms )2
If both the VCO and the reference clock powers are increased in the same proportion, then the optimum
UGB remains the same as it is dependent on the ratio of the VCO and reference clock powers (for a
fixed FOM as given by Eq.(237)). The power and jitter are related as inversely as given in the above
equations. Unlike the assymetric power scaling the power of the individual clocks is inversely proportional
to Jrms 2 . Using the results in Eq.(239) and Eq.(240), we can arrive at a relation between the total power
Ptot = Pre f + Pvco to jitter Jrms as follows
  !
πJrms 10FOMvco /10
Ptot,dBm = −20 log10 + 10 log10 fopt 10FOMre f /10 + (241)
C0 fopt
Substituting Eq.(237) in the above equation, the equation reduces to
  s r !
πJrms FOMvco + FOMre f Pvco Pre f
Ptot,dBm = −20 log10 + + 10 log10 + (242)
C0 2 Pre f Pvco
Since the FOM of the two clocks are kept constant and the power of both the VCO and reference clocks
are increased in the same proportion, from Eq.(242) and Eq.(237), it can be concluded that
1
Ptot ∝ & fopt = constant (243)
(Jrms )2
Thus in the symmetric power scaling approach, the total PLL power is inversely proportional to Jrms 2

35
Ptot,dBm
Pvco,dBm
30
106

25

20
fopt 209 kHz
fopt (Hz)
Ptot/vco (dBm)

15

10
-20 dB/dec 105

-5

-10 104
10-2 10-1 100 10-2 10-1 100
Jrms (ps) Jrms (ps)

Fig. 42. Figure showing the vairation of the total PLL power and the optimum UGB with the PLL jitter in the Symmetric power scaling approach

and the optimum UGB remains constant. For a ten fold reduction of jitter, the total power of the PLL
has to increase by one hundred times and the optimum UGB remains the same. This result should sound
intuitive as increasing the power of the clocks in same proportional results in a similar reduction of noise
of both the clocks which in turn results in the decrease of the overall jitter. Since both the clocks are
equally less noisy (due to higher power dissipation), the optimum UGB remains the same. Fig.42 shows
the variation of the total power with the PLL jitter. As the PLL jitter is reduced from 100 fs to 10 fs, the
VCO power (and even the total power) increases from 10 dBm to 30 dBm (a 20 dB increase in power) and
the optimum UGB remains constant as expected.

C. Comparison of the two approaches

In the asymmetric power scaling of keeping one of the clock powers constant, the power has to increase
with a higher exponent. Let Pvco and Pre f be the powers that correspond to the jitter Jrms . If the jitter is to
be reduced from 100 fs to 10 fs (by a factor of 10), then by choosing the second approach of increasing
both the powers of the VCO and reference clocks to 100Pvco and 100Pre f will result in a one-hundred
fold increase in the total power. On the other hand, the asymmetric power scaling approach leads to a ten
thousand fold increase in the power as discussed earlier.
In addition
p to that the optimum UGB also varies depending on the ratio of the powers of the clock
fopt ∝ Pre f /Pvco . If the asymmetric power scaling approach is used to achieve lower jitter, then the
UGB of the PLL has to changed exponentially with increasing jitter. For example if the VCO power
alone is increased by 104 times, to achieve a 10× reduction in jitter, then the optimum UGB has to be
decreased by 100 times. Or if the reference power alone is increased to achieve a ten-fold reduction in
jitter, then the optimum UGB has to be increased by 100 times. This might lead to values that are higher
than the maximum value of the UGB or much lower values leading to implementation problems like large
loop filter area. By choosing the symmetirc scaling appraoch to reduce the jitter by varying both the VCO
and reference powers in same proportion results in no change in the UGB. Thus it should be the preferred
option for achieving very low jitter levels.

D. Relation between FOM of the PLL and power scaling

Another interesting point to consider is the variation of the FOM of the overall PLL as the jitter is
decreased following both these approaches. The FOM of the PLL in Eq.(215) can be reduced by using
the result PPLL = Ptot = Pvco + Pre f to
s r !
FOMvco + FOMre f Pvco Pre f
FOMPLL = + 10 log10 + +C (244)
2 Pre f Pvco
To understand the impact of the asymmetric power scaling on the FOM of the PLL, we study what
happens to the PLL FOM as one of the clock powers is increased keeping the other one constant. In
asymmetric power scaling approach, the power of the clock has to be increased exponentially to achieve
low jitter levels. Assuming that the VCO power is varied, it can be safely assumed that at low jitter levels
Pvco >> Pre f . Thus the FOM of the PLL can be approximated to
FOMvco + FOMre f + Pvco,dBm − Pre f ,dBm
FOMPLL ≈ +C (245)
2
The VCO power Pvco,dBm is the only variable in the above equation as all the other quantities are kept

-205
Asymmetric Power Scaling
Symmetric Power Scaling
-210

-215

-220
FOMPLL (dBm)

-225

-230
-20 dB/dec

-235

-240

-245

-250
10-2 10-1 100
Jrms (ps)

Fig. 43. Plot showing the variation of FOM with jitter in the Symmetric and Asymmetric power scaling approaches.
constant. We can substitute Eq.(235) in the above equation to arrive at
 
Jrms
FOMPLL ≈ −20 log10 +C1 (246)
1s
where C1 = FOMre f + FOMvco − Pre f ,dBm is a constant. Eq.(245) shows that increasing the VCO power (to
achieve very low jitter levels) results in a degradation of the overall PLL FOM (a higher value of FOM is
an indicator of a poor PLL design). Eq.(246) shows that the FOM of the PLL increases with decreasing
jitter at the rate of 20 dB/decade of decreasing jitter values. A 10× reduction in jitter results in a 20 dB
reduction in the FOM of the PLL in the asymmetric power scaling approach. This should sound intuitive
as increasing the power of the only one of the clocks will result in a much higher power dissipation than
necessary which in turn results in the degradation of the overall FOM of the PLL.
In case of the symmetric power scaling, both the VCO and the reference clock powers are increased in
the same proportion. From Eq.(244) it can be seen that all the terms of the equation remain constant as
the power of the reference and VCO clocks are varied in the same proportion.
s r !
FOMvco + FOMre f Pvco Pre f
FOMPLL = + 10 log10 + +C = constant (247)
2 Pre f Pvco
It can be seen from the above expression that the best way to decrease the jitter of the PLL is to increase
both the VCO and reference powers in the same proportion. That is to choose symmetric power scaling
as this approach ensures that even as the jitter of the PLL is decreased (by increasing the power of both
the clocks), the FOM of the overall PLL will remain the same. Fig.43 shows the variation of the FOM
with the decreasing jitter levels in the symmetric and asymmetric power scaling approaches. The results
show the FOM remaining constant for the symmetric power scaling approach and degrades -20 dB/decade
in case of the asymmetric power scaling approach as predicted by equations Eq.(246) and Eq.(247).

XIII. O PTIMUM LOOP DYNAMICS , MINIMUM ACHIEVABLE JITTER AND FOM OF THE PLL IN THE PRESENCE OF THE
LOOP NOISE

UP f0 fdiv fdivs
D Q N D Q
VDD
ref
R Trst
0 clk
(b)
tr
VDD
VDD
VDD DN in
D RQ out
div 0 vn
0
tr
tr (a) (c)

Fig. 44. Simplified model of the different blocks in the PLL showing the input signals with their slopes for a) PFD, b) Divider and c) Equivalent model for
noise analysis using a CMOS buffer.

In the discussions so far, the PLL jitter is shown to be a function of the quality and FOM of the
reference and VCO clocks. In practice however, the PLL loop which performs the filtering action on the
reference and VCO phase noise also adds noise which raises the overall PLL jitter. It is therefore of
interest to understand the impact and the relationship between the PLL loop noise on the overall noise of
the PLL and on the FOM of the PLL. The main blocks in the PLL loop like the PFD, Divider, Chargepump
and the DTC (in case of low noise Fractional-N PLLs with quantization noise cancellation) add noise at
the input of the PLL which adds directly to the reference noise. This section discusses the different noise
sources and the models for the noise sources and the expressions for the FOM of the PLL loop in the
presence of the loop noise.

A. PFD and divider

A conventional tri-state PFD consists of two flip flops and an AND gate in the reset path as shown
in Fig.44.(a). the phase noise added due to the PFD is also mainly due to the flip flips that the reference
and divide signals pass through and also the inverters and gates in the reset path. The flip flops determine
the timing of the rising edge of the UP/DN signals and the reset path gates determine the falling edge
timing of the UP/DN path.
Most frequency dividers in PLLs are asynchronous dividers with the output of the dividers driving the
succeeding stages to save power 31 . The problem with asynchronous divider is that each of the cascaded
divider stages add noise to the edges as they propagate through them. Most practical PLLs solve this
problem using resynchronization flip flops at the divider output as shown in Fig.44.(b) where the divider
edges are resampled (resynchronized) using the high frequency VCO clock. Thus the noise added by the
frequency divider can be eliminated completely and the phase noise at the resynchronized divider output
is mainly due to the noise added by the resynchronization flip flops. The feedback divider power can be
significant part of the PLL power budget as the initial stages of the divider operate at the VCO frequency
and increasing or decreasing the power dissipated in the divider stages does not contribute to the overall
noise at the resynchronized divider output as the noise is eliminated by the resynchronization flip flops.
Thus the divider power (Pdiv ) will not figure in the expressions for the noise of the frequency divider
circuit.
Since the noise of both the PFD and the frequency divider are due to the flips flops and inverters, the
impact of the jitter can be understood by a simple equivalent model of a clock signal driving a noisy
buffer as shown in the Fig.44.(c). The jitter at the output of such a system is same of the jitter of a driven
system discussed in Chapter II. Assuming the slope of the input signal to be SL and the input referred
voltage noise of the buffer vn (t) with a noise PSD Svn ( f ), the phase noise at the buffer output is given by
Svn ( f )
Sφ,bu f ( f ) = 2
(2π fr )2 (248)
(SL)
The phase noise at the buffer output is determined by the input referred voltage noise and the slope
of the input clock. The block with the lowest value of the slope thus ends up determining the overall
noise at the PLL input. Assuming a CMOS inverter and that the devices are in saturation region near the
threshold point, the transconductance of the CMOS inverter can be approximated to Gm = gmp +gmn , where
gmn = 2Ibu f /Vov and gmp = 2Ibu f /Vov are the transconductance of the NMOS and PMOS devices (with the
same overdrive voltage Vov ) respectively. The current Ibu f here represents the short circuit current of the
CMOS inverter that is drawn from the supply during the transition phase of the inverter. The input referred
noise of the inverter or buffer can be approximated to
2EB γ 2EB γ EBVov
Svn ( f ) = = = (249)
Gm gmn + gmp 2Ibu f
where EB = kT is the product of Boltzmann constant and the temperature. To avoid confusion with the
reference period T , we will use EB in place of kT throughout this chapter. The input referred noise of
the buffers are determined by the device sizes in the inverters. Both the PFD and divider outputs are
digital signals that operate at frequencies close to the reference frequency and the signal will have very
31 The power in an asynchronous divider scales down exponentially as one moves down the divider path, with the first stage operating at the VCO frequency
dissipating the maximum power. Assuming a cascade of divide-by-2 stages, the power of the succeeding stages scale down exponentially by a factor of 2 as
one moves from the high frequency part of the divider to the lower frequency.
high slopes (due to the signal’s small rise times) at the rising/falling instants. Assuming VDD as the supply
voltage and tr as the rise time, the slope of the PFD and the divider signals can be approximated to
VDD
SL p f d = SLdiv ≈ (250)
tr
Substituting Eq.(250) and Eq.(249) in Eq.(251), the phase noise of the PFD and divider can be expressed
as
EB γtr 2 Vov EB γtr 2 Vov
Sφ,bu f ( f ) = (2π fr )2 = αbu f (2π fr )2 (251)
2VDD Ibu f VDD 2Pbu f VDD
The current Ibu f refers to the current drawn from the supply during the transition interval when the
input signal level is close to the inverter threshold and Pbu f = αbu f Ibu f VDD is the power dissipated in the
inverter 32 .

B. Reference clock and DTC

VDD
VDD
VDD T in out
0
T out vn
Trange
(a) (b)

Fig. 45. Simplified model of the a) Crystal oscillator circuit and b) DTC (showing only the comparator part).

A reference oscillator circuit consists of the piezoelectric crystal (which is modeled as a series RLC
circuit and capacitor in parallel) and an amplifier in feedback as shown in Fig.45. The high gain of the
amplifier produces a square wave at the output which then goes through the crystal (a series RLC circuit)
and is fed back as a sinusoid at the input of the inverter. The inverter than acts like a sine-wave to square
wave converter and the input of the inverter can be approximated to a sine wave of frequency fr and
amplitude VDD /2. The inverter acts like a threshold detector with a threshold at VDD /2 (which is where
the slope of the signal and also the gain of the inverter is maximum).
A DTC is a digital delay line and the manner in which the DTC generates the delay proportional to the
digital input is dependent on the DTC architecture. A DTC consists of two parts 1) the slope generator
and 2) the comparator. Depending on the mechanism of slope generation, there are two popular DTC
architectures in use called a) the constant slope DTC and 2) variable slope DTC [10], [11]. The slope
generator part of the DTC is very different in both the architectures. Even though the slope generation
circuits are different, the average slope of the signal seen at the input of the threshold detector (or
comparator) in both the architectures is dependent on the range of the DTC Trange and the supply voltage
VDD . The slope seen by the comparator can be approximated to VDD /Trange . The range of the DTC typically
varies between 1-4 VCO cycles depending on the order of the Σ − ∆ modulator as discussed in Chapter
III. Trange = nT0 = nT /N and n ≤ 4. The comparator is mostly a CMOS inverter which generates a signal
with sharp edges as shown in Fig.45.(b).
32 In case of the reference clock circuit, the inverter in Fig.44.(a) and Fig.44.(b) has three components of power. 1) The dynamic power which is dependent
on the load capacitance and the frequency of the operation of the circuit Cl fr VDD 2 , 2) the short circuit power, which is the power drawn from the supply
when the input signal is close to the threshold point and 3) the leakage power which is a fixed dc power drawn from the supply usually much smaller than
the other two components. The current Ibu f is the short circuit current drawn from the supply when the inverter is at the high gain point when the input signal
is close to the threshold point. The average current drawn from the supply will be lower than Ibu f . Hence the power dissipated in the circuit can be expressed
as Pbu f − αbu f Ibu f VDD . The value αbu f is smaller than one and can be estimated from simulations. It should be noted that for the inverters in the PFD and
divider which sees input signals with high slopes or small rise/fall times, the dynamic power dissipation will be the dominant contributor to the total power
dissipation. However the short circuit power dissipation will be proportional to the dynamic power dissipation. For example doubling the inverter size will
double both the dynamic and the short circuit power. So even though Pbu f is taking the short circuit power into consideration, it will still be proportional to
the dynamic power dissipation and the difference in values between the two values can be accounted for in the factor αbu f .
So in both the reference clock and the DTC circuits, the phase noise is mainly determined by an inverter
that is being driven by a slowly varying signal of a slope much smaller than the slopes of the reference
and divide signals. Assuming Svn ( f ) to be the input referred noise of the inverter, the phase noise of the
reference circuit and the DTC can be approximated to 33
Svn ( f ) 2Svn ( f )
Sφr ( f ) = 2
(2π fr )2 & Sφ,dtc ( f ) = 2
(2π fr )2 (252)
(SLre f ) (SLdtc )
The slopes of the input of the inverters in both the reference circuit and the DTC can be approximated to
VDD πVDD VDD NVDD
SLre f = ωr = & SLdtc = = (253)
2 T Trange nT
The input referred noise of the inverter can again be modeled in the same way as it was done for the
inverters in the PFD and divider. Substituting Eq.(253) in Eq.(254), the phase noise of the reference circuit
and the DTC can be expressed as
 
2EB γ Vov 8EB γ Vov 2πn 2
Sφr ( f ) = & Sφ,dtc ( f ) = (254)
IrVDD VDD IdtcVDD VDD N
Assuming Pre f = αr IrVDD and Pdtc = αdtc IdtcVDD are the reference and the DTC power and the phase
noise can be expressed in terms of the power dissipated in those blocks as follows 34
 
2EB γ Vov 8EB γ Vov 2πn 2
Sφr ( f ) = αr & Sφ,dtc ( f ) = αdtc (255)
Pre f VDD Pdtc VDD N
Eq.(255) shows that the phase noise of the reference and the DTC blocks decreases with increasing the
power as one would expect. Another interesting observation to make is that the reference phase noise
expression is not dependent on the reference frequency. As the reference frequency is increased, the phase
noise remains the same which translates to a better quality. The DTC noise should be included only in
Fractional-N PLLs with quantization noise cancellation, which is very common in low noise PLLs. The
DTC noise should also include the quantization noise of the re-quantization Σ − ∆ modulator as discussed
in the previous chapter. But the quantization noise of the re-quantizer is generally much smaller than the
residual quantization noise of the primary Σ − ∆ modulator even with a small gain error (in the order of
1-2% gain error). The thermal noise is the most dominating in-band noise contributor as the quantization
noise is highpass shaped and it is ignored in the loop noise calculations.

C. Intrinsic noise sources: chargepump and loop filter

The only block that is not considered so far is the chargepump and the phase noise of the CP can be
analyzed by referring the noise at the input of the PLL by dividing the CP noise by Icp /2π. And we can
define the quality of the CP by normalizing it with the reference frequency in a similar manner. Assuming
gm,cp = 4Icp /Vov and Sicpn ( f ) = 2EB γgm,cp D as the total CP current source transconductance and the CP
current noise PSD at the CP output, the input referred CP noise can be expressed as follows
Sicpn ( f ) 2 8EB γD VDD 2 8EB γTcp fr VDD
Sφ,cp ( f ) = 2
(2π) = αcp (2π) = αcp (2π)2 (256)
Icp Pcp Vov P cp Vov
33 The DTC noise is multiplied by 2 to account for the noise contribution from the slope generator. A well designed DTC should ensure that the noise from
the slope generator and the comparator should be equal. Thus the power dissipated in the comparator is Iinv = IDTC /2 =⇒ Pinv = 0.5Pdtc . This is the current
value used in computing the phase noise of the DTC.
34 It should be noted that the reference circuit and the DTC are not class-A circuits, their operating points change with the signal levels. For circuit like the
reference clock and the DTC, the short circuit power can be significant as the input slopes are much slower compared to the blocks like the divider or the
PFD. In the region close the threshold point, the inverter behaves like a class-A amplifier with a very high gain. The current Ir and Idtc represent the class-A
current drawn from the supply during this transition region. The actual average current drawn from the supply will be lower than these values and hence the
powers of the reference and DTC circuits will be lower than Pre f and Pdtc . So to account for this, we multiply the power of the reference and DTC circuits
by factors αr and αdtc respectively. The value of both these factors will be less than one and can be estimated from simulations. Thus we would actually end
up getting Pre f = αr Ir VDD and Pdtc = αdtc IdtcVDD
where D = Tcp /T is the duty cycle of the UP/DN current pulses in the steady state and Pcp = αcp IcpVDD
is the power dissipated in the chargepump 35 . Eq.(256) shows that the CP noise of the PLL decreases
as the power in the chargepump is increased. In addition to that, similar to the reference noise, the CP
noise increases in proportion to fr (for the quality to remain the same, the phase noise should increase
in proportion to fr 2 ) and thus the quality improves with increasing reference frequency (if the CP current
and the ON time of the UP/DN pulses is kept constant).
The other part of the intrinsic noise source is the noise from the loop filter. The noise from the loop filter
can also be modeled as a lowpass noise source (the detailed analysis is provided in the next chapter on
PLL loop design) and the input referred noise PSD of the loop filter is given by
   2
2EB Kv R 2 2EB 2π
Sφ,l p f ( f ) = NFl p f = NFl p f (257)
R N fu R Icp
where NFl p f is the noise factor of the loop filter given by NFl p f = (1 + Sopamp /2EB R) and Sopamp is the
input referred noise floor of the opamp in the active loop filter. For passive loop filters NFl p f = 1 and as
a good design practice the opamp noise floor is kept below the resistor noise floor and thus NFl p f ≤2.
The total input referred noise due to intrinsic noise sources from the PLL loop can be expressed as
   2
NFl p f 2π
Sφ,int ( f ) = Sφ,cp ( f ) + Sφ,l p f ( f ) = 2EB γDgm,cp 1 +
γDgm,cp R Icp
 
8EB γTcp fr VDD NFl p f
= αint (2π)2 1 + (258)
Pint Vov γDgm,cp R
where Pint = Pcp + Pl p f is the total power consumed by the chargepump and the loop filter and αint =
αcp (1 + Pl p f /Pcp ). For passive loop filters, there is no power dissipation in the filter and hence Pint = Pcp
and αint = αcp . For active loop filters Pint > Pcp and αint > αcp . Adding the loop noise degraded the noise
by the factor (1 + NFl p f /γDgm,cp R). It is implicit that an increase in the CP current will lead to a decrease
in the resistor value and thus an increase in the opamp in the active loop filter to reduce its input referred
noise by the same factor as the resistor noise.

D. Quality and FOM of the PLL loop

Having discussed the phase noise of the different blocks in the PLL loop and the reference clock, we
now consider the quality and FOM of the different blocks. The jitter at the PLL output depends upon
the quality of the reference and VCO clocks and PLL FOM depends upon the FOM of the reference and
VCO clocks. The problem is now to understand the impact of the PLL loop on the overall PLL jitter and
FOM. To do that we first define the Quality and FOM of the different blocks.
Since the noise sources are assumed to be white in nature and they operate at the reference frequency,
the quality of the different blocks can be considered in a similar manner as follows
Sφ ( f )
Q= (259)
fr 2
The quality of the different blocks based on the definition in Eq.(259) can be expressed as follows
Sφ,bu f ( f ) EB γ2π2 Vov 2
Q p f d = Qdiv = = αbu f tr (260)
fr 2 Pbu f VDD
Sφ,cp ( f ) 32EB γπ2 VDD
Qcp = = αcp Tcp T (261)
fr 2 Pcp Vov
35 The chargepump here is assumed to be a class-A circuit and hence the power dissipation is assumed to be equal to I V . However in some low power
cp DD
applications, the chargepump current is turned off once the UP and DN signals go to zero. In such cases the average power will be lower than IcpVDD . To
account for this, we multiply the IcpVDD by αcp so that Pcp = αcp IcpVDD . The factor αcp is less than one and can be found from simulations.
  
Sφ,int ( f ) 32EB γπ2 VDD NFl p f
Qint = = αint Tcp T 1 + (262)
fr 2 Pint Vov γDgm,cp R
 
Sφ,dtc ( f ) 32EB γπ2 Vov nT 2 32EB γπ2 Vov
Qdtc = = α dtc = αdtc (nT0 )2 (263)
fr 2 Pdtc VDD N Pdtc VDD
Sφr ( f ) 2EB γ Vov 2
Qre f = 2
= αr T (264)
fr Pre f VDD
Now that we defined the quality of the different blocks, the next step is to define the FOM of the different
blocks in a similar manner as it was defined for the reference and VCO clocks.
   
Pclk Pdtc
FOMclk = 10 log10 Qclk & FOMdtc = 10 log10 Qdtc (265)
1 mW 1 mW
The blocks in a PLL are driven systems unlike the reference and VCO clock circuits which are autonomous
systems (self sustaining oscillators). We treat the blocks as noise sources which corrupt the periodic signal
that passes through them and at the output of these blocks as the signals pass through them they will
appear as noisy clock signals very much like the outputs of the reference and VCO clocks and hence we
apply similar definitions for FOM of these blocks as well.
The FOM of the different blocks can be expressed as
   
Pbu f 2 Vov 2
FOMdiv = FOM p f d = 10 log10 Qbu f = 10 log10 αbu f 2EB γπ tr + 30 (266)
1 mW VDD
   
Pcp 2 VDD
FOMcp = 10 log10 Qcp = 10 log10 αcp 32EB γπ Tcp T + 30 (267)
1 mW Vov
    
Pint 2 VDD NFl p f
FOMint = 10 log10 Qint = 10 log10 αint 32EB γπ Tcp T 1 + + 30 (268)
1 mW Vov γDgm,cp R
   
Pdtc 2 Vov 2
FOMdtc = 10 log10 Qdtc = 10 log10 αdtc 32EB γπ (nT0 ) + 30 (269)
1 mW VDD
   
Pre f Vov 2
FOMre f = 10 log10 Qre f = 10 log10 αr 2EB γ T + 30 (270)
1 mW VDD
The Quality and FOM of the different blocks can be obtained from simulations and the Eq.(266)-Eq.(269)
can serve as estimates for comparison purposes and to understand intuitively which block contributes to
the total noise the most.
The VCO period is much larger than the rise and fall times of the PFD and divider signals as the rise
and fall times will be close to the delay time of a single CMOS inverter in any given technology. On the
other hand the VCO period is much smaller (N times smaller) compared to the reference period. Thus
the slopes of the input signals to the inverters in the PFD, divider, DTC and the reference clocks can be
related as
SLre f << SLdtc << SL p f d = SLdiv (271)
Thus if the buffers were to burn the same power, that is the input refered noise of the buffers are all the
same, then the phase noise of the different signals is related as follows
Sφr ( f ) >> Sφ,dtc ( f ) ≈ Sφ,int ( f ) >> Sφ,p f d ( f ) = Sφ,div ( f ) (272)
Similarly the quality of the different blocks can also be compared by examining equations Eq.(260)-
Eq.(264). The Quality of the PFD and divider is the least followed by the DTC and the charge pump and
then the reference source. One can a similar comparison of the FOM of the different block in a similar
manner. The quality and FOM of the different blocks can be written as follows
Qre f > Qdtc ≈ Qint > Q p f d = Qdiv (273)
 FOMre f > FOMdtc ≈ FOMint > FOM p f d = FOMdiv (274)
Another important observation to be made from equations for the quality and FOM of the different blocks
in the PLL loop in equations Eq.(260)-Eq.(264) and Eq.(266)-Eq.(270) is that quality and the FOM of
the reference and the chargepump improves with increasing reference frequency. The quality and FOM
of the DTC on the other hand depends upon the VCO or the output clock period or the range of the DTC
nT0 . Reducing the quantization step size at the multimodulus output in the Fractional-N PLL improves
the noise and hence the quality and FOM of the DTC. The quality of the PFD and divider is independent
of the reference or the output frequency and only depends upon the rise/fall times of the reference and
divide signals. As one moves towards lower technology nodes the rise/fall times decreases and the noise
and hence the quality of the PFD and divider should improve assuming that the noise of the devices
remains the same.

E. Impact of the PLL loop on the jitter and the FOM of the PLL
The total noise seen at the PLL input is given by
SφrT ( f ) = Sφr ( f ) + Sφ,dtc ( f ) + Sφ,p f d ( f ) + Sφ,div ( f ) + Sφ,cp ( f ) + Sφ,l p f ( f ) (275)
| {z }
Sφ,int ( f )

The quality of the total noise source seen at the PLL input is given by
Qre f T = Qre f + Qdtc + Qint + 2Qbu f (276)
The quality of the input signal can then be written in terms of the FOM and the power consumption of
each of the block as follows
!
10FOMre f /10 10FOMdtc /10 10FOMint /10 10FOMbu f /10
Qre f T = + + +2 · 10−3 (277)
Pre f Pdtc Pint Pbu f
The FOM of the reference and the loop combined is given by
 
Pre f T
FOMre f T = 10 log10 Qre f T · > FOMre f (278)
1 mW
where Pre f T = Pre f +Pint +Pdtc +2Pbu f is the total power combining the reference and the PLL loop power.
In the presence of the noise from the PLL loop, the quality of the reference noise should be substituted
by Qre f T in the expressions of optimum jitter and UGB. As seen in Eq.(276), the quality of the loop
Qre f T includes the contributions from the reference source and the PLL loop. Thus the optimum jitter,
UGB and the minimum achievable PLL FOM in the presence of the loop noise reduces to

1/4
1/4
Qre f Qvco Qre f T Qvco
Jopt = C0 → Jopt = C0 (279)
π π
s s
Qvco Qvco
fopt = → fopt = (280)
Qre f Qre f T
FOMre f T + FOMvco
FOMPLL,min = −5 (281)
2
The design goal here is to analyze and arrive at ways to design the overall system such that the FOM of
the entire system is minimized. That is to achieve a given noise specification how should the power be
distributed among the blocks such that overall power of the system is minimized.
To do this, we will consider a simpler case and lump all the noise from the PLL loop together as a single
block with phase noise Sloop ( f ) and quality Qloop and the corresponding FOM FOMloop .
Sloop ( f ) = Sφ,dtc ( f ) + Sφ,p f d ( f ) + Sφ,div ( f ) + Sφ,int ( f ) (282)
 !
10FOMdtc /10 10FOMint /10 10FOMbu f /10
Qloop = + +2 · 10−3 (283)
Pdtc Pint Pbu f
 
Ploop
FOMloop = 10 log10 Qloop · (284)
1 mW
where Ploop = Pint + Pdtc + 2Pbu f is the total power of the the PLL loop. Following an analysis similar to
the one presented in the rest of the section, one can derive closed form expressions for the overall FOM
of the PLL loop FOMloop in terms of the FOM of the individual blocks in the PLL loop by considering
two blocks at a time. But in the interest of brevity and to avoid cumbersome analysis, we assume that
FOMloop is known to the designer. FOMloop can be found from simulations by designing each of the
blocks in the PLL loop to achieve the same noise levels and measure the power required to achieved the
noise level. With this information, the FOM of the individual blocks are known and the quality of the
loop is also known Qloop . Substituting the loop quality and the loop power in Eq.(284) we can calculate
the FOM of the PLL loop. Intuitively the block with the poorest (highest) FOM will dominate the overall
FOM of the PLL loop. Assuming the loop FOM FOMloop and the loop power Ploop are known, the overall
quality of the reference clock after adding the noise from the blocks in the PLL loop can be written in a
much simpler form !
10 FOM re f /10 10FOM loop /10
Qre f T = + · 10−3 (285)
Pre f Ploop
The total power at the clock input including the reference and the PLL loop is Pre f T = Pre f + Ploop . The
design goal is to meet the desired quality Qre f T at the PLL input for a given FOMre f and FOMloop such
that the total power consumption Pre f T is minimized. It can be easily shown 36 to minimize the total PLL
loop power consumption (and hence the overall PLL FOM), the reference and the loop power and the
quality should be split as follows
Pre f T Pre f T
Pre f = & Ploop = (286)
1 + 10β1 /20 1 + 10−β1 /20
Qre f T Qre f T
Qre f = β /20
& Qloop = (287)
1 + 10 1 1 + 10−β1 /20
where β1 = FOMloop − FOMre f . Thus the distribution of power and noise (or quality) between the two
blocks is a strong function of the FOM of the two blocks. The FOM of the reference clock with the PLL
loop noise added can be shown to be
 
β1 /20
FOMre f T = FOMre f + 20 log10 1 + 10 (288)
If the FOM of the reference clock is very poor compared to the loop FOMre f >> FOMloop , then most
of the power and the noise specification should be bored by the reference circuit and vice versa
FOMre f >> FOMloop =⇒ Pre f ≈ Pre f T & Qre f ≈ Qre f T & FOMre f T ≈ FOMre f (289)
FOMloop >> FOMre f =⇒ Ploop ≈ Pre f T & Qloop ≈ Qre f T & FOMre f T ≈ FOMloop (290)
36 The goal is to minimize P
re f T = Pre f + Ploop for a given Qre f T . To do that we can simply multiply Pre f T with Qre f T and find the minimum value of the
product Qre f T Pre f T .
Ploop Pre f
Qre f T Pre f T = (Fre f + Floop ) + Fre f + Floop
Pre f Ploop

where Fre f = 10FOMre f /10 and Floop = 10FOMloop /10 are constants since the FOM of the blocks are known. The minimum value of the above equation can be
derived by assuming Ploop /Pre f = x and finding the minimum value of
s
Floop Floop
Fre f x + =⇒ x = = 10−β1 /20
x Fre f

where β1 = FOMloop − FOMre f .

When the FOM of the reference circuit and the PLL loop are equal β1 = 0, then the power and noise are
equally split between the two blocks
Pre f T Qre f T
FOMre f = FOMloop =⇒ Pre f = Ploop = & Qre f = Qloop = (291)
2 2
And the FOM of reference clock with added PLL loop noise case is given by
FOMre f = FOMloop =⇒ FOMre f T = FOMre f + 6 (292)

F. Impact on the PLL jitter and minimum achievable FOM of the PLL
The block with the larger (or poorer) FOM will dominate the overall FOM of the system. By substituting
Eq.(288) in Eq.(279), Eq.(280) and Eq.(281), the optimum jitter, UGB and the minimum achievable FOM
of the PLL can now be expressed as

1/4  1/4 Q Q
1/4
Qre f T Qvco (FOMloop −FOMre f )/20 re f vco
Jopt = C0 = 1 + 10 C0 (293)
π π
s s
Qvco Qvco 1
fopt = = p (294)
Qre f T Qre f 1 + 10(FOMloop −FOMre f )/20
FOMre f + FOMvco  
FOMPLL,min = − 5 + 10 log10 1 + 10(FOMloop −FOMre f )/20 (295)
2
When FOMre f >> FOMloop , the jitter, UGB and the minimum achievable FOM of the PLL reduces to
the case when the loop noise was absent

1/4 s
Qre f Qvco Qvco FOMre f + FOMvco
Jopt = C0 & fopt = & FOMPLL = −5 (296)
π Qre f 2
When FOMloop >> FOMre f , the jitter, UGB and the minimum achievable FOM of the PLL reduces to

1/4 s
Qloop Qvco Qvco FOMloop + FOMvco
Jopt = C0 & fopt = & FOMPLL = −5 (297)
π Qloop 2
The special case FOMre f = FOMloop is more practical in cases where the reference frequency is higher (when
the FOM of the reference clock is improved and becomes closer to the FOM of the loop), then the jitter,
UGB and the minimum achievable FOM of the PLL reduces to

1/4 s
2Qre f Qvco Qvco FOMre f + FOMvco
Jopt = C0 & fopt = & FOMPLL = −2 (298)
π 2Qre f 2
is equal to the reference noise level (FOMre f =
In the presence of the loop noise where the loop noise level √
FOMloop ), the overall PLL jitter is degraded (increased) by 2 times and the FOM of the PLL is degraded
by 3 dB. Choosing a PLL architecture with the lowest loop noise contribution will improve the FOM of
the PLL. In very low noise applications where the reference noise is very low, the loop noise can become
dominant and limit the FOM of the PLL. In such cases PLLs with low loop noise like Sub-sampling
PLLs or Injection locked PLLs are commonly used. Sub-sampling integer-N PLLs have much better loop
FOM compared to conventional CPPLLs [12] as the high phase detector gain suppresses the PLL loop
noise and thus can achieve much lower PLL FOM in the presence of loop noise. While Injection locked
PLLs (IL-PLLs) do not have a loop 37 and thus add no loop noise.
Having discussed the degradation of the FOM in the presence of loop noise, the next problem of interest
37 IL-PLLs suffer from the problem of harmonic locking where it can lock to any other harmonic closer to the desired harmonic N f of the reference
r
frequency like (N + 1) fr or (N − 1) fr . So an auxiliary frequency locked loop is used to ensure that the PLL output frequency is exactly equal to the desired
harmonic of the reference frequency f0 = N fr . The FLL is then turned disabled once the lock is achieved.
is the power dissipated in the reference, loop and the VCO circuits to improve the minimum FOM or very
low jitter levels. The next section discusses the power scaling approaches in the PLL to achieve minimum
jitter and PLL FOM in detail in the presence of loop noise.

XIV. P OWER SCALING TO ACHIEVE MINIMUM FOM OF THE PLL IN THE PRESENCE OF LOOP NOISE
With the addition of the PLL loop noise, the overall FOM of the PLL is degraded compared to the
ideal case where the loop noise was assumed to be zero. The jitter Jopt , UGB and the FOM of the PLL
in the presence of the loop noise are given by

1/4 s
Qre f T Qvco Qvco
Jopt = C0 & fopt = (299)
π Qre f T
s r !
FOMvco + FOMre f T Pvco Pre f T
FOMPLL = + 10 log10 + +C (300)
2 Pre f T Pvco
where C = 20 log10 (C0 /π) and it was assumed to be equal to -6 dB for practical applications. Since the
quality of the reference clock is degraded (increased) with the addition of the loop noise, the jitter of the
PLL increases. It can be seen from Eq.(299) that the only way to decrease the PLL jitter is to decrease
the quality of the reference or the VCO clocks. The quality of clock is inversely proportional to the power
of the clock and in a well designed PLL, it is the only available design variable for PLL engineers to
decrease jitter further. Based on how the power of the different blocks are scaled, the jitter can be lowered
in different ways. In this section we consider different approaches of scaling powers in the reference,
loop and VCO circuits to achieve the minimum FOM and the same jitter as the ideal case (when the loop
noise was considered to be zero). From the analysis we then arrive at the best approach of power scaling
to achieve the minimum PLL FOM.

A. Asymmetric power scaling

We start with an optimized PLL that is designed such that Pre f = Pvco = Popt to achieve minimum
PLL FOM initially. The loop noise increases the quality of the reference circuit and thus the jitter of the
PLL. The jitter can be lowered by either decreasing the quality of the reference and the loop or the VCO.
Assuming the reference circuit quality is decreased to restore the jitter level to the ideal case (where the
loop noise was assumed to be zero), the value of the new reference quality is given by

1/4
1/4
Qre f T Qvco Qre f Qvco Qre f T
Jopt = C0 = C0 =⇒ Qre f T = Qre f = (301)
π π 1 + 10β1 /20
where β1 = FOMloop − FOMre f . That is the reference quality has to decreased by a factor of 1 + 10β1 /20 .
This can be achieved by increasing the power of the reference and the loop by a factor of 1 + 10β1 /20 .
The power of the reference circuit and the loop is now increased to
Qre f T    2
β1 /20 β1 /20
Qre f T → = Q re f =⇒ P re f T → Pre f T 1 + 10 = P re f 1 + 10 (302)
1 + 10β1 /20
Initially the power in the reference circuit is Pre f = Popt and with the addition of the PLL loop noise, the
power of the loop and the reference circuit combined increases to Pre f T = Popt (1 + 10β1 /20 ). To further
decrease the jitter levels to the ideal value the power has to be increased further by the same factor of
2
1 + 10β1 /20 (hence the (1 + 10β1 /20 ) increase in reference power). The total power (reference+loop and
VCO power) after the power scaling is given by
  2 
β1 /20
PPLL = Pre f T + Pvco = Popt 1 + 1 + 10 (303)
With this change, the UGB and jitter remains the same as the ideal case. Since the power of the PLL
is increased to achieve the same jitter, the FOM of the PLL with the loop noise is degraded further.
Substituting Eq.(303) in Eq.(300), the FOM of the PLL can be shown to be
 2 
FOMvco + FOMre f 
β1 /20
FOMPLL = + 10 log10 1 + 1 + 10 +C (304)
2
The results can be better understood by considering an example case and then compare the increase in
power and FOM to the ideal case. Assuming FOMloop = FOMre f =⇒ β1 = 0, the PLL power is increased
to PPLL = 5Popt from its initial value of PPLL = Pre f + Pvco = 2Popt . So to achieve the same jitter levels as
the ideal case, the power of the PLL is increased by a factor of 2.5 (or a 150% increase in power). The
FOM of the PLL is given by
FOMvco + FOMre f
FOMPLL = +C + 10 log10 (5) (305)
2
Compared to the minimum achievable FOM of the ideal case, the FOM in this case increased by
10 log10 (5) − 10 log10 (2) ≈ 4 dB.
The other approach topasymmetric power scaling is to decrease both the VCO and the reference quality
by the same amount ( 1 + 10β1 /20 ) so that the jitter is restored back to its ideal value without loop noise.
!1/4
1/4
Qre f T Qvco C0 Qre f Qvco
Jopt = p p = C0 (306)
1 + 10β1 /20 1 + 10β1 /20 π π
Qre f T p Qvco
=⇒ Qre f T → p = Qre f 1 + 10β1 /20 & Qvco → p (307)
1 + 10β1 /20 1 + 10β1 /20
This
p is achieved by increasing the power of both the reference+loop and the VCO circuits by the factor
(1 + 10β1 /20 ). Since the reference and loop power is already increased by 1 + 10β1 /20 with the addition
of the PLL loop noise, the power of the reference+loop and the VCO are increased as follows
p  3/2 p
β β1 /20
Pre f T → Pre f T 1 + 10 1 /20 = Pre f 1 + 10 & Pvco → Pvco 1 + 10β1 /20 (308)
The power of the reference+loop and the VCO are increased in different proportions and so this is another
approach of asymmetric scaling. The total power in this approach is given by
p  
PPLL = Pre f T + Pvco = Popt 1 + 10β1 /20 2 + 10β1 /20 (309)
p
In this approach the jitter remains the same, but the optimum UGB is decreased by a factor of 1 + 10β1 /20
and the FOM of the PLL can be shown to be
FOMvco + FOMre f p
β /20

β1 /20

FOMPLL = + 10 log10 1 + 10 1 2 + 10 +C (310)
2
In a similar manner as it was carried out for the previous approach, the results can be better understood
by considering
√ an example case where FOMloop = FOMre f =⇒ β1 = 0. The PLL power is increased to
PPLL = 3 2Popt = 4.24Popt from its initial value of PPLL = 2Popt . So to achieve the same jitter levels as
the ideal case, the power of the PLL is increased by a factor of 2.12 (or a 112% increase in power). The
FOM of the PLL is given by
FOMvco + FOMre f  √ 
FOMPLL = +C + 10 log10 3 2 (311)
2
Compared  √to the minimum achievable FOM of the ideal case, the FOM in this case increased by
10 log10 3 2 − 10 log10 (2) ≈ 3.28 dB.
B. Symmetric power scaling
The other approach to power scaling to achieve low jitter levels is symmetric power scaling. The
addition of the PLL loop noise increases the total power consumption of the reference and the loop to
Pre f → Pre f T = Pre f (1 + 10β1 /20 ). The initial optimization was performed by choosing Pre f = Pvco and thus
with the addition of the loop noise, this condition no longer holds true Pre f T 6= Pvco and thus the FOM
of the PLL is no longer at the minimum possible value. So an intelligent design approach is to ensure
that the total power of the reference clock and the PLL loop be equal to the VCO power after adding the
loop noise to achieve the best FOM for the PLL.
   
Pre f T = Pvco = Pre f + Ploop = Pvco 1 + 10β1 /20 = Pre f 1 + 10β1 /20 (312)

Since the reference power is already increased by a factor of (1 + 10β1 /20 ), the VCO power should also be
increased by the same factor. This ensures that the quality of the VCO is decreased by the same amount
(1 + 10β1 /20 ) from its initial value. The total PLL jitter remains the same as the product of Qre f T Qvco
remains the same.
 1/4
Qvco Qvco C0
1/4 C0
Qvco →
=⇒ JrmsT = Qre f T = Q re f Qvco = Jrms (313)
1 + 10β1 /20 (1 + 10β1 /20 ) π π
By increasing the power of the VCO by an amount exactly equal to the reference+loop power, the optimum
jitter and the UGB will remain the same as the ideal case. The total power of the PLL is given by
 
β1 /20
PPLL = Pre f T + Pvco = 2Popt 1 + 10 (314)
The FOM of the PLL can be shown to be
FOMre f + FOMvco  
FOMPLL = + 10 log10 1 + 10β1 /20 + 10 log10 (2) +C (315)
2
This is the theoretical minimum value of the PLL FOM after adding the loop noise. To compare with the
previous results, we consider the case FOMloop = FOMre f =⇒ β1 = 0. The power of the PLL increase
to PPLL = 4Popt from its initial value of 2Popt . Thus the power increases by two fold (or a 100% increase).
The FOM of the PLL in that case is given by
FOMre f + FOMvco
FOMPLL = + 10 log10 (4) +C (316)
2
The PLL FOM has increased by 10 log10 (4) − 10 log10 (2) ≈ 3 dB from the ideal case with no loop noise.
Since the symmetric power scaling approach achieves the best PLL FOM equal to the theoretical minimum,
this should be the preferred approach of power scaling.
Fig.46 shows the plot of the power plane for the PLL before and after adding the PLL loop noise. In case
of the symmetric power scaling approach, the power of both the reference and the VCO clocks by 3 dB
each (10 log10 (1 + 10β1 /20 ) = 3 dB) and thus the constant jitter line shifts parallel to the line before adding
the loop noise. In case of the asymmetric power scaling approach, the VCO power is kept constant but
the reference power is increased to meet the desired jitter specification. The reference power is increased
by a factor of 6 dB (From Eq.(302) the power increases by 20 log10 (1 + 10β1 /20 ) = 6 dB) and it can be
seen that the constant jitter line shifts right by 6 dB as expected (as only the reference power is changed).

XV. PLL S WITH EXTERNAL REFERENCE SOURCE

In many PLL applications, the reference clock is external and the PLL is on-chip as shown in Fig.47
and a designer does not have much control in optimizing it for noise. The goal then is to find the optimum
jitter and the FOM of the PLL in such cases and arrive at some design guidelines.
Since the reference clock is external, the only design variables that are under the engineer’s control are
 Symmetric Power Scaling Asymmetric Power Scaling
25 25
With Loop Noise With Loop Noise
Without Loop Noise Without Loop Noise

20 20

15 15
Pvco,dBm

Pvco,dBm
10 10

5 5

Jrms = 100 fs Jrms = 100 fs

0
-5 0 5 10 15 20 -5 0 5 10 15 20 25
Pref,dBm Pref,dBm

Fig. 46. Plot showing the variation of the reference and VCO powers on a power plane with asymmetric and symmetric power scaling after the addition of
PLL loop noise

fr Vdd ON CHIP PLL

Icp
ref UP f0
fdiv
div DN Icp
Z(s)
VCO

External DTC N+n[k]

0.f
XO Σ∆ MOD

Fig. 47. Block diagram of the PLL showing the external reference source

the loop noise and the VCO noise. The reference signal quality Qre f can be treated as a constant and the
optimum jitter of the PLL in this case is given by
 

1/4 C0
1/4 C0 Qre f 1/4
Jrms = Qre f T Qvco = Qloop Qvco 1+ (317)
π π Qloop
If the loop noise is much smaller than the reference noise Qloop << Qre f , then the jitter is independent
of the loop noise as the low pass noise is dominated by the reference clock. If the loop noise is much
greater than the reference noise Qloop >> Qre f , the the jitter is independent of the reference noise.

1/4 C0
1/4 C0
Qre f >> Qloop =⇒ Jrms ≈ Qre f Qvco & Qre f << Qloop =⇒ Jrms ≈ Qloop Qvco (318)
π π

A. Design planes
Similar to the conventional design approach, we can arrive at design planes in this case as well. The
design variables in this case are the quality, power and FOM of the PLL loop and the VCO. By rearranging
the expression in Eq.(317), the quality plane equations can be expressed in linear and logarithmic form
as follows    
Qre f πJrms 4
Qvco Qloop 1 + = (319)
Qloop C0
   
Qre f πJrms
10 log10 (Qvco ) + 10 log10 (Qloop ) + 10 log10 1 + = 40 log10 (320)
Qloop C0
Unlike the usual case, the quality plane equations are not fully linear. As Qloop is decreased from a very
high value where Qloop >> Qre f , to achieve the same jitter, Qvco has to increase linearly on the quality
plane as expected. The quality plane equation in Eq.(320) can be approximated to
 
πJrms
10 log10 (Qvco ) + 10 log10 (Qloop ) ≈ 40 log10 (321)
C0
However as Qloop becomes smaller than Qre f , the quality plane equations reduce to
 
πJrms
10 log10 (Qvco ) ≈ 40 log10 − 10 log10 (Qre f ) = 10 log10 (Qvco,max ) (322)
C0
The VCO quality is independent of loop quality as its value is determined by the quality of the reference
clock given by Eq.(322) and shown in Fig.48.(a). This is the maximum value of Qvco permissible to
achieve a given jitter Jrms .
The power plane equations can be derived from Eq.(319), using the relation between the quality, FOM

10log(Qloop) Qloop=Qref fu,min

(0,0)
Pvco,dBm

fu,max Qvco,max Decreasing Jrms

fu,min

Pvcomin,dBm fu,max
Decreasing Jrms

Ploop=Pnom Ploop,dBm
(a) 10log(Qvco) (b)

Fig. 48. Illustrative shapes of the design planes of a PLL with external reference a) quality plane and b) power plane

and power of the blocks as follows

   
C0 4 Ploop
Pvco Ploop = 1+ 10−6 10(FOMloop +FOMvco )/10 (323)
πJrms Pnom
where Pnom is the power required to be spent in the loop filter to ensure that the total input referred noise due
to the PLL loop is equal to that of the reference noise floor. Qloop = Qre f =⇒ Sloop = KL =⇒ Ploop = Pnom .
10FOMloop /10 −3
Pnom = 10 =⇒ Pnom,dBm = FOMloop − 10 log10 (Qre f ) − 30 (324)
Qre f
The power plane equations can also be expressed on a log scale as follows
 
πJrms
Pvco,dBm + Ploop,dBm = −40 log10
C0
  
+10 log10 1 + 10(Ploop,dBm −Pnom,dBm )/10 + FOMloop + FOMvco (325)
Similar to the quality plane equations, the power plane equations are non-linear. The locus of all points
of the VCO and loop powers fall on a non-linear curve instead of a straight line like the conventional
case. For a given loop and VCO FOM, when the loop power is much lower than Pnom , that is the noise
of the reference is much lower than the loop noise 38 Qre f << Qloop =⇒ Ploop << Pnom , the power plane
equations reduce to
 
πJrms
Pvco,dBm + Ploop,dBm = −40 log10 + FOMloop + FOMvco (326)
C0
The locus of the constant jitter points lie on a straight line on the power plane when the loop noise is
much greater than the reference noise. When the loop power is increased to a point where the loop noise
becomes comparable and then lower than the reference noise Ploop >> Pnom . At this point, the VCO power
is not dependent on the loop power and remains constant as shown in Fig.48.(b) and its value is decided
by the rms jitter given by
 
πJrms
Pvco,dBm = −40 log10 + FOMloop + FOMvco − Pnom,dBm (327)
C0
This is the minimum possible value of Pvco to meet the jitter specification. For lower jitter levels, the
minimum VCO power increases as shown in Fig.48.(b) (with a 40 dB increase in VCO power for a decade
decrease in jitter as given by Eq.(327)).

B. Minimum achievable PLL FOM

The next step is to find the FOM of the PLL and ways to minimize it. Using the relation between the
rms jitter and the quality of the loop and the VCO, the FOM of the PLL can be expressed as
     
Jrms 2 PPLL p PPLL Qre f
FOMPLL = 10 log10 = 10 log10 Qloop Qvco + 5 log10 1 + +C (328)
1s 1mW 1mW Qloop
Assuming PPLL = Ploop + Pvco , the FOM can be simplified to
r s !  
FOMloop + FOMvco Ploop Pvco Qre f
FOMPLL = + 10 log10 + + 5 log10 1 + +C (329)
2 Pvco Ploop Qloop
The FOM of the PLL in this case is similar to the conventional case where the reference clock was under
the designer’s control, except for the last term. Assuming the FOM of the loop and VCO are fixed, the
design variables in FOM are the loop power Ploop and the VCO power Pvco . The FOM can be expressed
in terms of the ratio of the loop and VCO power as follows
r s !  
FOMloop + FOMvco Ploop Pvco Ploop Pvco
FOMPLL = + 10 log10 + + 5 log10 1 + · +C (330)
2 Pvco Ploop Pvco Pnom
Let P∆ denote the difference between the loop and VCO powers on a log scale (of ratio of loop and VCO
power Ploop /Pvco on linear scale). P∆ = Ploop,dBm − Pvco,dBm , the PLL FOM can be expressed as
 
FOMloop + FOMvco P∆ 
−P∆ /10
 Pvco P∆ /10
FOMPLL = + + 10 log10 1 + 10 + 5 log10 1 + 10 +C (331)
2 2 Pnom
By sweeping the ratio of the loop and VCO power, the minimum value of the PLL FOM can be obtained.
For large positive values of P∆ >> 0, the FOM reduces to
r 
FOMloop + FOMvco Pvco
FOMPLL ≈ + P∆ + 10 log10 +C (332)
2 Pnom
38 The loop noise is inversely proportional to the loop power. Increasing the loop power decreases the loop noise and vice versa.
For small values of P∆ << 0, the PLL FOM reduces to
FOMloop + FOMvco P∆
FOMPLL ≈ − +C (333)
2 2
Unlike the conventional case, the FOM does not vary symmetrically for large values of |P∆ |. The FOM

FOMPLL

Pvco,dBm
Pvco
Ploop
= 1+ 2PP
loop

nom

-0.5 1
Popt,vco
Min FOM point
FOMPLL,min

P∆,opt 0 P∆ Popt,loop Ploop,dBm

(a) (b)
Fig. 49. Illustrative shapes of a) a FOM vs P∆ graph and b) the optimum power curve for minimum FOM overlaid on the power plane.

of the PLL increases for large (positive) values of P∆ with a slope of +1 and for small (negative) values
of P∆ with a slope -0.5. Since the slope is changing its polarity and the FOM is a continuous function of
P∆ , it should go to zero somewhere in between. If the variation is symmetric, then the minimum value of
the FOM occurs at P∆ = 0. However in the case of external reference source, the minimum value of FOM
occurs at a point away from P∆ as shown illustratively in Fig.49.(a). The exact minimum value of the
PLL FOM can be found by differentiating Eq.(331) w.r.t P∆ and setting it to zero. To achieve minimum
PLL FOM, the power of the loop and the VCO should be chosen such that they satisfy the non-linear
equation given by 39
"  #  
Pnom Ploop 2 Ploop
Pvco = 1+4 − 1 = Ploop 1 + 2 (334)
8 Pnom Pnom
39 Let x denote the ratio of the loop and VCO powers x = P
loop /Pvco and α denote the ratio of the VCO power and the loop power Pnom that corresponds
to the reference noise floor α = Pvco /Pnom . The FOM of the PLL in Eq.(329), we get
r !
FOMloop + FOMvco √ 1
FOMPLL = + 10 log10 x+ + 5 log10 (1 + αx) +C
2 x

The FOM can be further reduced to   

FOMloop + FOMvco √ 1 √
FOMPLL = + 10 log10 x+ √ 1 + αx +C
2 x
The minimum value can be found by differentiating the PLL FOM w.r.t x and setting it equal to zero. To further simplify the problem, the minimum value
of the FOM can be found by finding the minimum value of the function enclosed in the log function in the above equation.
   "r # !
dFOMPLL d √ 1 √ d 1
= 0 =⇒ x+ √ 1 + αx = + α (1 + x) = 0
dx dx x dx x

1  √ 
=⇒ x = −1 ± 1 + 8α
4α
Since x is a ratio of powers, it can only be positive and thus discarding the negative solutions, there is only solution of x that minimizes the PLL FOM.
1 √ 
x= 1 + 8α − 1
4α
By substituting x = Ploop /Pvco and α = Pvco /Pnom in the above equation we get
r  "  #
Ploop Pnom Pvco Pnom Ploop 2
= 1+8 − 1 =⇒ Pvco = 1+4 −1
Pvco 4Pvco Pnom 8 Pnom
The powers of the VCO and the loop also satisfy the power plane equation in Eq.(325) given by
   
C0 4 1 1
Pvco = + 10−6 10(FOMloop +FOMvco )/10 (335)
πJrms Ploop Pnom
By finding the intersection of the nonlinear curve in Eq.(334) and the constant jitter curve on the power
plane in Eq.(335) as shown in Fig.49.(b), the optimum power of the loop Popt,loop and the VCO Popt,vco
that minimizes the PLL FOM can be obtained. The minimum achievable FOM can then be expressed as
follows
 
FOMloop + FOMvco √ 1
FOMPLL = + 10 log10 αmin + √ + 5 log10 (1 + αmin · βmin ) +C (336)
2 αmin
" r #
FOMloop + FOMvco 1
= + 10 log10 (1 + αmin ) + βmin +C (337)
2 αmin
where αmin = Popt,loop /Popt,vco and βmin = Popt,vco /Pnom . A simpler expression for PLL FOM can be derived
for a special case when the reference noise is much lower than the loop noise Qre f << Qloop . That is
the PLL is in the linear region on the power plane. The condition can also be expressed in terms of the
powers as Pnom >> Ploop , Pvco . Substituting this condition in Eq.(334), we get
 
Ploop
Pvco = Ploop 1 + 2 ≈ Ploop (338)
Pnom
This condition is similar to the condition for the minimum FOM in case of integer-N PLLs with on-
chip reference clock (here the loop acts like a reference source as it is the dominant source of noise).
Substituting this condition in Eq.(326, the optimum powers of the loop and VCO at the minimum FOM
condition are given by
FOMloop + FOMvco
Ploop,dBm = Pvco,dBm = − Jrms,dBs +C (339)
2
Since Pnom >> Ploop , Pvco and Pvco ≈ Pvco , we have αmin = Popt,loop /Popt,vco ≈ 1 and βmin = Popt,vco /Pnom ≈
0. Using these values of αmin and βmin in Eq.(337) the minimum achievable FOM in this case reduces to
FOMloop + FOMvco
FOMPLL,min ≈ +C + 3 (340)
2
which is as expected since the PLL is in the linear region of the power plane where the loop and VCO
noise trade similar to that of the reference and VCO powers in conventional Integer-N PLLs with internal
reference clocks as discussed in the previous sections.

C. Power scaling laws

The power scaling laws in this case vary depending on the levels of the reference noise when compared
to the loop noise. If the reference noise level is much lower compared to the loop noise floor (Qre f <<
Qloop ), then the reference noise can be ignored in the optimum jitter and UGB expression and hence even
in the PLL FOM expressions. The PLL is in the linear region on the power plane as shown in Fig.50.
The optimum jitter and the corresponding power jitter relation can be expressed as follows.
C0 1
Jrms = (Qloop Qvco )1/4 =⇒ Ploop Pvco ∝ (341)
π Jrms 4
This region (Qre f << Qloop ) can also be visualized on a power plane where the constant jitter curve is
a straight line with a slope of -1 as shown in Fig.50. In this region, both the symmetric and asymmetric
power scaling laws can be applied just as it was done in the PLLs with on-chip reference clock. In case
 Pvco,dBm
Pvco ∝ 1
(Jrms)2

Pvco ∝ 1
Qref<<Qloop (Jrms)4

Qloop<<Qref
Ploop=Pnom Ploop,dBm
Fig. 50. Power scaling laws in different regions on a Power plane

of asymmetric scaling the power of the loop or the VCO needs to be scaled inversely proportional to
Jrms 4 to achieve low jitter levels.
1 1 1
Ploop Pvco ∝ 4
=⇒ Ploop ∝ 4
or Pvco ∝ (342)
Jrms Jrms Jrms 4
In case of symmetric scaling, both the loop and VCO powers needs to be scaled in the same proportion
and thus both the loop and VCO powers needs to be scaled inversely proportional to Jrms 2 .
1 1 1
Ploop Pvco ∝ 4
=⇒ Ploop ∝ 2
& Pvco ∝ (343)
Jrms Jrms Jrms 2
Symmetric scaling should be the preferred choice as it is more power optimal and also the UGB and the
PLL FOM remains the same even as the powers are varied.
The other case is when the reference noise is much higher than the loop noise (or the loop noise is
much lower compared to the reference noise). This can happen in cases where the FOM of the loop is
much better than the reference source and it takes very little power in the loop to achieve very low noise
levels (examples of such PLLs will be discussed in the Section XVII in more detail). In this case where
Qre f >> Qloop , the VCO power can be expressed as
 
1/4 C0 C0 4 1
Jrms = (Qre f Qvco ) =⇒ Pvco = Qre f 10FOMvco /10 10−3 =⇒ Pvco ∝ (344)
π πJrms Jrms 4
This region where the condition Qre f >> Qloop applies, can be visualized on a power plane as shown in
non-linear part of Fig.50. The constant jitter curve flattens out as it no longer depends on the loop power.
And the VCO power scales inversely with jitter as 1/Jrms 4 .

XVI. FOM AND JITTER IN F RACTIONAL -N PLL S WITHOUT QUANTIZATION NOISE CANCELLATION
The analysis and design guidelines discussed so far concerned with the Integer-N PLLs and Fractional-
N PLLs with quantization noise cancellation. For the sake of completeness, the design considerations for
Fractional-N PLLs without quantization noise cancellation will be discussed in this section. Unlike the
Integer-N case, the design equations are not exact but still they can serve as a guideline to arrive at the
optimal solution.
A. Design equations and planes
In Fractional-N PLLs that do not employ quantization noise cancellation, the Σ − ∆ quantization noise
dominates the total integrated in-band noise contribution. The jitter and the optimum UGB in case of a
Fractional-N PLL are given by
s  1
2KH 2L 1 fr 12KH 2L
Jrms = · & fopt = (345)
fopt 2L − 1 2π f0 2π fr
Using the result KH = Qvco f0 2 , the rms jitter can also written as
 1−1/2L  
2 KH 2L 1 1 Qvco 1−1/2L 2L 1
Jrms = = √ (346)
fr 2L − 1 π f0 2 (12)1/2L fr 2L − 1 π( 12 f )1/L
0
By expressing Qvco in terms of the FOM and the power of the VCO, the above equation can also be
expressed on a log scale as follow

1 √ 
Jrms,dBs = α FOMvco − 10 log10 ( fr ) − Pvco,dBm − 10 log10 (πα) − 10 log10 12 f0 (347)
L
where α = (2L − 1)/2L. Once the frequency planning is completed, the reference and VCO frequencies
are fixed. Thus the only variable that a designer has from the above equation is to vary VCO power for
different jitter values. The VCO power and jitter are related as follows
−Jrms,dBs
Pvco,dBm ∝ =⇒ Pvco ∝ (Jrms )−2/α (348)
α
Since α < 1, the rate which the VCO power increases at a power greater than 2 with decreasing jitter.
Eq.(347) can be visualized graphically as a linear equation between the VCO power and the rms jitter
with a slope of −1/α as shown in Fig.51.(a).
It can be seen from Eq.(347) that the rms jitter is not only dependent on the VCO power (for a given
FOM) but also on the reference frequency. In many cases the reference frequency is decided based on the
available reference clock on the chip. In system-on-chip integrated circuits, the reference clock is shared
by many systems and the PLL designer may not have much freedom to vary the reference frequency.
However in some applications like a standalone PLL chips, the PLL designer may have the freedom
of choosing the desired reference frequency that can be optimized for performance. Thus the reference
frequency can also be treated as a variable. Now the problem of the Fractional-N PLLs is also very
similar to integer-N PLLs (or Fractional-N PLLs with quantization noise cancellation) where the rms jitter
depends on two variables and thus Eq.(347) can be visualized as constant jitter lines on a Pvco − fr plane
as shown in Fig.51.(b). As the reference frequency is increased, the noise contribution from the Σ − ∆
modulator decreases and the VCO power can be decreased to achieve the same jitter. However at some
point, as the reference frequency decreases further, the loop and reference noise starts to dominate the
Σ − ∆ quantization noise. At this point the PLL enters the Integer-N regime where any further increase
in the reference frequency will have not impact on the overall noise and the rules of an Integer-N PLL
apply in this regime. The constant jitter curve flattens out as shown in the figure after than point. The
point where the reference+loop noise dominates the Σ − ∆ modulator quantization noise can computed by
equating the noise powers of the modulator and the reference+loop noise.
In case of integer-N PLLs, the expression for the rms jitter was derived in terms of the reference and the
VCO powers and thus the design equation could be visualized on a power plane (unlike the power and
reference frequency plane in case of Fractional-N PLLs). A similar visualization on a power plane is also
possible for Fractional-N PLLs by realizing that there is a proportional relation between the reference
frequency and the power dissipation of the Σ−∆ modulator (an increase in the reference frequency amounts
to increase in the power dissipation of the Σ − ∆ modulator). The Σ − ∆ modulator is a digital circuit and
 fu,min fu,min
Jrms Jrms

Pvco,dBm

Pvco,dBm

Pvco,dBm
2L-1
α=
2L
Integer-N Integer-N
regime regime
-1
α
Pvcomin,dBm fu,max Pvcomin,dBm fu,max

Jrms,dBs 10log(fr) Pdsm,dBm

(a) (b) (c)

Fig. 51. Constant jitter lines on a power plane for a Fractional-N PLL with no quantization noise cancellation

hence its power dissipation is proportional to the frequency of operation of the block and the power
dissipation of the Σ − ∆ modulator can be expressed as 40
 
Edsm
Pdsm = Edsm fr =⇒ Pdsm,dBm = 10 log10 ( fr ) + 10 log10 (349)
1 mJ
where Edsm is the energy lost or dissipated in the modulator every reference cycle. Similar to the
reference and the VCO clocks, we define the quality of the Σ − ∆ modulator to arrive at the figure-
of-merit (FOM) expression. In case of the VCO, the phase noise was multiplied by f 2 to eliminate
the frequency dependence and then divided by the VCO frequency to compare the clock of different
frequencies. Similarly, to compare different modulator architectures of the same order, we apply similar
operations to arrive at a quality metric that is frequency independent. The quality of a modulator is defined
by
Sφ,Σ−∆ ( f ) 1
Qdsm = 2 2L−2 = 2
(2π)2 (350)
fr Ω 12 f0 fr
where Ω = 2π f / fr . The definition of quality of the modulator here is order independent and noise of the
modulator is approximated to an 2L − 2 order highpass filter with 2L − 2 zeroes at dc 41 . Now that the
quality and the power of the Σ − ∆ modulator are known, the FOM of the modulator can be defined as
   
Pdsm 2π
FOMdsm = 10 log10 Qdsm = 20 log10 √ + Pdsm,dBm − 10 log10 ( fr ) (351)
1 mW 12 f0
Since the power of the DSM is proportional to the reference frequency and the quality of the modulator is
inversely proportional to the reference frequency, the FOM of the Σ − ∆ modulator is independent of the
40 The power dissipation of the Σ − ∆ modulator can be expressed as
1
Pdsm = ndsmC parVsup 2 fr
2
where ndsm is the number of gates switching at the reference frequency and C par is the parasitic capacitance at each node in the Σ − ∆ modulator. C par is
a technology dependent number and its value decreases as one moves to lower technology nodes. ndsm is the average number of gates/flip flops that switch
every reference cycle and is proportional to the order L of the modulator. ndsm ∝ L. And Vsup is the supply voltage of the Σ − ∆ modulator. Thus the power
dissipation of the Σ − ∆ modulator can be expressed as
Pdsm = Edsm fr
where Edsm = 0.5ndsmC parVDD 2 is the energy lost or dissipated per clock cycle and is a constant for given modulator order and technology node. Using the
fact that 1 mW = 1 mJ·1 Hz, the power can also be expressed in dBm units as follows
   
Pdsm Edsm
Pdsm,dBm = 10 log10 = 10 log10 ( fr ) + 10 log10
1 mJ·1 Hz 1 mJ
For given technology and modulator order, a Σ − ∆ architecture with the least number of transitions per cycle or least ndsm will have the least value of Edsm .
As one moves to lower technology nodes, the parasitic capacitors at each node C par will decrease and again leading to lower Edsm .
 2L−2
41 The noise of the modualtor in the analysis is approximated to S 1 2 2π f
Σ−∆ ( f ) = (2π f r ) This is the assumption made in deriving the
12 f0 2 fr fr
optimum jitter expressions for Fractional-N PLLs as well.
reference frequency and also on the order L of the modulator. Rearranging Eq.(351), the relation between
the reference frequency and power can be derived to be
 
2π
10 log10 ( fr ) = 20 log10 √ + Pdsm,dBm − FOMdsm (352)
12 f0
Now that the quality and FOM are defined for the SDM, the design equations for the Fractional-N PLLs
can be derived easily. The quality equation can be derived by substituting the value of fr from Eq.(350)
in Eq.(346) to be
 
1 α√ L−1 √
10 log10 (Qvco ) + 10 log10 (Qdsm ) = Jrms,dBs + 20 log10 ((2π) πα) − 20 log10 ( 12 f0 ) (353)
α L
Similarly substituting Eq.(352) in Eq.(347), the expression for jitter can be rewritten in terms of the VCO
and Σ − ∆ modulator powers as follows
 
α √

 (2π) πα 
Jrms,dBs = α FOMvco + FOMdsm − Pdsm,dBm − Pvco,dBm − 20 log10  √ (L−1)/L  (354)
12 f0
Rearranging the above expression, we can arrive at the power plane equation to be
  
α√
1  (2π) πα 
Pdsm,dBm + Pvco,dBm = − Jrms,dBs + 20 log10  √ (L−1)/L  + FOMvco + FOMdsm (355)
α
12 f0
Eq.(355) can be visualized on a power plane as shown in Fig.51.(c) and unlike the integer-N PLL, the
locus of the constant jitter points on the power plane is not entirely a straight line as the equation suggests.
As the power of the Σ − ∆ modulator increases (with an increase in the reference frequency), ideally the
VCO power can be decreased in the same proportion to achieve the same jitter (the optimum UGB will
be adjusted to ensure that the jitter remains the same). However as the Σ − ∆ modulator power increases
further, at some point the noise of the reference and the loop starts to dominate the in-band noise and the
PLL enters the Integer-N regime as shown in the figure. From that point onward, any increase in Pdsm
will not result in any change in the VCO power as the lowpass noise is no longer dominated by the Σ − ∆
modulator quantization noise and the constant jitter line then starts to flatten out as shown in the figure.

B. Minimum achievable FOM in a Fractional-N PLL

Let PPLL = Pvco + Pdsm denote the total PLL power which is expressed as the sum of the VCO and
Σ − ∆ modulator powers 42 . The FOM of the PLL is given by
 
  α √
Jrms 2 PPLL  (2π) πα 
FOMPLL = 10 log10 = α (FOMvco + FOMdsm ) − 20 log10  √ (L−1)/L 
1 s 1 mW
12 f0
"    #
Pvco 1−α Pdsm α
+(1 − 2α)Pdsm,dBm + 10 log10 + (356)
Pdsm Pvco
The FOM can be expressed in terms of P∆ = Pvco,dBm − Pdsm,dBm as follows
h i
FOMPLL = F1 + (1 − 2α)Pdsm,dBm + (1 − α)P∆ + 10 log10 1 + 10−P∆ /10 (357)
42 The loop power or the power of the reference circuit is assumed to be much smaller compared to the VCO and the Σ − ∆ modulator powers.
 √ √ (L−1)/L
where F1 = α (FOMvco + FOMdsm ) − 20 log10 [(2π)α πα/ 12 f0 ] is a constant for given VCO
FOM and Σ − ∆ modulator order and FOM. It is assumed that Pvco is varied keeping Pdsm,dBm con-
stant (which is a reasonable assumption as the reference frequency and the order of the modulator are
kept constant in the FOM analysis). For large values of |P∆ | the FOM can be approximated as follows
FOMPLL ≈ F1 + (1 − 2α)Pdsm,dBm + (1 − α)P∆ for P∆ >> 0 (358)
FOMPLL ≈ F1 + (1 − 2α)Pdsm,dBm − αP∆ for P∆ << 0 (359)
Since the slope changes its polarity with increasing and decreasing value of P∆ , it must vanish to zero

FOMPLL

Pvco,dBm
2L-1
α=
Pvco=(2L-1)Pdsm

2L
-α 1-α Popt,vco
Min FOM point
FOMPLL,min

0 P∆,opt P∆ Popt,dsm Pdsm,dBm

(a) (b)
Fig. 52. a) Illustrative plot of the FOM vs P∆ graph and b) the optimum point on the power plane

at some point and at that point the FOM of the PLL is minimum as shown in Fig.52.(a). The minimum
FOM is achieved when 43
P∆,opt = 10 log10 (2L − 1) =⇒ Pvco,dBm = 10 log10 (2L − 1) + Pdsm,dBm =⇒ Pvco = (2L − 1)Pdsm (360)
The above result should not be surprising as the noise contribution from the VCO is 2L − 1 times the
quantization noise contributed by the Σ−∆ modulator. It can be readily seen that for a first order modulator
L = 1, the quantization noise of the modulator appears as white noise at the PLL input very similar in
shape of the reference noise floor. The minimum FOM condition reduces to Pvco = Pdsm , which is again
similar to the Integer-N case as expected. The interesting implication of Eq.(360) is that for a given VCO
phase noise, there is an unique reference frequency (or Pdsm ) where the overall FOM of the Fractional-
N PLL is minimized. The optimum values of Pvco and Pdsm can be obtained graphically as shown in
Fig.52.(b) by plotting Eq.(360) on the power plane or it can also be found by substituting Eq.(360) in
Eq.(355)
1
FOMvco + FOMdsm + 10 log10 (2L − 1)
Popt,vco = − Jrms,dBs + F2 + (361)
2α 2
43 The FOM of the PLL is given by " 1−α  α #
Pvco Pdsm
F1 + (1 − 2α)Pdsm,dBm + 10 log10 +
Pdsm Pvco
| {z }
to be minimized

To minimize the FOM, the terms in the right side of the above expression needs to be minimized as they are the only variables in the equation. Let
x = Pvco /Pdsm , then the expression to be minimized reduces to
   
Pvco 1−α Pdsm α 1
Y= + = x1−α + α
Pdsm Pvco x
The minimum value is found by differentiating the above expression w.r.t x and setting it to zero
dY α
= 0 =⇒ x = = 2L − 1 =⇒ P∆ = 10 log10 (2L − 1)
dx 1−α
 1
FOMvco + FOMdsm − 10 log10 (2L − 1)
Popt,dsm = − Jrms,dBs + F2 + (362)
2α 2
 √ 
Since 10 log10 ( fr ) = Pdsm,dBm − FOMdsm + 20 log10 2π/( 12 f0 ) , the optimum reference frequency that
minimizes the overall PLL FOM can be derived as
 
1
FOMvco − FOMdsm − 10 log10 (2L − 1) 2π
10 log10 ( fr,opt ) = − Jrms,dBs + F2 + + 20 log10 √
2α 2 12 f0
√ (363)
α√
where F2 = 20 log10 ((2π) πα) − ((L − 1)/L)·20 log10 ( 12 f0 ). The only remaining PLL specification is
the loop bandwidth at the minimum FOM condition. The optimum UGB can be found by substituting
Eq.(360) in Eq.(345) and then using Eq.(351) to be
 (L−1)/L FOMvco − FOMdsm
fr 1
fopt = ·10 20L · (364)
2π (2L − 1)1/2L
 
L−1 fr FOMvco − FOMdsm 1
=⇒ 10 log10 ( fopt ) = 10 log10 + − 10 log10 (2L − 1) (365)
L 2π 2L 2L
One can quickly verify by substituting L = 1, the expression for the optimum UGB reduces to that of an
integer-N PLL. This is because the SDM noise appears like a white noise floor at the PLL input, very
much in shape like the reference noise floor.
FOMvco − FOMdsm
FOMvco − FOMdsm
fopt = 10 20 or 10 log10 ( fopt ) = (366)
2
The next step is to arrive at the exact expression for the minimum achievable FOM. By substituting
Eq.(362) and Eq.(360) in the FOM expression in Eq.(356), the minimum achievable FOM of the PLL can
be derived to be
q √ 
2L/ 2L − 1
FOMPLL,min = αFOMvco + (1 − α)FOMdsm + (1 − 2α)10 log10 ( fr ) + 20 log10  √  (367)
(2π)1−α πα

Replacing α = (2L − 1)/2L, the minimum achievable FOM of the PLL can be rewritten as follows
 
2L − 1 1 L−1 2L(2π)−1/2L
FOMPLL,min = FOMvco + FOMdsm − 10 log10 ( fr ) + 20 log10  q  (368)
2L 2L L 3
π(2L − 1)
Inference from the analysis: Eq.(368) shows that the FOM of the Fractional-N PLLs depends on the
order L of the modulator and the reference frequency unlike Integer-N PLLs. For a first order Σ − ∆
modulator, L = 1, α = 1/2, it can be easily shown that the minimum PLL FOM reduces to
√ !
FOMvco + FOMdsm 2 FOMvco + FOMdsm
FOMPLL,min = + 20 log10 = − 6.94 (369)
2 π 2
The expression for the FOM reduces to that of an Integer-N PLL when the lowpass and highpass filters
are ideal brick-wall filters 44 . A few quick observations on the FOM. 1) The FOM is independent of
44 The minimum FOM of an integer-N PLL is given by
FOMre f + FOMvco
FOMPLL,min = +C + 3
2
where C = 20 log10 (C0 /π). For an ideal brick-wall filter, the value of C0 = 1 and thus the minimum PLL FOM reduces to
FOMre f + FOMvco
FOMPLL,min = − 6.94
2
the reference frequency and 2) The overall PLL FOM is equally dependent on the VCO and the Σ − ∆
modulator. As explained earlier for the optimum UGB, the FOM expression for first order SDM in Eq.(369)
resembling an Integer-N PLL should sound intuitive 45 .
For any general order the dependence of FOM of the PLL on the SDM order and the reference frequency
can be expressed as
2L − 1 1 L−1
FOMPLL,min ∝ FOMvco + FOMdsm & FOMPLL,min ∝ − 10 log10 ( fr ) (370)
2L 2L L
As the order of the modulator increases, the FOM of the VCO starts to dictate the overall FOM. Another
important point to note is that for a given modulator order L, the minimum PLL FOM improves (decreases)
with increasing reference frequency. For second order modulator L = 2 and α = 3/4, the minimum PLL
FOM reduces to
3 1 1
FOMPLL,min = FOMvco + FOMdsm − 10 log10 ( fr ) − 11.23 (371)
4 4 2
The FOM improves by 3 dB for a four-fold increase in the reference frequency. For a third order modulator
L = 3 and α = 5/6 and the minimum achievable FOM reduces to
5 1 2
FOMPLL,min = FOMvco + FOMdsm − 10 log10 ( fr ) − 13.03 (372)
6 6 3
For a third order modulator the VCO FOM contribution is five times that of the SDM. This result should
again not be surprising as it can be recalled from the noise analysis of Fractional-N PLLs in Section V
that the noise contribution from the VCO is 2L − 1 times the noise contribution from the Σ − ∆ modulator.
Thus to minimize the overall FOM, most of the power burden should be bore by the VCO and thus its
FOM ends up determining the overall FOM.
One should bear in mind the result derived here assumes that the dominant sources of noise in the PLL
are the VCO and the Σ − ∆ modulator. If the reference frequency is very high where the reference+loop
noise dominates the inband noise, then the PLL enters the Integer-N regime and the minimum PLL FOM
is determined by the VCO and the reference FOM as discussed in the previous sections.

C. Power scaling laws in Fractional-N PLLs

Having discussed the power-jitter relations and the minimum achievable FOM, the next step is to study
the power and jitter trade-offs in Fractional-N PLLs. It is often the case with Analog/RF blocks that are
optimized for a desired performance metric be reused for future generations of the design and in such
cases, the problem of interest is how to scale the power of these blocks to meet a different (and often more
tighter) performance specification. That is once a PLL design is optimized a desired jitter level, how does
one scale the same PLL to achieve lower jitter levels. How does the PLL power scale as the desired jitter
levels decrease or what are the power scaling laws that govern Fractional-N PLLs. This section attempts
to answers these questions.
In cases where the reference frequency is already decided based on external factors, the VCO power and
the jitter are related as
−Jrms,dBs 1
Pvco,dBm ∝ =⇒ Pvco ∝ (Jrms )−2/α = for L = 3 (373)
α (Jrms )2.4
For a 3rd order modulator, the power of the VCO is inversely proportional to Jrms 2.4 . That is the power
scales at a rate higher than the integer-N PLLs (2 in case of symmetric power scaling approach).
In cases where the designer has the freedom to choose or vary the reference frequency of the PLL, the
power and jitter relation are given by
Jrms,dBs 1
Pdsm,dBm + Pvco,dBm ∝ − =⇒ Pdsm Pvco ∝ (Jrms )−2/α = for L = 3 (374)
α (Jrms )2.4
45 The quantization noise of the first order Σ − ∆ modulator appears like a white noise floor at the PLL input, very much like the reference noise floor and
hence the minimum PLL FOM should resemble that of an Integer-N PLL
 There are two variable that can be changed to scale the PLL design to achieve lower jitter levels. In

Pvco,dBm fu,min
Pvco ∝ (Jrms)-2/α (Assym) Integer-N
Pvco ∝ (Jrms)-1/α (Symm) regime
2L-1
α= Pvco ∝ (Jrms)-4 (Assym)
2L
Pvco ∝ (Jrms)-2 (Symm)

Pvcomin,dBm
fu,max

Pdsm,dBm
Fig. 53. Power scaling laws in the Fractional-N and the Integer-N regimes shown on a power plane.

a similar manner as it was done for integer-N PLLs, we can define asymmetric and symmetric power
scaling laws in Fractional-N PLLs as well.
Asymmetric power scaling In this approach only one of the two powers is varied and the other is kept
constant, starting from the jitter and power relations in Eq.(355), we can arrive at the asymmetric power
scaling laws as follows
1 1
Pdsm Pvco ∝ (Jrms )−2/α =⇒ Pvco ∝ 2/α
or Pdsm ∝ (375)
(Jrms ) (Jrms )2/α
Since varying the Σ − ∆ modulator power amounts to varying the reference frequency, the asymmetric
power scaling laws can also be expressed in terms of the reference frequency and the VCO power
1 1
Pvco ∝ 2/α
or fr ∝ (376)
(Jrms ) (Jrms )2/α
That is either the reference frequency or the VCO power should be increased by a factor of 102/α to
achieve ten fold reduction in jitter levels.
Symmetric power scaling: In a symmetric power scaling approach, both the VCO and the Σ−∆ modulator
powers are varied in the same proportion to achieve lower jitter. And the power scaling laws can be
expressed as
1 1 1
Pdsm Pvco ∝ (Jrms )−2/α =⇒ Pvco ∝ and P dsm ∝ → f r ∝ (377)
(Jrms )1/α (Jrms )1/α (Jrms )1/α
These scaling laws apply as long as the Fractional-N PLL in the fractional regime as shown in Fig.53.
When the reference frequency is very high where the inband noise is dominated by the reference+loop
noise or the PLL is in the Integer-N regime, then the laws of power scaling that apply to Integer-N PLLs
will be applicable here as well.
 XVII. J ITTER AND FOM OF PLL IN SPECIAL CASES
In some applications, extremely low noise reference sources are available to engineers whose quality
and FOM are much superior to any on-chip VCO. Similarly in some specific applications like jitter
cleaning PLLs, the reference source is much noisier compared to the VCO clock. It is of practical interest
to understand the design equations and guidelines in such special case of ’lopsided’ PLLs, where one of
the two clocks is of much greater quality (lower in noise) compared to other.
The overall rms jitter of the PLL can be expressed in terms of jitter of the VCO and the reference
clocks (ignoring the loop noise) as follows
   
2 2 2 Qre f fu C0 2 Qvco C0 2
Jrms = Jre f + Jvco = + (378)
2 π 2 fu π
In an optimally designed√PLL, the reference clock jitter and the VCO clock jitter at the PLL output are the
same. Jre f = Jvco = Jopt / 2. Even if one of the clocks is of very poor quality (Qre f >> Qvco & Qvco >>
Qre f ), the UGB of the PLL is adjusted such that at the optimum jitter point, the noise contributions from
both the clocks is the same.
 2  2 s
Q f 2
re f opt C0 Qvco C0 Jrms Qvco
Jre f 2 = Jvco 2 = = = & fopt = (379)
2 π 2 fopt π 2 Qre f
In such lopsided PLLs where the noise of the one of the clocks is much higher than the other clock, the
optimum UGB of the PLL is either very high or very low (since it depends on the ratio of the quality of the
two clocks). In some cases the optimum UGB is either much lower or higher than the minimum ( fu,min )
and maximum ( fu,max ) permissible values of the UGB.
Qre f >> Qvco =⇒ fopt << fu,min & Qvco >> Qre f =⇒ fopt >> fu,max (380)
The minimum achievable jitter in such cases will be higher than the theoretical minimum jitter values
Qref fu (C /π)2
Jrms ≈ 0
2
Jrms ≈
Qvco (C /π)2
0
Qvco >> Qref Qref >> Qvco
Jrms 2fu Jrms
Qref fu (C /π)2
Jrms ≈ 0
Qvco (C /π)2
Jrms ≈ Jvco >> Jref 2 Jrms ≈ 0 Qref fu,min
2fu Jrms ≈ (C0/π)2
Qvco (C /π)2 Jvco=Jref 2
Jrms ≈ 0 Jvco=Jref
2fu,max Jrms ≈ Jref >> Jvco

fu,max fopt fu fopt fu,min fu

Fig. 54. Illustrative shapes of the Jitter vs UGB plot for the special cases with lopsided noise Qvco >> Qre f and Qre f >> Qvco

possible as shown graphically in Fig.54. For the PLL to have optimum jitter, the values of ratios of the
quality of the clocks should be within the range of the UGB values.
s
Qvco
fu,min < < fu,max (381)
Qre f
=⇒ 20 log10 ( fu,min ) < 10 log10 (Qvco ) − 10 log10 (Qre f ) < 20 log10 ( fu,max ) (382)
If the ratio of the quality of the two clocks (or the difference between the Q values on a log scale) falls
outside this range, then the minimum achievable value of the jitter will be higher than the theoretical
minimum value of the jitter in Eq.(379).
The other important performance metric of interest in such lopsided PLLs is the minimum achievable
FOM of the PLL. It was discussed earlier that if the reference and the VCO powers are equal (Pre f = Pvco )
then the FOM of the PLL is minimized. The minimum achievable FOM of the PLL and the corresponding
optimum UGB is a strong function of the FOM of the reference and the VCO clocks.
FOMvco − FOMre f
FOMre f + FOMvco
FOMPLL,min ≈ − 5 & fopt = 10 20 (383)
2
Eq.(383) shows that the minimum achievable FOM of the PLL can be improved (decreased) by either
improving the FOM of the reference or the VCO clocks. By having either an ideal noiseless reference
clock (FOMre f = −∞) or an ideal noiseless VCO (FOMvco = −∞) the equation shows that it is possible
to realize an ideal PLL with no jitter. FOMPLL = −∞. At the point of optimum jitter both the reference
and the VCO clocks contribute equally. So if we have one ideal clock with zero jitter, the optimum jitter
is also zero and this is achieved by forcing the other clock jitter to be zero, because at the optimum point
the jitter of the reference and VCO clocks should be equal.
Jvco = 0 ⇐⇒ Jre f = 0 =⇒ Jrms = 0 (384)
To achieve zero jitter or the theoretical minimum PLL FOM at the PLL output (FOMPLL = −∞) with
an ideal reference clock, the jitter from the VCO should also be made zero and this is accomplished by
setting the UGB of the PLL to be infinite to suppress the VCO noise completely Jvco = 0. Similarly if
we have an ideal VCO FOMvco = −∞, then to realize an ideal PLL with zero jitter, the UGB of the PLL
should be zero to completely suppress the reference noise. Both these conditions are not practical as it
is not possible to have an infinite UGB or zero UGB. So the minimum FOM of the PLL in Eq.(383) is
valid only for a range of values of the reference and VCO clock FOMs that ensures that the optimum
UGB is within the practically achievable values.
Using the condition that the PLL bandwidth has an upper and lower limit fu,max and fu,min , we can derive
the range of values of the FOM of the clocks over which the minimum PLL FOM can be achieved. The
optimum UGB of the PLL designed to achieve the minimum FOM is given by
FOMvco − FOMre f
fu,min ≤ fu = 10 20 ≤ fu,max (385)
Since the UGB of the PLL is within the range fu ∈ [ fu,min , fu,max ], we can arrive at the inequality relating

20log(fu,max)
FOMvco+FOMref 5
FOMPLL,min=
2

20log(fu,min)

FOMref (0,0)

FOMvco

Fig. 55. Illustrative figure showing range over which the minimum PLL FOM is valid.

the reference and VCO clock FOM to the maximum and minimum UGB.
20 log10 ( fu,min ) ≤ FOMvco − FOMre f ≤ 20 log10 ( fu,max ) (386)
The difference between the FOMs of the two clocks should be within the range given in Eq.(386) 46 . The
range of values of the reference and VCO clock FOMs over which the minimum PLL FOM is dependent
on both the clock FOMs as given in Eq.(383) can also be visualized on a FOM plane as shown in Fig.55.
The shaded region in the figure shows all the possible range of values of the reference and VCO clock
FOMs where Eq.(383) is valid.
In some PLL applications as discussed earlier in Section IV, either the reference or the VCO FOM is
much lower than the other and the difference between the FOMs of the two clocks will fall out of the
range given in Eq.(386). In such cases the jitter will depend only on one of the two clocks (VCO or the
reference) as the other clock can be treated as ideal and noiseless and the minimum achievable FOM of
the PLL will no longer be given by Eq.(383). In this section, the design equations and the power, FOM
and quality requirements for a given jitter specification are discussed and then the minimum achievable
FOM of the PLL is derived for such special cases.

A. PLL with dominant VCO noise or very low reference noise

In PLLs with much lower reference noise or with much noisier VCOs (like ring oscillator PLLs) the
quality of the VCO clock is much worser (higher) compared to the reference clock . Qvco >> Qre f . The
overall jitter at the PLL output is dominated by the VCO. Examples of such PLLs include the Sub-
sampling PLLs [12] and the Injection locked PLLs [13] with very low reference clock noise levels. The
jitter the PLL output is given by
     
2 2 2 Qre f fu C0 2 Qvco C0 2 Qvco C0 2
Jrms = Jre f + Jvco = + ≈ (387)
2 π 2 fu π 2 fu π
The optimum UGB that minimizes the jitter in the above equation is the maximum possible UGB fu,max .
The minimum jitter is then given by s
Qvco C0
Jrms = (388)
2 fu,max π
The jitter can also be expressed in dBs units as follows
Jrms,dBs = 10 log10 (Qvco ) − 10 log10 ( fu,max ) +C − 3 (389)
where C = 20 log10 (C0 /π). Expressing the quality of the VCO in terms of the VCO FOM and power, we
get
Jrms,dBs = FOMvco − Pvco,dBm − 10 log10 ( fu,max ) +C − 3 (390)
For a given reference frequency fu,max is fixed and that leaves us with only one design variable (quality
or power or FOM of the VCO clock). So unlike the usual case, we will not be dealing with design planes
but rather single variable design equations and lines. The three design equations for Quality, power and
FOM can be derived from Eq.(389) and Eq.(389) to be
10 log10 (Qvco ) = Jrms,dBs + K1 (391)
Pvco,dBm = −Jrms,dBs + FOMvco − K1 (392)
FOMvco = Jrms,dBs + Pvco,dBm + K1 (393)
46 One might wonder why do we deal with reference and VCO clock FOMs in place of clock quality as it was done earlier in Section IX. The expression
p
for the UGB can be expressed in terms of the quality of the clocks as fu = Qvco /Qre f . If one of the clocks is of very high quality, then the optimum UGB
value can be either very high or very low. The minimum and maximum values of the reference and the VCO clock quality Qre f and Qvco were derived in
Section IX from the minimum and maximum values of the UGB. However since the PLL is designed to achieve minimum FOM, the power of the reference
and the VCO clocks are the same and the UGB now depends only on the FOM of the two clocks. Hence in the analysis we dealt with clock FOMs instead
of the quality of the clocks. We can arrive at the same expressions for the range of FOM values starting from the range of the reference and VCO clock
quality as given in Section IX.
where K1 = 10 log10 ( fu,max ) + 3 − C is a constant. On a log scale all the design variables vary linearly
with Jrms,dBs . The FOM of the PLL in this case can be derived to be
 
PPLL
FOMPLL = FOMvco − 10 log10 ( fu,max ) +C − 3 + 10 log10 (394)
Pvco
Since it is assumed that the VCO FOM is much greater than the reference clock, the PLL power will
be dominated by the VCO and it can be assumed that PPLL ≈ Pvco . The FOM expression can be further
reduced to
FOMPLL ≈ FOMvco − 10 log10 ( fu,max ) +C − 3 (395)
For a given VCO FOM, the FOM of the PLL can be improved by increasing the maximum UGB fu,max .
Since the maximum UGB is dependent on the reference frequency of the PLL, increasing the reference
frequency (and hence the UGB) will decrease the VCO noise and improve the PLL FOM. The PLL FOM
can also expressed in terms of the reference frequency
FOMPLL ≈ FOMvco − 10 log10 ( fr ) − 10 log10 (a0 ) +C − 3 (396)
where fu,max = a0 fr and a0 is the ratio of the maximum achievable UGB to the reference frequency
a0 = fu,max / fr and is dependent on the PLL architecture. In Type-II CPPLLs, the maximum UGB is always
less than 0.1 fr and so the value of a0 = 0.1 and in case of injection locked PLLs or Injection locked
clock multipliers (ILCM) the maximum UGB [13] can be increased to 0.4 fr and the value of a0 = 0.4 and
in case of Type-I PLLs the maximum UGB [14] can be as high as 0.5 fr and so the maximum value of
a0 is 0.5.
Furthermore PLLs with very low noise reference sources needs to have low loop noise (so that the loop
noise does not submerge the reference noise) to achieve good jitter performance. In such cases, Sub-
sampling PLLs and Injection locked PLLs are more commonly used as both these PLLs have very good
loop FOM (very low loop noise). While there is no loop noise in Injection locked PLLs 47 , the loop noise
is suppressed by the high phase detector gain in case of the SSPLLs.
The minimum achievable FOM of the different PLLs architectures can be computed and compared
p based
on the maximum achievable bandwidth as follows. Using the minimum value of C0 = π/2, we can
arrive at the theoretical minimum achievable values of the FOM of the PLLs with low reference noise to
be
FOMPLL,min ≈ FOMvco − 10 log10 ( fr ) − 10 log10 (a0 ) − 11 (397)
Now since the value of a0 is dependent on the PLL architecture, the minimum achievable values of
FOM for the Type-I SSPLL, ILCM and a Type-II SSPLL 48 with very low reference noise levels can be
expressed as
FOMSSPLL,type1 ≈ FOMvco − 10 log10 ( fr ) − 8 (398)
FOMILCM ≈ FOMvco − 10 log10 ( fr ) − 7 (399)
FOMSSPLL,type2 ≈ FOMvco − 10 log10 ( fr ) − 1 (400)
Based on the expressions of the FOM of the PLLs, one can order the FOMs of the different PLLs with
low reference noise as follows
FOMSSPLL,type1 < FOMILCM < FOMSSPLL,type2 (401)
Since the FOM and the jitter of the PLL is dependent on the reference frequency 49 , one might wonder
from Eq.(397) and Eq.(402) that if the PLL jitter and hence PLL FOM can be improved indefinitely by
47 Injection locked PLLs do not need a loop once the frequency locking is achieved. They are driven systems which maintain frequency stability by the
external perturbation frequency.
48 Only SSPLLs were considered for comparison as they have very low loop noise and hence can be compared to the Injection locked PLLs.
49 A higher reference frequency translates to a higher bandwidth and thus better suppression of the VCO noise.
increasing the reference frequency. The rms jitter in dBs units and the minimum achievable PLL FOM in
Eq.(402) and Eq.(397) can be expressed in terms of the reference frequency as follows
Jrms,dBs = b0 − Pvco,dBm − 10 log10 ( fr ) & FOMPLL,min ≈ b0 − 10 log10 ( fr ) (402)
where b0 = FOMvco − 10 log10 (a0 ) − 11 is a constant. Assuming that the PLL power is still dominated

10log10(fr) 10log10(fr)

Jrms ∝ 1/ √fr

FOMvco+FOMref Jref,dBs Jrms ≈ Jref

≈ 5
2

FOMPLL,min Jrms,dBs

Fig. 56. Illustrative figure showing the variation of the minimum achievable FOM and jitter of the PLL with varying reference frequency

by the VCO noise, the jitter and FOM of the PLL improves (decreases) with√increasing reference fre-
quency (linearly with 10 log10 ( fr ) on a log scale or exponentially Jrms ∝ 1/ fr on a linear scale) as
shown in Fig.56. But at some point where the noise contribution of the VCO becomes comparable to
the reference noise, then the reference noise comes into the picture and the minimum achievable FOM
of the PLL saturates at the minimum FOM value of the conventional PLL as shown in the figure 50 . The
jitter on the other hand will be dominated by the reference source completely as the VCO noise is fully
eliminated by the high PLL UGB.
FOMvco + FOMre f
FOMPLL,min ≈ FOMvco − 10 log10 ( fr ) − 10 log10 (a0 ) − 11 → −5 (403)
2
Jrms,dBs = FOMvco − 10 log10 (a0 ) − Pvco,dBm − 10 log10 ( fr ) − 11 → Jre f ,dBs (404)
Another FOM is often used to characterize the PLL in these special cases to arrive at a measure of ’how
good’ the PLL design is irrespective of the reference frequency. The jitter-power-reference FOM [13] or
FOMPLL,re f . The conventional FOM of the PLL is multiplied by the reference frequency to eliminate the
reference frequency dependence.
 
Jrms 2 PPLL fr
FOMPLL,re f = 10 log10 · · (405)
(1 s)2 1 mW frx
where frx is the nominal reference frequency and fr / frx is the normalized reference frequency. The choice
of frx is arbitrary and and does not affect values of the FOM as it is a constant even if the reference
frequency is changing. Assuming PPLL ≈ Pvco , Eq.(405) can be reduced to
 
fr
FOMPLL,re f ≈ FOMvco − 10 log10 ( fr ) − 10 log10 (a0 ) +C − 3 + 10 log10 (406)
frx
50 The total power dissipation in the PLL includes the power in the reference clock and also the power in the VCO and the PLL loop. In case of Injection
lock PLLs, there is no loop and at high reference frequency values, the VCO noise is fully suppressed and the VCO power can be lowered since the reference
frequency is large enough to suppress high noise levels from the VCO. Then the noise of the PLL will be due to the reference source itself and PLL power
is also much lower than the reference power. That is the PLL then acts like a ’nearly noiseless clock multiplier’. In such cases, the jitter and FOM of the
PLL will be equal to the jitter and FOM of the reference clock itself.
Jrms ≈ Jre f & FOMPLL ≈ FOMre f
This holds true even in case of Sub-sampling PLLs as well. In most practical PLLs however as the VCO noise becomes comparable to the reference noise,
the usual rules of PLL optimization of choosing the right bandwidth to minimize the noise will apply. In such cases the PLL FOM converges to the minimum
PLL FOM shown in Fig.56. Even if PLL is not optimized for low noise and the PLL UGB is kept at its maximum value, the VCO noise is significantly
reduced and one can still argue that the FOM of the PLL will be higher than the theoretical minimum value of the conventional PLL and the rms jitter will
also be higher than the optimum jitter.
FOMvco + FOMre f
FOMPLL > − 5 & Jrms ≈ Jre f > Jopt
2
 =⇒ FOMPLL,re f = FOMvco − 10 log10 (a0 ) +C − 3 − 10 log10 ( frx ) (407)
Assuming frx = 1 Hz, the jitter-power-reference FOM can be expressed as
FOMPLL,re f = FOMvco − 10 log10 (a0 ) +C − 3 (408)
By eliminating the reference frequency dependence, PLLs of different reference frequency inputs can be
compared against each other. FOMPLL,re f depends upon the VCO FOM and the maximum UGB factor
a0 . The constant a0 = fu,max / fr is the ratio of the UGB to reference frequency of the PLL and maximizing
it will lead to a large PLL bandwidth and thus a good suppression of the VCO noise. Thus to minimize
the jitter-power-reference FOM, the UGB of the PLL should be maximized.

B. PLLs with dominant reference noise or low VCO noise

In PLLs with a much worse reference clock compared to the VCO clock like the Jitter cleaning PLLs,
the jitter is mainly determined by the quality and FOM of the reference clock Qre f >> Qvco . The PLL
jitter is given by
     
2 2 2 Qre f fu C0 2 Qvco C0 2 Qre f fu C0 2
Jrms = Jre f + Jvco = + ≈ (409)
2 π 2 fu π 2 π
In such PLLs, the jitter is minimized by choosing the smallest bandwidth possible. Let fu,min denote the
minimum bandwidth of the PLL, then the jitter of the PLL is given by
r
Qre f fu,min C0
Jrms = → Jrms,dBs = 10 log10 (Qre f ) + 10 log10 ( fu,min ) +C − 3 (410)
2 π
For a fixed fu,min , the three design equations for quality, power and FOM in this case can be shown to be


10 log10 Qre f = Jrms,dBs − K2 (411)
Pre f ,dBm = −Jrms,dBs + FOMre f + K2 (412)
FOMre f = Jrms,dBs + Pre f ,dBm − K2 (413)
where K2 = 10 log10 ( fu,min ) + C − 3 is a constant. On a log scale all the design variables vary linearly
with Jrms,dBs .
From Eq.(410), it can be seen that the rms jitter decreases with decreasing UGB.
p
Jrms,dBs ∝ 10 log10 ( fu,min ) =⇒ Jrms ∝ fu,min (414)
As the minimum UGB is reduced further, the jitter from the reference clock is reduced significantly
and at some point the jitter of the reference clock will become comparable to the VCO noise and from
that point onward the usual rules of optimization apply. When the minimum UGB becomes equal to the
optimum UGB, then the jitter of the PLL will equal the optimum jitter of the PLL as shown illustratively
in Fig.57.(a).

1/4 C0
fu,min → fopt =⇒ Jrms → Jopt = Qre f Qvco (415)
π
Any further increase in the UGB will result in an increase in jitter as the VCO noise will start to become
greater than the reference noise as shown in the figure.
The PLL FOM also follows a similar pattern as the rms jitter as the minimum UGB is varied. The PLL
FOM can be expressed in terms of the minimum UGB as follows
 
PPLL
FOMPLL = FOMre f + 10 log10 ( fu,min ) +C − 3 + 10 log10 (416)
Pre f
Since it is assumed that the reference clock FOM is much greater than the VCO FOM, the PLL power
 10log10(fopt) 10log10(fu,min) 10log10(fopt) 10log10(fu,min)
Jrms ∝ √fu,min

Jopt,dBs FOMvco+FOMref
Jrms,min ≈ Jopt ≈ 5
2
Jrms,dBs (a) FOMPLL,min (b)

Fig. 57. Illustrative figure showing the variation of the minimum achievable FOM and jitter of the PLL with UGB

will be dominated by the reference clock and it can be assumed that PPLL ≈ Pre f . The FOM in that cases
reduces to
FOMPLL ≈ FOMre f + 10 log10 ( fu,min ) +C − 3 (417)
The FOM of the PLL is improved by decreasing the minimum UGB fu,min and when the reference noise
becomes comparable to the VCO noise, the VCO noise will start to contribute to the overall noise and
thus the PLL FOM will reach a minimum value of that of the conventional PLL as shown illustratively
in Fig.57.(b)
FOMvco + FOMre f
FOMPLL,min ≈ FOMre f + 10 log10 ( fu,min ) +C − 3 → −5 (418)
2
Any decrease in the UGB after this point will result in the jitter increasing than the optimum value and
thus leads to a degradation in the PLL FOM.

C. Power scaling laws in the PLLs with low reference noise

In case of the conventional PLLs where both the noise (reference and VCO clock) sources were
contributing equally to the PLL output jitter, two power scaling laws called the Asymmetric and Symmetric
power scaling were discussed. But in the special case of PLLs with one of the clocks being ideal (or
noiseless), there is only one design variable (Qvco or Qre f ) and thus we can vary only one of the powers
to achieve low jitter levels. So it is important to understand how the power scales as the desired jitter
levels are decreased and what are the minimum achievable jitter levels in this case.
In PLLs with a low reference noise (as it is more common compared to the other one), the jitter and
power at the PLL output are related as
Jrms,dBs = FOMvco − Pvco,dBm − 10 log10 ( fu,max ) +C − 3 (419)
Assuming that the reference frequency is fixed and the VCO FOM is also fixed, then we arrive at
1
Jrms,dBs = −Pvco,dBm + K3 =⇒ Pvco ∝ (420)
Jrms 2
where K3 = FOMvco − 10 log10 ( fu,max ) + C − 3 is a constant. The power of the VCO has to increase
quadratically with decreasing jitter. Since the product of Pvco Jrms 2 remains the same in this power scaling
approach, the FOM of the PLL remains constant even as the VCO power is varied. As the VCO power is
increased the jitter of the PLL decreases exponentially. Eq.(420) shows that as the power of the VCO is
increased indefinitely the jitter of the PLL tends to zero. Pvco → ∞ =⇒ Jrms → 0. However as the VCO
power is increased, the quality and hence the noise of the VCO is decreased and at some point the noise
contribution of the VCO will become equal to that of the reference source and then become smaller than
the reference noise as the VCO power is increased further. At this point, the jitter at the PLL output is
limited by the reference clock noise.
r
Qre f fu,max C0
Pvco → ∞ =⇒ Qvco → 0 =⇒ Jrms ≈ Jre f = (421)
2 π
As long as the power scaling applies, the VCO power increases at the rate of 20 dB/decade for every

Psat,dBm
Pvco,dBm

Jrms ∝ 1/ √Pvco

Jrms ≈ Jref
Jref,dBs

Jrms,dBs
Fig. 58. Illustrative figure showing the variation of the rms jitter in dBs units Jrms,dBs with the VCO power Pvco,dBm .

decade decrease in the PLL jitter and after the saturation point (Pvco = Psat ), any further increase in the
VCO power does not improve the PLL jitter and the PLL jitter is limited by the reference clock jitter as
shown in Fig.58. The power of the VCO at the saturation point Pvco = Psat can be calculated by equating
the VCO and reference noise levels
Qre f fu,max Qvco 10FOMvco /10 10FOMre f /10
Jre f 2 = Jvco 2 =⇒ = =⇒ = fu,max 2 (422)
2 2 fu,max Psat Pre f
=⇒ Psat,dBm = FOMvco − FOMre f + Pre f ,dBm − 20 log10 ( fu,max ) (423)
If the FOM of the reference clock (or its power dissipation) is not available, then the VCO power can also
be expressed in terms of the reference noise floor and reference frequency by using the result Qre f = KL / fr 2
in Eq.(422).  
fu,max
=⇒ Psat,dBm = FOMvco − 10 log10 (KL ) − 20 log10 (424)
fr
If the quality of the reference clock remains the same with increasing reference frequency, the jitter of
the PLL should increase with increasing UGB as the reference jitter starts to increase following Eq.(421).
However as discussed in Section XIII the reference clock quality decreases with increasing reference
frequency and thus one should expect lower jitter levels even as the reference frequency increases.
A final point to end the discussion on lopsided PLLs. In the analysis throughout this section, the loop
noise was not taken into account as it was assumed that the loop noise was much smaller in comparison
to the reference noise. This assumption holds true in PLLs like SSPLLs and ILPLLs, which are the most
commonly used PLLs in case of very low reference noise. However if the loop noise is taken into account,
the results and analysis presented in Section XV will apply in such PLLs.

XVIII. S UMMARY OF THE DESIGN APPROACH

Since the analysis involves many steps with a fairly large number of design equations, it is only prudent
that all the salient results and design steps be summarized. This chapter dealt with a holistic approach
towards the analysis and design of analog PLLs. The subject discussed in the chapter can be split into
two parts. The first half of the chapter dealt with deriving the results for the optimum jitter and the UGB
in Integer-N and Fractional-N PLLs in terms of the reference and VCO noise levels. The second half of
the chapter dealt with developing a systematic design procedure for low noise PLLs that minimizes the
PLL FOM. The major results and design guidelines in the two parts of the chapter are listed below
A. Optimum jitter and loop dynamics in analog PLLs
1) For a reference clock of noise floor KL and a VCO with a phase noise profile KH / f 2 , there is an
optimum UGB that minimizes the rms jitter. The value of the optimum jitter and the UGB were
derived to be r
(KL KH )1/4 KH
Jopt = √ T ·C0 & fopt = (425)
π N N 2 KL
where C0 is a pconstant dependent on the filter model p used in the analysis. 1) C0 = 1 for brick-wall
C0 = π/2 for a first order filter, 3) C0 = Qπ/2 for second order filter with finite Q and
filter, 2) p
4) C0 = π/(2M sin(π/2M)) for an Mth order Butterworth filter model. p For most analog PLLs, the
value of C0 depends on the PLL phase margin and lies in the range [ π/2, ∞). The optimum UGB
does not depend on the value of C0 for PLLs that are designed to maximize phase margin or the
phase response should be symmetric around the UGB on a log frequency scale.
2) When the PLL design is optimized, the reference and the VCO contribute equally to the overall
noise at the PLL output.
Jopt
Jre f = Jvco = √
2
3) A very useful design metric called as "Quality" was defined to characterize noisy clock signals.
Quality of the clock is a performance metric that enables the designer to compare clocks of different
frequencies and phase noise profiles. For a reference clock of noise floor KL and the VCO clock of
frequency f0 and phase noise KH / f 2 , the quality was defined as
KL KH
Qre f = 2 & Qvco = 2 (426)
fr f0
4) The optimum jitter and the UGB were also expressed in terms of clock quality to gain a more
intuitive understanding of the results.

1/4 s
Qre f Qvco Qvco
Jopt = ·C0 & fopt = (427)
π Qre f
5) In case of Fractional-N PLLs the analysis is not as trivial as it was Integer-N PLLs and several
assumptions were made regarding the lowpass and highpass filter transfer functions and the Σ − ∆
modulator noise profiles. The optimum jitter and UGB in case of Fractional-N PLLs is given by
s  1
2KH 2L 1 fr 12KH 2L
Jopt = · & fopt = (428)
fopt 2L − 1 2π f0 2π fr
6) In an optimized Fractional-N PLL, the VCO noise is the dominant source of noise at the PLL output
for higher order modulators. The jitter contribution from the VCO and the Σ − ∆ modulator are
related to the overall jitter as follows
r r
1 2L − 1
JΣ−∆ = Jopt & Jvco = Jopt
2L 2L
7) It was shown that the optimum jitter decreased almost linearly with increasing reference frequency.

B. Design of low noise analog PLLs

The second half of the chapter deals with laying out a systematic design guideline for PLLs. Some of
the salient steps are listed below
1) The first step is to decide on the frequency planning of the PLL. The reference and output frequencies
are decided in this step. This is decided based on the available options of the crystal oscillator and
the desired output frequency.
2) The design of the PLL then starts with the jitter specification. From the knowledge of the jitter
specification, the specifications can be visualized using the design planes. On a quality plane, one
can obtain the range of values for the quality of the reference and VCO clocks. It is useful to have
both the power plane and the FOM plane as well at this stage to get an idea of the range of values
that needs to be met before a first cut design of the reference and VCO clocks are attempted. For
the power plane, the FOM of the reference and VCO clocks can be assumed to be fixed, the values
of the FOMs can be obtained from a previous generation of the PLLs that were designed by the
engineer or from the research literature. Similarly to obtain the FOM plane, an upper limit on the
power can be decided from a rough estimate of the power budget for the PLL. The three design
equations for the three planes are listed below
  s

πJrms Qvco
10 log10 (Qvco ) + 10 log10 Qre f = 40 log10 & fopt = (429)
C0 Qre f
  r
πJrms Pre f
Pvco,dBm + Pre f ,dBm = −40 log10 + λ0 & fopt = · 10λ1 /20 (430)
C0 Pvco
 
πJrms
FOMvco + FOMre f = 40 log10 + λ2 & fopt = λ3 · 10(FOMvco −FOMre f )/20 (431)
C0
where λ0 = FOMvco + FOMre f andpλ1 = FOMvco − FOMre f are constants in the power plane and
λ2 = Pvco,dBm + Pre f ,dBm and λ3 = Pre f /Pvco are constants in a FOM plane as the powers of the
VCO and reference clocks are fixed.
3) Start with the first cut design of the reference circuit, the VCO and the PLL loop to meet the desired
quality from step one to get an idea about the power consumption. From the design the FOM and
quality of the reference circuit, the PLL loop (FOMre f T ) and the VCO (FOMvco ) can be obtained.
4) Once the FOM values are available, the jitter specification will give the power needed to be spent
in these blocks and also the optimum loop dynamics for the minimum FOM case. To achieve the
minimum FOM the power of the reference+PLL loop should be equal to the power of the VCO
Pre f T = Pvco . A rough estimate of the reference, loop and VCO power and optimum UGB for the
minimum FOM PLL can be obtained from the following equations
 
πJrms FOMvco + FOMre f T
Pre f T,dBm = Pvco,dBm = −20 log10 + (432)
C0 2
FOMvco − FOMre f T
fopt = 10 20 (433)
 
Pre f ,dBm = Pre f T,dBm − 10 log10 1 + 10(FOMloop −FOMre f )/20 (434)
 
Ploop,dBm = Pre f T,dBm − 10 log10 1 + 10(FOMre f −FOMloop )/20 (435)
5) This gives an initial estimate of the PLL power and also the desired FOM and thus the noise levels
for the reference, PLL loop and the VCO circuits. At an architecture level these are the major
specifications of the PLL.
6) The final step at the architecture level is to then find the minimum achievable FOM of the PLL
and compare it with the analytical expression. A good PLL design should be able to achieve the
theoretical FOM in the equation below with a dB or two of margin.
FOMre f + FOMvco  
FOMPLL = − 5 + 10 log10 1 + 10(FOMloop −FOMre f )/20 (436)
2
 The PLL architecture that has the minimum FOMloop will be able to achieve the theoretical minimum
FOM of
FOMre f + FOMvco
FOMPLL,min ≈ −5 (437)
2
Sub-sampling PLLs have much better loop FOM [12] compared to conventional chargepump PLLs
and hence can achieve the better (closer to the theoretical minimum FOM) PLL FOMs compared
to CPPLLs. The design procedure discussed in points 1-6 apply to Integer-N PLLs and Fractional-
N PLLs with quantization noise cancellation. In Fractional-N PLLs it is assumed that the power
dissipated in the Σ − ∆ modulator is much lower than the reference, VCO and the loop power.
7) Power scaling laws in PLLs were then introduced to gain an understanding of the power and jitter
trade-offs in low noise PLLs. Two power scaling laws called the Asymmetric and Symmetric power
scaling were discussed in detail. The powers of the VCO and the reference+loop are related to the
jitter in asymmetric scaling approach (where only one of the two clocks is varied) as
1 1
Pvco ∝ & Pre f ∝
(Jrms )4 (Jrms )4
In case of Symmetric power scaling, the power jitter relations are given by
1 1
Pvco ∝ 2
& Pre f ∝
(Jrms ) (Jrms )2
Symmetric power scaling is the preferred approach to achieve low jitter levels, as it is more power
optimal and the FOM of the PLL remains the same even the powers are varied to achieve low jitter
levels.
8) In PLLs where the reference clock is external and the designer does not have any control over its
power or performance. The quality and power plane are very different and the relations become
non-linear. The design equations are non-linear
   
Qre f πJrms
10 log10 (Qvco ) + 10 log10 (Qloop ) + 10 log10 1 + = 40 log10
Qloop C0
 
πJrms
Pvco,dBm + Ploop,dBm = −40 log10
C0
 
+10 log10 1 + 10(Ploop,dBm −Pnom,dBm )/10 + FOMloop + FOMvco (438)
where Pnom,dBm = FOMloop − 10 log10 (Qre f ) − 30. The condition to achieve minimum PLL FOM is
given by  
Ploop
Pvco = Ploop 1 + 2 (439)
Pnom
To arrive at the optimum VCO and loop powers, the two non-linear equations Eq.(439) and Eq.(438)
needs to be solved either numerically or graphically. For the desired jitter values, if the reference
noise levels are much smaller than the loop noise levels, then the design equations are linear and
the PLL design can be treated like a conventional Integer-N PLL where the loop noise and VCO
noise are the dominant lowpass and highpass noise sources. All the design equations discussed in
points 2-6 in the summary will apply by replacing the reference FOM, quality and power with the
loop FOM, quality and power. Similar power scaling laws apply in this case as well as it was in the
case of PLLs with on chip reference clocks.

9) In Fractional-N PLLs with no quantization noise cancellation, where the noise is dominated by
the highpass quantization noise at the PLL input and the VCO noise at the PLL output, the design
 equations depend on the order and reference frequency of Σ − ∆ modulator. The main power equation
relating the jitter to the VCO and SDM powers is given by
  
α√
1  (2π) πα 
Pdsm,dBm + Pvco,dBm = − Jrms,dBs + 20 log10  √ (L−1)/L  + FOMvco + FOMdsm (440)
α
12 f0
The condition for the minimum achievable FOM in this case is Pvco = (2L − 1)Pdsm . That is the VCO
power should be 2L − 1 times the power of the SDM. Since the power of SDM is proportional to
the reference frequency, the minimum FOM condition also gives rise to another interesting insight.
In Fractional-N PLLs for a given jitter specification, there is a unique VCO power and reference
frequency combination that minimizes the PLL FOM. The minimum achievable PLL FOM is given
by
 
2L − 1 1 L−1 2L(2π)−1/2L
FOMPLL,min = FOMvco + FOMdsm − 10 log10 ( fr ) + 20 log10  q  (441)
2L 2L L 3
π(2L − 1)
The minimum PLL FOM is dependent on the order of the modulator and also on the reference
frequency. For first order modulators, the FOM is independent of the reference frequency but for any
modulator order greater than two, the FOM improves (decreases) with increasing reference frequency.
Also for higher order modulators, the overall FOM is dominated by the VCO FOM (In Integer-N
PLLs the FOM is the average value of the FOMs of the reference and VCO clocks.)
10) In PLLs with lopsided noise levels where either the reference or the VCO clock is much noisier than
the other clock, then the performance of the PLL will depend only on the noisier clock. In case of
PLLs with very low reference noise the FOM of the PLL is determined by the VCO FOM and the
maximum UGB of the PLL
FOMPLL ≈ FOMvco − 10 log10 ( fu,max ) +C − 3 (442)
where C = 20 log10 (C0 /π). PLLs with low reference noise needs to have low loop noise to achieve
low jitter levels and low loop noise PLL architectures such as Sub-sampling PLLs and Injection
locked PLLs are more commonly used in such applications.
11) These results help guide the detailed block by block design of the PLL at every step of the design
phase.

XIX. C ONCLUSION
In this chapter, we discussed a holistic design approach to an analog PLL. In the first half of the
work a general design procedure for a PLL of any Type and order to find the optimum noise for a given
reference and VCO noise levels was discussed. Closed form expressions for the PLL jitter in terms of
the reference and VCO quality were discussed which were in close agreement to the simulated results.
Then a rigorous analysis was carried out to study the impact of the reference and VCO frequencies on
the optimum jitter and loop dynamics. It was shown that an increasing reference frequency lead to lower
jitter levels in both Integer-N and Fractional-N PLLs if the quality of the reference clock is improved
with increasing reference frequency. In case of Fractional-N PLLs the optimum jitter decreases almost
linearly with increasing reference frequency. An increasing output frequency on the other hand was shown
to degrade the jitter performance of the PLL as the quality and FOM of the high frequency VCO decrease
with increasing frequency.
The other half of the work dealt with the problem of arriving at PLL specifications from the jitter
specifications. Starting from the PLL jitter specifications, we derived specifications of the reference and
VCO clocks, which involves relating the PLL jitter and FOM to the FOM and power of the reference
and VCO clocks. Another important design guideline that was discussed is the visualization of the PLL
specifications on a design plane. Three such design planes called the quality plane, power plane and FOM
plane were discussed which help the designer in the initial phase of the design to visually understand
the range of the values of the power and FOM of the blocks in a PLL needed to meet a given jitter
specifications. It was shown that the locus of the power, quality and the FOM of the reference and VCO
clocks lie on a straight line on the design plane. Closed form expressions were derived for the FOM of
the PLL in terms of the FOM of the reference and VCO clocks and then the condition and an expression
for the minimum achievable PLL FOM was also presented. Finally the impact of the PLL loop noise
on the optimum jitter and PLL FOM were discussed in detail. From the analysis it was shown that the
minimum achievable PLL FOM for the special case of loop FOM being equal to the reference clock FOM
is degraded by 3 dB with the addition of the PLL loop noise.
The analysis was then extended to PLLs that employ external reference clock and Fractional-N PLLs
without quantization noise cancellation. Design equations and the guidelines were discussed in detail.
Finally the analysis was carried out for low noise PLLs where the reference noise is much lower compared
to the VCO noise. Such PLLs were referred to as Lopsided PLLs and the deisgn equations and FOM
analysis of such PLLs were carried out. The whole deign approach with all the important design equations
and guidelines were then summarized at the end of the chapter.
As a final concluding remark it should be noted that the derivations for fundamental limits on the PLL
FOM does not include other noise sources, mainly deterministic sources, like spurs and non-linearity.
Both these noise sources will increase the PLL jitter and thus degrade the PLL FOM further. As a design
guideline it should be ensured that these noise sources are much smaller compared to the random noise
sources in the PLL. The results derived still serve as performance bounds that helps the designer understand
how close or far away is their design from the limits.
Once the PLL loop dynamics (the desired UGB and phase margin) is known, the next step of the design
is to arrive at a suitable low noise PLL loop architecture that meets the noise requirements. This step
takes a considerable design time and requires a good understanding of the noise of the PLL loop and the
different PLL loop architectures. The next chapter discusses a detailed analysis and survey of different
PLL loop architectures including all the noise sources and also present some important ideas to minimize
PLL loop noise.

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