CHAPTER 6

INPUT/OUTPUT UNIT
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OUTLINE
 Introduction
 Input/output Modules
 I/O Module Function
 I/O Module Structure

 Input/output Techniques
 Programmed I/O
 I/O Commands
 I/O Instructions

 Interrupt Driven I/O

 Direct Memory Access

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 INTRODUCTION
 I/O modules
 Third key element of a computer system, next to
processor and memory
 Interfaces to a system bus and controls one or more
peripheral devices
 Contains logic/intelligence
 To perform communication function b/n the peripherals and
the bus

 Definition : Peripheral device/ Peripheral

 An external device connected to an I/O module

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 INTRODUCTION…
 Why peripheral devices not connected directly to the system
bus ?

 Reasons
 Wide variety of peripherals with different method of operation
 Impractical to incorporate the necessary logic within the processor to
control a range of devices
 Delivering different amounts of data
 At different speeds
 In different formats
 All slower than CPU and RAM

 Hence, an I/O module is required

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 INTRODUCTION…
 Input/output module has two functions:
 Interface to CPU and Memory via the system bus
 Interface to one or more peripherals via data links

 Generic model of I/O

module

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 INTRODUCTION…
 External devices
 Used to accomplish I/O operations
 Provides a means of exchanging data between
 External environment
 Computer

 Attached to a computer by a link to an I/O module

 The link is used to exchange
 Control, status and data

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 INTRODUCTION…
 External devices broadly classified into three
categories:
 Human readable devices
 Suitable for communicating with the computer user
 E.g., Screen, printer, keyboard

 Machine readable devices

 Suitable for communicating with equipment
 E.g., magnetic disk and tape system

 Communication devices
 Allow the computer to exchange data with a remote device
 E.g., Modem, Network Interface Card (NIC)

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 I/O MODULE FUNCTION
 The major functions performed by I/O module fall into
the following categories
 Control & Timing
 Processor Communication
 Device Communication
 Data Buffering
 Error Detection

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 I/O MODULE STRUCTURE
 A block diagram of an I/O module

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 I/O MODULE STRUCTURE…
 Module connects to the rest of the computer through a set of signal lines –
system bus

 Data transferred to and from the module are buffered in one or more data
registers

 Status information provided through status registers

 Status registers may also function as control registers, to accept detailed control
information from the processor

 Module logic interacts with processor via a set of control signal lines

 Processor uses control signal lines to issue commands to the I/O module
 Some of the control lines may be used by the I/O module, for arbitration and status
signals

 Module must recognize and generate addresses for devices it controls

 The I/O module contains logic specific to the interface with each device that it 10
controls
 INPUT OUTPUT TECHNIQUES
 Three techniques exist for I/O operations:
 Programmed I/O
 The processor issues an I/O command to the I/O module and
waits until the I/O operation is complete
 If the processor is faster than the I/O module, it wastes

processor time
 Interrupt driven I/O
 The processor issues an I/O command, continues to execute
other instructions and is interrupted by the I/O module
when the latter has completed its work
 Direct Memory Access (DMA)
 The I/O module and main memory exchange data directly,
without the processor involvement
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 PROGRAMMED I/O…
 Overview of Programmed I/O
 CPU issues an I/O command to the appropriate I/O module
 I/O module performs the requested operation
 I/O module sets status bits in the I/O status register
 CPU checks status bits periodically
 I/O module does not inform/interrupt CPU directly
 CPU waits for I/O module to complete operation
 Wastes CPU time

 Note that, when the processor encounters an instruction

relating to I/O, it executes that instruction by issuing a
command to I/O module

 Programmed I/O can be explained further, from point of

view of
 I/O commands issued by the processor to the I/O module
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 I/O instructions executed by the processor
 PROGRAMMED I/O…
I/O COMMANDS
 When executing an I/O related instruction, the processor issues
 An address
 Specifying the particular I/O module & external device, and
 An I/O command

 There are four types of I/O commands that an I/O module may
receive, when it is addressed by a processor:
 Control
 Used to activate a peripheral and tell it what to do
 Test
 Used to test various status condition associated with an I/O module and
its peripherals
 Read
 Causes the I/O module to obtain an item of data from the peripheral
and place it in an internal buffer
 The processor can then obtain the data item by requesting that the I/O
module place it on the data bus
 Write
 Causes the I/O module to take an item of data (byte or word) from the 13
data bus and subsequently transmit that data item to the peripheral.
 PROGRAMMED I/O…
I/O INSTRUCTIONS
 With programmed I/O, there is a close correspondence between
 The l/O related instructions that the processor fetches from
memory and
 The I/O commands that the processor issues to an I/O module
to execute the instructions

 Often a simple one-to-one relationship exits as the

instructions are easily mapped into I/O commands

 The form of the instruction depends on the way in which

external devices are addressed

 When the processor, main memory, and I/O share a

common bus, two modes of addressing are possible:
 Memory mapped I/O
 Isolated I/O 14
 PROGRAMMED I/O…
I/O INSTRUCTIONS
 Memory-mapped I/O
 There is a single address space for both memory and I/O
devices
 Disadvantage – uses up valuable memory address space

 I/O module registers treated as memory addresses

 Same machine instructions used to access both memory
and I/O devices
 Advantage – allows for more efficient programming
 Single read line and single write lines needed
 Commonly used
 Isolated I/O
 There is separate address space for both memory and
I/O devices
 Separate memory and I/O select lines needed
 Small number of I/O instructions 15
 Commonly used
 INTERRUPT DRIVEN I/O…
 Interrupt Driven I/O Features
 Overcomes CPU waiting of programmed I/O
 No repeated CPU checking of device
 I/O module interrupts when ready

 Overview of Interrupt Driven I/O

 The CPU issues an I/O command to the I/O module,
and then continue to do some other useful work
 The I/O module will interrupt the processor to
request service when it is ready to exchange data
with the processor
 The processor executes the data transfer and then
resumes its former processing 16
 INTERRUPT DRIVEN I/O…
 Basic Operation (for input)
 CPU issues read command
 I/O module gets data from peripheral while CPU does other
work
 I/O module interrupts CPU
 CPU requests data
 I/O module transfers data

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 INTERRUPT DRIVEN I/O…
 CPU Viewpoint (for input)
 Issue read command
 Do other work
 Check for interrupt at end of each instruction cycle
 If interrupted:
 Save context (registers) of the current program
 Process the interrupt
 Read a data from the I/O module and store it in memory

 I/O module viewpoint (for input)

 I/O module receives read command from the CPU
 I/O module reads data from associated peripheral
 I/O module puts the data in its data registers
 The module signals an interrupt over control line
 The module places the data on the data bus when requested
by the processor
 The module is ready for another I/O operation 18
 INTERRUPT DRIVEN I/O…
 Two design issues arise in implementing
interrupt
 How does the processor determine which device
issued the interrupt ?
 If multiple interrupts have occurred, how does the
processor decide which one to process?

 To identify the interrupting module four

techniques are common:
 Multiple interrupt lines
 Software poll
 Daisy chain
 Bus arbitration 19
 INTERRUPT DRIVEN I/O…
 Multiple interrupt lines
 The most straight forward approach
 Different interrupt line for each module
 Impractical due to no of pins required on the CPU as well as
the number of bus lines needed

 Software poll
 CPU asks each module in turn when an interrupt
occurs by running a generic interrupt service routine
 Once the correct module is identified
 The CPU branches to a device service routine specific to
that device
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 Time consuming, slow
 INTERRUPT DRIVEN I/O…
 Daisy chain /Hardware poll
 All modules share a common interrupt request line
 Interrupt ack line is daisy chained through modules
 Ack signal propagates through a series of I/O modules until
it gets to a requesting module
 The module responsible places (data) vector on bus
 CPU uses vector to identify handler routine

 Bus master
 Module must claim the bus before it can raise
interrupt
 Only one module can raise the line at a time 21
 INTERRUPT DRIVEN I/O…
 Which interrupt to process when multiple
interrupts occur at the same time
 With multiple lines
 Each interrupt line has a priority
 CPU picks the interrupt line with high priority

 With software polling

 The order of polling modules determines their priority
 With daisy chaining
 The order of modules on the daisy chain determines their
priority
 With Bus arbitration
 Only current master can interrupt, current master selection
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 COMPARISON
 Comparison of the three techniques used when a block of
data is read from a peripheral device into a memory

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DIRECT MEMORY ACCESS…
 The need for Direct Memory Access
 Interrupt driven I/O efficient than programmed I/O
 But both, interrupt driven and programmed I/O,
require active CPU intervention
 Any data transfer traverses a path through the processor
 Both forms of I/O suffer from two inherent drawbacks
 I/O transfer rate is limited by speed of the processor to test
and service a device
 CPU is tied up in managing an I/O transfer

 A no of instructions must be executed for each I/O

transfer

 DMA is the solution

 More efficient technique to move large blocks of data 24
DIRECT MEMORY ACCESS…
 DMA Function
 DMA involves an additional module on the system
bus
 DMA module/controller
 DMA module/ Controller
 Can take over control of the system bus from the processor
 When the processor does not need it OR

 Force the processor to suspend operation temporarily

 Often called cycle stealing, as the DMA module in effect

steals a bus cycle
 Why ? to transfer data to/from memory over the system bus

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DIRECT MEMORY ACCESS…
 Typical DMA Module Diagram

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DIRECT MEMORY ACCESS…
 DMA Operation
 When the processor wants to read/write a block of data. It tells the
DMA controller the following information:
 Whether Read/Write is requested
 Using the read/write control line b/n the processor and the DMA module
 The address of the I/O device involved
 Communicated over data bus

 Starting location in memory to read from or write to

 Communicated over data lines and stored by the DMA in its data register
 Amount of data to be transferred
 Communicated via data lines and stored in the data count register

 CPU carries on with other work

 DMA controller deals with transfer
 DMA controller sends interrupt when finished

 The processor is involved only

 At the beginning
 At end of the transfer
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DIRECT MEMORY ACCESS…
 DMA Transfer Cycle Stealing
 DMA controller takes over bus for a cycle
 Transfer one word of data
 Not an interrupt
 CPU does not switch context

 CPU suspended just before it accesses bus

 i.e. before an operand or data fetch or a data write

 Slows down CPU but not as much as CPU doing

transfer

DMA and Interrupt

Breakpoints During
an Instruction Cycle 28
End of Chapter 6

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