Differences between machine dependent and machine independent code

optimization techniques:
Machine-dependent code optimization is applied to object code. Machine-independent code
optimization is applied to intermediate code. Machine-dependent optimization involves CPU
registers and absolute memory references. Machine-independent code optimization does not
involve CPU registers or absolute memory references.

Machine Independent Code

Machine Dependent Code Optimization Optimization

Machine dependent code optimization refers to Machine independent code

optimizing code specifically for a particular type optimization refers to optimizing code
of computer or hardware platform for use on any type of hardware.

The purpose of machine dependent code The purpose of machine independent

optimization is to take advantage of specific code optimization is to make the code
features or characteristics of a particular hardware as efficient as possible across all
platform. hardware platforms.

Machine independent code

Machine dependent code optimization is limited to
optimization is applicable to any
a specific hardware platform.
hardware platform.

Machine independent code

Machine dependent code optimization may result
optimization produces code that is
in code that is incompatible with other hardware
compatible with all hardware
platforms
platforms

Machine dependent code optimization may make

Machine independent code
it more difficult to port the code to other hardware
optimization makes it easier to port
platforms.Machine-independent code optimization
the code to other platforms.
aims

Machine dependent code optimization may require Machine independent code

more maintenance and updates to keep the code optimization requires fewer updates
optimized for different hardware platforms. and is easier to maintain.
 Machine Independent Code
Machine Dependent Code Optimization Optimization

Machine dependent code optimization may take

Machine independent code
longer to develop, as it requires specialized
optimization can be developed more
knowledge of the hardware platform and may
quickly.
require testing on multiple platforms.

Machine independent code

Machine dependent code optimization may result
optimization may result in more
in better performance on the specific hardware
consistent performance across all
platform.
platforms.

Machine dependent code optimization may require

Machine independent code
more complex code, as it needs to take into
optimization can use simpler, more
account the specific features of the hardware
generic code.
platform.

Machine independent code

Machine dependent code optimization may not be
optimization can be easily reused on
reusable on other hardware platforms.
any platform.

Advantages of machine-dependent code:

 Improved performance

 Greater control

 Reduced portability

 Higher maintenance costs

Advantages of machine-independent code:

 Portability

 Ease of development and maintenance.

 Flexibility and scalability

 Improved security

 Improved performance
Disadvantages of machine-dependent code:

 Lack of portability

 Increased development and maintenance effort

 Limited flexibility and scalability

 Vulnerability to hardware-specific attacks

 Reduced performance

 Machine-dependent

Disadvantages of machine-independent code:

 Complexity

 Reduced performance

 Additional dependencies

 Limited access to low-level hardware features

 Increased debugging effort

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Code Generator:
OR

A Simple code-generation algorithm:

OR
Explain about code generation algorithm and generate code for the following sequence
of three address statements.
t := a – b
u := a – c
v := t + u
d := v + u

Answer:
A code-generation algorithm:

Code generator is used to produce the target code for three-address statements. It uses
registers to store the operands of the three address statement.

A code-generation algorithm uses getreg() function assign registers to variables.

A code-generation algorithm uses two data structures.

1. Register descriptor:
A register descriptor contains the track of what is currently in each register. The register
descriptors show that all the registers are initially empty.
2.Address descriptor:
An address descriptor is used to store the location where current value of the name can
be found at run time. Location may be register, memory address and stack.

The algorithm takes a sequence of three-address statements as input. For each three
address statement of the form x= y op z perform the various actions. Assume L is the
location where the output of y op z to be stored.

These are as follows:

1. Call a function getreg to find out the location L where the result of computation y op z
should be stored.
2. Determine the current location of y by consulting the address descriptor of y. If y is not
presented in the L then generate the instruction MOV y’, L to place a copy of y to L.
3. Generate the instruction OP z' , L where z' is used to show the current location of z.
Update the address descriptor of x to indicate that x is in location L. If x is in L then
update its descriptor and remove x from all other descriptor.
4. If the current value of y or z have no next uses or not live on exit from the block or in
register then alter the register descriptor to indicate that after execution of x : = y op z
those register will no longer contain y or z.

Generating Code for Assignment Statements:

The assignment statement d:= (a-b) + (a-c) + (a-c) can be translated into the following
sequence of three address code:

t:= a-b
u:= a-c
v:= t +u
d:= v+u
Code sequence for the example is as follows:

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Design Issues
In the code generation phase, various issues can arises:

1. Input to the code generator

2. Target program
3. Memory management
4. Instruction selection
 5. Register allocation
6. Evaluation order

1. Input to the code generator

o The input to the code generator contains the intermediate representation of the source
program and the information of the symbol table. The source program is produced by
the front end.
o Intermediate representation has the several choices:
a)Postfix notation
b)Syntax tree
c) Three address code
o We assume front end produces low-level intermediate representation i.e. values of
names in it can directly manipulated by the machine instructions.
o The code generation phase needs complete error-free intermediate code as an input
requires.

2. Target program:
The target program is the output of the code generator. The output can be:

a) Assembly language: It allows subprogram to be separately compiled.

b) Relocatable machine language: It makes the process of code generation easier.

c) Absolute machine language: It can be placed in a fixed location in memory and can
be executed immediately.

3. Memory management
o During code generation process the symbol table entries have to be mapped to actual p
addresses and levels have to be mapped to instruction address.
o Mapping name in the source program to address of data is co-operating done by the
front end and code generator.
o Local variables are stack allocation in the activation record while global variables are in
static area.
4. Instruction selection:
o Nature of instruction set of the target machine should be complete and uniform.
o When you consider the efficiency of target machine then the instruction speed and
machine idioms are important factors.
o The quality of the generated code can be determined by its speed and size.

Example:
The Three address code is:

a:= b + c
d:= a + e

Inefficient assembly code is:

MOV b, R0 R0→b
ADD c, R0 c + R0
MOV R0, a a → R0
MOV a, R0 R0→ a
ADD e, R0 R0 → e + R0
MOV R0, d d → R0

5. Register allocation
Register can be accessed faster than memory. The instructions involving operands in
register are shorter and faster than those involving in memory operand.

The following sub problems arise when we use registers:

Register allocation: In register allocation, we select the set of variables that will reside
in register.

Register assignment: In Register assignment, we pick the register that contains

variable.

Certain machine requires even-odd pairs of registers for some operands and result.

For example:
Consider the following division instruction of the form:

D x, y

Where,

x is the dividend even register in even/odd register pair

y is the divisor

Even register is used to hold the reminder.

Old register is used to hold the quotient.

6. Evaluation order
The efficiency of the target code can be affected by the order in which the computations
are performed. Some computation orders need fewer registers to hold results of
intermediate than others.

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Peephole optimization
Peephole is a small, moving window on the target program.Peephole optimization is a simple
and effective technique for locally improving target code. This technique is applied to improve
the performance of the target program by examining the short sequence of target instructions
(called the peephole) and replace these instructions replacing by shorter or faster sequence
whenever possible.

Peephole Optimization Techniques are:

1. Redundant instruction elimination:

In this technique the redundancy is eliminated.

For e.g.

Initial code:
y = x + 5;
i = y;
z = i;
w = z * 3;

Optimized code:
 y = x + 5;
i = y;
w = y * 3;

2. Constant folding:
The code that can be simplified by user itself, is simplified.
For e.g.
Initial code:
x = 2 * 3;

Optimized code:
x = 6;

3. Strength Reduction:

The operators that consume higher execution time are replaced by the operators consuming
less execution time.

For e.g.

Initial code:
y = x * 2;

Optimized code:
y = x + x;

4. Algebraic Simplification:
Peephole optimization is an effective technique for algebraic simplification. The statements such
as x = x + 0 or x = x * 1 can eliminated by peephole optimization.

5. Machine idioms:
The target instructions have equivalent machine instructions for performing some operations.
Hence we can replace these target instructions by equivalent machine instructions in order to
improve the efficiency.
For e.g., some machine have auto-increment or auto-decrement addressing modes that are used
to perform add or subtract operations.
EX: a=a+1 can be performed by Inc a