Int. J. Mach. Learn. & Cyber.
DOI 10.1007/s13042-014-0324-3
ORIGINAL ARTICLE
Optimal sizing of CMOS analog circuits using gravitational search
algorithm with particle swarm optimization
S. Mallick • R. Kar • D. Mandal • S. P. Ghoshal
Received: 5 September 2014 / Accepted: 24 December 2014
 Springer-Verlag Berlin Heidelberg 2015
Abstract In this paper, a hybrid population based meta-
heuristic search algorithm named as gravitational search
algorithm (GSA) combined with particle swarm optimiza-
tion (PSO) (GSA–PSO) is proposed for the optimal designs
of two commonly used analog circuits, namely, comple-
mentary metal oxide semiconductor (CMOS) differential
amplifier circuit with current mirror load and CMOS two-
stage operational amplifier circuit. PSO and GSA are sim-
ple, population based robust evolutionary algorithms but
have the problem of suboptimality, individually. The pro-
posed GSA–PSO based approach has overcome this dis-
advantage faced by both the PSO and the GSA algorithms
and is employed in this paper for the optimal designs of two
amplifier circuits. The transistors’ sizes are optimized using
GSA–PSO in order to minimize the areas occupied by the
circuits and to improve the design/performance parameters
of the circuits. Various design specifications/performance
parameters are optimized to optimize the transistor’s sizes
and some other design parameters using GSA–PSO. By
using the optimal transistor sizes, Simulation Program with
Integrated Circuit Emphasis simulation has been carried out
in order to show the performance parameters. The simula-
tion results justify the superiority of GSA–PSO over dif-
ferential evolution, harmony search, artificial bee colony
S. Mallick  R. Kar (&)  D. Mandal
Department of Electronics and Communication Engineering,
NIT Durgapur, Durgapur, India
e-mail: rajibkarece@gmail.com
D. Mandal
e-mail: durbadal.bittu@gmail.com
S. P. Ghoshal
Department of Electrical Engineering, NIT Durgapur, Durgapur,
India
e-mail: spghoshalnitdgp@gmail.com
and PSO in terms of convergence speed, design specifica-
tions and performance parameters of the optimal design of
the analog CMOS amplifier circuits. It is shown that GSA–
PSO based design technique for each amplifier circuit yields
the least MOS area, and each designed circuit is shown to
have the best performance parameters like gain, power
dissipation etc., as compared with those of other recently
reported literature. Still the difficulties and challenges faced
in this work are proper tuning of control parameters of the
algorithms GSA and PSO, some conflicting design/perfor-
mance parameters and design specifications, which have
been partially overcome by repeated manual tuning. Multi-
objective optimization may be the proper alternative way to
overcome the above difficulties.
Keywords CMOS  Circuit sizing  Two-stage op-amp 
Differential amplifier  GSA–PSO  Evolutionary
optimization techniques  Low power design
1 Introduction
Analog circuits have a significant role almost in all inte-
grated circuits (ICs). They are extensively used as the
interface between the real world and the digital world
signals. Therefore, the importance of the analog design in
ICs cannot be underestimated. Compared to the digital
design, the analog design has not been automated to a great
extent due to its immense complexity [1]. The automation
of analog circuit design has attracted great attention of the
researchers across the world [2]. Analog circuit sizing is a
very composite, iterative and monotonous and time con-
suming process.
The analog design procedure consists of three major
steps: topology selection, component sizing and layout
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extraction [3]. The expert designers can make the analog
sizing and design process by their perception and experi-
ence [4]. However, when the circuit complexity increases,
the search space increases accordingly and it becomes an
excessive time consuming method for the designers to
obtain the optimal design parameters. In fact, the optimal
design of analog components is a bottleneck in the design
procedure. Automatically optimizing the sizes of the ana-
log components used in the circuits is an important issue
towards the ability to design the high performance circuits
quickly [5, 6]. In CMOS analog IC design method, the
relations among aspect ratios, channel lengths and widths
of MOS transistors ensure that the search space and opti-
mization technique are smooth and reliable. For the auto-
mation of optimal sizing of CMOS analog IC, effective
optimization techniques are essential.
Several classical optimization techniques are employed
for the optimal sizing of CMOS analog IC. Classical
optimization methods are of two types: deterministic
methods and statistical methods. Deterministic techniques
like Simplex method [7], Automatic method [8], Goal
Programming [9], and Dynamic Programming [10] etc., are
applicable for small size optimization problems. Statistical
methods usually start by finding a suitable Direct Current
(DC) operating point which is provided by the proficient
analog designer. After that, a simulation-based method is
employed. However, these statistical methods are also
time-consuming and do not ensure the convergence
towards the global optimum solution [11]. Several draw-
backs of classical optimization methods are:
(i) Highly sensitive to starting points when the
number of solution variables and hence the size
of the solution space increases.
(ii) Frequent convergence to local optimum solution
or divergence or revisiting the same suboptimal
solution.
(iii) Requirement of continuous and differentiable
objective cost function (gradient search methods).
(iv) Requirement of the piecewise linear cost approx-
imation (linear programming).
(v) Problem of convergence and algorithm complex-
ity (nonlinear programming).
Hence, classical optimization methods are mostly not
appropriate for optimal sizing of the total large size analog
IC design process, which is a complicated, highly con-
strained, nonlinear process.
Heuristics based approaches are essential to solve the
large size problems [12]. Some mathematical heuristic
methods were previously used, e.g., local search (LS) [13],
simulated annealing (SA) [14, 15], tabu search (TS) [16,
17], scatter search (SS) [18], genetic algorithms (GA) [19,
20] etc.
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Int. J. Mach. Learn. & Cyber.
Most of the circuit design optimization problems are
formulated with different types of constraints, variables
and objective functions. Therefore, the aforementioned
optimization methods usually require much more time for
the computation when the problems become more com-
plicated and involve a very large search space. In order to
overcome the drawbacks associated with these optimiza-
tion methods, a new set of nature-inspired meta-heuristic
optimization algorithms based on swarm intelligence [21]
is proposed. The idea behind these algorithms is inspired
from the collective behaviour of decentralized, self-orga-
nized systems. Swarm intelligence based systems typically
employ a population of particles interacting locally with
each other and globally with their environment. Although
the particles follow the conventions but there is no cen-
tralized control over the behaviour of each particle. The
complexity of global behaviour arises when the particles
interact with each other. Some of the well accepted opti-
mization techniques are: ant colony optimization (ACO)
[22], particle swarm optimization (PSO) [23–25] and arti-
ficial bee colony (ABC) [26]. PSO is very popular opti-
mization algorithm among researchers because it offers
good performance in several application domains [27].
These optimization techniques are integrated into the
analog computer-aided design (CAD) tools for the topol-
ogy selection as well as for the optimal sizing of complex
ICs and for the actual layout extraction of the circuits [28,
29]. Among the different CAD tools available, OPASYN
[30] and DELIGHT.SPICE [31] employ classical optimi-
zation techniques whereas, IDAC [32], OASYS [33] and
ASLIC [34] are heuristic based system design approaches.
There are different types of methodologies reported for
analog circuit design automation. The first one equation
based method. It is based on the reverse process of circuit
analysis technique. Since circuit sizing is being done
mathematically, due to the simplified device equations and
approximations [34, 35], automation is faster but the
accuracy is compromised. The second one is the simulation
based method, which optimizes a set of performance con-
straints characterized by complex trade-offs and makes a
monotonous use of complete circuit simulator embedded in
the optimization tool. This method usually requires several
iterations to adjust transistor sizes and an optimization tool
needs to evaluate the performance every time. The method
is more accurate but it takes a very long time to complete
the IC design process.
Sizing rules are proposed for CMOS and bipolar ana-
log IC synthesis in [36]. For topology selection and cir-
cuit sizing, a GA based CMOS operational amplifier
synthesizer called DARWIN is proposed [37]. An auto-
mated circuit design system for the evolution and sub-
sequent design of CMOS amplifiers using genetic
programming and current flow analysis has been reported
Int. J. Mach. Learn. & Cyber.
in [38]. Using geometric programming techniques CMOS
op-amp design can be approximated as convex optimi-
zation (CO) problem [39]. An evolution-based approach
called memetic algorithm is developed for automatic
sizing of high performance analog IC design in [40].
Multi-objective evolutionary algorithm (EA) based on
decomposition has been proposed for the optimization of
second-generation current conveyors where HSPICE is
used as a circuit evaluator [41]. For optimal current
conveyors design without circuit evaluator, a multi-
objective heuristic [42, 43] and PSO algorithm [44] are
used. PSO is employed for dynamic reconfiguration of
field-programmable analog circuits [45]. For this purpose,
an op-amp with predefined design constraints has been
designed using PSO, considering different external
parameters like high temperature and fabrication faults.
PSO is also employed for reconfigurable sensor elec-
tronics in [46]. Low-power and low-voltage analog cir-
cuits have been designed using hierarchical particle
swarm optimization (HPSO) [47]. In [48], an automatic
synthesis tool of a cascaded low noise amplifier (LNA) is
developed based on simulated annealing (SA) algorithm
having adaptive tunnelling mechanism and post-optimi-
zation sensitivity analysis with respect to process, design
and temperature, which has been presented in [49]. Most
of the aforementioned heuristic algorithms show the
problems of fixing algorithm’s control parameters, pre-
mature convergence, stagnation and revisiting the same
solution over and again. In [50], detailed investigations
about the application of EA for the synthesis and sizing of
analog ICs are discussed.
Some of the real-life applications of various soft com-
puting techniques in different engineering fields are men-
tioned in [51–60].
The limitations of the conventional PSO are premature
convergence and stagnation problem [61, 62]. In order to
overcome these problems, the authors propose an alterna-
tive superior hybrid optimization technique called GSA–
PSO, which is the combination of gravitational search
algorithm (GSA) [63–66] and PSO for the optimal designs
of CMOS differential amplifier circuit with current mirror
load and CMOS two-stage op-amp circuit. This type of
work is not done widely. So, this is the motivation of the
work.
Some real-life practical applications of evolutionary
optimization techniques are mentioned in [67–71].
Some papers on PSO techniques are mentioned in [72–
74].
The authors have adopted CMOS differential amplifier
with current mirror load and CMOS two-stage operational
amplifier circuit. Besides these two circuits other analog
circuits like CMOS folded cascode operational transcon-
ductance amplifier (FCOTA), CMOS comparator can be
adopted. The authors will also work on the abovemen-
tioned CMOS analog circuits as forthcoming works.
The contribution made in this paper is the optimal sizing
and design of different CMOS amplifier circuits with
higher gain, lower power dissipation and lesser MOS area
compared with those methods reported in the existing lit-
erature. With particular technology parameters, GSA–PSO
algorithm is applied to the design problems. The problem
considered in this work is the optimal CMOS transistors’
sizing, which yields the minimum area of the total design.
As a global optimization technique, GSA–PSO has smaller
number of primitive mathematical operators whereas, in
GA, mathematical operations are required for reproduction,
mutation and crossover and hence, it leads to longer
computation time. The simulation results justify the fact
that the proposed GSA–PSO based amplifier design yields
the least area, higher gain and dissipates the least power,
satisfying the other performance parameters in the best
manner, as compared with the results reported in recent
literature.
The major difficulty and limitation of this work is the
proper tuning of the control parameters for GSA and PSO.
Here, the hybridization has been done between GSA and
PSO to get GSA–PSO technique. Actually the acceleration
term (in 29) of GSA has been incorporated with the
velocity of PSO (in 41).
For GSA–PSO the best weighting factors (determined
by 30 trial runs) were found as: w = 0.01; c1 = c2 = 1.0;
through experimentation, the best results were obtained
with a = 20; the other best parameters of GSA–PSO were:
G0 = 1,000; rNorm = 2; rPower = 1; e = 0.0001;
velocity = zeros (np, D).
After successful execution of the program in MATLAB,
minimum area is achieved in terms of design parameters.
But when the W values and L values are put in Cadence,
some parameters are conflicting with each other. This is
another limitation of this work. For example, when the gain
increases, the phase margin decreases and vice versa. Even
when the value of CL increases, UGB decreases. Then
some manual tuning is needed to get better result in terms
of design specifications and design parameters. In this work
single objective function is considered but the abovemen-
tioned problem can be overcome by using multi-objective
function and multi-objective optimization.
Similar to hybridization of GSA with PSO adopted in
this paper, there may be many other alternatives of
hybridizations like PSO with DE, GSA with DE, Firefly
with DE, GSA with wavelet mutation, PSO with wavelet
mutation, opposition based Bat algorithm etc. The authors
of the paper have tried with all these alternatives for dif-
ferent optimization problems and established the superi-
ority of any such hybrid algorithm over the basic
algorithms on case-to-case basis. In this paper GSA–PSO
123

hybridization has been adopted to show its comparative
superiority over the basic GSA and PSO. To limit the
length of the paper, the authors have not included the
results of all abovementioned hybrid algorithms for the
present problem.
The rest of the paper is organized as follows: In Sect. 2,
design procedures of two different analog IC structures are
discussed and the objective functions are formulated. In
Sect. 3, GSA, PSO and the GSA–PSO algorithms are
briefly discussed and the steps involved in the CMOS
analog IC designs are elaborated. In Sect. 4, comprehen-
sive and demonstrative sets of results are reported and are
validated with SPICE simulator. Finally, Sect. 5 concludes
the paper.
2 Design specifications and objective function
formulation
The design process consists of two types of information:
the design criteria and the design parameters. In this paper,
the optimal design of a CMOS differential amplifier with
current mirror load (Fig. 1) and the optimal design of a
CMOS two-stage operational amplifier (Fig. 2) circuit are
carried out.
For the aforementioned two structures, all the design
specifications considered which may be called as perfor-
mance parameters also are slew rate (SR), small-signal
differential voltage gain (Av), cut-off frequency (f-3dB),
maximum input common mode range (ICMR) (VIC (max)),
minimum ICMR (VIC (min)), unity gain bandwidth (UGB)
and power dissipation (Pdiss), all having certain minimum
and maximum ranges. In addition, the design parameters
considered are as follows: aspect ratio (W/L) values of
different MOS transistors used in the circuits, load capac-
itances (CL) and compensation capacitances (CC). CL and
CC are also performance parameter.
Fig. 1 CMOS differential amplifier with current mirror load
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Int. J. Mach. Learn. & Cyber.
Fig. 2 CMOS two-stage operational amplifier
The design process is implemented with the help of the
relationships that define the specifications. From the rela-
tionships, an objective function or cost function (CF) is
developed to obtain the optimal (W/L) values of all the
MOS transistors used in the circuit and the DC bias cur-
rents in order to minimize the total area occupied by the
MOS transistors as well as the total power dissipations in
the circuits.
2.1 Design criteria for the CMOS differential amplifier
with current mirror load
The performance specifications responsible for the design
of the CMOS differential amplifier with current mirror load
are SR, Av, f-3dB, VIC (max), VIC (min) and Pdiss. The
detailed analysis and relations of different performance
specifications can be found in [75]. The input variables
considered are given as follows:
VDD is the positive power supply (V); VSS is the neg-
ative power supply (V); Vin is the threshold voltage of
NMOS (V); Vip is the threshold voltage of PMOS (V);
VDS is the drain to source voltage of MOSFET (V) and
VGS is the gate to source voltage of MOSFET (V);
Kn0 ¼ ln  Cox , where Kn0 is the transconductance parame-
ter for NMOS (lA/V2); Kp0 ¼ lp  Cox , where Kp0 is the
transconductance parameter for PMOS (lA/V2). ln and lp
are the electron mobility and hole mobility (cm2/Vs),
respectively. Cox is the gate oxide capacitance per unit
area (F/m2). kn and kp are the channel length modulation
parameters for NMOS and PMOS (V-1), respectively. ID
is the drain current of MOSFET. gm is the transconduc-
tance and gds is the output conductance, Rout is the output
resistance of the CMOS differential amplifier considered
in this paper.
The steps involved for the design of the CMOS differ-
ential amplifier circuit with current mirror load are as
follows:
Int. J. Mach. Learn. & Cyber.

• Determine the range of IDS to satisfy SR. • Determine the value of ID5 in order to satisfy SR and
ID5 Pdiss.
SR ¼ ð1Þ
CL ID5 ¼ SR  CC ð12Þ
1 • Determine the transconductance of the input transistors
f3dB ¼ ð2Þ
Rout CL (M1, M2) (refer to Fig. 2) from CC and UGB.
 
• Determine WL11 ¼ WL22 in order to satisfy Av, where gm1 ¼ 2p  UGB  CC ð13Þ
rffiffiffiffiffiffiffiffiffiffiffi
ffi    
W1 W2
gm1 2 Kn0 W1 • Determine the values of L1 and L2 from (14).
Av ¼ gm1 Rout ¼ ¼
gds2 þ gds4 ðkn þ kp Þ ID5 L1
W1 W2 gm1
ð3Þ ¼ ¼ 0 ð14Þ
L1 L2 Kn ID5
     
W3
• Determine L3 ¼ WL44 in order to satisfy the maximum • Estimate WL33 and WL44 from the maximum value of
value of ICMR. ICMR.
VIC ðmaxÞ ¼ VDD  VSG3 þ Vtn1 ð4Þ
W3 W4
W3 2ID5 ¼
¼  2 ð5Þ L3 L4
L3 Kp0 VSG3 þ Vtp ID5
¼
  Kp0 ½VDD  Vin ðmaxÞ  Vtp ðmaxÞ þ Vtn ðminÞ2
• Estimate WL55 ¼ WL66 in order to satisfy the minimum
ð15Þ
value of ICMR.    
W5 W8
VIC ðminÞ ¼ VSS þ VDS5 ðsatÞ þ VGS1 • Estimate L5 and L8 from the minimum value of
¼ VSS þ VDS5 ðsatÞ þ VGS2 ð6Þ ICMR.
W5 2ID5 W5 W8 2I D5
¼ ð7Þ ¼ ¼ ð16Þ
L5 Kn ½VDS5 ðsatÞ2
0
L5 L8 Kn ½VDS5 ðsatÞ2
0

• Determine ID5 to satisfy Pdiss, where where

Pdiss ¼ ID5 ðVDD þ jVSS jÞ ð8Þ s
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
ffi
ID5 L1
VDS5 ðsatÞ ¼ Vin ðminÞ  VSS  Vtn ðmaxÞ 
Kn0 W1
2.2 Design specifications of CMOS two-stage ð17Þ
operational amplifier circuit  
W6
• Estimate L6 from (18).
The performance specifications for the design of CMOS  
two-stage op-amp are Slew rate (SR), DC voltage gain W6 W4 gm6
¼ ð18Þ
(Av), unity gain bandwidth (UGB), Maximum ICMR (VIC L6 L4 gm4
(max)), Minimum ICMR (VIC (min)) and Power dissipa-
where
tion (Pdiss). The design steps carried out for the optimal
design of CMOS two-stage op-amp are as follows [75]: gm6  10gm1 ð19Þ

• Choose the smallest value for CC and place the pole, p2 and
at 2.2 times higher than the unity gain bandwidth qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
gm4 ¼ Kp0 ðW4 =L4 ÞID5 ð20Þ
(UGB). For 60 phase margin it is assumed that right
half plane (RHP) zero, z1 is beyond ten times to that of
• Determine ID6 required for Pdiss.
the UGB.
CC [ 0:22CL ð9Þ ðgm6 Þ2
ID6 ¼ ð21Þ
gm6 2Kp ðW6 =L6 Þ
p2 ¼  ð10Þ
CL  
W7
gm6 • Estimate the value of L7 to achieve the current ratio
z1 ¼ ð11Þ
CC between ID6 and ID5.

123

 
W7 W5 ID6
¼ ð22Þ
L7 L5 ID5
• Estimate the gain and power dissipation as per (23) and
(24), respectively.
2gm2 gm6
Av ¼
ID5  ID6 ðkn þ kp Þ2
Pdiss ¼ ðID5 þ ID6 ÞðVDD þ jVSS jÞ
Initial population matrix size for the GSA–PSO algo-
rithm has been considered as (P 9 Q), where P = 60 and
Q = 7. The row number (P) indicates the number of par-
ticles in the population and column number (Q) indicates
the dimension of each particle vector. The particle vectors
structured for the two CMOS analog circuit structures
considered in this paper are expressed in (25) and (26),
respectively.
Each particle vector is nothing but a row vector, con-
sisting of design specifications/performance parameters as
column elements.
XDiff Amp ¼ ½SR; CL ; Av ; f 3dB ; VIC ðminÞ; VIC ðmaxÞ; Pdiss 
XTwo stage Opamp ¼ ½SR; CL ; Av ; UGB; VIC ðminÞ;
VIC ðmaxÞ; Pdiss 
where SR is the slew rate (V/ls); CL is the output capac-
itance (pF); Av is the DC gain (dB); f-3dB is the cut-off
frequency (KHz); UGB is the unity gain bandwidth (MHz);
Pdiss is the power dissipation (lW); VIC(min) is the lower
value of ICMR (V) and VIC(max) is the upper value of
ICMR (V).
For GSA–PSO, the parameters are taken as follows:
a = 20; G0 = 1,000; rNorm = 2; rPower = 1; e =
0.0001; velocity = zeros (np, D).
The algorithm has been run for an upper limit of 200
iterations. The Cost Function (CF) is defined as the total
area occupied by the MOS transistors, i.e., sum of the
width multiplied by the length of each MOS transistor for
all the MOS transistors of the circuits considered in this
paper. The CF used in this paper is given in (27).
X
N
CF ¼ ðWi  Li Þ
i¼1
where N is the total number of MOS transistors used to
design the circuit. The desired value of CF is intended
to be smaller than 300 lm2 for both the optimally
designed amplifier circuits. CF is to be minimized using
GSA–PSO algorithm to obtain the desired optimal
values.
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Int. J. Mach. Learn. & Cyber.
3 Evolutionary algorithm employed
Evolutionary algorithms are based on the meta-heuristics,
which are characterized as stochastic, adaptive and learn-
ing in order to construct intelligent optimization methods
are adopted in this work. Such methods have the potential
ð23Þ
to become accustomed to their ever-changing dynamic
environment through the previously acquired knowledge.
ð24Þ In this section, GSA, PSO and GSA–PSO optimization
techniques are briefly discussed for the optimal sizing of
the MOS transistors used in the CMOS amplifier circuits as
well as for the minimization of total MOS transistors area
and the total power dissipation of the CMOS amplifier
circuits (Figs. 1, 2).
3.1 Gravitational search algorithm
In GSA [53–56] particles/solution vectors are considered as
objects and their performances are measured by their
masses. All these objects attract each other by gravity
forces, and these forces produce global movements of all
objects towards the objects with heavier masses. Hence,
ð25Þ masses cooperate using a direct form of communication
through gravitational forces. The heavier masses (which
correspond to better solutions) move more slowly than
ð26Þ
lighter ones. This guarantees the exploitation step of the
algorithm.
Three kinds of masses are defined in theoretical physics:
(a) Active gravitational mass (Ma) is a measure of the
strength of the gravitational field due to a particular
object. Gravitational field of an object with small
active gravitational mass is weaker than the object
with more active gravitational mass.
(b) Passive gravitational mass (Mp) is a measure of the
strength of an object’s interaction with the gravita-
tional field. Within the same gravitational field, an
object with a smaller passive gravitational mass
experiences a smaller force than an object with a
larger passive gravitational mass.
(c) Inertial mass (Mt) is a measure of an object’s
resistance to changing its state of motion when a
force is applied. An object with large inertial mass
ð27Þ changes its motion more slowly, and an object with
small inertial mass changes it rapidly.
In GSA, each mass has four specifications: position,
inertial mass, active gravitational mass and passive gravi-
tational mass. The position of the mass corresponds to the
solution of the problem and its gravitational and inertial
masses are determined using a fitness function. In other
words, each mass presents a solution; the algorithm is
Int. J. Mach. Learn. & Cyber.

navigated by properly adjusting gravitational and inertial where randj is a random number in the interval [0, 1].
masses. By lapse of generation cycles, it is expected that Hence, by the law of motion, the acceleration of the ith
masses be attracted by the heaviest mass. This particle/ particle at generation cycle t, and in dth dimension, adi ðtÞ is
vector with the heaviest active gravitational mass will given by (32).
present the optimum solution in the search space.
Fid ðtÞ
GSA considers an isolated system of particles/agents adi ðtÞ ¼ ð32Þ
Mii ðtÞ
with masses. It is like a small artificial world of masses
obeying the Newtonian laws of gravitation and motion. where Mii ðtÞ is the inertial mass of the ith particle vector.
More precisely, masses obey the following two laws: Furthermore, the next velocity of a particle is considered
i. as a fraction of its current velocity added to its acceleration.
Law of gravity: Each particle attracts every other particle Therefore, its velocity and its position could be calculated
and the gravitational force between two particles is by employing (33) and (34), respectively.
directly proportional to the product of their masses and vdi ðt þ 1Þ ¼ randi  vdi ðt þ 1Þ þ adi ðtÞ ð33Þ
inversely proportional to the square of the distance
xdi ðt þ 1Þ ¼ xdi ðtÞ þ vdi ðt þ 1Þ ð34Þ
(R) between them. R is used as RrPower (rPower = 1)
because R offers better results than R2 in all the In (33), is a uniform random variable in [0, 1]. This random
experimental cases with benchmark functions [63]. number is utilized to give a randomized characteristic to
ii. the search.
Law of motion: The current velocity of any particle/ The gravitational constant (G) is initialized at the
vector is equal to the sum of the fraction of its previous beginning and will be reduced with generation cycle to
velocity and the variation in the velocity. Variation in control the search accuracy. In other words, G as a function
the velocity or acceleration of any particle is equal to the of the initial value (G0) and generation cycle (t) is
force acted on the system divided by the mass of inertia. expressed as in (35).
  
Now, let us consider a system with N particles with t
G ¼ G0 exp a  ð35Þ
various masses. The position of the ith particle is defined maxGenCycles
by
Gravitational and inertia masses are simply calculated by the
Xi ¼ ðx1i ; . . .; xdi ; . . .; xni Þ for i ¼ 1; 2; . . .; N ð28Þ cost function (CF) evaluation. A heavier mass means a more
where xdi presents the position of ith particle in the dth efficient particle. This means that better particles have higher
dimension. attractions and walk more slowly. Assuming the equality of
At a specific generation cycle t, the force acting on ith the gravitational and the inertia mass, the values of masses
particle from jth particle is defined by the following are calculated using the map of fitness. Gravitational and
equation: inertial masses are updated by the following equations:
Mai ¼ Mpi ¼ Mii for i ¼ 1; 2; . . .; N ð36Þ
Mpi ðtÞ  Maj ðtÞ  d 
Fijd ðtÞ ¼ G ðtÞ Xj ðtÞ  Xid ðtÞ ð29Þ fiti ðtÞ  worstðtÞ
Rij ðtÞ þ e mi ðtÞ ¼ ð37Þ
bestðtÞ  worstðtÞ
where Maj ðtÞ is the active gravitational mass related to the
jth particle at generation cycle t, Mpi ðtÞ is the passive mi ðtÞ
Mi ðtÞ ¼ PN ð38Þ
gravitational mass related to the jth particle at generation 1 mi ðtÞ
cycle t, GðtÞ is gravitational constant at generation cycle t, where fiti ðtÞ represents the fitness value of the ith particle at
e is a small constant, and Rij ðtÞ is the Euclidian distance
generation cycle t, and worstðtÞ and bestðtÞ are defined in
between the two particles i and j given by (30). (39) and (40), respectively, for our minimization problem.
Rij ðtÞ ¼ Xi ðtÞ; Xj ðtÞ ; rNorm is usually 2 ð30Þ fitj ðtÞ
rNorm bestðtÞ ¼ min ð39Þ
j2f1;...;Ng
To give a stochastic characteristic to the algorithm, it is
fitj ðtÞ
expected that the total force that acts on ith particle in dth worstðtÞ ¼ max ð40Þ
j2f1;...;Ng
dimension be a randomly weighted sum of dth components
of the forces exerted from other particles given by (31). One way to perform a good compromise between explo-
ration and exploitation is to reduce the number of particles
X
N
Fid ðtÞ ¼ randj Fijd ðtÞ ð31Þ with lapse of generation cycles in (31). Hence, it is sup-
j¼1;j6¼i posed that a set of particles with bigger masses apply their

123

forces to the other. However, this policy is to be adopted
carefully because it may reduce the exploration power and
increase the exploitation capability.
In order to avoid trapping into a local optimum, the
algorithm must use the exploration at the beginning. By lapse
of iterations, exploration must fade out and exploitation must
fade in. To improve the performance of GSA by controlling
exploration and exploitation, only the Kbest particles will
attract the others. Kbest is a function of generation cycle with
the initial value K0 and it decreases with generation cycle. In
such a way, all particles apply forces at the beginning, and as
generation cycle progresses, Kbest is decreased linearly. At
the end, there will be just one particle applying force to the
others. Therefore, (31) could be modified as (41).
X until it hits the boundary. Namely, it corresponds to a kind
Fid ðtÞ ¼ randj Fijd ðtÞ ð41Þ
j2Kbest;j6¼i
In (41), Kbest is the set of first K particles with the best
fitness values and the biggest masses.
3.2 Particle swarm optimization (PSO)
PSO is a flexible, robust population-based stochastic
search/optimization technique with implicit parallelism,
which can easily handle with non-differential objective
functions, unlike traditional optimization methods. PSO is
less susceptible to getting trapped on local optima unlike
GA, Simulated Annealing, etc. Eberhart et al. [23, 24]
developed PSO concept similar to the behaviour of a
swarm of birds. PSO is developed through simulation of
bird flocking in multidimensional space. Bird flocking
optimizes a certain objective function. Each particle (bird)
knows its best value so far (pbest). This information cor-
responds to personal experiences of each particle. More-
over, each particle knows the best value so far in the group
(gbest) among pbests. Namely, each particle tries to modify
its position using the following information:
• The distance between the current position and the pbest
• The distance between the current position and the gbest
Similar to GA, in PSO techniques also, real-coded par-
ticle vectors of population np are assumed. Each particle
vector consists of components or sub-strings as required
number of design parameters need to be optimized.
Mathematically, velocities of the particle vectors are
modified according to the following equation:
Vid ðk þ 1Þ ¼ w  Vid ðkÞ þ C1  rand1
 
 pbestid ðkÞ  Xid ðkÞ þ C2  rand2
 
 gbestd ðkÞ  Xid ðkÞ ð42Þ
where Vid ðkÞ is the velocity of ith particle in the dth
dimension at kth iteration; w is the weighting function; C1
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Int. J. Mach. Learn. & Cyber.
and C2 are the positive weighting factors; rand1 and rand2
are the random numbers between 0 and 1; Xid ðkÞ is the
current position of ith particle vector in the dth dimension
at kth iteration; pbestid ðkÞ is the personal best of ith particle
vector in the dth dimension at kth iteration; gbestd ðkÞ is the
group best of the group in the dth dimension at kth itera-
tion. The searching point in the solution space may be
modified by the following equation:
Xid ðk þ 1Þ ¼ Xid ðkÞ þ vdi ðk þ 1Þ ð43Þ
The first term of (42) is the previous velocity of the particle
vector. The second and third terms are used to change the
velocity of the particle. Without the second and third terms,
the particle will keep on ‘‘flying’’ in the same direction
of inertia represented by the inertia constant, w and tries to
explore new areas.
3.3 Gravitational search algorithm hybridized
with particle swarm optimization (GSA–PSO)
In GSA–PSO, the next velocity of the particle vector is
considered as a fraction of its current velocity added to its
weighted acceleration (provided by GSA) and weighted
difference between the social/group best particle vector and
the present position (provided by PSO). It is to be noted
here that the first term and the third term are equivalent to
the inertia term and the social/group best term, respec-
tively, of conventional PSO algorithm. Therefore, its
position and its velocity for the next cycle (t ? 1) are
calculated by employing (44) and (45), respectively.
vdi ðt þ 1Þ ¼ w  vdi ðtÞ þ c1  adi ðtÞ þ c2
 
 gbestd ðtÞ  Xid ðtÞ ð44Þ
where gbestd(t) is the dimension of the social or group best
particle vector corresponding to the best fitness best(t) in
the whole population for the current cycle (t ? 1); The best
weighting factors (determined by 30 trial runs) are found
as: w = 0.01; c1 = c2 = 1.0.
Xid ðt þ 1Þ ¼ Xid ðtÞ þ vdi ðt þ 1Þ ð45Þ
The third factor of the velocity updating expression of
GSA–PSO represents the term involved with social best
position of the particle vector. So, the updated position is
not allowed to move in an apparently uncontrolled way as
given by GSA, rather it is always restricted to follow the
social best position of the current iteration. This is the
reason that GSA–PSO has performed better than GSA and
PSO individually.
The algorithmic steps of GSA–PSO are as follows:
Step 1. Initialization: Population (swarm size) of
particle vectors, np(=60); dimension of
Int. J. Mach. Learn. & Cyber.

optimization problem, D (=7); maximum xj ofi

iteration cycles (=200); maximum and mini- Sfxij  ð46Þ
fi oxj
mum bound for each design parameter. a is a
decrement factor for G. It is required for According to (46), there is one sensitivity for each objec-
reducing the acceleration continuously as tive function f and for each variable in X. Then, it is pos-
generation (iteration) cycle progresses from sible to define the multi-parameter sensitivity which sums
initial stage global search to final stage local the different single sensitivities regarding the different
search, since agents/particles are to be less variables for each objective as follows [77]:
perturbed during final stage local search than sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
Xn
f 2
fj
initial stage global search. Through experi- S ¼ Sxji r2xi ð47Þ
mentation by several trial runs, the best results i¼1
were obtained with a = 20; the other best f
where Sxji is calculated by (46); rxi is a variability param-
parameters of GSA–PSO are: G0 = 1,000;
eter of xi and the square root is used to preserve the same
rNorm = 2; rPower = 1; e = 0.0001; veloc-
units. In this way, the multi-parameter sensitivity for the
ity = zeros (np, D).
cost functions CFDiff Amp (for differential amplifier with
w = 0.01; c1 = c2 = 1.0. All these control
parameters as set have achieved good results current mirror load) and CFTwo stage Opamp (for two-stage
and good convergence. operational amplifier), respectively, can be calculated as:
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
!
Step 2. Generate initial particle vectors of design u 6
u X CF 2 X 6 2
SCFDiff Amp ¼ t
parameters of number D randomly within CF
S Diff Amp r2 þ
Wi Wi S Diff Amp r2
Li Li
limits. i¼1 i¼1
Step 3. Computation of CF values of the total pop- ð48Þ
ulation, nP.
Step 4. Computation of the population based best SCFTwoStageOpamp
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
!ffi
solution particle vector. u 8
u X CF 2 X 8 2
¼t
CF
Step 5. Update G(t), best(t), worst(t) and Mi(t) for S TwoStageOpamp r2 þ
Wi Wi S TwoStageOpamp r2
Li Li
i ¼ 1; 2; . . .; np ; t is current iteration cycle. i¼1 i¼1

Step 6. Calculation of the total forces in different ð49Þ

directions.
Step 7. Calculation of accelerations and velocities of where xi is replaced by variable transistor width parameter
particles. Wi or, variable transistor length parameter Li.
Step 8. Updating particles’ positions.
Step 9. Repeat Steps 3–8 until the stopping criterion 3.5 Various assumptions taken in algorithm portion
(maximum generation cycles) is met. and optimization problem
Step 10. Finally, gbest is the vector of optimal design
parameters (D). 3.5.1 Assumptions taken in the algorithmic portion (GSA)

Each particle attracts every other particle and the gravita-

3.4 Multi-parameter sensitivity analysis
The relative or normalized sensitivity (s) can be defined
as the cause and effect relationship between the circuit
elements’ variations, and the resulting changes in the
performance responses [76, 77]. Furthermore, in the
design of analog ICs, the lowest sensitivity is much
desirable.
Let fi(x) be an objective function (performance
response), where X ¼ ½x1 ; . . .; xn T is the vector of the
design variables. It is possible to relate small changes in the
response of the performance ðofi ; i 2 ½1; mÞ to variations in
 
the design variables oxj ; j 2 ½1; n . It leads to the single
parameter sensitivity definition given by,
tional force between two particles is directly proportional
to the product of their masses and inversely proportional to
the square of the distance (R) between them. Here R is used
as RrPower where rPower = 1 because R1 offers better
results than R2 in all the experimental cases with bench-
mark functions [63]. This is one deviation cum assumption
from the exact Newton’s gravitation law.
Rij(t) is the Euclidian distance between the two particles
i and j given by (30)/(50).
Rij ðtÞ ¼ Xi ðtÞ; Xj ðtÞ ; rNorm is assumed as 2:
rNorm
 This is another assumption: ð50Þ
The gravitational constant (G) is initialized at the
beginning and will be reduced with generation cycle to

123

control the search accuracy. In other words, G as a function
of the initial value (G) and generation cycle (t) is expressed
as in (35)/(51).
  
t
G ¼ G0 exp a  ð51Þ
maxGenCycles
This is another deviation cum assumption from Newton’s
gravitation law, where G is assumed to be constant.
Gravitational and inertia masses are simply calculated
by the cost function (CF) evaluation. A heavier mass
means a much better particle. This means that better par-
ticles have less attraction and move more slowly.
Another assumption taken in this algorithm is the
equality of gravitational and internal masses.
fiti ðtÞ represents the fitness value of the ith particle at
generation cycle t, worstðtÞ and bestðtÞ are defined in (39)/
(52) and (40)/(53), respectively, for our minimization
problem.
bestðtÞ ¼ min fitj ðtÞ
ð52Þ
j2f1;...;Ng
fitj ðtÞ
worstðtÞ ¼ max ð53Þ
j2f1;...;Ng
This is another deviation from Newton’s gravitation law,
where G is assumed to be constant. Gravitational and
inertia masses are simply calculated by the cost function
(CF) evaluation. A heavier mass means a much better
particle. This means that better particles have less attrac-
tion and move more slowly. Another assumption taken in
this algorithm is the equality of gravitational and internal
masses.
One way to perform a good compromise between
exploration and exploitation is to reduce the number of
particles with lapse of generation cycles in (31). Hence, it
is assumed that some particles with bigger masses apply
their forces to the others. However, this policy is to be
adopted carefully because it may reduce the exploration
power and increase the exploitation capability, which may
yield sub-optimal solutions.
3.5.2 Assumptions taken in the algorithmic portion (GSA–
PSO)
In GSA–PSO, the next velocity of the particle vector is
considered as a fraction of its current velocity added to its
weighted acceleration (provided by GSA) and weighted
difference between the social/group best particle vector and
the present position (provided by PSO). It is to be noted
here that the first term and the third term are equivalent to
the inertia term and the social/group best term, respec-
tively, of conventional PSO algorithm.
The third factor of the velocity updating expression of
GSA–PSO, inherited from PSO, represents the term
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Int. J. Mach. Learn. & Cyber.
involved with the social best position of the particle vector.
So, the updated position is not allowed to move in an
apparently uncontrolled way as given by GSA, rather it is
always restricted to follow the social best position of the
current iteration. This is the reason that GSA–PSO has
performed better than GSA and PSO individually.
3.5.3 Assumptions taken for parameter selection
for GSA–PSO
Through experimentation by several trial runs, the best
results were obtained with a = 20; the other best param-
eters of GSA–PSO are: G0 = 1,000; rNorm = 2; rPow-
er = 1; e = 0.0001; velocity = zeros (np, D); w = 0.01;
c1 = c2 = 1.0. The very small value of e (=0.0001) is
chosen to avoid any divide-by-zero condition if two par-
ticles come very near to each other or, fall on each other.
3.5.4 Assumptions taken for the actual design process
of the CMOS analog circuit
The smallest value has been chosen for CC, which places
the pole, p2 at 2.2 times higher than the unity gain band-
width (UGB). For 60 phase margin it is assumed that right
half plane (RHP) zero, z1 is beyond ten times of the UGB.
In order to minimize the channel length modulation
effect, lengths of MOS transistors are chosen as L1 -
= L2 = L3 = L4 = 3.5 lm and L5 = L6 = 1.4 lm for
CMOS differential amplifier with current mirror load and
2 lm for CMOS two-stage operational amplifier circuit.
4 Simulation results and discussions
Extensive MATLAB simulation has been performed for the
optimal design of CMOS differential amplifier circuit with
current mirror load and CMOS two-stage op-amp circuit
(Figs. 1, 2) using the proposed GSA–PSO algorithm. The
results achieved by the GSA–PSO based designs are
compared with those results already reported in the existing
literature like GA [37], CO [39], PSO [78–80], HS [79],
DE [79] and ABC [79]. The values of the input variables
used for this work are given in Table 1.
All optimization programs were run in MATLAB
R2013a version on CPU Intel coreTM i5-2430M
@3.00 GHz processor with 4 GB RAM. Circuit simula-
tions were executed with Cadence version 5 (IC 5.1.41)
with model parameters of Taiwan Semiconductor Manu-
facturing Company (TSMC) 0.35 lm technology for vali-
dation purpose.
The aim of this work is to minimize the total MOS
transistor area, power dissipation and maximizing the gains
of the amplifiers while satisfying performance parameters
Int. J. Mach. Learn. & Cyber.
Table 1 Technology, inputs Inputs, technology, lengths
and lengths considered
Vdd (V)
Vss (V)
Vtp (V)
Vtn (V)
Kn (A/V2)
Kp (A/V2)
Technology
Length (L)i in (lm) (Fig. 1)
Length (L)i in (lm) (Fig. 2)
as design specifications and design parameters. Specifying
the design specifications and design parameters, the opti-
mal circuit sizing is aimed to be determined by the GSA–
PSO algorithm for both the circuit design case studies. The
optimal design problem is formulated as minimization of
Cost Function (CF) given by (24) by composing equations
consisting of design specifications and input variables as
given by (22) or, (23). The task of GSA–PSO is to mini-
mize the CF. Initially the design optimization requires two
types of information. The first one is the technology and
the power supply, which are set by the designer. The sec-
ond one is the design criteria. The range of design
parameters, design specifications, power supply values and
technology information are set as inputs to the GSA–PSO
optimization technique and the optimal solution set is
obtained, which comprises of the optimal values of design
parameters (Wi/Li) where (i = 1, 2, …, 6) for CMOS
differential amplifier with current mirror load and (i = 1,
2, …, 8) for CMOS two-stage op-amp circuit. GSA–PSO
algorithm was run for 100 times to get the best sets of
optimized device parameters and the best results have been
reported in this paper.
During its development, PSPICE has evolved into an
analog mixed signal simulator. The software, now devel-
oped towards more complex industry requirements, is
integrated in the complete systems design flow in ORCAD
and Cadence. It includes features such as analysis of a
circuit with automatic optimization, encryption, a model
editor, and support for parameterized models, auto-con-
vergence and checkpoint restart.
Circuit simulations were executed with Cadence version
5 (IC 5.1.41) with model parameters of Taiwan Semicon-
ductor Manufacturing Company (TSMC) 0.35 lm tech-
nology for validation purpose. The authors have chosen
Cadence for validation of the models but other than
Cadence, TSPICE or PSPICE can also be used for vali-
dation purpose. Compared to TSPICE or PSPICE, Cadence
is much user-friendly and it does not require program for
simulation of the model circuit. Another high end analog
circuit simulator is HSPICE. In Cadence, the circuit has to
Values considered
2.5
-2.5
-0.6513
0.4761
181.2
65.8
0.35 lm
3.5 for i = 1, …, 4 and 1.4 for i = 5, 6
2 for i = 1, 2, …, 8
be drawn and then simulation has to be performed to val-
idate the design specifications/performance parameters.
This section provides the simulation results obtained for
the GSA–PSO based amplifier designs along with the
comparative results reported in different recent literature.
4.1 Simulation results for CMOS differential amplifier
with current mirror load
The proposed GSA–PSO is employed for the optimal
design of a CMOS differential amplifier with current mir-
ror load having inputs, design specifications and design
parameters are shown in Tables 1 and 2. In order to min-
imize the channel length modulation effect, lengths of
MOS transistors are chosen as L1 = L2 = L3 = -
L4 = 3.5 lm and L5 = L6 = 1.4 lm as shown in Table 1.
The desired value of CF is targeted to be smaller than
300 lm2. The simulation results show that by using GSA–
PSO, the least total MOS transistor area of 238.28 lm2
with the exact values of design specifications and design
parameters (Wn, Wp, Ibias and CL) are obtained in 1.0293 s.
CMOS differential amplifier circuit with current mir-
ror load is practically redesigned by using the optimal
design parameters (shown in the last column of Table 4)
obtained by employing GSA–PSO algorithm in SPICE
simulator to validate the fact that GSA–PSO based
design is satisfying the desired specifications. The
SPICE simulation results obtained from the optimally
designed CMOS differential amplifier with current mir-
ror load are shown in Figs. 3, 4, 5, 6, 7, 8, 9, 10,
respectively. SPICE simulation results justify that the
proposed GSA–PSO based differential amplifier circuit
design not only satisfies all design specifications and
design parameters but also minimizes the total area
occupied by the MOS transistors in comparison with GA
[37], PSO [78], HS [79], DE [79] and ABC [79]. The
comparison summary is shown in Tables 3. The values
of the optimal design parameters achieved by using
GSA–PSO as well as those values reported in existing
literature are given in Table 4.
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 Int. J. Mach. Learn. & Cyber.

Table 2 Constraints of the Outputs Ranges considered

proposed GSA–PSO based
analog circuit design method CMOS differential amplifier CMOS two-stage
with current mirror load operational amplifier

SR (V/ls) C10 C10

Av (V/V) [100 [1,000
CL in (pF) C4 C7
CC in (pF) Not required C2.5
UGB in (MHz) Not required C3
f-3dB (cut-off) in (KHz) C100 Not required
Aspect ratio (Wi/Li) 100 C (Wi/Li) C 3 100 C (Wi/Li) C 2
ICMR in (V) -1.5 B ICMR B 2 -1.5 B ICMR B 2
Pdiss (lW) B2,000 B2,500

Fig. 3 Plots of gain and phase

of the proposed GSA–PSO
based CMOS differential
amplifier circuit with current
mirror load

Fig. 4 Plot of slew rate of the

proposed GSA–PSO based
CMOS differential amplifier
circuit with current mirror load

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Int. J. Mach. Learn. & Cyber.

Fig. 5 Plot of positive PSRR of

the proposed GSA–PSO based
CMOS differential amplifier
circuit with current mirror load

Fig. 6 Plot of negative PSRR

of the proposed GSA–PSO
based CMOS differential
amplifier circuit with current
mirror load

Fig. 7 Plot of CMRR of the

proposed GSA–PSO based
CMOS differential amplifier
circuit with current mirror load

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 Int. J. Mach. Learn. & Cyber.

Fig. 8 Plots of ICMR along

with ID5 and (VGS - Vtn) of the
proposed GSA–PSO based
CMOS differential amplifier
circuit with current mirror load

Fig. 9 Plot of power

dissipation of the proposed
GSA–PSO based CMOS
differential amplifier circuit
with current mirror load

Fig. 10 Plot of propagation

delay of the proposed GSA–
PSO based CMOS differential
amplifier circuit with current
mirror load

123
Int. J. Mach. Learn. & Cyber.
Figure 3 shows the plots of gain and phase, Fig. 4 shows
the plot of slew rate, Fig. 5 shows the plot positive Power
Supply Rejection Ratio (PSRR?), Fig. 6 shows the plot of
negative Power Supply Rejection Ratio (PSRR-), Fig. 7
shows the plot of Common Mode Rejection Ratio
(CMRR), Fig. 8 shows the plot of power dissipation, Fig. 9
shows the plots of minimum and maximum Input Common
Mode Range (ICMR) along with ID5, VDS1 and (VGS1 -
Vin). Figure 10 shows the plot of propagation delay.
Vural et al. [78, 79] employed PSO, HS, DE and ABC
techniques to design the same circuit considered in this
paper. The results reported in [78] show that the small
signal differential voltage gain Av of 42 dB, CMRR of
84.2 dB, PSRR? of 40.1 dB, PSRR- of 68 dB, power
dissipation of 1,260 lW and total MOS area of 296 lm2
have been achieved using PSO algorithm. In this paper, the
proposed GSA–PSO based design is shown to have all
higher Av, CMRR, PSRR?, PSRR- and the least total
MOS area as 44.52, 93.23, 48, 110.4 dB and 238.28 lm2,
respectively. All the design specifications are shown in
Figs. 3, 4, 5, 6, 7, 8, 9, 10 and Table 3. The optimal design
parameters achieved by using GSA–PSO algorithm for the
design of CMOS differential amplifier circuit with current
mirror load are shown in Table 4. Power dissipation across
the transistors present in the circuit under consideration is
the grand least (=511.6 lW) as compared with those of
other recent works [78, 79], except [37].
So, from Figs. 3, 4, 5, 6, 7, 8, 9, and 10 and Tables 3 and
4, it can be noted that the proposed GSA–PSO based
CMOS differential amplifier design technique is shown to
have the least MOS area, much superior improved gain,
power supply rejection ratio, common mode rejection ratio
and total power dissipation as compared with those results
reported in the recent literature [37, 78, 79]. So, GSA–PSO
optimizes the best optimizer for this optimal design.
4.2 Simulation results for two-stage operational
amplifier
GSA–PSO is also utilized for the optimal design of CMOS
two-stage op-amp having inputs, design specifications and
design parameters are all shown in Tables 1 and 2. In order
to minimize the effect of the channel length modulation,
the length of each MOS transistor is chosen as 2 lm [75].
The target value of CF is set to be smaller than 300 lm2.
The proposed GSA–PSO based optimal design of two-
stage op-amp results in the least total MOS transistor area
of 109.6 lm2 along with the exact values of the design
specifications and the optimizing design parameters (Wn,
Wp, Ibias, CC and CL). The design steps are completed after
a total execution time of 0.5966 s. CMOS two-stage op-
amp is redesigned using the optimal transistor sizes
achieved by using GSA–PSO in SPICE simulator in order
to validate the fact that the GSA–PSO based design meets
the design specifications.
Figure 11 shows the plots of gain and phase, Fig. 12
shows the plot slew rate, Fig. 13 shows the plot of PSRR?,
Fig. 14 shows the plot of PSRR-, Fig. 15 shows the plot of
CMRR, Fig. 16 shows the plots of maximum and the
minimum ICMR along with ID5, VDS1 and (VGS1 - Vin),
Fig. 17 shows the plot of power dissipation, Fig. 18 shows
the plot of propagation delay.
Vural et al. [78, 80] employed PSO algorithm for the
optimal design of two-stage op-amp circuit and the said
design is reported to have unity gain bandwidth (UGB)
of 5.32 MHz, DC voltage gain Av of 63.8 dB, CMRR of
83.74 dB, PSRR? of 78.27 dB PSRR- of 93.56 dB,
power dissipation of 2,370 lW and total MOS area of
265 lm2.
In this paper, GSA–PSO based two-stage op-amp circuit
design approach results in much improved superior values
of UGB, Av, CMRR, PSRR?, PSRR-, the least power
dissipation and the least total MOS transistor area of
5.776 MHz, 75.43, 87, 83.2, 110.4 dB, 712.8 lW and
109.6 lm2, respectively, as compared with the results of
PSO based approach reported in [78, 80]. All the design
specifications are shown in Figs. 11, 12, 13, 14, 15, 16, 17,
and 18 and Table 5 The optimal design parameters which
have been achieved by using GSA–PSO algorithm for the
design of the CMOS two-stage operational amplifier circuit
are as follows and are also given in Table 6.
The best values obtained for all the performance
parameters and the objective function (least MOS area)
prove GSA–PSO to be the best optimizer for this design.
Extensive SPICE simulations have been carried out to
validate the design of the CMOS two-stage op-amp circuit
using the optimal device sizes (shown in the last column of
Table 6) obtained by using GSA–PSO algorithm. SPICE
simulations (Figs. 11, 12, 13, 14, 15, 16, 17, 18) demon-
strate that the proposed GSA–PSO based design not only
satisfies all the design specifications and design parameters
but also minimizes the total area occupied by the MOS
transistors, and also the total power dissipation as com-
pared with CO based method [39] and PSO based method
[78, 80]. The different performance specifications of the
designed two-stage op-amp circuit using GSA–PSO are
shown in Table 5 along with those results reported in dif-
ferent literature. Table 6 shows the optimal design
parameters achieved for CMOS two-stage operational
amplifier circuit based on GSA–PSO algorithm. Table 6
also shows the different optimal design parameters repor-
ted in different literature.
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 Int. J. Mach. Learn. & Cyber.

Table 3 Comparison of design criteria/specifications of CMOS differential amplifier with current mirror load
Design criteria Specifications GA [37] PSO [78] HS [79] DE [79] ABC [79] GSA–PSO

Output capacitance (pF) C4 2 5 5 5 5 4

SR (V/ls) C10 3.2 22.4 14.916 18.451 15.67 16.77
Power dissipation (lW) B2,000 31 1,260 886 990 830 511.6
Phase margin () [45 72 83.8 89.1 88.81 91.248 82.74
Cut-off frequency (kHz) C100 NR* 100 114 129.7 112.367 100
Gain (dB) [40 60 42 40.98 41.23 42.045 44.52
VIC (min) (V) C-1.5 -1.3 -0.8 -0.7 -0.92 -0.97 -0.365
VIC (max) (V) B2 1.9 1.4 1.2 1.15 1.2 1.717
CMRR (dB) [40 NR* 84.2 78.5 78.39 79.67 93.23
?
PSRR (dB) [40 NR* 40.1 42.93 43.14 43.857 48
PSRR- (dB) [40 NR* 68 67.64 68.175 68.423 110.4
Total MOS area (lm2) \300 6,500 296 NR* NR* NR* 238.28
NR*: not reported in the refereed literature

Table 4 Design parameters obtained for CMOS differential amplifier MOS area as compared with the previously reported recent
with current mirror load literature.
Design parameters GA [37] PSO [78] GSA–PSO
4.3 Plot of convergence profiles of the proposed GSA–
Ibias (lA) 2 125 119.03
PSO
W1/L1 (lm/lm) 240/13.2 29.4/3.5 25/3.5
W2/L2 (lm/lm) 240/13.2 29.4/3.5 25/3.5 The convergence profile plot of GSA–PSO algorithm for
W3/L3 (lm/lm) 7.3/7.7 11.3/3.5 7.5/3.5 the differential amplifier circuit has been shown in Fig. 19.
W4/L4 (lm/lm) 7.3/7.7 11.3/3.5 7.5/3.5 The total area occupied by the MOS transistor is of
W5/L5 (lm/lm) 4.6/2.4 4.2/1.4 2.9/1.4 238.28 lm2 and the total time taken for the execution is
W6/L6 (lm/lm) 2.4/2.4 4.2/1.4 4.8/1.4 1.0293 s for 200 number of fitness evaluations (which is
CL (pF) 2 5 4 computed as product of number of cost function evaluations
per generation cycle and number of generation cycles).
Figure 20 shows the plot of convergence profile of the
Thus, GSA–PSO based optimal CMOS analog amplifier proposed GSA–PSO for the two-stage operational amplifier
circuit design technique ensures to have a much improved circuit. The total area has been occupied by the MOS
voltage gain, power supply rejection ratio, common mode transistor is 109.6 lm2 and the total time taken for the
rejection ratio, power dissipation and as well as the total execution is 0.5966 s for 200 number of fitness evaluations

Fig. 11 Plots of gain and phase

of the proposed GSA–PSO
based CMOS two-stage
operational amplifier circuit

123
Int. J. Mach. Learn. & Cyber.

Fig. 12 Plot of slew rate of the

proposed GSA–PSO based
CMOS two-stage operational
amplifier circuit

Fig. 13 Plot of positive PSRR

of the proposed GSA–PSO
based CMOS two-stage
operational amplifier circuit

Fig. 14 Plot of negative PSRR

of the proposed GSA–PSO
based CMOS two-stage
operational amplifier circuit

123

Fig. 15 Plot of CMRR of the
proposed GSA–PSO based
CMOS two-stage operational
amplifier circuit
Fig. 16 Plots of ICMR along
with ID5 and (VGS - Vtn) of the
proposed GSA–PSO based
CMOS two-stage operational
amplifier circuit
(which is computed as product of number of cost function
evaluations per generation cycle and number of generation
cycles).
From the convergence plots, it is evident that GSA–PSO
achieves the near-global optimal minimum values of total
MOS area in less than 100 number of fitness evaluations
for each circuit design. So, GSA–PSO algorithm optimizes
the best for the present study.
4.4 Plot of multi-parameter sensitivity
Figure 21 shows the plot of multi-parameter sensitivity of
CFDiff Amp evaluated by (45), with r ¼ 1 for the differen-
tial amplifier with current mirror load. Figure 22 shows the
plot of multi-parameter sensitivity of CFTwoStageOpamp
evaluated by (46), with r ¼ 1 for the two-stage operational
amplifier. So, the optimal designs of two CMOS analog
circuits are guaranteed.
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Int. J. Mach. Learn. & Cyber.
5 Conclusions
In this paper, a hybrid evolutionary optimization technique
based on GSA–PSO algorithm is employed for the optimal
designs of CMOS differential amplifier with current mirror
load and CMOS two-stage operational amplifier circuit.
The optimal designs are aimed to be met by optimizing the
design specifications such as slew rate, gain, power dissi-
pation, etc. The design equations are utilized for the cost
function considering those several conflicting design
specifications. The design parameters such as widths of
MOS transistors, DC bias current, etc., achieved by
employing GSA–PSO algorithm are utilized for the rede-
sign of the circuits in SPICE simulator in order to validate
the exact values of design specifications/performance
parameters obtained. Simulation results prove that each
GSA–PSO based analog circuit design not only meets all
design specifications but also minimizes the total MOS
Int. J. Mach. Learn. & Cyber.
Fig. 17 Plot of power
dissipation of the proposed
GSA–PSO based CMOS two-
stage operational amplifier
circuit
Fig. 18 Plot of propagation
delay of the proposed GSA–
PSO based CMOS two-stage
operational amplifier circuit
area and the power dissipation with respect to the previ-
ously reported methods. GSA–PSO is proved to have
superior performance for CMOS differential amplifier with
current mirror load with much improved gain, CMRR,
PSRR?, and PSRR- and the total power dissipation, the
least total MOS area with respect to other reported litera-
ture. GSA–PSO based approach is also found to have
superior performance for the CMOS two-stage operational
amplifier with improved UGB, gain, CMRR, PSRR?,
PSRR-, total power dissipation and the least total area
occupied by the MOS transistors in comparison with those
of other reported methods. From the simulation study, it is
established that the proposed GSA–PSO based optimiza-
tion technique adopted for the analog IC optimization is
efficient in finding the near-global optimal solution in
multidimensional search space, where the other reported
algorithms are entrapped to suboptimal solutions. Hence, it
can be inferred that the proposed GSA–PSO based CMOS
amplifier designs are the best in comparison with those
resulted in by the other reported techniques.
Automation of CMOS analog circuit optimization is a
very difficult and time consuming task. The emphasis of
this work is optimal designing of CMOS differential
amplifier with current mirror load and CMOS two-stage
operational amplifier circuits. After successful execution of
the program in MATLAB, minimum area is achieved in
terms of design parameters. But some difficulties have been
faced during the design. When the W values and L values
are put in Cadence, some parameters are conflicting with
each other. For example, when gain increases, the phase
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 Int. J. Mach. Learn. & Cyber.

Table 5 Comparison of design Design criteria Specifications CO [39] PSO [78, 80] GSA–PSO
criteria/specifications of CMOS
two-stage operational amplifier Output capacitance (pF) C7 3 10 7.2
Slew rate (V/ls) C10 88 11.13 10.88
Power dissipation (lW) B2,500 5,000 2,370 712.8
Phase margin () [45 60 66.55 66.2
Unity gain bandwidth (MHz) C3 86 5.32 5.776
Gain (dB) [60 89.2 63.8 75.43
VIC (min) (V) C - 1.5 NR* -0.8 -0.886
VIC (max) (V) B2 NR* 1.75 1.9
CMRR (dB) [60 92.5 83.74 87
PSRR? (dB) [70 116 78.27 83.2
-
PSRR (dB) [70 98.4 93.56 110.4
NR*: not reported in the Total MOS area (lm2) \300 8,200 265 109.6
refereed literature

Table 6 Design parameters obtained for CMOS two-stage opera- -10

x 10
tional amplifier 1.106
Design parameters CO [39] PSO [78, 80] GSA–PSO 1.105

1.104
Ibias (lA) 10 40.39 28
Total MOS Area (mxm) 1.103
W1/L1 (lm/lm) 232.8/0.8 4.9/2 4/2
W2/L2 (lm/lm) 232.8/0.8 4.9/2 4/2 1.102
W3/L3 (lm/lm) 143.6/0.8 5.9/2 4/2 1.101
W4/L4 (lm/lm) 143.6/0.8 5.9/2 4/2 1.1
W5/L5 (lm/lm) 64.6/0.8 2.1/2 2.8/2
1.099
W6/L6 (lm/lm) 588.8/0.8 90.9/2 24/2
1.098
W7/L7 (lm/lm) 132.6/0.8 16.3/2 9.2/2
W8/L8 (lm/lm) 2/0.8 2.1/2 2.8/2 1.097

CL (pF) 3 10 7.2 1.096

0 20 40 60 80 100 120 140 160 180 200
Cc (pF) 3.5 3 2.8 Number of fitness evaluations

Fig. 20 Plot of Convergence profile of the proposed GSA–PSO for

two-stage operational amplifier

-10
x 10 0.7745
2.398
0.774
2.396
0.7735
Total MOS Area (mxm)

2.394
0.773
SCFDiff-Amp

2.392
0.7725

2.39 0.772

2.388 0.7715

2.386
0.771

0.7705
2.384
0.77
2.382 2.382 2.384 2.386 2.388 2.39 2.392 2.394 2.396 2.398 2.4
0 20 40 60 80 100 120 140 160 180 200 -10
CF Diff-Amp
x 10
Number of fitness evaluations

Fig. 19 Plot of Convergence profile of the Proposed GSA–PSO for Fig. 21 Plot of multi-parameter sensitivity of CFDiff Amp for differ-
differential amplifier with current mirror load ential amplifier with current mirror load

123
Int. J. Mach. Learn. & Cyber.
0.341
0.3405
0.34
0.3395
SCFTwo-Stage-Opamp
0.339
0.3385
0.338
0.3375
0.337
0.3365
0.336
1.096 1.097 1.098 1.099 1.1 1.101 1.102 1.103 1.104
CFTwo-Stage-Opamp
Fig. 22 Plot of multi-parameter sensitivity of CFTwoStageOpamap for
the two-stage operational amplifier
margin decreases and vice versa. Even when the value of
CL increases, UGB decreases. Then some manual tuning is
needed to get better results in terms of performance
parameters as design specifications and design parameters.
In this work single objective function is considered but
the abovementioned difficulty can be overcome by using
multi-objective function and multi-objective optimization.
Future direction of research would be to evaluate the
optimization performance of other state-of-the-art meta-
heuristic algorithms on more complex analog circuit
structures with particular design specifications.
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