2023 10th IEEE International Conference on Power Systems (ICPS)
13-15 December 2023, Cox’s Bazar, Bangladesh
Third Order Integral Terminal Sliding Control for
DC-DC Converter Voltage Stability
Asrafun Nahar Sasa1, Mst. Fateha Samad2, and Md. Kamal Hosain3
1,2,3
Department of Electronics & Telecommunication Engineering
Rajshahi University of Engineering & Technology, Rajshahi, Bangladesh
2023 10th IEEE International Conference on Power Systems (ICPS) | 979-8-3503-1873-9/23/$31.00 ©2023 IEEE | DOI: 10.1109/ICPS60393.2023.10428961
Email- asrafunnahar16sasa@gmail.com, fatehaeteruet@gmail.com, kamaleteruet@gmail.com
Abstract—In DC bus, constant power loads (CPLs) are
connected in DC distribution networks (DCDNs) which causes
the system instability due to the negative impedance properties
of CPLs. To ensure system stability, a third-order integral
terminal sliding mode controller (3-ITSMC) is proposed using
an improved quick-reaching law. In this proposed control
scheme, an improved reaching law is used to mitigate chattering
from the system and tackles the underlying issue of the non-
minimum phase in DC-DC boost converters (DDBCs). Through
the Lyapunov stability theory, 3-ITSMC controller can ensure
the stability of the entire system which is the main aim of this
proposed 3-ITSMC. The performance of the proposed control
scheme is validated through the simulation investigations
implemented in MATLAB/Simulink under major fluctuations
demonstrating that it enhances the stability of DCDNs in every
aspect as compared to the existing sliding mode controllers.
After the simulation, the tracking error of 3-ITSMC is 20% for
DC voltage variation. Additionally, for the variations in CPLs’
power, the tracking error of 3-ITSMC is 18%.
Keywords—constant power load, DC distribution networks,
DC-DC boost converters, third-order integral terminal sliding
mode controller, Lyapunov stability criteria
I. INTRODUCTION
Power electronics converter (PEC) sources generally
employ renewable energy sources (RES) such as solar power
generation systems (SPGs) and wind power generation
systems (WPGs). PECs are extensively used because of their
adaptability, versatile voltage management at present, high
efficiency, and output voltage stability [1]. DC-DC boost
converters (DDBCs) are utilized in such instances for
coupling the RES to the DC bus [2]. The DC bus in a DC
distribution network (DCDN) has an enormous number of
loads attached to it. One of them is the constant power load
(CPL), has been set up to consume a constant volume of power
[3]. As a result, research has concentrated on enhancing the
reliability and sustainability of DCDNs with CPLs [4].
Feeding CPLs in DDBCs present two major challenges:
regulating DDBCs to achieve desirable DC bus voltage and
reducing the negative impedance characteristics of CPLs. This
type of impedance of CPLs causes the voltage to drop
exponentially with increasing current, which significantly
impacts the stability of the power systems. Negative
incremental impedance of the constant power loads results in
significant power system instability [5].
Usually, linear controllers have been employed; however,
the nonlinear system feeding CPLs cannot be controlled via
conventional techniques [6]. Direct model reference adaptive
control based on the PI linear control scheme was proposed in
[7] to deal with this issue. All of the aforementioned linear
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control systems, however, could not ascertain the stability of
the DDBC feeding load of the CPL. Two improved linear
quadratic regulator (LQR) control systems, m-LQR and M-
LQR, had been claimed in [8] to deal with all of the
aforementioned issues. These two control strategies, however,
could not be sufficient to compensate for the impedance
characteristics of CPLs which had a bad impact on the overall
system stability. Fuzzy logic (FL), sliding mode (SM), and
model predictive control (MPC) schemes are just a few of the
examples of nonlinear control mechanisms that the
researchers had developed in some research works to get over
these constraints [9-11].
To ensure the whole system's stability, the adaptive energy
shaping (AES) control method has been proposed in [12].
However, the AES control method could not ensure a fast
dynamic response as well as fewer dynamic tracking errors in
the whole system. In [11], the author presented an explicit
MPC (eMPC) for assurance of a fast dynamic response. If the
system characteristics were not exactly comprehended, then
the MPC controller could not work effectively. To resolve this
limitation, a backstepping controller (BSC) was proposed in
[13] to alleviate and enhance the DC bus voltage stability in
DCDNs. A new nonlinear integral BSC scheme was proposed
by Andalibi et al. [14] to ensure a fast dynamic response.
However, the BSC could not ensure the tracking error and the
transient response of the output DC bus voltage if the user-
defined constants were improperly chosen by trial-and-error
approaches.
By inspiring the above mentioned works and for
stabilizing the DC bus voltage of DDBCs feeding CPLs, a 3-
ITSMC method is presented. This proposed control scheme is
developed by making use of improved quick-reaching law
theories and third-order integral terminal sliding mode control
(3-ITSMC). To lessen chattering in the overall system, this
research use a third-order integral terminal sliding mode
surface. The overall stability of the entire system is
investigated by employing the Lyapunov stability theory.
Finally, the performance is compared to that of the existing
sliding mode controller to show its positive consequences.
And the simulation results under various circumstances and
disturbances based on real-life scenarios are shown such as
reference DC bus voltage and reference power of CPLs'
fluctuations in a certain time range.
The work is structured as follows: Section II covers
problem formulation and system modeling, while Section III
explains the recommended controller design process using
appropriate equations. In Section IV, the simulated results and
its analysis are given. The conclusion and future works are
described in Section V.
 In contrast to the combined form of the resistive load and
CPL, the DC load is assessed as a pure CPL in the present
work. It implies RL equals infinity which has the biggest
negative influence on the overall system stability
requirements of the system. The DDBC is considered to be
functioning in continuous conduction mode (CCM) for the
purpose of simplicity. Thus, Kirchhoff's current law
(KCL) and Kirchhoff's voltage law (KVL) may be used in
DDBC with a CPL as illustrated in Fig. 2 to obtain the
standard dynamical model of DDBC. Then, the mathematical
equations can be expressed as follows:
Fig. 1. Characteristics of voltage-current relationships for CPLs [15].
di L V g − Vdc Vdc
II. PROBLEM FORMULATION AND SYSTEM MODELING = + µ (3)
dt L L
A. Problem Formulation of CPLs dV dc 1 P i
= (i L − CPL ) − L (4)
The primary system is unstable due to the property of dt C V dc C
CPLs. Voltage-current characteristics of a CPL are shown in
Fig. 1. Fig. 1 shows that the incremental impedance value is where, the symbols carry their normal meanings, as presented
negative. The load's current consumption therefore has a in [16].
detrimental impact on the system's stability, leading to a
negative incremental impedance that fluctuates when III. PROPOSED CONTROLLER DESIGN
compared to the DC bus voltage [15]. This section covers the design approach of the proposed
The generalized electrical equation of CPLs can be control scheme which is 3-ITSMC. The central objective is
represented as follows: achieving quick transient response and a lower zero steady-
state tracking error of the main DC bus voltage under CPL
PCPL changes and is to stabilize the whole system. By considering
iCPL = (1) all, Eq. (3) and Eq. (4) are used as the main equations to design
Vdc this proposed control scheme. Several numbers of steps are
needed to be followed to get the desirable control law of 3-
where, denotes the current of CPLs, PCPL denotes the ITSMC. Thus, all necessary steps are given as follows:
power of CPLs, and is the main DC bus voltage. By applying The design procedure of the proposed controller is
a signal perturbation to Eq. (1) in the region of equilibrium, presented in detail in the following:
the negative impedance characteristic of CPLs can be
described as follows. Step 1: Third-order integral terminal sliding surface can be
defined as,
∂V dc P
RCPL = = − 2CPL (2) α
∂ iCPL I CPL S = c1e2 + c2  e2 sign (e2 ) dt (5)

where, RCPL indicates the equivalent internal impedance of where, c1 and c2 are positive constants which satisfy the
conditions of c1 > 0 and c2 > 0. And α is a positive constant
CPLs and I CPL is the steady-state current value at the
which satisfies the condition of < α < 1.
equilibrium point under small signal disturbances. Because of
the negative impedance characteristics of CPLs, it poses a Therefore, dynamic errors are determined as follows:
negative impact on system stability under load variations
which is seen in Eq. (1) and Eq. (2). e1 = Vdc − Vdc ( ref ) (6)
B. Modeling of the DDBC Feeding CPLs
e2 = iL − iL ( ref ) (7)
In Fig. 2, the DC voltage supply Vg is attached to the main
where, with Ϛ > 0. From Eq. (6), it is obtained as,
DC bus, which serves as the main source through a DDBC,
and the resistive load is connected in parallel to the main DC • •
bus through the CPLs. e1 = Vdc (8)

The derivative form of the second dynamic error can be

expressed as:
• • •
e2 = i L − ς (Vdc ) (9)

Then, placing Eq. (4) into Eq. (9), it is found as,

• Vg − Vdc Vdc 1 P i (10)
e2 = ( + µ ) − ς { (iL − CPL ) − L µ}
L L C Vdc C

Fig. 2. Proposed simplified structure of DC-DC boost feeding CPLs.

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 Step 2: Determining the main control law, IV. SIMULATION RESULT AND ANALYSIS
• •
α On the MATLAB/Simulink platform, a primitive
S = c1 e 2 + c 2 e 2 sign ( e 2 ) (11) simulation model, depicted in Fig. 2, has been constructed to
illustrate the effectiveness of the designed controller. Table I
Switching rules are well known for their significance in contains a list of the system parameters. The following gain
reducing chattering and achieving finite-time convergence. To parameters are chosen to run the simulation: c=4, c1=0.09,
meet this control objective and reduce the limitations of c2=0.009, c3=0.67, a=0.0001, α=0.2, and ϛ=5.01. Several
conventional reaching law, a novel improved quick-reaching trials and errors are conducted to find an appropriate gain
law can be represented as follows: parameter for each parameter.
•
S = − c (b
S
− 1) sign ( S ) − c 3 S sign ( S )
a
(12) This proposed control scheme shows strong performance
when considering the alteration of the DC bus voltage and the
where, c, c3, a, and b are positive constants that satisfy all the variation of the reference power of CPLs. Both are discussed
in more detail below.
c3
conditions such as c > 0, c3 > 0, 0 < a < 1, and b = 1 + . A. DC Bus Voltage Variation
c
By equating Eq. (11) and Eq. (12), the following expression Initially, the controller's performance is evaluated through
can be written: fluctuations in the DC bus voltage of DDBC. As a result, a DC
bus voltage of 120 V is initially evaluated, and it is
•
α S a subsequently raised from 120 V to 130 V at t = 1.5 sec. Fig. 3
c1e2 +c2 e2 sign(e2 ) = −c(b −1)sign(S) − c3 S sign(S) (13)
(a) depicts all the possibilities described. On the other hand,
• the supply voltage is 60 V, and the reference power of CPLs
Putting the values of e2 and e2 in Eq. (13) and the main is assumed to be 1800 W respectively. The main DC bus
voltage stability with reduced tracking error and a quicker
control law of the proposed control scheme from Eq. (13) can settling time cannot be assured by the existing sliding mode
be expressed as follows: controller when the reference DC bus voltage of a DC-DC
1 1 P V − Vdc α
boost converter fluctuates, as is seen in Fig. 3 (b). On the other
µ= [ς (iL − CPL ) − c1 ( g ) − c2 e2 sign(e2 ) hand, the proposed 3-ITSMC can offer a quick dynamic
Vdc i C Vdc L
(c1 +ς L ) reaction and a quick settling time with minimized tracking
L C errors.
S a
− c(b − 1) sign( S ) − c3 S sign( S )]
(14)
Inserting the value into Eq. (11) will yield as,
•
S a
S = − c (b − 1) sign ( S ) − c 3 S sign ( S ) (15)

Then, to assure the entire system stability, the final

Lyapunov function is:
1 2 (16)
W = S
2
(a) Reference DC bus voltage variation.
Using Eq. (5) and Eq. (16), the expression of the time
derivative of W is:
•
S a +1
W = − S c (b − 1) − c 3 S (17)

•
Since c > 0 , c3 < 0 , and W ≤ 0 are with the designed
control law, the whole system stability is assured. The control
law is represented in Eq. (14). In the following section, the
simulation results are employed to validate the efficacy of the
proposed 3-ITSMC.

TABLE I. SYSTEM PARAMETERS

(b) DC bus voltage response.
Parameters Value
Vg 60 V Fig. 3. Dynamic response of the entire system with the variation reference
Vdc 120 V DC bus voltage.
PCPL 1.8 kW
L 4.8 m H It is obvious from the investigation described above that
rb 1.2 m Ω when the reference DC bus voltage of DDBC is changed, the
C 6mF proposed controller superior to the existing controller in terms
R ∞
of tracking error and settling time. When the reference DC bus
voltage is varied at 1.5 sec, the tracking error for the proposed

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 controller is less than 17% which means the difference
between the measured DC bus voltage and the reference DC
bus voltage is 0.17. On the other hand, the tracking error for
the existing sliding mode controller is greater than 97% for the
DC bus voltage response which also means that the difference
value of the measured DC bus voltage and the reference DC
bus voltage is 0.97. Additionally, the proposed control
method's reaction time for the DC bus voltage is significantly
less than the response for the existing sliding mode control
scheme.
B. Variation in CPLs’s Reference Power
To demonstrate the influence of this real-life scenario on
DCDNs, the reference power of CPLs is set to 1850 W at the
beginning. The power is decreased from 1850 W to 1800 W
at t = 1.9 sec, as illustrated in Fig. 4 (a). This type of
circumstance is regularly observed in practical life scenarios.
In contrast, the reference DC bus voltage is 120 V while the
DDBC’s rated input voltage is 60 V. As shown in Fig. 4 (b),
3-ITSMC can offer main DC bus voltage traceability with a
shorter settling time and smaller tracking error when the
reference power of CPLs is altered. Conversely, the existing
sliding mode controller is unable to ensure a quick dynamic
reaction and minimal tracking error. The suggested controller
beats the existing controller in terms of tracking error and
settling time when the reference power of CPLs is altered.
(a) Reference power of CPLs′ fluctuation.
(b) DC bus voltage response.
Fig. 4. Dynamic response of the entire system with the reference power
variation of the CPL.
From Fig. 4(b), the proposed 3-ITSMC controller
performs better in terms of tracking errors than the existing
works. When the reference power of CPL is varied at 1.9 sec,
the tracking error for the proposed controller is less than 18%
which means the difference between the measured DC bus
voltage and the reference DC bus voltage is 0.18. In contrast,
the tracking error for the existing sliding mode controller is
greater than 98% for the DC bus voltage response where the
difference value of the measured DC bus voltage and the
reference DC bus voltage is 0.98. Therefore, the suggested 3-
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ITSMC is superior to the existing sliding mode controller in
terms of settling time and dynamic tracking error.
V. CONCLUSION AND FUTURE WORK
The negative impedance properties of CPLs, which lead to
system instability, are tackled in this research via a third-order
integral terminal sliding mode controller. The Lyapunov
theory guarantees the system’s overall stability. It can be
determined that the suggested 3-ITSMC is more efficient than
the existing sliding mode controller, when the reference power
of the CPL and system DC bus voltage fluctuates in terms of
settling time and dynamic tracking errors. The contribution of
the proposed controller is verified through the simulated
results. It is obtained from the simulation outcomes that the
proposed controller can ensure a more stable DC bus voltage
under different conditions. In future work, another type of
advanced reaching law can be used to reduce chattering from
whole system feed CPLs.
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