Logic Families and IC Specifications

Marks 10%
Q1) Objective questions (1)
1) The amount of noise voltage that an input can tolerate without causing a false
change in output state is -----
Noise immunity.
2) At low operating frequency, among the different logic families power dissipation is
least in -----
Low power Schottky.
3) Among the TTL family the logic gates of TTL sub family that have smallest product
of propagation delay and power dissipation is -----
74LSXX.
4) The TTL family with minimum value of figure of merit is ----
Low power Schottky.
5) The figure of merit of digital IC is expressed in -----
Pico joule.
6) The speed of operation of digital IC is expressed in -----
Nano second.
7) Totem pole transistor produce -----
Low output impedance.
8) Wiring the output of open collector devices to common pull up resistor
gives ---- action.
ANDing.
9) In tri-state logic when the control or enable is zero, the output is ---- (O 04)
9) In tri-state logic the third state is ---- state. (M18)
High impedance.
10) The TTL families has an output stage known as -----
Totem pole stage.
11) CMOS logic families gives ----
High noise immunity, High fans out.
12) TTL families gives -----
High speed operation, Low output impedance.
13) MOS technology gives ----
Small size, Low power dissipation, High packing density.
13) A bipolar device is the one ----
Whose working depends on majority as well as minority charge carriers.
14) Open input of TTL logic families is equivalent to ---- at input.
High voltage.
15) Possibility of both transistors at totem pole output going in saturation is
avoided by ----
Diode at output.
16) The IC that can drive maximum standards load of its own subfamily is ----
74CXX.
17) In any logic families when speed of operation is increased, the total amount of
power dissipated in it -----
increases.
18) Bipolar technology is preferred for ----
Small scale and medium scale integration.
19) ---- is the most widely used bipolar family.
TTL
20) The totem pole output produces a ---- impedance in either state.
Low output
21) A floating TTL input has same effect as ----
High input.
22) The maximum number of TTL loads a TTL device can drive is known as ---
Fan out.
23) The figure of merit of a digital IC is ------- (M 12)
Propagation delay  power.
24) In any logic family when speed of operation is increased the total amount of
power dissipated in it --- (O 05)
Increases
Q1) What is logic family? Give different types of logic families.
(M 01, 11, O 02, 13)
(3 M = Definition 1Mark, Types of families 2 Marks)
Ans: - Logic gates and other digital circuits can be constructed by using different
circuits arrangement. Each arrangement possesses definite advantages and
disadvantage. To improve properties like speed, reduce the effect of noise and reduce
power consumption, different circuits are developed.
Different forms of such circuits are known as logic families.
Types of logic families are.

Q2) What is meant by propagation delay and noise margin in digital IC’S?
Q2) Write note on characteristics of digital IC’s.
Q2) Define the following characteristic of Digital IC’s
1) Figure of merit, (2) Fan out, (3) Noise margin, (4) Operating temperature,
5) Power Dissipation. (M 02, 04, 06,07,08,09, 10, 13, 14, 15, 16, 17, 18, O 01, 02, 03, 06,
08)
(1 Mark for each characteristic)
Ans: - 1) Speed of operation: - It is specified in terms of propagation delay time.
This delay time is measured between 50% voltage levels of input and output
waveforms. There are two types of delay time.
1) TPHL: - It is the time required when output goes from high level to low level.
2) TPLH: - It is the time required when output goes from low level to high level.
The propagation delay time is given by
TPHL + TPLH
TP =
2
 Propagation delay time is expressed in nanoseconds.
2) Power dissipation: - This is the power dissipation in IC which is measured in mill
watts. It is actually product of DC voltage supplied and current drawn by the logic
circuit.
3) Figure of merit: - It is defined as product of propagation delay time and power
dissipation (speed and power). As speed is expressed in nanosecond and power in
mill watt figure of merit is expressed in pico joule.
4) Fan out: - This number of similar gates which can be driven by gate. High fan out
is an advantage of digital circuit because it reduces the need of additional driver and
hence hardware used is minimized.
5) Noise margin: - A magnetic and electric field induces unwanted voltage which is
known as noise. There are two types of noise a) Environmental noise, b) Manmade
noise.
Due to noise the voltage at input drops below high-level input voltage (VIH) and
rises above low level input voltage (VIL) and due to which circuit produces undesirable
operation, hence the circuit must have ability to tolerate the noise signal which is
known as noise immunity. A quantitative measure of this is known as noise margin.
6) Operating temperature: - The temperature range in which IC functions properly
is known as temperature range. The temperature range of IC used in commercial and
industrial applications is 00C to 700C while the temperature range of IC used in
military applications is -550C to 1700C.
7) Fan in: - It is total number of inputs which can be supplied to logic circuit. It is
the total number of inputs provided for the gate.
8) High level input voltage (VIH):- It is minimum voltage which is recognized by gate
as high logic (1).
b) Low level input voltage (VIL):- It is maximum input voltage that can be recognized
by gate as low logic (0).
c) High level output voltage (VOH):- It is minimum voltage available at output terminal
when logic is high (1).
d) Low level output voltage (VOL):- It is maximum voltage available at output terminal
when logic is low (0).
e) High level input current (IIH):- It is minimum current supplied by driving source
corresponding to high logic (1).
f) Low level input current (IIL):- It is maximum current supplied by driving source
corresponding to low logic (0).
Q3) Explain working of TTL NOT gate with circuit diagram. (O 07, 09)
(3 Marks = 1 Mark for Diagram & Truth table, 2 Marks for explanation)
Ans: - In TTL circuit totem pole arrangement is used in the output stage. In this
arrangement two transistors are connected in series. When upper transistor becomes
on output goes to high level (1) and when lower transistor becomes on output goes
to low level (0)
Circuit Diagram: - Truth Table:-

A Y
0 1
1 0
 When input ‘A’ is low base of transistor pull down sufficient biasing potential
hence Q1 conduct while Q2 does not get sufficient base potential to conduct and goes
to off state the result of this collector potential of Q 2 becomes high which biases the
transistor Q3 and output becomes high (1).
When input ‘A’ is high transistor Q1 stops conduction due to which base potential
of Q2 increases and Q2 conduct. As Q2 conducts it provides biasing potential to
transistor Q4 and it also becomes on. The result of all this output goes to low level
(0).
Q4) Explain the working of open collector TTL NAND gate. (M 04, 07, 15, 16)
(3 Marks = 1 Mark for Diagram & Truth table, 2 Marks for explanation)
Ans: - In many TTL circuits an open collector output stage is used. In this output
stage only the lower transistor of totem pole is used. As collector of Q 3 is open output
stage could not work properly hence external pull up resistor is connected to the
collector of transistor Q3.
Circuit diagram: - Truth Table:-

A B Y

0 0 1

0 1 1

1 0 1

1 1 0

When input A and B are low or any one of them is low transistor Q 3 does not get
the biasing potential and gets cutoff but there is no upper transistor to pull up the
voltage (to get high output), hence pull up resistor is used. As this resistor is passive
component switching from low to high level is known as passive pull up.
When A and B are high transistor Q1 becomes off and it provides biasing potential
to transistor Q2 and Q3. Hence Q2 and Q3 conducts the result of this output drops to
low level (0). In this case transistor Q 3 is used to make the output low hence this is
known as active pull down.
The main drawback of this circuit is that passive pull up is much slower than
active pull down.
Q5) Draw the circuit of TTL NAND gate and explain its working.
(O 03, 04, M 01, 02, 03, 08, 09, 12, 14, 16, 18)
(3 Marks = 1 Mark for Diagram & Truth table, 2 Marks for explanation)
Ans:-As this gate has two inputs there are two emitters for transistor Q 1, Each
emitter acts like a diode while the remaining circuit inverts the signal so that the
overall circuit acts as a dual input NAND gate.
Circuit diagram: - Truth Table:-

A B Y
0 0 1
0 1 1
1 0 1
1 1 0

In TTL circuit totem pole arrangement is used in the output stage. In this
arrangement two transistors are connected in series. When upper transistor becomes
on output goes to high level (1) and when lower transistor becomes on output goes
to low level (0)
If A and B or any one of them is zero the base of transistor Q 1pull down all the
potential and it conducts, due to which there is no sufficient base potential provided
to transistor Q2 and it remains in cutoff state. As Q2 is in cutoff state there is no
biasing potential applied to transistor Q4 while transistor Q3 gets sufficient biasing
potential, and it conducts. The result of all this output goes to high level.
When both A and B are high transistor Q1 becomes off and it provides the biasing
potential to transistor Q2 and it conducts. As Q2 conducts it provides sufficient
biasing potential to transistor Q4 and it also conducts. As Q4 conducts output drops
to a low level.
Q6) Draw and explain the basic circuit of TTL NOR gate. (O 01, 08, 13, M 11, 13)
(3 Marks = 1 Marks for Diagram & Truth table, 2 Marks for explanation)
Ans: - TTL NOR gate is basically modified version on NAND gate.
Circuit diagram: - Truth Table:-

A B Y
0 0 1
0 1 0
1 0 0
1 1 0
 In this circuit two transistors Q5 and Q6 are introduced. The second logic input is
applied to the circuit through transistor Q5. Transistors Q2 and Q6 are connected in
the shunt with each other. This combination gives basic OR operation and the
remaining circuit is used to invert the output to obtained NOR gate.
When both A and B are low Q1 and Q5 conducts which reduces the base potential
of Q2 and Q6 and makes it off due to which transistor Q3 gets required biasing
potential and it conducts. The result of this output becomes high.
When A or B or both A and B are high transistor Q 1 or Q5 or both Q1 and Q5
remains off due to which either Q2 or Q6 gets biasing potential they conducts due to
which transistor Q4 conducts and output drops to low level.
Q7) Explain working of Tristate Logic (TSL) inverter with the help of circuit
diagram and truth table. (M17)
Q7) Explain concept of tristate logic with neat diagram. (M 10, 11, 12, O 05)
(4 Marks = 2 Marks for Diagram & Truth table, 2 Marks for explanation)
Q7) Explain concept of Tri-state logic with help of neat diagram, explain the
working of TSL Inverter. (M16)
(4 Marks = 1 Mark for Concept, 1MarkDiagram, 2 Marks for explanation& Truth table)
Ans: - In complex circuits such as microprocessors and control systems more
number of gates are required. The output of gates is connected by a common line
known as Bus. When no of gates are connected to Bus some problems are created,
the problems are.
1) In totem pole very large current drains from source which increases
temperature of IC, and it may get damage.
2) In the case of open collector, the speed of operation is very low.
To overcome this drawback a special circuit is developed in which there is one
more output state, which is known as third state or high impedance state.
Circuit Diagram: - Truth Table:-

Control A Y
Input
0 X High Impedance
1 0 1
1 1 0

When control input is low diode conducts due to which base potential of Q 3 and
Q4 is removed hence they are in cut off state and behaves like open circuit. The
output at this stage is neither high or nor low and it is considered as high impedance
state.
When control input is high diode is in reverse mode, the output depends upon
data input.
If data input A is low (0) transistor Q1 conducts and removes the base potential
of transistor Q2 and Q4 hence transistor Q2 and Q4 are in off state while transistor Q3
conducts, and output becomes high (1).
 If data input is low transistor Q1 is in reverse mode and behaves like an open
circuit. Transistor Q2 and Q4 get required biasing potential and conduct hence output
drops to low level (0).
Q8) Explain the working of CMOS NOR gate. (M 01, 04, 06, 08, 10, 12, O 06)
Q8) Draw circuit diagram of two input CMOS NOR gate and explain its working
with truth table. (M14)
(3 Marks = 1 Marks for Diagram & Truth table, 2 Marks for explanation)
Ans: -In CMOS NOR gate two N channel MOSFETs are connected in shunt while
P-channel MOSFETs are connected in series.
Circuit Diagram: - Truth Table: -

A B Y

0 0 1

0 1 0

1 0 0

1 1 0

When inputs A and B are low transistors Q1 and Q2 conducts while transistor Q3
and Q4 are in off state due to which supply potential appears across output terminal
and output becomes high.
When input A is high, and B is low transistor Q1 and Q4 are in off state while Q2
and Q3 conduct due to which output is connected to ground and it becomes low.
When A is low, and B is high transistors Q1 and Q4 conducts while Q2 and Q3 are
in off state once again output is connected to ground, and it becomes low.
When both A and B are high transistor Q1 and Q2 are in off state while Q3 and Q4
conduct due to which output is connected to ground terminal and once again it
becomes low.
Q9) Draw and explain basic circuit of CMOS inverter. (M 02, 07, 13, 15, O 03, 05)
(3 Marks = 1 Marks for Diagram & Truth table, 2 Marks for explanation)
Ans: -In CMOS P-channel and N channel MOSFETS are connected in series. Drain
terminals are connected to each other similarly gates are connected to each other,
Output is taken from drain terminal.
Circuit Diagram: - Truth Table: -

A Y

0 1

1 0
 When input A is low P-channel MOSFET i.e. Q1 conducts while N- channel
MOSFET i.e.Q2 is in off state. The result of this supply potential remains across
output terminal and output becomes high.
When input A is high transistor Q1 becomes off while transistor Q2 conducts hence
output terminal is connected to ground terminal through transistor Q 2 hence output
drops to low level.
Q10) Explain with the help of neat diagram, the working of CMOS NAND gate.
(O 04, 08, 09, M 05, 17, 18)
(3 Marks = 1 Marks for Diagram & Truth table, 2 Marks for explanation)
In this case P channel MOSFETs are connected in shunt with each other while
N channel MOSFETs are connected in series with each other.
Circuit Diagram: - Truth Table:-

A B Y
0 0 1
0 1 1
1 0 1
1 1 0

When both inputs A and B are low, transistor Q1 and Q4 conducts while transistor
Q2 and Q3 becomes off, hence the output at this stage becomes high.
When any one input is high and the remaining one is low P channel MOSFETs
which has low input conducts while N channel MOSFETs which has low input
becomes off, i.e. either transistor Q1and Q3 or Q2 and Q4 conducts and due to which
output becomes high.
When both inputs are high transistor Q1 and Q4 becomes off while transistor Q2
and Q3 conducts. The result of this output drops to a low level.

Q11) Compare TTL and CMOS logic families. (O 02, 07, 13)
(4 Marks =1 Mark for each difference )
Ans:-
Points TTL CMOS

1)Fan out 10 50

2) Noise margin 0.4V 1.5V

3) Propagation delay 10ns 70ns

time

4) Power dissipation 10mw 0.01mw

5) Noise immunity Good Excellent

6)Noise generation High Low

 7) Logic functions Limited Very large number

8) Basic Logic function NAND gate NOT gate

9)Component Bipolar (Transistors) Unipolar (PMOS and

NMOS)

10) Power supply Exact 5V Between 3 to 20V

required

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