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Building-in reliability in BCD (Bipolar-CMOS-DMOS) technologies

Conference Paper · October 2013

DOI: 10.1109/ASICON.2013.6811954

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 Building-In Reliability in BCD (Bipolar-CMOS-DMOS) Technologies
Jifa Hao1* and T. E. Kopley2
1
Fairchild Semiconductor, 333 Western Avenue, South Portland, ME 04106 USA
2
Fairchild Semiconductor, 3030 Orchard Parkway, San Jose, CA 95134 USA
* Email:jifa.hao@fairchildsemi.com
Abstract
This paper discusses the “Building-In Reliability” (BIR)
approach to process development, particularly for
technologies integrating Bipolar, CMOS, and DMOS
devices (so-called BCD technologies). Examples of BIR
reliability assessments include gate oxide integrity (GOI)
through Time-Dependent Dielectric Breakdown (TDDB)
studies and degradation of laterally diffused MOS
(LDMOS) devices by Hot-Carrier Injection (HCI) stress.
TDDB allows calculation of gate oxide failure rates based
on operating voltage waveforms and temperature. HCI
causes increases in LDMOS resistance (Rdson), which
decreases efficiency in power applications.
1. Introduction
High volume manufacturing of integrated circuit (IC)
products has many quality and reliability risks. The
complexity of the Bipolar-CMOS-DMOS (BCD) process,
which integrates high voltage lateral DMOS (LDMOS)
devices into an already complex dual-gate BiCMOS
process, adds many interacting process steps that can
increase manufacturing defects. When the volume of
shipped parts numbers in the billions, even sub
part-per-million (ppm) levels of defects lead to many
defective parts. In addition, the product exercises
devices differently depending on the actual circuit design
and application. This must be taken into account when
calculating reliability wearout failure rates. Finally,
market pressures are forcing shorter device and process
development times even as the processes become more
complex and devices shrink in size. Many
semiconductor manufacturers have been trying to cut
qualification time and cost. Therefore, finding and
correcting reliability problems early in the design and
development cycle is much cheaper and faster than
finding the problem during qualification and field
application.
In this paper, we discuss reliability assessment during
BCD technology development. Such an approach has
been used for many years, and got the moniker
“Building-In Reliability” (BIR) in the early 1990’s[1].
We consider reliability assessment an integral part of the
design and technology development process to reduce or
eliminate reliability concerns prior to qualification.
978-1-4673-6417-1/13/$31.00 ©2013 IEEE
Through BIR, we have a clear understanding of reliability
risks before products are introduced to customers. The
reliability assessment we perform includes testing of gate
oxide integrity (GOI), electromigration, stress migration
(SM) or stress induced voiding, hot carrier injection (HCI)
and HCI Safe Operating Area (HCI SOA), negative bias
temperature instability (NBTI), plasma process induced
charge (P2IC), inter-/intra-metal dielectric (IMD)
breakdown, high temperature reverse bias (HTRB) stress,
and unclamped inductive switching (UIS). In this paper,
we first discuss the BIR methodology. Then we discuss
key reliability wear-out failures mechanisms in BCD
processes such as Time-Dependent Dielectric Breakdown
(TDDB) to assess GOI, and HCI in LDMOS devices.
2. BIR methodology
During the product concept phase, reliability
requirements based on the application are defined and are
used to drive reliability in the design phase. The design,
choice of materials, and development of new processes
impact primarily the wear-out and infant failure
mechanisms. By using Potential Failure Modes and
Effects Analysis (FMEA) [2], we can analyze the possible
failure modes that could occur with a design or process
and prioritize areas requiring improvement. The primary
component of the BIR methodology is the Failure
Mechanism Driven Reliability Characterization (FMDRC)
[3]. The process flow used for the FMDRC approach is
summarized in Fig. 1. The FMDRC uses as inputs the
potential failure mechanisms of concern from FMEAs
and characterizes the process robustness against each
concern through experimental designs (DOEs). It does
this using standard as well as non-traditional test methods
such as wafer level reliability (WLR). The reliability
testing is focused on early learning to identify important
failure modes and to drive reliability improvements
during each phase of the product development cycle.
For example, one reliability concern during technology
development is high voltage JFET leakage current and
breakdown voltage instability at high temperature. We
have developed a fast wafer level HTRB test method
instead of the traditional package level, long stress time
HTRB test. The breakdown voltage (BV) degradation
versus stress time is shown in Fig. 2. There is good
correlation between wafer level and package level HTRB 3. Gate Oxide Integrity and screening process
data. Moreover, this fast stress can significantly reduce
the duration of a DOE learning cycle to improve JFET The gate oxide is one of the key components of BCD
leakage and breakdown voltage instability during the technologies. Designers often ask to increase the gate
process development phase. oxide operating voltage as that decreases the MOSFET
channel resistance (Rdson). To assess the impact of
1. DEFINE WORST 2. DEFINE QUALITY
3. DEFINE
POTENTIAL
4. DEFINE higher gate voltages on reliability, TDDB studies are
RELEVANT
CASE USE
ENVIRONMENT
AND RELIABILITY
EXPECTATIONS
RELIABILITY
FAILURE
RELIABILITY required.
MODELS
MECHANISMS

• Temp, RH, # On/Off • Max. ppm allowable, • Corrosion, • Arrhenius, Eyring,

Cycles product lifetime,
cumulative ppm
electromigration,
TDDB, HCI, NBTI
Coffin-Manson
Fig. 3 shows gate oxide TDDB data with three different
oxide electric field stresses (Eox is related to gate voltage,
8. PERFORM
MATERIAL
7. PERFORM
CONSTRUCTION
6. DEFINE STRESS
LIMITATIONS
5. IDENTIFY
ACCELERATING
Vg, to first order, by Eox=Vg/tox, where tox is the oxide
ANALYSIS ANALYSIS FACTORS thickness) at an elevated temperature. Based on the data,
• Dry vs. wet Tg, CTE1, • Demonstrated mfg. • Max. temperature, • Temperature, voltage,
we can predicate the gate oxide failure rate at any
CTE2, Young’s
Modulus
construction quality,
compliance to design
max. current density current density, RH operating voltage by using the E-model [4] or 1/E model
rules
[5, 6]. The 1/E model was proposed based on anode hole
9. PERFORM
PKG / PROCESS
10. WLR/ALR
TEST
11. FINALIZE POR injection (AHI) [5]. This model claims traps are caused
(Process of Record)
SIMULATIONS CHARACTERIZATION
by energy dissipation from electrons Fowler-Nordheim
• Thermal, electrical, • Gate Oxide QBD, HCI,
tunneling through the gate oxide. In this case, time to
mechanical, NBTI, HTRB, bond shear
failure (TTF) was proportional to the inverse of the
Figure 1: Process of FMDRC [3]. applied gate oxide electric field, TTF ~ exp(G/E), where
G is the electric field acceleration parameter. The
E-model (thermochemical model) [4] claims traps are
880 caused by dipole moments interacting with the electric
870 y = -2.424ln(x) + 868.75 field across the gate oxide. In this model, time to failure
R² = 0.9631
860
can be written as TTF ~ exp(-ȖE), where Ȗ is the electric
B
850
field acceleration parameter.
V 840
y = -3.144ln(x) + 830.43
830 R² = 0.9083
(

V
820 These two models fit the data very well at the stress
)

810 conditions. The question is which model we should use

800
790
1 10 100
Stress Time (seconds)
W8 POR (Pass + PIX), (37,21)
W8 POR (Pass + PIX) (34,18)
W13 PIX only (no PASS) (36, 22)
Log. (W8 POR (PASS + PIX) (36,22))
Figure 2: JFET BV degradation at HTRB stress at 125C.
Using the BIR approach, we can understand how
vulnerable our technologies are to specific failure
mechanisms, and we can modify our process and designs
to avoid areas of potential reliability concern. The
product qualification becomes lower risk and requires
fewer resources to verify the reliability that has already
been built in.
In addition, we use fast WLR testing as an on-going
process reliability monitor of critical process modules.
Maintaining tight distributions of reliability metrics is
crucial for IC reliability. The fast WLR monitors include
GOI (Jramp and Vramp), P2IC, SWEAT (Standard
Wafer-level Electromigration Accelerated Test), SM,
IMD, mobile ion contamination, and threshold voltage
(Vth) instability.
1000 10000 100000
W8 POR (PASS + PIX) (36,22)
W13 PIX only (no Pass) (37,21)
W13 PIX only (np Pass) (34, 18)
Log. (W13 PIX only (np Pass) (34, 18))
to extrapolate to operating conditions. The E-model
gives a shorter time to failure than the 1/E model at
operating conditions. So to be conservative, we here use
the E-model [7]. Based on the experimental data and the
E-model, we provide the gate oxide failure rate with
different voltages and temperature to designers through a
calculator. The designer uses this information to obtain
the maximum operation voltage (plus a voltage tolerance
of up to 10%) allowed across the gate oxide. The gate
oxide failure rate is cumulative in time. That means any
voltage across the gate will reduce the gate oxide time to
failure and increase the failure rate. For example,
voltage overshooting during switching must be
considered in gate oxide failure rate calculations.
For GOI, we also perform charge to breakdown (Qbd)
testing by using a fast Jramp or Vramp [8]. The Qbd data
is shown in Fig. 4. The data exhibits a bimodal
distribution: the intrinsic distribution and extrinsic
distribution. The question is how to reduce or eliminate
the extrinsic defects in the gate oxide. We have
employed an Elevated Voltage Screening (EVS) method
as shown in Fig. 5. The infant failure caused by oxide
defects are significantly reduced by performing the EVS
method, greatly increasing product quality. Note that the
TDDB data of Fig. 3 show no defect tail. This is because
in Qbd testing, the sample size is over 20 times larger than
in TDDB testing, so the total gate oxide area sampled is
much larger.
widely used in smart power applications with currents in
the 1-5 ampere range and voltages in the 20-100 volt
range [9]. For these devices, total channel resistance,
Rdson, is the most important parameter. One of the main
reliability issues during device and process development
is to obtain the best trade-off between Rdson and hot
carrier degradation. Rdson can be reduced by increasing
the drift region doping concentration or shrinking the drift
region length. These changes result in higher lateral
electric field in the drift region and increase hot carrier
degradation.

Hot carrier stress on LDMOSFETs is performed by

applying constant DC drain and gate voltages at room
temperature. Device parameters, including linear region
drain current, (Idlin, directly related to Rdson),
transconductance (GM), threshold voltage (Vth), and
Figure 3: TDDB Stress data with three different gate
saturation drain current (Idsat), are measured at
oxide stress fields. Gate oxide thickness is 11.5 nm.
logarithmic time intervals by removing the stress bias and
performing the device measurements. In this example,
the device is an n-type LDMOSFET processed in a 0.5um
CMOS technology as shown in Fig. 6. The gate oxide
thickness is 11.5nm.

Gate Gate
Drain Drain
Source

N+ N+ P+ N+ N+
N drift PBODY N drift

N-tub

Qbd (C/cm^2)
Figure 4: Qbd Weibull distribution by using Jramp test.
Figure 6: Cross section of LNDMOS structure.

After E screening Unlike conventional LDD CMOS devices, LDMOS

devices can show maximum HCI degradation at a bias
different from the bias giving peak substrate current
Weibull Plot

[9,10]. One needs to first find the bias value, that is, the
Vgs at max operating Vds, that results in the most HCI
Before screening degradation. The results of such a study are shown in
After ideal screening
Fig. 7. The data shows that Vth and Idsat have a
negligible degradation, whereas Idlin and GM exhibit
significant degradation. The worst Rdson and Idlin
degradation is at approximately Vgs=2 V, which is not at
Qbd or Tbd peak substrate current. The Vgs at the first peak
substrate current is about 1.5 V. At a Vgs ~ 2 V stress
Figure 5: EVS Method for screening the defects in gate condition, the data strongly suggested that the
oxide. degradation is due to interface trapped charge which was
generated by HCI stress in the interface between Si and
field oxide near the bird’s beak and accumulation region.
4. HCI Effects on LDMOS
This interface charge attracts holes and depletes the
negative charge in the n-drift region, increasing Rdson.
LDMOSFETs (Laterally Diffused MOSFETs) have been This effect has the greatest impact on Rdson since the
 Idlin current path is along the interface between Si and the 1-7 (1991).
field oxide. This also can explain why the Vth and Idsat [2] AIAG, “Potential Failure Mode and Effect Analysis
have a very small degradation since the interface trapped (FMEA),” 4th Edition, Automotive Industry Action
charge from HCI stress is located near the isolation bird’s Group (2008).
beak. [3] Mark Rioux, “Built in Reliability,” The Quality
Management Forum, Vol. 33, p. 4 (2007).
10.00
10.00
[4] J. W. McPherson and H.C. Mogul, “Underlying
physics of the thermochemical E model in describing
Percent Degradation
Percent Degradation

1.00
low-field time-dependent dielectric breakdown in SiO2
1.00 thin films,” J. Appl. Phys., Vol. 84, p.1513 (1998).
0.10
[5], I.C. Chen, S. Holland, and C. Hu, “A quantitative
physical model for time-dependent breakdown in SiO2,”
0.10 0.01
IRPS 1985, Vol. 23, p. 24 (1985).
50 500 5000 50000 500000
50 500 5000 50000 500000
Stress time (sec)
[6], E.Y. Wu, W.W. Abadeer, L.-K. Han, S.H. Ho, and G.
Stress time (sec)
IDLIN_1.258 IDLIN_1.48 IDLIN_1.554 IDLIN_1.702
GM_MAX_1.258 GM_MAX_1.48 GM_MAX_1.554 Huechel, “Challenges for accurate reliability projections
GM_MAX_1.702 GM_MAX_1.85 GM_MAX_3.2
IDLIN_1.85 IDLIN_3.2 IDLIN_4.5 GM_MAX_4.5 in the ultra-thin oxide regime,” IRPS 1999, Vol. 37, p. 57
(1999).
(a) (b) [7], J.W. McPherson, “Reliability Physics and
0.1000 10.00
Engineering,” p. 171, Springer (2010).
0.0100 [8], JEDEC JP001 (2006).
Percent Degradation

[9], P. Moens, J. Mertens, F. Bauwens, P. Joris, W. De

Vt shift (V)

0.0010
1.00 Cenuinck, and M. Tack, “A Comprehensive Model for
Hot Carrier Degradation In LDMOS Transistors,” IRPS
2007, p. 492 (2007).
0.0001

0.0000
[10], D. Brisbin, P. Lindorfer, and P. Chaparala,
50 500 5000 50000 500000
0.10
50 500 5000 50000 500000
“Anomalous Safe Operating Area and Hot Carrier
V_TH_1.258 V_TH_1.48
Stress time (sec)
V_TH_1.554 V_TH_1.702
Stress time (sec) Degradation of NLDMOS Devices,” IRPS 2006, p. 364
V_TH_1.85 V_TH_3.2 V_TH_4.5
IDSAT_1.258
IDSAT_1.85
IDSAT_1.48
IDSAT_3.2
IDSAT_1.554
IDSAT_4.5
IDSAT_1.702
(2006).
(c) (d)
Figure 7 (a): HCI Idlin degradation; (b): HCI GM
degradation, (c): HCI Vth Degradation; (d): HCI Idsat
degradation.

5. Summary

In this paper, we discussed the Building-In Reliability

methodology as used in BCD technology development.
By using this approach, we get a clear understanding of
the process and device reliability risks before products are
introduced to customers.

Acknowledgment

The authors would like to thank James Colbath and

Robert Murphy for testing support and Mark Rioux for
helpful discussions and management support.

References

[1] H.A. Schafft, D.A. Baglee, P.E. Kennedy,

“Building-In Reliability: Making It Work,” IRPS 1991, pp.

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