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Partially and Fully Depleted SOI MOSFETs

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 Partially and Fully Depleted SOI MOSFET’s

Rituraj
Dept. of Electrical Engineering
IIT Kanpur
Kanpur, India
rituraj@iitk.ac.in

Abstract— A physics based analytical model for partially and

fully depleted MOSFET’s is presented. Various non-idealities like II. PDSOI MOSFET MODEL
short channel effects, floating body effect etc. present in a A PDSOI MOSFET is similar to a bulk MOSFET and hence
MOSFET are also discussed. Several devices based on PDSOI or the I-V characteristics are also similar. Following model [25] is
FDSOI are contrasted qualitatively.
presented for an n channel MOSFET working in strong
Index Terms— Modelling, short channel effects, electrostatic inversion region (VGS > VT).
control, scaling, SOI substrate.
𝑊 1
′
𝜇𝑁 𝐶𝑂𝑋 ((𝑉𝐺𝑆 − 𝑉𝑇 )2 − 𝑉𝐷𝑆 2 ) ; 𝑉𝐷𝑆 < 𝑉𝐷𝑆𝐴𝑇
I. INTRODUCTION 𝐿 2
𝐼𝐷𝑆 = { (1)
The quest for scaling down MOSFET size has been going on 1𝑊
𝜇 𝐶 ′ (𝑉 − 𝑉𝑇 )2 (1 + 𝜆𝑁 𝑉𝐷𝑆 ); 𝑉𝐷𝑆 > 𝑉𝐷𝑆𝐴𝑇
since its advent due to obvious advantages like speed 2 𝐿 𝑁 𝑂𝑋 𝐺𝑆
enhancement, reduction in power consumption and cost [22].
The conventional bulk Si MOSFET has already reached its limit Similarly the current in weak inversion region varies
and can’t be scaled down any more without compromising any exponentially with the gate voltage. The above model is the
performance metric. Many novel device structures [2,15] like Level 1 NMOS model and only an approximation. A surface
FinFET, multiple gate (MuGate), gate all around (GAA), ultra potential based all region model is succinctly given below (2).
thin body (UTB) etc. have been proposed to continue the scaling
down to sub-micron range [13,14]. Fully depleted substrate is at 𝑉𝐺𝐵 = Ψ𝑂𝑋 + Ψ𝑆 + 𝑉𝐹𝐵
the heart of all of the above mentioned devices. Fabricating a
device on SOI substrate improves performance by reducing 𝑄𝐺′ + 𝑄𝑂′ + 𝑄𝐶′ = 0
parasitic capacitances and various leakage currents [17]. A SOI
MOSFET is also suitable for uses in harsher environment. This 𝑄𝐺′ = 𝐶𝑂𝑋
′
Ψ𝑂𝑋
motivates one to undertake a study of SOI based devices.
Si body thickness varies for different SOI devices and is
𝑄𝐶′ = −𝑠𝑔𝑛(Ψ𝑆 )√2𝑞𝜖𝑆 𝑁𝐴 ∗
tailored based on specific application. A SOI MOSFET with
thick Si body is similar to a bulk MOSFET (except for floating 2𝜙𝐹 +𝑉𝐶𝐵 Ψ𝑆
√𝜙 𝑒 −Ψ𝑆 /𝜙𝑡 + Ψ − 𝜙 + 𝑒 − 𝜙𝑡 (𝜙 𝜙
body effects). For such devices the depletion region depth below 𝑡 𝑆 𝑡 𝑡𝑒 𝑡 − Ψ𝑆 − 𝜙𝑡 )
the gate is smaller than the body thickness and hence the name
Partially Depleted SOI MOSFET. SOI devices with very thin Si 𝑄𝐶′ = 𝑄𝐵′ + 𝑄𝐼′
body (which is fully depleted) have better control of gate over
channel and thus reduced short channel and floating body 𝑄𝐵′ = −√2𝑞𝜖𝑆 𝑁𝐴 𝐶𝑂𝑋
′
√Ψ𝑠
effects. This enables scaling down of channel lengths up to nm
range. Generally the body in such a device is either undoped or
The above equations are non-linear and can be solved
very lightly doped reducing the random dopant effects [6,10].
numerically or using suitable approximations for different
Also the subthreshold swing in FDSOI is close to unity (ideal).
modes of operation. Also note that Ψ𝑆 , 𝑄𝐵′ , 𝑄𝐼′ 𝑒𝑡𝑐. are
This paper is organized as follows. In section II a model for
functions of position when a drain to source bias is applied. The
PDSOI MOSFET is presented. Floating body and associated
problem becomes 2-D and can be solved using only numerical
kink effects present in a PDSOI device are also discussed. In
techniques. To simplify the situation “gradual channel
section III a surface potential based model is derived for FDSOI
approximation” is made which is justified for long channel
under different modes of operation. In section IV novel devices
devices and small horizontal electric fields. The error made by
– FinFETs, MuGate and GAA and their corresponding scaling
such simplification is modelled as various short channel effects.
is presented. Some non-idealities associated with these devices
In steady state current is same at all points and consists of drift
are also introduced. Conclusion is presented along with a short
and diffusion components which can be position dependent.
discussion of future prospects in the final section V.
𝐼𝐷𝑆 = 𝐼𝑑𝑟𝑖𝑓𝑡 (𝑥) + 𝐼𝑑𝑖𝑓𝑓 (𝑥)
 Fig.1 – PDSOI and FDSOI MOSFET’s Fig.2 – Kinks in I-V curves because of FBE

𝑑Ψ𝑆 III. EFFECTS OF FLOATING SUBSTRATE POTENTIAL

𝐼𝑑𝑟𝑖𝑓𝑡 (𝑥) = 𝜇𝑊(−𝑄𝐼′ )
𝑑𝑥
In this section we analyze the non-idealities arising from the
𝑑𝑄𝐼′ floating body in a PDSOI device [3,9].
𝐼𝑑𝑖𝑓𝑓 (𝑥) = 𝜇𝑊𝜙𝑡
𝑑𝑥 A. Threshold voltage change
′
In saturation the electrons gain very high kinetic energy near
Ψ𝑆𝐿 𝑄𝐼𝐿
the drain because of large electric fields present and thus may
𝑊
𝐼𝐷𝑆 = 𝜇 [ ∫ (−𝑄𝐼′ )𝑑Ψ𝑆 + 𝜙𝑡 ∫ 𝑑𝑄𝐼′ ] cause avalanche generation of electron hole pairs (EHPs). The
𝐿 electrons flow towards the drain whereas the holes are swept by
Ψ𝑆0 ′
𝑄𝐼0
the field in the body. This increases the substrate potential and
results in lowering of threshold voltage leading to further rise in
Again the above expression can be only evaluated numerically the drain current. This is observed as the first kink in Fig.2.
because 𝑄𝐼′ is a complex function of Ψ𝑆 . In strong inversion
using some approximation an explicit expression for 𝐼𝐷𝑆 is B. Parasitic Bipolar Transistor
obtained as given in (equ.-1). This model can be further If the body current and substrate resistance is significant, the
modified to incorporate short channel effects considering one substrate voltage can rise to an extent where the source-body
effect at a time. Thus a semi-empirical model is obtained whose junction gets forward biased. If the drain voltage is increased
parameters can be adjusted suitably to model different devices. further the hole current would also rise, but this doesn’t change
Note that the substrate voltage appreciably because of the forward biased
𝑊 diode action. A MOSFET inherently has a npn structure but
𝐼𝐷𝑆 = 𝐹(Ψ𝑆𝐿 , Ψ𝑆0 )
𝐿 normally the neutral base width is too large for any transistor
action to occur. With sufficiently high VDS the body nearby the
𝑊 drain can get completely depleted decreasing the neutral base
𝐼𝐷𝑆 = 𝐹(Ψ𝑆 (𝑥), Ψ𝑆0 )
𝑥 width. The length of undepleted substrate is also a strong
function of surface potential. When the MOSFET is on the
𝑥 𝐹(Ψ𝑆 (𝑥), Ψ𝑆0 ) substrate can get completely depleted if the surface potential
=
𝐿 𝐹(Ψ𝑆𝐿 , Ψ𝑆0 ) 𝑉𝐶𝐵 (𝑥) is larger than 𝑉𝐷𝑒 which is given by
𝑡𝑆𝑖 2
Ψ𝑆0 and Ψ𝑆𝐿 can be computed from equation set (2) by 𝑉𝐷𝑒 = 𝑞𝑁𝐴
2𝜖𝑆
substituting 𝑉𝐶𝐵 = 𝑉𝑆𝐵 and 𝑉𝐷𝐵 respectively. So the above In such a case the neutral base width can reduce to the extent of
equation gives the relationship between x and Ψ𝑆 (𝑥). allowing the BJT action. The neutral base width (WB) can be
determined as follows. For this analysis it has been assumed that
VDS has been fixed at VDSat.
 2
𝑥 2𝑉𝐺𝑆 𝑉𝐶𝑆 (𝑥) − 𝑉𝐶𝑆 (𝑥) IV. FDSOI MOSFET MODEL
= 2
𝐿 𝑉𝐺𝑆 In a FDSOI MOSFET the Si substrate being very thin is fully
depleted eliminating any floating body effect. The front and
2
𝑊𝐵 2𝑉𝐺𝑆 𝑉𝐷𝑒 − 𝑉𝐷𝑒 back gates (bulk Si below the insulator can be viewed as the
= 2 <1 second gate) are electrostatically coupled. Unlike PDSOI, Ψ𝑆𝐹
𝐿 𝑉𝐺𝑆
is a function of Ψ𝑆𝐵 . This is shown in the figure below. Only the
Fig.4 shows the variation of normalized base width with 𝑉𝐺𝑆 and valence and conduction band edges are shown for simplicity.
substrate doping. The variation of effective of the parasitic
BJT with 𝑉𝐺𝑆 , channel length and lifetime is shown in Fig.5.

Fig.6 – Band diagram of PDSOI and FDSOI

Fig.3 – Parasitic BJT and EHP generation in drain region
So, a based on front and back gate biasing FDSOI device can
operate in 9 different modes as shown below for an n type
MOSFET [12].

Fig.7 – Various modes of operation of FDSOI MOSFET

The surface potential based analysis for FDSOI is fundamentally

similar to that for a bulk Si MOSFET and is presented below
[5,12,21,23,24]. All relevant parameters are shown in Fig.8.
First let’s consider FDSOI electrostatics without any drain or
source biasing. As in conventional MOSFET it’s assumed that
all the mobile charges are present at Si surface (delta-depletion
approximation).
Applying Gauss’ law to FD bulk:

−
𝑞𝑁𝐴 𝑡𝑆𝑖 𝑄𝐵′
𝐸(𝑡𝑆𝑖 ) − 𝐸(0+ ) = − =
𝜖𝑆𝑖 𝜖𝑆𝑖
 From the equations (3) and (4) it can be seen that for a given
1 − 𝑉𝐺𝐹 increasing 𝑉𝐺𝐵 increases Ψ𝑆𝐹 , thus effectively reducing
∆Ψ = Ψ𝑆𝐹 − Ψ𝑆𝐵 = (𝐸(𝑡𝑆𝑖 ) + 𝐸(0+ ))𝑡𝑆𝑖
2 𝑉𝑇𝐹 . So the back gate (substrate) biasing can be used to tune
the threshold voltage. This is shown in fig.9 and is modelled
−
From these equations we get expressions for 𝐸(𝑡𝑆𝑖 ) and 𝐸(𝑡0+ ) below for different regions [8].

Fig.8

Fig.9 – Threshold voltage control using back gate in FDSOI

Ψ𝑆𝐹 − Ψ𝑆𝐵 𝑞𝑁𝐴 𝑡𝑆𝑖 A. Back Inverted ( 𝛹𝑆𝐵 = 2𝜙𝐵 )

𝐸(0+ ) = +
𝑡𝑆𝑖 2𝜖𝑆𝑖
𝑄𝐵′
𝑉𝑇𝐹 = 𝑉𝐹𝐵𝐹 + 2𝜙𝐵 − ′
Ψ𝑆𝐹 − Ψ𝑆𝐵 𝑞𝑁𝐴 𝑡𝑆𝑖 2𝐶𝑂𝐹
−
𝐸(𝑡𝑆𝑖 )= −
𝑡𝑆𝑖 2𝜖𝑆𝑖
Even when 𝑉𝐺𝐹 < 𝑉𝑇𝐹 current flows because the back
′
𝑉𝐺𝐹 − Ψ𝑆𝐹 side remains inverted and the device does not turn off.
′
𝐸0𝐹 = 𝑤ℎ𝑒𝑟𝑒 𝑉𝐺𝐹 = 𝑉𝐺𝐹 − 𝑉𝐹𝐵𝐹 So this mode of operation is not useful.
𝑡𝑂𝐹
B. Back Accumulated ( 𝛹𝑆𝐵 ≈ 0 )
𝜖𝑂𝑥 𝐸0𝐹 = 𝜖𝑆𝑖 𝐸(0+ ) − 𝑄𝐼𝐹
′

′ ′ 𝑄𝐵′ 𝐶𝑆𝑖′
𝜖𝑂𝑥 𝑉𝐺𝐹 − Ψ𝑆𝐹 𝑄𝐼𝐹 𝑉𝑇𝐹 = 𝑉𝐹𝐵𝐹 + 2𝜙𝐵 − + ′ 2𝜙𝐵
𝐸(0+ ) = + ′
2𝐶𝑂𝐹 𝐶𝑂𝐹
𝜖𝑆𝑖 𝑡𝑂𝐹 𝜖𝑆𝑖
For the aforementioned regions, this mode of operation
Doing a similar analysis for back gate -
is also not useful.
′ ′ Now the total shift ∆𝑉𝑇𝐹 can be obtained.
−
𝜖𝑂𝑥 Ψ𝑆𝐵 − 𝑉𝐺𝐵 𝑄𝐼𝐵
𝐸(𝑡𝑆𝑖 )= −
𝜖𝑆𝑖 𝑡𝑂𝐵 𝜖𝑆𝑖 ∆𝑉𝑇𝐹 = 𝑉𝑇𝐹 (𝑏𝑎𝑐𝑘 𝑎𝑐𝑐) − 𝑉𝑇𝐹 (𝑏𝑎𝑐𝑘 𝑖𝑛𝑣)
Eliminating the field terms from these equations – 𝐶𝑆𝑖′ 𝜖𝑆𝑖 𝑡𝑂𝐹
∆𝑉𝑇𝐹 = ′ 2𝜙𝐵 = 2𝜙𝐵
𝑄 ′ 𝐶𝑂𝐹 𝜖𝑜𝑥 𝑡𝑆𝑖
′
𝑄𝐼𝐹 + 2𝐵 ′
𝐶𝑆𝑖
𝑉𝐺𝐹 = 𝑉𝐹𝐵𝐹 + Ψ𝑆𝐹 − ′ + ′ (Ψ𝑆𝐹 − Ψ𝑆𝐵 ) (3) ′
𝐶𝑂𝐹 𝐶𝑂𝐹 C. Back Depleted (𝑄𝐼𝐵 ≈ 0)
𝑄 ′
′
𝑄𝐼𝐵 + 2𝐵 ′
𝐶𝑆𝑖 We need to relate Ψ𝑆𝐵 to 𝑉𝐺𝐵 . This can be done in a
𝑉𝐺𝐵 = 𝑉𝐹𝐵𝐵 + Ψ𝑆𝐵 − ′ − ′ (Ψ𝑆𝐹 − Ψ𝑆𝐵 ) (4) similar manner as in bulk Si MOSFET [25]. But exact
𝐶𝑂𝐵 𝐶𝑂𝐵
analysis is complex and gives only an implicit
From equation (3) ,𝑉𝑇𝐹 is obtained by setting Ψ𝑆𝐹 = 2𝜙𝐵 equation. For our purpose, we assume that 𝑉𝑇𝐹 varies
linearly with 𝑉𝐺𝐵 . Thus the task is to find the
𝑄𝐵′ 𝐶𝑆𝑖′ corresponding slope or rate of change. Note that this
𝑉𝑇𝐹 = 𝑉𝐹𝐵𝐹 + 2𝜙𝐵 − ′ + ′ (2𝜙𝐵 − Ψ𝑆𝐵 ) approximation is very good as seen from fig.9.
2𝐶𝑂𝐹 𝐶𝑂𝐹
At front threshold (or beyond) Ψ𝑆𝐹 = 2𝜙𝐵
 ′ ′
𝑄𝐵 𝐶𝑆𝑖
𝑉𝐺𝐵 = 𝑉𝐹𝐵𝐵 + Ψ𝑆𝐵 − ′ − ′ (2𝜙𝐵 − Ψ𝑆𝐵 ) (5)
2𝐶𝑂𝐵 𝐶𝑂𝐵

At the start of back accumulation ( Ψ𝑆𝐵 = 0 )

′ ′
𝑄𝐵 𝐶𝑆𝑖
𝑉𝐺𝐵 (𝑎𝑐𝑐) = 𝑉𝐹𝐵𝐵 − ′ − ′ 2𝜙𝐵 (6)
2𝐶𝑂𝐵 𝐶𝑂𝐵

The back surface is depleted when 𝑉𝐺𝐵 > 𝑉𝐺𝐵 (𝑎𝑐𝑐).

From equations (5) and (6) –
′
𝐶𝑂𝐵
Ψ𝑆𝐵 = (𝑉 − 𝑉𝐺𝐵 (𝑎𝑐𝑐))
′
𝐶𝑂𝐵+ 𝐶𝑆𝑖′ 𝐺𝐵

Using this in equation and then differentiating –

𝑑𝑉𝑇𝐹 𝑡𝑂𝐹 1
=− X
𝑑𝑉𝐺𝐵 𝑡𝑂𝐵 𝐶′
1 + 𝑂𝐵
𝐶𝑆𝑖′
The above figure shows Drain induced barrier lowering (DIBL),
a short channel effect present in MOSFET devices [7,20].
Similarly subthreshold swing (m) can be computed.
Following figure shows the dependence of minimum possible
gate length on silicon thickness. Beyond this critical length
𝑑𝑉𝐺𝐹 𝐶𝑆𝑖′ 𝐶𝑂𝐵
′
𝑚= = 1+ ′ electrostatic integrity of device is lost [1].
′
𝑑 Ψ𝑆𝐹 𝐶𝑂𝐵 (𝐶𝑂𝐵 + 𝐶𝑆𝑖′ )

′
If the bottom oxide is thick 𝐶𝑂𝐵 < 𝐶𝑆𝑖′ , 𝑚 → 1
So an ideal subthreshold swing is obtained.

V. MOSFET ARCHITECTURES BASED ON THIN (FD) SUBSTRATE

Having thin body, increases the control of gate over the drain
current as the conduction occurs quite close to the gate. This
mitigates the short channel effects present in conventional
MOSFETs and thus helps in further scaling down of device
sizes[4,6,18,19]. Similarly increasing the number of gates adds
further control on channel. Gate all around (GAA) device is the
ultimate device using this approach. This is shown in the figure
below [1].

VI. CONCLUSION
In this paper we discussed the scaling bottlenecks for
conventional MOSFET’s and motivated the need for PDSOI and
FDSOI based devices. SOI devices offer less parasitics but
suffer from self heating effects. We then presented a physics
based model for PDSOI device and analyzed floating body
effects namely threshold voltage lowering and parasitic BJT
effects. A FDSOI device has no such problems and allows for a
tighter gate control over channel because of better electrostatics.
We also derived a surface potential based model for FDSOI
devices. The threshold voltage can be tuned using back gate bias.
A simple model was presented showing this dependence for
various modes of operation. An ideal subthreshold swing is yet
another benefit of FDSOI devices. We also derived an
expression for the same and discussed the design criteria
required for improving this factor. Various devices architectures
exist today based on FD body. A brief introduction to such
devices was given along with their scaling issues. These devices
can be analyzed in a similar manner as adopted in this paper.
Improved short channel effects in such devices was also
discussed using 2-D simulation results. All these device
structures are promising and it’s difficult to predict which one
would be adopted for nanometer size devices. Fabrication issues
(cost , compatibility with present technology etc.) are likely to
play a deciding role in this regard [1,6,11,15,16,22].
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