Computer System Organization

Unit 1 :STRUCTURES OF COMPUTER AND MICRO OPERATION
Functional Units of Digital System
o A computer organization describes the functions and design of the various units of a digital system.
o A general-purpose computer system is the best-known example of a digital system. Other examples
include telephone switching exchanges, digital voltmeters, digital counters, electronic calculators and
digital displays.
o Computer architecture deals with the specification of the instruction set and the hardware units that
implement the instructions.
o Computer hardware consists of electronic circuits, displays, magnetic and optic storage media and
also the communication facilities.
o Functional units are a part of a CPU that performs the operations and calculations called for by the
computer program.
o Functional units of a computer system are parts of the CPU (Central Processing Unit) that performs
the operations and calculations called for by the computer program. A computer consists of five main
components namely, Input unit, Central Processing Unit, Memory unit Arithmetic & logical unit,
Control unit and an Output unit.
Input unit
o Input units are used by the computer to read the data. The most commonly used input devices are
keyboards, mouse, joysticks, trackballs, microphones, etc.
o However, the most well-known input device is a keyboard. Whenever a key is pressed, the
corresponding letter or digit is automatically translated into its corresponding binary code and
transmitted over a cable to either the memory or the processor.
Central processing unit
o Central processing unit commonly known as CPU can be referred as an electronic circuitry within a
computer that carries out the instructions given by a computer program by performing the basic
arithmetic, logical, control and input/output (I/O) operations specified by the instructions.
Memory unit
o The Memory unit can be referred to as the storage area in which programs are kept which are
running, and that contains data needed by the running programs.
o The Memory unit can be categorized in two ways namely, primary memory and secondary memory.
o It enables a processor to access running execution applications and services that are temporarily
stored in a specific memory location.
o Primary storage is the fastest memory that operates at electronic speeds. Primary memory contains
a large number of semiconductor storage cells, capable of storing a bit of information. The word
length of a computer is between 16-64 bits.
o It is also known as the volatile form of memory, means when the computer is shut down, anything
contained in RAM is lost.
o Cache memory is also a kind of memory which is used to fetch the data very soon. They are highly
coupled with the processor.
o The most common examples of primary memory are RAM and ROM.
o Secondary memory is used when a large amount of data and programs have to be stored for a long-
term basis.
o It is also known as the Non-volatile memory form of memory, means the data is stored permanently
irrespective of shut down.
o The most common examples of secondary memory are magnetic disks, magnetic tapes, and optical
disks.
Arithmetic & logical unit
o Most of all the arithmetic and logical operations of a computer are executed in the ALU (Arithmetic
and Logical Unit) of the processor. It performs arithmetic operations like addition, subtraction,
multiplication, division and also the logical operations like AND, OR, NOT operations.
Control unit
o The control unit is a component of a computer's central processing unit that coordinates the
operation of the processor. It tells the computer's memory, arithmetic/logic unit and input and
output devices how to respond to a program's instructions.
o The control unit is also known as the nerve center of a computer system.
o Let's us consider an example of addition of two operands by the instruction given as Add LOCA, RO.
This instruction adds the memory location LOCA to the operand in the register RO and places the sum
in the register RO. This instruction internally performs several steps.
Output Unit
o The primary function of the output unit is to send the processed results to the user. Output devices
display information in a way that the user can understand.
o Output devices are pieces of equipment that are used to generate information or any other response
processed by the computer. These devices display information that has been held or generated
within a computer.
o The most common example of an output device is a monitor.
Von-Neumann Model
Von-Neumann proposed his computer architecture design in 1945 which was later known as Von-Neumann
Architecture. It consisted of a Control Unit, Arithmetic, and Logical Memory Unit (ALU), Registers and
Inputs/Outputs.
Von Neumann architecture is based on the stored-program computer concept, where instruction data and
program data are stored in the same memory. This design is still used in most computers produced today.
A Von Neumann-based computer:

o Uses a single processor
o Uses one memory for both instructions and data.
o Executes programs following the fetch-decode-execute cycle
Components of Von-Neumann Model:
o Central Processing Unit

o Buses
o Memory Unit
Central Processing Unit
The part of the Computer that performs the bulk of data processing operations is called the Central
Processing Unit and is referred to as the CPU.
The Central Processing Unit can also be defined as an electric circuit responsible for executing the
instructions of a computer program.
The CPU performs a variety of functions dictated by the type of instructions that are incorporated in the
computer.
The major components of CPU are Arithmetic and Logic Unit (ALU), Control Unit (CU) and a variety of
registers.
Arithmetic and Logic Unit (ALU)
The Arithmetic and Logic Unit (ALU) performs the required micro-operations for executing the instructions.
In simple words, ALU allows arithmetic (add, subtract, etc.) and logic (AND, OR, NOT, etc.) operations to be
carried out.
Control Unit
The Control Unit of a computer system controls the operations of components like ALU, memory and
input/output devices.
The Control Unit consists of a program counter that contains the address of the instructions to be fetched
and an instruction register into which instructions are fetched from memory for execution.
Registers
Registers refer to high-speed storage areas in the CPU. The data processed by the CPU are fetched from the
registers.
Following is the list of registers that plays a crucial role in data processing.
Registers Description
MAR (Memory Address This register holds the memory location of the data that needs to be
Register) accessed.
MDR (Memory Data Register) This register holds the data that is being transferred to or from memory.
AC (Accumulator) This register holds the intermediate arithmetic and logic results.
PC (Program Counter) This register contains the address of the next instruction to be executed.
CIR (Current Instruction This register contains the current instruction during processing.
Register)
Buses
Buses are the means by which information is shared between the registers in a multiple-register
configuration system.
A bus structure consists of a set of common lines, one for each bit of a register, through which binary
information is transferred one at a time. Control signals determine which register is selected by the bus
during each particular register transfer.
Von-Neumann Architecture comprised of three major bus systems for data transfer.
Bus Description
Address Address Bus carries the address of data (but not the data) between the processor and the
Bus memory.
Data Bus Data Bus carries data between the processor, the memory unit and the input/output
devices.
Control Bus Control Bus carries signals/commands from the CPU.

Memory Unit
A memory unit is a collection of storage cells together with associated circuits needed to transfer information
in and out of the storage. The memory stores binary information in groups of bits called words. The internal
structure of a memory unit is specified by the number of words it contains and the number of bits in each
word.
Two major types of memories are used in computer systems:
1. RAM (Random Access Memory)

2. ROM (Read-Only Memory)
Bus and Memory Transfers
A digital system composed of many registers, and paths must be provided to transfer information from one
register to another. The number of wires connecting all of the registers will be excessive if separate lines are
used between each register and all other registers in the system.
A bus structure, on the other hand, is more efficient for transferring information between registers in a multi-
register configuration system.
A bus consists of a set of common lines, one for each bit of register, through which binary information is
transferred one at a time. Control signals determine which register is selected by the bus during a particular
register transfer.
The following block diagram shows a Bus system for four registers. It is constructed with the help of four 4 *
1 Multiplexers each having four data inputs (0 through 3) and two selection inputs (S1 and S2).
We have used labels to make it more convenient for you to understand the input-output configuration of a
Bus system for four registers. For instance, output 1 of register A is connected to input 0 of MUX1.
The two selection lines S1 and S2 are connected to the selection inputs of all four multiplexers. The selection
lines choose the four bits of one register and transfer them into the four-line common bus.
When both of the select lines are at low logic, i.e. S1S0 = 00, the 0 data inputs of all four multiplexers are
selected and applied to the outputs that forms the bus. This, in turn, causes the bus lines to receive the
content of register A since the outputs of this register are connected to the 0 data inputs of the multiplexers.
Similarly, when S1S0 = 01, register B is selected, and the bus lines will receive the content provided by
register B.
The following function table shows the register that is selected by the bus for each of the four possible binary
values of the Selection lines.
A bus system can also be constructed using three-state

gates instead of multiplexers.
The three state gates can be considered as a digital circuit that has three gates, two of which are signals
equivalent to logic 1 and 0 as in a conventional gate. However, the third gate exhibits a high-impedance
state.
The most commonly used three state gates in case of the bus system is a buffer gate.
The graphical symbol of a three-state buffer gate can be represented as:
The following diagram demonstrates the construction of a bus system with three-state buffers.
o The outputs generated by the four buffers are connected to form a single bus line.
o Only one buffer can be in active state at a given point of time.
o The control inputs to the buffers determine which of the four normal inputs will communicate with
the bus line.
o A 2 * 4 decoder ensures that no more than one control input is active at any given point of time.
Memory Transfer
Most of the standard notations used for specifying operations on memory transfer are stated below.
o The transfer of information from a memory unit to the user end is called a Read operation.
o The transfer of new information to be stored in the memory is called a Write operation.
o A memory word is designated by the letter M.
o We must specify the address of memory word while writing the memory transfer operations.
o The address register is designated by AR and the data register by DR.
o Thus, a read operation can be stated as:
1. Read: DR ← M [AR]
o The Read statement causes a transfer of information into the data register (DR) from the memory
word (M) selected by the address register (AR).
o And the corresponding write operation can be stated as:
1. Write: M [AR] ← R1
o The Write statement causes a transfer of information from register R1 into the memory word (M)
selected by address register (AR).
Basic Operational Concepts
o The primary function of a computer system is to execute a program, sequence of instructions. These
instructions are stored in computer memory.
o These instructions are executed to process data which are already loaded in the computer memory
through some input devices.
o After processing the data, the result is either stored in the memory for further reference, or it is sent
to the outside world through some output port.
o To perform the execution of an instruction, in addition to the arithmetic logic unit, and control unit,
the processor contains a number of registers used for temporary storage of data and some special
function registers.
o The special function registers include program counters (PC), instruction registers (IR), memory
address registers (MAR) and memory and memory data registers (MDR).
o The Program counter is one of the most critical registers in CPU.
o The Program counter monitors the execution of instructions. It keeps track on which instruction is
being executed and what the next instruction will be.
o The instruction register IR is used to hold the instruction that is currently being executed.
o The contents of IR are available to the control unit, which generate the timing signals that control,
the various processing elements involved in executing the instruction.
o The two registers MAR and MDR are used to handle the data transfer between the main memory and
the processor.
o The MAR holds the address of the main memory to or from which data is to be transferred.
o The MDR contains the data to be written into or read from the addressed word of the main memory.
o Whenever the processor is asked to communicate with devices, we say that the processor is servicing
the devices. The processor can service these devices in one of the two ways.
o One way is to use the polling routine, and the other way is to use an interrupt.
o Polling enables the processor software to check each of the input and output devices frequently.
During this check, the processor tests to see if any devices need servicing or not.
o Interrupt method provides an external asynchronous input that informs the processor that it should
complete whatever instruction that is currently being executed and fetch a new routine that will
service the requesting device.
Data Representation in Computer Organization
In computer organization, data refers to the symbols that are used to represent events, people, things and
ideas.
Data Representation
The data can be represented in the following ways:
Data
Data can be anything like a number, a name, notes in a musical composition, or the color in a photograph.
Data representation can be referred to as the form in which we stored the data, processed it and transmitted
it. In order to store the data in digital format, we can use any device like computers, smartphones, and iPads.
Electronic circuitry is used to handle the stored data.
Digitization
Digitization is a type of process in which we convert information like photos, music, number, text into digital
data. Electronic devices are used to manipulate these types of data. The digital revolution has evolved with
the help of 4 phases, starting with the big, expensive standalone computers and progressing to today's digital
world. All around the world, small and inexpensive devices are spreading everywhere.
Binary Digits
The binary digits or bits are used to show the digital data, which is represented by 0 and 1. The binary digits
can be called the smallest unit of information in a computer. The main use of binary digit is that it can store
the information or data in the form of 0s and 1s. It contains a value that can be on/off or true/false. On or
true will be represented by the 1, and off or false will be represented by the 0. The digital file is a simple file,
which is used to collect data contained by the storage medium like the flash drive, CD, hard disk, or DVD.
Representing Numbers
The number can be represented in the following way:
Numeric Data
Numeric data is used to contain numbers, which helps us to perform arithmetic operations. The digital
devices use a binary number system so that they can represent numeric data. The binary number system
can only be represented by two digits 0 and 1. There can't be any other digits like 2 in the system. If we want
to represent number 2 in binary, then we will write it as 10.
Representing Text
The text can be represented in the following ways:
Character Data
Character data can be formed with the help of symbols, letters, and numerals, but they can?t be used in
calculations. Using the character data, we can form our address, hair colour, name, etc. Character data
normally takes the data in the form of text. With the help of the text, we can describe many things like our
father name, mother name, etc.
Digital Devices
Several types of codes are employed by the digital devices to represent character data, including Unicode,
ASCII, and other types of variants. The full form of ASCII is American Standard Code for Information
Interchange. It is a type of character encoding standard, which is used for electronic communication. With
the help of telecommunication equipment, computers and many other devices, ASCII code can represent
the text. The ASCII code needs 7 bits for each character, where the unique character is represented by every
single bit. For the uppercase letter A, the ASCII code is represented as 1000001.
Extended ASCII
Extended ASCII can be described as a superset of ASCII. The ASCII set uses 7 bits to represent every character,
but the Extended ASCII uses 8 bits to represent each character. The extended ASCII contains 7 bits of ASCII
characters and 1 bit for additional characters. Using the 7 bits, the ASCII code provides code for 128 unique
symbols or characters, but Extended ASCII provides code for 256 unique symbols or characters. For the
uppercase letter A, the Extended ASCII code is represented as 01000001.
Unicode
Unicode is also known as the universal character encoding standard. Unicode provides a way through which
an individual character can be represented in the form of web pages, text files, and other documents. Using
ASCII, we can only represent the basic English characters, but with the help of Unicode, we can represent
characters from all languages around the World.
ASCII code provides code for 128 characters, while Unicode provide code for roughly 65,000 characters with
the help of 16 bits. In order to represent each character, ASCII code only uses 1 bit, while Unicode supports
up to 4 bytes. The Unicode encoding has several different types, but UTF-8 and UTF-16 are the most
commonly used. UTF-8 is a type of variable length coding scheme. It has also become the standard character
encoding, which is used on the web. Many software programs also set UTF-8 as their default encoding.
ASCII Code
ASCII code can be used for numerals like phone numbers and social security numbers. ASCII text contains
plain and unformatted text. This type of file will be saved in a text file format, which contains a name ending
with .txt. These files are labelled differently on different systems, like Windows operating system labelled
these files as "Text document" and Apple devices labelled these files as "Plain Text". There will have no
formatting in the ASCII text files. If we want to make the documents with styles and formats, then we have
to embed formatting codes in the text.
Microsoft Excel
Microsoft word is used to create formatted text and documents. It uses the DOCX format to do this. If we
create a new document using the Microsoft Word 2007 or later version, then it always uses DOCX as the
default file format. Apple pages use PAGES format to produce the documents. As compared to Microsoft
Word, it is simpler to create and edit documents using page format. Adobe Acrobat uses the PDF format to
create the documents. The files that saved in the PDF format cannot be modified. But we can easily print
and share these files. If we save our document in PDF format, then we cannot change that file into the
Microsoft Office file or any other file without specified software.
HTML is the hypertext markup language. It is used for document designing, which will be displayed in a web
browser. It uses HTML format to design the documents. In HTML, hypertext is a type of text in any document
containing links through which we can go to other places in the document or in other documents also. The
markup language can be called as a computer language. In order to define the element within a document,
this language uses tags.
Representing Bits and Bytes
The bits and bytes can be represented in the following ways:
Bits and Bytes
In the field of digital communication or computers, bits are the most basic unit of information or smallest
unit of data. It is short of binary digit, which means it can contain only one value, either 0 or 1. So bits can
be represented by 0 or 1, - or +, false or true, off or on, or no or yes. Many technologies are based on bits
and bytes, which is extensively useful to describe the network access speed and storage capacity. The bit is
usually abbreviated as a lowercase b.
In order to execute the instructions and store the data, the bits are grouped into multiple bits, which are
known as bytes. Bytes can be defined as a group of eight bits, and it is usually abbreviated as an uppercase
B. If we have four bytes, it will equal 32 bits (4*8 = 32), and 10 bytes will equal 80 bits (8*10 = 80).
Uses
Bits are used for data rates like speeds while movie download, speed while internet connection, etc. Bytes
are used to get the storage capacity and file sizes. When we are reading something related to digital devices,
it will be frequently encountered references like 90 kilobits per second, 1.44 megabytes, 2.8 gigahertz, and
2 terabytes. To quantify digital data, we have many options such as Kilo, Mega, Giga, Tera and many more
similar terms, which are described as follows:
104 KB: Kb is also called a kilobyte or Kbyte. It is mostly used while referring to the size of small computer
files.
56 Kbps: Kbps is also called kilobit, Kbit or Kb. The 56 kbps means 56 kilobits per second which are used to
show the slow data rates. If our internet speed is 56 kbps, we have to face difficulty while connecting more
than one device, buffering while streaming videos, slow downloading, and many other internet connectivity
problems.
50 Mbps: Mbps is also called Megabit, MB or Mbit. The 50 Mbps means 50 Megabit per second, which are
used to show the faster data rates. If our internet speed is 50 Mbps, we will experience online activity
without any buffering, such as online gaming, downloading music, streaming HD, web browsing, etc. 50
Mbps or more than that will be known as fast internet speed. With the help of fast speed, we can easily
handle more than one online activity for more than one user at a time without major interruptions in
services.
3.2 MB: 3.2 MB is also called Megabyte, MB or MByte. It is used when we are referring to the size of files,
which contains videos and photos.
100 Gbit: 100 Gbit is also called Gigabit or GB. It is used to show the really fast network speeds.
16 GB: 16 GB is also called Gigabyte, GB or GByte. It is used to show the storage capacity.
Data Compression
The digital data is compressed to reduce transmission times and file size. Data compression is the process of
reducing the number of bits used to represent data. Data compression typically uses encoding techniques to
compress the data. The compressed data will help us to save storage capacity, reduce costs for storage
hardware, increase file transfer speed.
Compression uses some programs, which also uses algorithms and functions to find out the way to reduce
the data size. Compression can be referred "zipping". The process of reconstructing files will be known as
unzipping or extracting. The compressed files will contain .gz, or.tar.gz, .pkg, or .zip at the end of the files.
Compression can be divided into two techniques: Lossless compression and Lossy compression.
Lossless Compression
As the name implies, lossless compression is the process of compressing the data without any loss of
information or data. If we compressed the data with the help of lossless compression, then we can exactly
recover the original data from the compressed data. That means all the information can be completely
restored by lossless compression.
Many applications want to use data loss compression. For example, lossless compression can be used in the
format of ZIP files and in the GNU tool gzip. The lossless data compression can also be used as a component
within the technologies of lossy data compression. It is generally used for discrete data like word processing
files, database records, some images, and information of the video.
According to this image, when we compress the original data using the lossless, we are able to restore all
the original data.
Lossy Compression
Lossy compression is the process of compressing the data, but that data cannot be recovered 100% of
original data. This compression is able to provide a high degree of compression, and the result of this
compression will be in smaller compressed files. But in this process, some number of video frames, sound
waves and original pixels are removed forever.
If the compression is greater, then the size of files will be smaller. Business data and text, which needs a full
restoration, will never use lossy compression. Nobody likes to lose the information, but there are a lot of
files that are very large, and we don't have enough space to maintain all of the original data or many times,
we don't require all the original data in the first place. For example, videos, photos and audio recording files
to capture the beauty of our world. In this case, we use lossy compression.
According to this image, when we compress the original data using the lossy, we are only able to restore
some amount of data. We will not restore 100% of the original data.
Types of Operands in Computer Organization
Computer instruction is a binary code that determines the micro-operations in a sequence for a computer.
They are saved in the memory along with the information. Each computer has its specific group of
instructions. They can be categorized into two elements as Operation codes (Opcodes) and Address. Opcodes
specify the operation for specific instructions, and an address determines the registers or the areas used for
that operation.
Operands are definite elements of computer instruction that show what information is to be operated on.
The most important general categories of data are
1. Addresses
2. Numbers
3. Characters
4. Logical data
In many cases, some calculation must be performed on the operand reference to determine the main or
virtual memory address.
In this context, addresses can be considered to be unsigned integers. Other common data types are numbers,
characters, and logical data, and each of these is briefly described below. Some machines define specialized
data types or data structures. For example, machine operations may operate directly on a list or a string of
characters.
Addresses
Addresses are nothing but a form of data. Here some calculations must be performed on the operand
reference in an instruction, which is to determine the physical address of an instruction.
Numbers
All machine languages include numeric data types. Even in non-numeric data processing, numbers are
needed to act as counters, field widths, etc. An important difference between numbers used in ordinary
mathematics and numbers stored in a computer is that the latter is limited. Thus, the programmer is faced
with understanding the consequences of rounding, overflow and underflow.
Here are the three types of numerical data in computers, such as:
1. Integer or fixed point: Fixed point representation is used to store integers, the positive and negative
whole numbers (… -3, -2, -1, 0, 1, 2, 3, …). However, the programmer assigns a radix point location to each
number and tracks the radix point through every operation. High-level programs, such as C and BASIC usually
allocate 16 bits to store each integer. Each fixed point binary number has three important parameters that
describe it:
o Whether the number is signed or unsigned,

o The position of the radix point to the right side of the sign bit (for signed numbers), or the position
of the radix point to the most significant bit (for unsigned numbers).
o And the number of fractional bits stored.
2. Floating point: A Floating Point number usually has a decimal point, which means 0, 3.14, 6.5, and-
125.5 are Floating Point
The term floating point is derived from the fact that there is no fixed number of digits before and after the
decimal point, which means the decimal point can float. There are also representations in which the number
of digits before and after the decimal point is set, called fixed-point representations. In general, floating-
point representations are slower and less accurate than fixed-point representations, but they can handle a
larger range of numbers.
3. Decimal number: The decimals are an extension of our number system. We also know that decimals
can be considered fractions with 10, 100, 1000, etc. The numbers expressed in the decimal form are called
decimal numbersor decimals. For example:1, 4.09, 13.83, etc. A decimal number has two parts, and a dot
separates these parts (.) called the decimal point.
o Whole number part: The digits lying to the left of the decimal point form the whole number part. The
places begin with ones, tens, hundreds, thousands and so on.
o Decimal part: The decimal point and the digits laying on the right of the decimal point form the
decimal part. The places begin with tenths, hundredths, thousandths and so on.
Characters
A common form of data is text or character strings. While textual data are most convenient for humans. But
computers work in binary. So, all characters, whether letters, punctuation or digits, are stored as binary
numbers. All of the characters that a computer can use are called character sets. Here are the two common
standards, such as:
1. American Standard Code for Information Interchange (ASCII)

2. Unicode
ASCII uses seven bits, giving a character set of 128 characters. The characters are represented in a table
called the ASCII table. The 128 characters include:
o 32 control codes (mainly to do with printing)

o 32 punctuation codes, symbols, and space
o 26 upper-case letters
o 26 lower-case letters
o numeric digits 0-9
We can say that the letter 'A' is the first letter of the alphabet; 'B' is the second, and so on, all the way up to
'Z', which is the 26th letter. In ASCII, each character has its own assigned number. Denary, binary and
hexadecimal representations of ASCII characters are shown in the below table.
Character Denary Binary Hexadecimal
A 65 1000001 41
Z 90 1011010 5A
a 97 1100001 61
z 122 1111010 7A
0 48 0110000 30
9 57 0111001 39
Space 32 0100000 20
! 33 0100001 21
A is represented by the denary number 65 (binary 1000001, hexadecimal 41), B by 66 (binary 1000010,
hexadecimal 42) and so on up to Z, which is represented by the denary number 90 (binary 1011010,
hexadecimal 5A).
Similarly, lower-case letters start at denary 97 (binary 1100001, hexadecimal 61) and end at denary 122
(binary 1111010, hexadecimal 7A). When data is stored or transmitted, its ASCII or Unicode number is used,
not the character itself.
For example, the word "Computer" would be represented as:
1000011 1101111 1101101 1110000 1110101 1110100 1100101 1110010
On the other hand, IRA is also widely used outside the United States. A unique 7-bit pattern represents each
character in this code. Thus, 128 different characters can be represented, and more than necessary to
represent printable characters, and some of the patterns represent control characters. Some control
characters control the printing of characters on a page, and others are concerned with communications
procedures.
IRA-encoded characters are always stored and transmitted using 8 bits per character. The 8 bit may be set
to 0 or used as a parity bit for error detection. In the latter case, the bit is set such that the total number of
binary 1s in each octet is always odd (odd parity) or always even (even parity).
Logical data
Normally, each word or other addressable unit (byte, half-word, and so on) is treated as a single unit of data.
Sometimes, it is useful to consider an n-bit unit consisting of 1-bit items of data, each item having the value
0 or 1. When data are viewed this way, they are considered to be logical data.
The Boolean data can only represent two values: true or false. Although only two values are possible, they
are rarely implemented as a single binary digit for efficiency reasons. Many programming languages do not
have an explicit Boolean type, instead of interpreting 0 as false and other values as true. Boolean data refers
to the logical structure of how the language is interpreted to the machine language. In this case, a Boolean
0 refers to the logic False, and true is always a non zero, especially one known as Boolean 1.
There are two advantages to the bit-oriented view:
o We may want to store an array of Boolean or binary data items, in which each item can take on only
the values 0 and 1. With logical data, memory can be used most efficiently for this storage.
o There are occasions when we want to manipulate the bits of a data item.
Error Detection and Correction Code
Error detection and correction code plays an important role in the transmission of data from one source to
another. The noise also gets added into the data when it transmits from one system to another, which causes
errors in the received binary data at other systems. The bits of the data may change(either 0 to 1 or 1 to 0)
during transmission.
It is impossible to avoid the interference of noise, but it is possible to get back the original data. For this
purpose, we first need to detect either an error z is present or not using error detection codes. If the error
is present in the code, then we will correct it with the help of error correction codes.
Error detection code
The error detection codes are the code used for detecting the error in the received data bitstream. In these
codes, some bits are included appended to the original bitstream.
Error detecting codes encode the message before sending it over the noisy channels. The encoding scheme
is performed in such a way that the decoder at the receiving can find the errors easily in the receiving data
with a higher chance of success.
Parity Code
In parity code, we add one parity bit either to the right of the LSB or left to the MSB to the original bitstream.
On the basis of the type of parity being chosen, two types of parity codes are possible, i.e., even parity code
and odd parity code.
Features of Error detection codes
These are the following features of error detection codes:
o These codes are used when we use message backward error correction techniques for reliable data
transmission. A feedback message is sent by the receiver to inform the sender whether the message
is received without any error or not at the receiver side. If the message contains errors, the sender
retransmits the message.
o In error detection codes, in fixed-size blocks of bits, the message is contained. In this, the redundant
bits are added for correcting and detecting errors.
o These codes involve checking of the error. No matter how many error bits are there and the type of
error.
o Parity check, Checksum, and CRC are the error detection technique.
Error correction code
Error correction codes are generated by using the specific algorithm used for removing and detecting errors
from the message transmitted over the noisy channels. The error-correcting codes find the correct number
of corrupted bits and their positions in the message. There are two types of ECCs(Error Correction Codes),
which are as follows.
Block codes
In block codes, in fixed-size blocks of bits, the message is contained. In this, the redundant bits are added for
correcting and detecting errors.
Convolutional codes
The message consists of data streams of random length, and parity symbols are generated by the sliding
application of the Boolean function to the data stream.
The hamming code technique is used for error correction.
Hamming Code
Hamming code is an example of a block code. The two simultaneous bit errors are detected, and single-bit
errors are corrected by this code. In the hamming coding mechanism, the sender encodes the message by
adding the unessential bits in the data. These bits are added to the specific position in the message because
they are the extra bits for correction.
Register Transfer
The term Register Transfer refers to the availability of hardware logic circuits that can perform a given micro-
operation and transfer the result of the operation to the same or another register.
Most of the standard notations used for specifying operations on various registers are stated below.
o The memory address register is designated by MAR.

o Program Counter PC holds the next instruction's address.
o Instruction Register IR holds the instruction being executed.
o R1 (Processor Register).
o We can also indicate individual bits by placing them in parenthesis. For instance, PC (8-15), R2 (5),
etc.
o Data Transfer from one register to another register is represented in symbolic form by means of
replacement operator. For instance, the following statement denotes a transfer of the data of
register R1 into register R2.
1. R2 ← R1
o Typically, most of the users want the transfer to occur only in a predetermined control condition.
This can be shown by following if-then statement:
If (P=1) then (R2 ← R1); Here P is a control signal generated in the control section.
o It is more convenient to specify a control function (P) by separating the control variables from the
register transfer operation. For instance, the following statement defines the data transfer operation
under a specific control function (P).
1. P: R2 ← R1
The following image shows the block diagram that depicts the transfer of data from R1 to R2.
Here, the letter 'n' indicates the number of bits for the register. The 'n' outputs of the register R1 are
connected to the 'n' inputs of register R2.
A load input is activated by the control variable 'P' which is transferred to the register R2.
Arithmetic Micro-operations
In general, the Arithmetic Micro-operations deals with the operations performed on numeric data stored in
the registers.
The basic Arithmetic Micro-operations are classified in the following categories:
1. Addition
2. Subtraction
3. Increment
4. Decrement
5. Shift
Some additional Arithmetic Micro-operations are classified as:
1. Add with carry

2. Subtract with borrow
3. Transfer/Load, etc.
The following table shows the symbolic representation of various Arithmetic Micro-operations.
Symbolic Representation Description
R3 ← R1 + R2 The contents of R1 plus R2 are transferred to R3.
R3 ← R1 - R2 The contents of R1 minus R2 are transferred to R3.
R2 ← R2' Complement the contents of R2 (1's complement)
R2 ← R2' + 1 2's complement the contents of R2 (negate)
R3 ← R1 + R2' + 1 R1 plus the 2's complement of R2 (subtraction)
R1 ← R1 + 1 Increment the contents of R1 by one
R1 ← R1 - 1 Decrement the contents of R1 by one
Logic operations are binary micro-operations implemented on the bits saved in the registers. These
operations treated each bit independently and create them as binary variables.
For example, the exclusive-OR micro-operation with the contents of two registers R1 and R2 is denoted by
the statement
P: R1←R1[Math Processing Error]⊕R2
It determines a logic micro-operation to be implemented on the single bits of the registers supported that
the control variable P = 1. Consider that each register has four bits. Let the content of R1 be 1010 and the
content of R2 be 1100.
The exclusive-OR micro-operation stated above represent the following logic computation −
1010 Content of R1
1100 Content of R2
0110 Content of R1 after P = 1
The content of R1, after the implementation of the micro-operation, is similar to the bit-by-bit exclusive-OR
operation on pairs of bits in R2 and previous values of R1.
Special Symbols
Special symbols will be approved for the logic micro-operations OR, AND, and complement, to categorize
them from the matching symbols that can define Boolean functions. The symbol V can indicate an OR micro-
operation and the symbol can indicate an AND micro-operation.
The complement micro-operation is similar to the 1's complement and supports a bar on the highest of the
symbol that indicates the registered name. There are various symbols, and it will be applicable to
differentiate between a logic micro-operation and a control (or Boolean) function.
There is another sense for supporting two sets of symbols can that recognize the symbol +, when can
symbolize arithmetic plus, from a logic OR operation. Although the + symbol has two meanings, it will be
available to determine between them by observing where the symbol appears.
When the symbol + appears in a micro-operation, it will indicate an arithmetic plus. When it appears in a
control (or Boolean) function, it will indicate an OR operation. We cannot use it to symbolize an OR micro-
operation.
For example, in the statement
P+Q: R1←R2+R3,R 4←R5V R6
The + between P and Q is an OR operation between two binary variables of a control function. The + between
R2 and R3 determines an add micro-operation. The OR micro-operation is named by the symbol V between
registers R5 and R6.
Shift Micro-operations
There are three types of shift micro-operations are as follows −
Logical Shift
It transfers 0 by the serial input. The symbol "shl" can be used for logical shift left and "shr" can be used for
logical shift right.
R1 ←R1 shl R1
R2 ←R1 shr R2
The register symbol should be the equivalent on both sides of the arrows.
Circular Shift
This circulates or pivots the bits of register around the two ends without any trouble of data or contents. In
circular shift, the serial output of the shift register is linked to its serial input. "cil" and "cir" is used for circular
shift left and right respectively. The symbolic documentation for the shift micro-operations is demonstrated
in the table.
Shift Micro-operations
Symbolic Designation Description
R ←R1 shl R Shift-left register R
R ←R1 shr R Shift-right register R
R ←R1 cil R Circular shift-left register R
R ←R1 cir R Circular shift-right register R
R ←R1 ashl R Arithmetic shift-left R
R ←R1 ashr R Arithmetic shift-right R
Arithmetic Shift
This shifts a signed binary number to left or right. An arithmetic shift left multiplies a signed binary number
by 2 and shift left divides the number by 2. Arithmetic shift micro-operation leaves the sign bit constant due
to the signed number remains equal when it is multiplied or divided by 2.
Rn-1 Rn-2 R→ R1
Sign bit
Arithmetic Shift Right
The leftmost bit in a register influences the sign bit, and the remaining bits influence the number. The sign
bit is 0 for positive and 1 for negative. Negative numbers are in 2's complement form. The figure displays a
symbolic register of n bits.
Bit Rn-1 in the leftmost position holds the sign bit.
Rn-2 is the most significant bit of the number and
R0 is the least significant bit. The arithmetic shift-right leaves the sign bit constant and shifts the number
(involving the sign bit) to the right. Therefore
Rn-1 remains the equal,
Rn-2 receives the bit from
Rn-1 and so on for the other bits in the register. The bit in
R0 is lost.
A computer systems create use of several storage registers that are linked to a typical operational unit is
known as the arithmetic and logic unit (ALU). ALU is the central and one of the most essential units internal
the CPU of the computer.
All the logical and numerical operations of a computer are implemented here. The contents of a particular
register are arranged in the input of ALU. ALU implements the given operation and then transfers it to the
target register.
The one stage of an arithmetic logic shift unit is demonstrated in the figure. The subscript i nominate a
frequent stage. There are two inputs are used for both the arithmetic and logic units.
A specific micro-operation is choosing with inputs S1 and S0 A 4 x 1 multiplexer at the output select between
an arithmetic output inand a logic output in . The data in the multiplexer are chosen with inputs S 3 and S2.
There are two data inputs to the multiplexer receive inputs A i-1 for the shift-right operation and Ai+1 for the
shift-left operation. The circuit should be continued n times for an n-bit ALU.
The output carry Ci+1 of a given arithmetic stage should be linked to the input carry Ci of the next stage in the
series. The input carries to the first stage is the input carry Cin It can support a selection variable for the
arithmetic operations.
The circuit whose one stage is determined in the diagram. It provides eight arithmetic operations, four logic
operations, and two-shift operations. Each operation is selected with the five variables S3,S2,S1,S0The input
carries Ci∧Cin can be used for selecting an arithmetic operation only.
Functional Table for Arithmetic Logic Shift Unit
S3 S2 S1 S0 Cin Operation Function
0 0 0 0 0 F=A Transfer A
0 0 0 0 1 F=A+1 Increment A
0 0 0 1 0 F=A+B Addition
0 0 0 1 1 F=A+B+1 Add with carry
0 0 1 0 0 F = A + B’ Subtract with borrow
0 0 1 0 1 F = A + B’ + 1 Subtraction
0 0 1 1 0 F=A–1 Decrement A
0 0 1 1 1 F=A Transfer A
0 1 0 0 X F = A ∧∧ B AND
0 1 0 1 X F = A ∨∨ B OR
0 1 1 0 X F = A⊕⊕B XOR
0 1 1 1 X F = A’ Complement A
1 0 X X X F = shr A Shift right A into F
1 1 X X X F = shl A Shift Left A into F
This table shows the 14 operations of the ALU. The first eight are arithmetic operations and are selected with
S3S2 = 00. The next four are logic operations and are selected with S3S2 = 01. The final two operations are
shift operations and are selected with S3S2 = 10 and 11. The other three selection inputs do no influence the
shift.
Unit 2 : COMPUTER ARCHITECTURE AND PIPELING
Design of Control Unit
The Control Unit is classified into two major categories:
1. Hardwired Control
2. Microprogrammed Control
Hardwired Control
The Hardwired Control organization involves the control logic to be implemented with gates, flip-flops,
decoders, and other digital circuits.
The following image shows the block diagram of a Hardwired Control organization.
o A Hard-wired Control consists of two decoders, a sequence counter, and a number of logic gates.
o An instruction fetched from the memory unit is placed in the instruction register (IR).
o The component of an instruction register includes; I bit, the operation code, and bits 0 through 11.
o The operation code in bits 12 through 14 are coded with a 3 x 8 decoder.
o The outputs of the decoder are designated by the symbols D0 through D7.
o The operation code at bit 15 is transferred to a flip-flop designated by the symbol I.
o The operation codes from Bits 0 through 11 are applied to the control logic gates.
o The Sequence counter (SC) can count in binary from 0 through 15.
Micro-programmed Control
The Microprogrammed Control organization is implemented by using the programming approach.
In Microprogrammed Control, the micro-operations are performed by executing a program consisting of

micro-instructions.
The following image shows the block diagram of a Microprogrammed Control organization.
o The Control memory address register specifies the address of the micro-instruction.
o The Control memory is assumed to be a ROM, within which all control information is permanently
stored.
o The control register holds the microinstruction fetched from the memory.
o The micro-instruction contains a control word that specifies one or more micro-operations for the
data processor.
o While the micro-operations are being executed, the next address is computed in the next address
generator circuit and then transferred into the control address register to read the next
microinstruction.
o The next address generator is often referred to as a micro-program sequencer, as it determines the
address sequence that is read from control memory.
Addressing Sequencing in Computer Organization
The control memory is used to store the microinstructions in groups. Here each group is used to specify a
routine. The control memory of each computer has the instructions which contain their micro-programs
routine. These micro-programs are used to generate the micro-operations that will be used to execute the
instructions. Suppose the address sequencing of control memory is controlled by the hardware. In that case,
that hardware must be capable to branch from one routine to another routine and also able to apply
sequencing of microinstructions within a routine. When we try to execute a single instruction of computer,
the control must undergo the following steps:
o When the power of a computer is turned on, we have to first load an initial address into the CAR
(control address register). This address can be described as the first microinstruction address. With
the help of this address, we are able to activate the instruction fetch routine.
o Then, the control memory will go through the routine, which will be used to find out the effective
address of operand.
o In the next step, a micro-operation will be generated, which will be used to execute the instruction
fetched from memory.
We are able to transform the bits of instruction code into an address with the help of control memory where
routine is located. This process can be called the mapping process. The control memory required the
capabilities of address sequencing, which is described as follows:
o On the basis of the status bit conditions, the address sequencing selects the conditional branch or
unconditional branch.
o Addressing sequence is able to increment the CAR (Control address register).
o It provides the facility for subroutine calls and returns.
o A mappings process is provided by the addressing sequence from the instructions bits to a control
memory address.
In the above diagram, we can see a block diagram of a control memory and associative hardware, which is
required for selecting the address of next microinstruction. The microinstruction is used to contain a set of
bits in the control memory. With the help of some bits, we are able to start the micro-operations in a
computer register. The remaining bits of microinstruction are used to specify the method by which we are
able to obtain the next address.
In this diagram, we can also see that the control address register are able to recover their address with the
help of four different directions. The CAR is incremented with the help of incrementer and then chooses the
next instruction. The branching address will be determined in the multiple fields of microinstruction so that
they can provide results in branching.
If there are status bits of microinstruction and we want to apply conditions on them, in this case, we can use
conditional branching. An external address can be shared with the help of a mapping logic circuit. The return
address will be saved by a special register. This saved address will be helpful when the micro-program
requires returning from the subroutine. At that time, it requires the value from the unique register.
Conditional Branching
In the above diagram, the branch logic is used to provide the decision-making capabilities in the control unit.
There are special bits in the system which is described by the status conditions. These bits are used to
provide the parameter information such as mode bits, the sign bit, carry-out, and input or output status.
If these status bits come together with the microinstruction field, they are able to control the decision of a
conditional branch, which is generated in the branch logic. Here the microinstruction field is going to specify
a branch address. The multiplexer is used to implement the branch logic hardware. If the condition is met,
it will be branch to the initial address. Otherwise, it will increment the address register.
If we load the branch address into the control address register from the control memory, we are able to
implement the unconditional branch microinstruction. If the condition is true, it will go to the branch, which
is referred to as the address from the next address field of the current microinstruction. Otherwise, it will
fall through. There are various types of conditions that need to be tested: Z(zero), C(carry), O(overflow),
N(negative), etc.
Mapping of Instructions
In the control memory, if the microinstruction specifies a branch to the first work, in this case, there will be
a special type of branch. Here an instruction contains their micro-program routine. For this special branch,
the status bits will be the bits in the operation code, which is the part of instruction.
The above image shows a type of easy mapping process which are going to convert the 4-bit operation code
into the 7-bit address for control memory. In the mapping process, the 0 will be placed in the most significant
bit of address. After that, the four operation code bits will be transferred. Lastly, the two least significant
bits of CAR will be cleared.
With the help of this process, a micro-program will be provided to each computer instruction. The micro-
program contains the capacity of four microinstructions. If less than four microinstructions are used by the
routine, the location of unused memory can be used for other routines. If more than four microinstructions
are used by the routine, it will use the addresses 1000000 through 1111111.
This concept can be extended to a more general mapping rule with the help of PLD (Programmable logic
device) or ROM (Read-only memory).
The above image shows the mapping of address of microinstruction from the OP-code of an instruction. In
the execution program, this microinstruction is the starting microinstruction.
Subroutine
Subroutines can be referred to as programs that are used to accomplish a particular task by the other
routines. With the help of employing subroutines, we can save the microinstructions. These subroutines use
the common sections of microcode, such as effective address computation. The main routine is able to get
the address for the return with the help of a subroutine register. In another word, we can say that it becomes
a source to transfer the address to a main routine. The register file is used to store the addresses for
subroutines. These register files can be structured in a way that the register will be organized in the 'Last in
first out' (LIFO) stack.
Addition
In arithmetic, addition is a type of basic mathematical operation. In primary education, students are taught
to add numbers in the decimal system, starting with single digits and progressively tackling more difficult
problems. In this section, we will learn the addition of two or more numbers.
Addition
The addition is a term used to describe to add two or more numbers together. In other words, it adds two
or more numbers together. The number that is left and right of the plus symbol is called addend, and the
number after the equal sign is called addition or sum.
Notation
A plus symbol (+) is used to denote the addition. It appears between the two numbers that are called infix
notation. The other synonym of addition is added, sum, plus, and total. Sometimes it is also represented by
the symbol ∑ (sigma). It is used when we have to add a large number.
By using the plus symbol, we can perform addition between different numbers such as integers, real
numbers, decimal numbers, complex numbers, etc. Besides this, it is also used in algebra to
add vectors and matrices.
For example, in the first basket, there are five apples, and in the second basket, there are 4 apples. If we
count the apples of both the basket, we get 9 apples.
In arithmetic, we can represent it in the mathematical expression as:
5+4=9
Addition Facts
o In addition, the order of addition does not matter. It always gives the same answer.
2+4+6+8=20 or 8+6+4+2=20 or 6+2+8+4=20
o Adding 0 to any number or vice-versa gives the same number as a result.
7+0=7 or 0+7=7
o If we add any number to itself two-times, it is the same as multiplying a number by 2.
8+8=16
It is same as:
8×2=16
o The repeated addition of 1 is the same as counting.
1+1=2,1+1+1=3
Addition Table
The following table helps the children to memorize the sum of two numbers. You can find the sum of two
numbers, between 0 to 10.
Before moving to the addition, we must be aware of the term carry.
In arithmetic, a carry is a digit that is transferred from the right column to the left column and added to the
transferred column.
Addition of one-digit Numbers
We can find the addition of one-digit numbers with the help of the above table. Suppose we want to add 2
and 3 together. Search 2 in the left-most column, and 3 in the topmost row. In the current row, move down
until you reach in front of the selected column. The square contains the addition of the numbers 2 and 3,
i.e., 5.
Similarly, we can find the sum of any single-digit number.
Addition of Two-digit Numbers

o Arrange the given numbers in the column for easy understanding.
o Add the ones place digits together, transfer the carry, if any. It gives the unit place of the answer.
o Add the tens place digits and carry them from the previous step (if any).
o Write the answer.
Let's implement the above steps in an example.
Example: Add 24 and 32.
Solution:
Solution:
Addition of Three-digit Numbers

o Arrange the given numbers in the column for easy understanding.
o Add the ones place digits together, transfer the carry, if any. It gives the unit place of the answer.
o Add the tens place digits, and carry from the previous step (if any), transfer the carry, if any. It gives
the tens place of the answer.
o Add the hundreds of place digits, and carry from the previous step (if any). It gives the hundreds or
thousands or both (depend on the sum) place of the answer.
o Write the answer.
Let's implement the above steps in an example.
Solution:
Solution:
Similarly, we can add four-digit numbers, also.
Addition of Integers
An integer includes all positive and negative numbers, including 0. A number may have a positive or negative
sign. The addition of integers with the sign follows the rules. Generally, we do not represent a positive
number with + sign. In the following table, we have summarized the additional rule of positive and negative
numbers.
We have taken two numbers a and b as addend and z as sum.
Sign Remarks Examples
(+) + (+) = + Always gives positive result a+b=z
(+) + (-) = - If a>b, the result will be +ive else -ive a + (-b) = z or -z
(-) + (+) = - If a<b, the result will be -ive else +ive (-a) + b = -z or z
(-) + (-) = - Always gives negative result (-b) + (-b) = -z
Examples
10+20=30
25+(-20)=25-20=5
20+(-25)=20-25=-5
(-22)+(10)=10-22=-12
(-10)+(22)=22-10=12
(-40)+(-20)=-40-20=-60
Addition of Decimal Numbers
To add two or more decimal numbers, follow the rules given below:
o Write the number in the column form but remember that decimal point must be lined up.
o Make the number of equal lengths, if unequal.
o Add the columns together and put a decimal point in the answer.
Example: Add 56.3457 and 2.4.
Solution:
Example: Add 12.02 and 45.11.
Solution:
Example: Add 33.89, 0.0073, and 6.
Solution:
Addition of Rational Number
The rational numbers are the numbers that are in the fraction form . Let's see how to add the rational
number.
When the denominator of each fraction is the same:
o Add the numerators and put the resultant in the answer.

o Simplify the fraction if required.
In general, we can say that if are two fractions, the addition of fractions will be:
Remember: To simplify a fraction, numerator and denominator must be divisible by the same number.
Example: Find the sum of .
Solution:
On simplifying the fraction , we get 2.

Hence, the sum of is 2.
When the denominator of each fraction is unlike (not similar):
o Find the LCM of the denominators because we need to make denominators the same.
o Divide the LCM by the denominators.
o Multiply the resultant in the numerators, respectively, and simplify.
o Add numerators, and get the answer.
In general, we can say that if are two fractions, the addition of fractions will be:
Example:
Solution:
Let's solve the question according to the above steps.
Find the LCM of the denominators.
Divide the LCM by the denominators.
Multiply the resultant (from the above step) in the numerators, respectively, and simplify.
Add the numerators.

Addition of Complex Numbers
Complex numbers are added by adding real and imaginary parts separately. In general, we can say that
if a+bi and c+di are two complex numbers, then the addition of these numbers will be:
(a+bi)+(c+di)=(a+c)+(b+d)i
Example: Add (6+4i) and (5+3i).
Solution:
In the above example, 6 and 5 are real parts, and 4i and 3i are imaginary parts. So, we will add real parts
together and imaginary parts together.
(6+4i)+(5+3i)=(6+5)+(4i+3i)
(6+4i)+(5+3i)=(11+7i)
The sum of (6+4i) and (5+3i) is (11+7i).
Example: Add (12+10i) and (7-9i).
Solution:
(12+10i)+(7-9i)=(12+7)+(10i-9i)
(6+4i)+(5+3i)=(19+i)
The sum of (12+10i) and (7+9i) is (19+i)
Program to calculate the subtraction of 2 matrices
Explanation
In this program, we need to subtract two matrices and print the resulting matrix.
Subtraction of two matrices:
Matrix B can be subtracted from matrix A or vice versa if and only if they have same dimensions that are, the
same number of rows and columns. It is not possible to subtract a 2 × 3 matrix from a 3 × 2 matrix.
Subtraction of two matrices can be performed by subtracting their corresponding elements as
1. (A - B)ij = Aij - Bij
Subtraction of two matrices can be performed by looping through the first and second matrix. Calculating
the difference between their corresponding elements and store the result in the third matrix.
Algorithm
1. Declare and initialize two two-dimensional arrays a and b.
2. Calculate the number of rows and columns present in the array a (as dimensions of both the arrays
are same) and store it in variables rows and cols respectively.
3. Declare another array diff with dimensions present in rows and columns.
4. Loop through the arrays a and b, calculate the difference between the corresponding elements
e.g a11 - b11 = diff11
5. Display the elements of array diff.
Booth's Multiplication Algorithm
The booth algorithm is a multiplication algorithm that allows us to multiply the two signed binary integers in
2's complement, respectively. It is also used to speed up the performance of the multiplication process. It is
very efficient too. It works on the string bits 0's in the multiplier that requires no additional bit only shift the
right-most string bits and a string of 1's in a multiplier bit weight 2k to weight 2m that can be considered as 2k+
1 - 2m .
Following is the pictorial representation of the Booth's Algorithm:
In the above flowchart, initially, AC and Qn + 1 bits are set to 0, and the SC is a sequence counter that
represents the total bits set n, which is equal to the number of bits in the multiplier. There are BR that
represent the multiplicand bits, and QR represents the multiplier bits. After that, we encountered two bits
of the multiplier as Qn and Qn + 1, where Qn represents the last bit of QR, and Qn + 1 represents the incremented
bit of Qn by 1. Suppose two bits of the multiplier is equal to 10; it means that we have to subtract the
multiplier from the partial product in the accumulator AC and then perform the arithmetic shift operation
(ashr). If the two of the multipliers equal to 01, it means we need to perform the addition of the multiplicand
to the partial product in accumulator AC and then perform the arithmetic shift operation (ashr), including Qn
+ 1. The arithmetic shift operation is used in Booth's algorithm to shift AC and QR bits to the right by one and
remains the sign bit in AC unchanged. And the sequence counter is continuously decremented till the
computational loop is repeated, equal to the number of bits (n).
Working on the Booth Algorithm
1. Set the Multiplicand and Multiplier binary bits as M and Q, respectively.
2. Initially, we set the AC and Qn + 1 registers value to 0.
3. SC represents the number of Multiplier bits (Q), and it is a sequence counter that is continuously
decremented till equal to the number of bits (n) or reached to 0.
4. A Qn represents the last bit of the Q, and the Qn+1 shows the incremented bit of Qn by 1.
5. On each cycle of the booth algorithm, Qn and Qn + 1 bits will be checked on the following parameters
as follows:
i. When two bits Qn and Qn + 1 are 00 or 11, we simply perform the arithmetic shift right
operation (ashr) to the partial product AC. And the bits of Qn and Qn + 1 is incremented by 1
bit.
ii. If the bits of Qn and Qn + 1 is shows to 01, the multiplicand bits (M) will be added to the AC
(Accumulator register). After that, we perform the right shift operation to the AC and QR bits
by 1.
iii. If the bits of Qn and Qn + 1 is shows to 10, the multiplicand bits (M) will be subtracted from the
AC (Accumulator register). After that, we perform the right shift operation to the AC and QR
bits by 1.
6. The operation continuously works till we reached n - 1 bit in the booth algorithm.
7. Results of the Multiplication binary bits will be stored in the AC and QR registers.
There are two methods used in Booth's Algorithm:
1. RSC (Right Shift Circular)
It shifts the right-most bit of the binary number, and then it is added to the beginning of the binary bits.
2. RSA (Right Shift Arithmetic)
It adds the two binary bits and then shift the result to the right by 1-bit position.
Example: 0100 + 0110 => 1010, after adding the binary number shift each bit by 1 to the right and put the
first bit of resultant to the beginning of the new bit.
Example: Multiply the two numbers 7 and 3 by using the Booth's multiplication algorithm.
Ans. Here we have two numbers, 7 and 3. First of all, we need to convert 7 and 3 into binary numbers like 7
= (0111) and 3 = (0011). Now set 7 (in binary 0111) as multiplicand (M) and 3 (in binary 0011) as a multiplier
(Q). And SC (Sequence Count) represents the number of bits, and here we have 4 bits, so set the SC = 4. Also,
it shows the number of iteration cycles of the booth's algorithms and then cycles run SC = SC - 1 time.
Qn Qn + 1 M = (0111) AC Q Qn + 1 SC
M' + 1 = (1001) & Operation
1 0 Initial 0000 0011 0 4
Subtract (M' + 1) 1001
1001
Perform Arithmetic Right Shift operations (ashr) 1100 1001 1 3
1 1 Perform Arithmetic Right Shift operations (ashr) 1110 0100 1 2
0 1 Addition (A + M) 0111
0101 0100
Perform Arithmetic right shift operation 0010 1010 0 1
0 0 Perform Arithmetic right shift operation 0001 0101 0 0
The numerical example of the Booth's Multiplication Algorithm is 7 x 3 = 21 and the binary representation
of 21 is 10101. Here, we get the resultant in binary 00010101. Now we convert it into decimal, as
(000010101)10 = 2*4 + 2*3 + 2*2 + 2*1 + 2*0 => 21.
Example: Multiply the two numbers 23 and -9 by using the Booth's multiplication algorithm.
Here, M = 23 = (010111) and Q = -9 = (110111)
Qn Qn + 1 M=010111 AC Q Qn + 1 SC
M' + 1 = 1 0 1 0 0 1
Initially 000000 110111 0 6
1 0 Subtract M 101001
101001
0 1 Addition (A + M) 010111
010100
1 0 Subtract M 101001
110011
Qn + 1 = 1, it means the output is negative.
Hence, 23 * -9 = 2's complement of 111100110001 => (00001100111)
Restoring Division Algorithm for Unsigned Integer
Restoring division is usually performed on the fixed point fractional numbers. When we perform division
operations on two numbers, the division algorithm will give us two things, i.e., quotient and remainder. This
algorithm is based on the assumption that 0 < D < N. With the help of digit set {0, 1}, the quotient digit q will
be formed in the restoring division algorithm. The division algorithm is generally of two types, i.e., fast
algorithm and slow algorithm. Goldschmidt and Newton-Raphson are the types of fast division algorithm,
and STR algorithm, restoring algorithm, non-performing algorithm, and the non-restoring algorithm are the
types of slow division algorithm.
In this section, we are going to perform restoring algorithm with the help of an unsigned integer. We are
using restoring term because we know that the value of register A will be restored after each iteration. We
will also try to solve this problem using the flow chart and apply bit operations.
Here, register Q is used to contain the quotient, and register A is used to contain the remainder. Here, the
divisor will be loaded into the register M, and n-bit divided will be loaded into the register Q. 0 is the starting
value of a register. The values of these types of registers are restored at the time of iteration. That's why it
is known as restoring.
Now we will learn some steps of restoring division algorithm, which is described as follows:
Step 1: In this step, the corresponding value will be initialized to the registers, i.e., register A will contain
value 0, register M will contain Divisor, register Q will contain Dividend, and N is used to specify the number
of bits in dividend.
Step 2: In this step, register A and register Q will be treated as a single unit, and the value of both the registers
will be shifted left.
Step 3: After that, the value of register M will be subtracted from register A. The result of subtraction will be
stored in register A.
Step 4: Now, check the most significant bit of register A. If this bit of register A is 0, then the least significant
bit of register Q will be set with a value 1. If the most significant bit of A is 1, then the least significant bit of
register Q will be set to with value 0, and restore the value of A that means it will restore the value of register
A before subtraction with M.
Step 5: After that, the value of N will be decremented. Here n is used as a counter.
Step 6: Now, if the value of N is 0, we will break the loop. Otherwise, we have to again go to step 2.
Step 7: This is the last step. In this step, the quotient is contained in the register Q, and the remainder is
contained in register A.
For example:
In this example, we will perform a Division restoring algorithm.
1. Dividend = 11
2. Divisor = 3
N M A Q Operation
4 00011 00000 1011 Initialize
00011 00001 011_ Shift left AQ
00011 11110 011_ A=A-M
00011 00001 0110 Q[0] = 0 And restore A
3 00011 00010 110_ Shift left AQ
00011 11111 110_ A=A-M
00011 00010 1100 Q[0] = 0
2 00011 00101 100_ Shift left AQ
00011 00010 100_ A=A-M
00011 00010 1001 Q[0] = 1

1 00011 00101 001_ Shift left AQ
00011 00010 001_ A=A-M
00011 00010 0011 Q[0] = 1
So we should not forget to restore the value of the most significant bit of A, which is 1. So, register A contains
the remainder 2, and register Q contains the quotient 3.
Arithmetic Pipeline
Arithmetic Pipelines are mostly used in high-speed computers. They are used to implement floating-point
operations, multiplication of fixed-point numbers, and similar computations encountered in scientific
problems.
To understand the concepts of arithmetic pipeline in a more convenient way, let us consider an example of
a pipeline unit for floating-point addition and subtraction.
The inputs to the floating-point adder pipeline are two normalized floating-point binary numbers defined as:
X = A * 2a = 0.9504 * 103
Y = B * 2b = 0.8200 * 102
Where A and B are two fractions that represent the mantissa and a and b are the exponents.
The combined operation of floating-point addition and subtraction is divided into four segments. Each
segment contains the corresponding suboperation to be performed in the given pipeline. The suboperations
that are shown in the four segments are:
1. Compare the exponents by subtraction.

2. Align the mantissas.
3. Add or subtract the mantissas.
4. Normalize the result.
We will discuss each suboperation in a more detailed manner later in this section.
The following block diagram represents the suboperations performed in each segment of the pipeline.
Instruction Pipeline
Pipeline processing can occur not only in the data stream but in the instruction stream as well.
Most of the digital computers with complex instructions require instruction pipeline to carry out operations
like fetch, decode and execute instructions.
In general, the computer needs to process each instruction with the following sequence of steps.
1. Fetch instruction from memory.

2. Decode the instruction.
3. Calculate the effective address.
4. Fetch the operands from memory.
5. Execute the instruction.
6. Store the result in the proper place.
Each step is executed in a particular segment, and there are times when different segments may take
different times to operate on the incoming information. Moreover, there are times when two or more
segments may require memory access at the same time, causing one segment to wait until another is
finished with the memory.
The organization of an instruction pipeline will be more efficient if the instruction cycle is divided into
segments of equal duration. One of the most common examples of this type of organization is a Four-
segment instruction pipeline.
A four-segment instruction pipeline combines two or more different segments and makes it as a single one.
For instance, the decoding of the instruction can be combined with the calculation of the effective address
into one segment.
The following block diagram shows a typical example of a four-segment instruction pipeline. The instruction
cycle is completed in four segments.
Segment 1:
The instruction fetch segment can be implemented using first in, first out (FIFO) buffer.
Segment 2:
The instruction fetched from memory is decoded in the second segment, and eventually, the effective
address is calculated in a separate arithmetic circuit.
Segment 3:
An operand from memory is fetched in the third segment.
Segment 4:
The instructions are finally executed in the last segment of the pipeline organization.
1. Compare exponents by subtraction:
The exponents are compared by subtracting them to determine their difference. The larger exponent is
chosen as the exponent of the result.
The difference of the exponents, i.e., 3 - 2 = 1 determines how many times the mantissa associated with the
smaller exponent must be shifted to the right.
2. Align the mantissas:
The mantissa associated with the smaller exponent is shifted according to the difference of exponents
determined in segment one.
X = 0.9504 * 103
Y = 0.08200 * 103
3. Add mantissas:
The two mantissas are added in segment three.
Z = X + Y = 1.0324 * 103
4. Normalize the result:
After normalization, the result is written as:
Z = 0.1324 * 104
RISC stands for Reduced Instruction Set Computers. It was introduced to execute as fast as one instruction
per clock cycle. This RISC pipeline helps to simplify the computer architecture’s design.
It relates to what is known as the Semantic Gap, that is, the difference between the operations provided in
the high-level languages (HLLs) and those provided in computer architectures.
To avoid these consequences, the conventional response of the computer architects is to add layers of
complexity to newer architectures. This also increases the number and complexity of instructions together
with an increase in the number of addressing modes. The architecture which resulted from the adoption of
this “add more complexity” are known as Complex Instruction Set Computers (CISC).
The main benefit of RISC to implement instructions at the cost of one per clock cycle is continually not
applicable because each instruction cannot be fetched from memory and implemented in one clock cycle
correctly under all circumstances.
The method to obtain the implementation of an instruction per clock cycle is to initiate each instruction with
each clock cycle and to pipeline the processor to manage the objective of single-cycle instruction execution.
RISC compiler gives support to translate the high-level language program into a machine language program.
There are various issues in managing complexity about data conflicts and branch penalties are taken care of
by the RISC processors, which depends on the adaptability of the compiler to identify and reduce the delays
encountered with these issues.
Principles of RISCs Pipeline
There are various principles of RISCs pipeline which are as follows −
 Keep the most frequently accessed operands in CPU registers.

 It can minimize the register-to-memory operations.
 It can use a high number of registers to enhance operand referencing and decrease the processor
memory traffic.
 It can optimize the design of instruction pipelines such that minimum compiler code generation can
be achieved.
 It can use a simplified instruction set and leave out those complex and unnecessary instructions.
Let us consider a three-segment instruction pipeline that shows how a compiler can optimize the machine
language program to compensate for pipeline conflicts.
A frequent collection of instructions for a RISC processor is of three types are as follows −
 Data Manipulation Instructions − Manage the data in processor registers.

 Data Transfer Instructions − These are load and store instructions that use an effective address that
is obtained by adding the contents of two registers or a register and a displacement constant
provided in the instruction.
 Program Control Instructions − These instructions use register values and a constant to evaluate
the branch address, which is transferred to a register or the program counter (PC).
ctor processing is a central processing unit that can perform the complete vector input in individual
instruction. It is a complete unit of hardware resources that implements a sequential set of similar data
elements in the memory using individual instruction.
The scientific and research computations involve many computations which require extensive and high-
power computers. These computations when run in a conventional computer may take days or weeks to
complete. The science and engineering problems can be specified in methods of vectors and matrices using
vector processing.
Features of Vector Processing
There are various features of Vector Processing which are as follows −
 A vector is a structured set of elements. The elements in a vector are scalar quantities. A vector
operand includes an ordered set of n elements, where n is known as the length of the vector.
 Each clock period processes two successive pairs of elements. During one single clock period, the
dual vector pipes and the dual sets of vector functional units allow the processing of two pairs of
elements.
As the completion of each pair of operations takes place, the results are delivered to appropriate
elements of the result register. The operation continues just before the various elements processed
are similar to the count particularized by the vector length register.
 In parallel vector processing, more than two results are generated per clock cycle. The parallel vector
operations are automatically started under the following two circumstances −
o When successive vector instructions facilitate different functional units and multiple vector
registers.
o When successive vector instructions use the resulting flow from one vector register as the
operand of another operation utilizing a different functional unit. This phase is known as
chaining.
 A vector processor implements better with higher vectors because of the foundation delay in a
pipeline.
 Vector processing decrease the overhead related to maintenance of the loop-control variables which
creates it more efficient than scalar processing.
Unit 3 : Microprocessor Architecture
Computer Instructions
Computer instructions are a set of machine language instructions that a particular processor understands
and executes. A computer performs tasks on the basis of the instruction provided.
An instruction comprises of groups called fields. These fields include:
o The Operation code (Opcode) field which specifies the operation to be performed.
o The Address field which contains the location of the operand, i.e., register or memory location.
o The Mode field which specifies how the operand will be located.
A basic computer has three instruction code formats which are:
1. Memory - reference instruction

2. Register - reference instruction
3. Input-Output instruction
Memory - reference instruction
In Memory-reference instruction, 12 bits of memory is used to specify an address and one bit to specify the
addressing mode 'I'.
Register - reference instruction
The Register-reference instructions are represented by the Opcode 111 with a 0 in the leftmost bit (bit 15)
of the instruction.
A Register-reference instruction specifies an operation on or a test of the AC (Accumulator) register.

Input-Output instruction
Just like the Register-reference instruction, an Input-Output instruction does not need a reference to
memory and is recognized by the operation code 111 with a 1 in the leftmost bit of the instruction. The
remaining 12 bits are used to specify the type of the input-output operation or test performed.
Note
o The three operation code bits in positions 12 through 14 should be equal to 111. Otherwise, the
instruction is a memory-reference type, and the bit in position 15 is taken as the addressing mode I.
o When the three operation code bits are equal to 111, control unit inspects the bit in position 15. If
the bit is 0, the instruction is a register-reference type. Otherwise, the instruction is an input-output
type having bit 1 at position 15.
Instruction Set Completeness
A set of instructions is said to be complete if the computer includes a sufficient number of instructions in
each of the following categories:
o Arithmetic, logical and shift instructions

o A set of instructions for moving information to and from memory and processor registers.
o Instructions which controls the program together with instructions that check status conditions.
o Input and Output instructions
Arithmetic, logic and shift instructions provide computational capabilities for processing the type of data the
user may wish to employ.
A huge amount of binary information is stored in the memory unit, but all computations are done in
processor registers. Therefore, one must possess the capability of moving information between these two
units.
Program control instructions such as branch instructions are used change the sequence in which the program
is executed.
Input and Output instructions act as an interface between the computer and the user. Programs and data
must be transferred into memory, and the results of computations must be transferred back to the user.
Software architecture is described as the organization of a system, where the system represents a set of
components that accomplish the defined functions.
Architectural Style
The architectural style, also called as architectural pattern, is a set of principles which shapes an
application. It defines an abstract framework for a family of system in terms of the pattern of structural
organization.
The architectural style is responsible to −
 Provide a lexicon of components and connectors with rules on how they can be combined.
 Improve partitioning and allow the reuse of design by giving solutions to frequently occurring
problems.
 Describe a particular way to configure a collection of components (a module with well-defined
interfaces, reusable, and replaceable) and connectors (communication link between modules).
The software that is built for computer-based systems exhibit one of many architectural styles. Each style
describes a system category that encompasses −
 A set of component types which perform a required function by the system.

 A set of connectors (subroutine call, remote procedure call, data stream, and socket) that enable
communication, coordination, and cooperation among different components.
 Semantic constraints which define how components can be integrated to form the system.
 A topological layout of the components indicating their runtime interrelationships.
Common Architectural Design
The following table lists architectural styles that can be organized by their key focus area −
Category Architectural Design Description
Prescribes use of a software system that can

Message bus receive and send messages using one or more
communication channels.
Communication
Defines the applications that expose and
Service–Oriented Architecture (SOA) consume functionality as a service using
contracts and messages.
Separate the system into two applications,

Client/server where the client makes requests to the
server.
Deployment
Separates the functionality into separate
3-tier or N-tier segments with each segment being a tier
located on a physically separate computer.
Focused on modeling a business domain and

Domain Domain Driven Design defining business objects based on entities
within the business domain.
Breakdown the application design into

Structure Component Based
reusable functional or logical components
that expose well-defined communication
interfaces.
Divide the concerns of the application into

Layered
stacked groups (layers).
Based on the division of responsibilities of an

application or system into objects, each
Object oriented
containing the data and the behavior relevant
to the object.
Types of Architecture
There are four types of architecture from the viewpoint of an enterprise and collectively, these
architectures are referred to as enterprise architecture.
 Business architecture − Defines the strategy of business, governance, organization, and key
business processes within an enterprise and focuses on the analysis and design of business
processes.
 Application (software) architecture − Serves as the blueprint for individual application systems,
their interactions, and their relationships to the business processes of the organization.
 Information architecture − Defines the logical and physical data assets and data management
resources.
 Information technology (IT) architecture − Defines the hardware and software building blocks that
make up the overall information system of the organization.
Architecture Design Process
The architecture design process focuses on the decomposition of a system into different components and
their interactions to satisfy functional and nonfunctional requirements. The key inputs to software
architecture design are −
 The requirements produced by the analysis tasks.

 The hardware architecture (the software architect in turn provides requirements to the system
architect, who configures the hardware architecture).
The result or output of the architecture design process is an architectural description. The basic
architecture design process is composed of the following steps −
Understand the Problem
 This is the most crucial step because it affects the quality of the design that follows.
 Without a clear understanding of the problem, it is not possible to create an effective solution.
 Many software projects and products are considered failures because they did not actually solve a
valid business problem or have a recognizable return on investment (ROI).
Identify Design Elements and their Relationships
 In this phase, build a baseline for defining the boundaries and context of the system.
 Decomposition of the system into its main components based on functional requirements. The
decomposition can be modeled using a design structure matrix (DSM), which shows the
dependencies between design elements without specifying the granularity of the elements.
 In this step, the first validation of the architecture is done by describing a number of system
instances and this step is referred as functionality based architectural design.
Evaluate the Architecture Design
 Each quality attribute is given an estimate so in order to gather qualitative measures or quantitative
data, the design is evaluated.
 It involves evaluating the architecture for conformance to architectural quality attributes
requirements.
 If all estimated quality attributes are as per the required standard, the architectural design process
is finished.
 If not, the third phase of software architecture design is entered: architecture transformation. If the
observed quality attribute does not meet its requirements, then a new design must be created.
Transform the Architecture Design
 This step is performed after an evaluation of the architectural design. The architectural design must
be changed until it completely satisfies the quality attribute requirements.
 It is concerned with selecting design solutions to improve the quality attributes while preserving
the domain functionality.
 A design is transformed by applying design operators, styles, or patterns. For transformation, take
the existing design and apply design operator such as decomposition, replication, compression,
abstraction, and resource sharing.
 The design is again evaluated and the same process is repeated multiple times if necessary and
even performed recursively.
 The transformations (i.e. quality attribute optimizing solutions) generally improve one or some
quality attributes while they affect others negatively
Key Architecture Principles
Following are the key principles to be considered while designing an architecture −
Build to Change Instead of Building to Last
Consider how the application may need to change over time to address new requirements and challenges,
and build in the flexibility to support this.
Reduce Risk and Model to Analyze
Use design tools, visualizations, modeling systems such as UML to capture requirements and design
decisions. The impacts can also be analyzed. Do not formalize the model to the extent that it suppresses
the capability to iterate and adapt the design easily.
Use Models and Visualizations as a Communication and Collaboration Tool

Efficient communication of the design, the decisions, and ongoing changes to the design is critical to good
architecture. Use models, views, and other visualizations of the architecture to communicate and share the
design efficiently with all the stakeholders. This enables rapid communication of changes to the design.
Identify and understand key engineering decisions and areas where mistakes are most often made. Invest
in getting key decisions right the first time to make the design more flexible and less likely to be broken by
changes.
Use an Incremental and Iterative Approach
Start with baseline architecture and then evolve candidate architectures by iterative testing to improve the
architecture. Iteratively add details to the design over multiple passes to get the big or right picture and
then focus on the details.
Key Design Principles
Following are the design principles to be considered for minimizing cost, maintenance requirements, and
maximizing extendibility, usability of architecture −
Separation of Concerns
Divide the components of system into specific features so that there is no overlapping among the
components functionality. This will provide high cohesion and low coupling. This approach avoids the
interdependency among components of system which helps in maintaining the system easy.
Single Responsibility Principle
Each and every module of a system should have one specific responsibility, which helps the user to clearly
understand the system. It should also help with integration of the component with other components.
Principle of Least Knowledge
Any component or object should not have the knowledge about internal details of other components. This
approach avoids interdependency and helps maintainability.
Minimize Large Design Upfront
Minimize large design upfront if the requirements of an application are unclear. If there is a possibility of
modifying requirements, then avoid making a large design for whole system.
Do not Repeat the Functionality
Do not repeat functionality specifies that functionality of components should not to be repeated and
hence a piece of code should be implemented in one component only. Duplication of functionality within
an application can make it difficult to implement changes, decrease clarity, and introduce potential
inconsistencies.
Prefer Composition over Inheritance while Reusing the Functionality
Inheritance creates dependency between children and parent classes and hence it blocks the free use of
the child classes. In contrast, the composition provides a great level of freedom and reduces the
inheritance hierarchies.
Identify Components and Group them in Logical Layers
Identity components and the area of concern that are needed in system to satisfy the requirements. Then
group these related components in a logical layer, which will help the user to understand the structure of
the system at a high level. Avoid mixing components of different type of concerns in same layer.
Define the Communication Protocol between Layers
Understand how components will communicate with each other which requires a complete knowledge of
deployment scenarios and the production environment.
Define Data Format for a Layer
Various components will interact with each other through data format. Do not mix the data formats so that
applications are easy to implement, extend, and maintain. Try to keep data format same for a layer, so that
various components need not code/decode the data while communicating with each other. It reduces a
processing overhead.
System Service Components should be Abstract
Code related to security, communications, or system services like logging, profiling, and configuration
should be abstracted in the separate components. Do not mix this code with business logic, as it is easy to
extend design and maintain it.
Design Exceptions and Exception Handling Mechanism
Defining exceptions in advance, helps the components to manage errors or unwanted situation in an
elegant manner. The exception management will be same throughout the system.
8086 microprocessor
Intel 8086
o Intel 8086 microprocessor is the enhanced version of Intel 8085 microprocessor. It was designed by
Intel in 1976.
o The 8086 microprocessor is a16-bit, N-channel, HMOS microprocessor. Where the HMOS is used for
"High-speed Metal Oxide Semiconductor".
o Intel 8086 is built on a single semiconductor chip and packaged in a 40-pin IC package. The type of
package is DIP (Dual Inline Package).
o Intel 8086 uses 20 address lines and 16 data- lines. It can directly address up to 220 = 1 Mbyte of
memory.
o It consists of a powerful instruction set, which provides operation like division and multiplication very
quickly.
o 8086 is designed to operate in two modes, i.e., Minimum and Maximum mode.
Difference between 8085 and 8086 Microprocessor
8085 Microprocessor 8086 Microprocessor
It is an 8-bit microprocessor. It is a 16-bit microprocessor.
It has a 16-bit address line. It has a 20-bit address line.
It has a 8-bit data bus. It has a 16-bit data bus.
The memory capacity is 64 KB. The memory capacity is 1 MB.
The Clock speed of this microprocessor is 3 MHz. The Clock speed of this microprocessor varies
between 5, 8 and 10 MHz for different versions.
It has five flags. It has nine flags.
8085 microprocessor does not support memory 8086 microprocessor supports memory
segmentation. segmentation.
It does not support pipelining. It supports pipelining.
It is accumulator based processor. It is general purpose register based processor.
It has no minimum or maximum mode. It has minimum and maximum modes.
In 8085, only one processor is used. In 8086, more than one processor is used. An
additional external processor can also be
employed.
It contains less number of transistors compare to It contains more number of transistors compare to
8086 microprocessor. It contains about 6500 8085 microprocessor. It contains about 29000 in
transistor. size.
The cost of 8085 is low. The cost of 8086 is high.

8086 pins configuration
The description of the pins of 8086 is as follows:
AD0-AD15 (Address Data Bus): Bidirectional address/data lines. These are low order address bus. They are
multiplexed with data.
When these lines are used to transmit memory address, the symbol A is used instead of AD, for example,
A0- A15.
A16 - A19 (Output): High order address lines. These are multiplexed with status signals.
A16/S3, A17/S4: A16 and A17 are multiplexed with segment identifier signals S3 and S4.
A18/S5: A18 is multiplexed with interrupt status S5.
A19/S6: A19 is multiplexed with status signal S6.
BHE/S7 (Output): Bus High Enable/Status. During T1, it is low. It enables the data onto the most significant
half of data bus, D8-D15. 8-bit device connected to upper half of the data bus use BHE signal. It is multiplexed
with status signal S7. S7 signal is available during T3 and T4.
RD (Read): For read operation. It is an output signal. It is active when LOW.
Ready (Input): The addressed memory or I/O sends acknowledgment through this pin. When HIGH, it
denotes that the peripheral is ready to transfer data.
RESET (Input): System reset. The signal is active HIGH.
CLK (input): Clock 5, 8 or 10 MHz.
INTR: Interrupt Request.
NMI (Input): Non-maskable interrupt request.
TEST (Input): Wait for test control. When LOW the microprocessor continues execution otherwise waits.
VCC: Power supply +5V dc.
GND: Ground.
Operating Modes of 8086
There are two operating modes of operation for Intel 8086, namely the minimum mode and the maximum
mode.
When only one 8086 CPU is to be used in a microprocessor system, the 8086 is used in the Minimum mode of
operation.
In a multiprocessor system 8086 operates in the Maximum mode.
Pin Description for Minimum Mode
In this minimum mode of operation, the pin MN/MX is connected to 5V D.C. supply i.e. MN/MX = VCC.
The description about the pins from 24 to 31 for the minimum mode is as follows:
INTA (Output): Pin number 24 interrupts acknowledgement. On receiving interrupt signal, the processor
issues an interrupt acknowledgment signal. It is active LOW.
ALE (Output): Pin no. 25. Address latch enable. It goes HIGH during T1. The microprocessor 8086 sends this
signal to latch the address into the Intel 8282/8283 latch.
DEN (Output): Pin no. 26. Data Enable. When Intel 8287/8286 octal bus transceiver is used this signal. It is
active LOW.
DT/R (output): Pin No. 27 data Transmit/Receives. When Intel 8287/8286 octal bus transceiver is used this
signal controls the direction of data flow through the transceiver. When it is HIGH, data is sent out. When it
is LOW, data is received.
M/IO (Output): Pin no. 28, Memory or I/O access. When this signal is HIGH, the CPU wants to access
memory. When this signal is LOW, the CPU wants to access I/O device.
WR (Output): Pin no. 29, Write. When this signal is LOW, the CPU performs memory or I/O write operation.
HLDA (Output): Pin no. 30, Hold Acknowledgment. It is sent by the processor when it receives HOLD signal.
It is active HIGH signal. When HOLD is removed HLDA goes LOW.
HOLD (Input): Pin no. 31, Hold. When another device in microcomputer system wants to use the address
and data bus, it sends HOLD request to CPU through this pin. It is an active HIGH signal.
Pin Description for Maximum Mode
In the maximum mode of operation, the pin MN/¯MX is made LOW. It is grounded. The description about
the pins from 24 to 31 is as follows:
QS1, QS0 (Output): Pin numbers 24, 25, Instruction Queue Status. Logics are given below:
QS1 QS0 Operation
0 0 No operation
0 1 1st byte of opcode from queue.
1 0 Empty the queue
1 1 Subsequent byte from queue
S0, S1, S2 (Output): Pin numbers 26, 27, 28 Status Signals. These signals are connected to the bus controller
of Intel 8288. This bus controller generates memory and I/O access control signals. Logics for status signal
are given below:
S2 S1 S0 Operation
0 0 0 Interrupt acknowledgement
0 0 1 Read data from I/O port
0 1 0 Write data from I/O port
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 Memory read
1 1 0 Memory write
1 1 1 Passive state
LOCK (Output): Pin no. 29. It is an active LOW signal. When this signal is LOW, all interrupts are masked and
no HOLD request is granted. In a multiprocessor system all other processors are informed through this signal
that they should not ask the CPU for relinquishing the bus control.
RG/GT1, RQ/GT0 (Bidirectional): Pin numbers 30, 31, Local Bus Priority Control. Other processors ask the
CPU by these lines to release the local bus.
In the maximum mode of operation signals WR, ALE, DEN, DT/R etc. are not available directly from the
processor. These signals are available from the controller 8288.
Functional units of 8086
8086 contains two independent functional units: a Bus Interface Unit (BIU) and an Execution Unit (EU).
Fig: Block Diagram of Intel 8086 Microprocessor (8086 Architecture)
Bus Interface Unit (BIU)
The segment registers, instruction pointer and 6-byte instruction queue are associated with the bus interface
unit (BIU).
The BIU:
o Handles transfer of data and addresses,

o Fetches instruction codes, stores fetched instruction codes in first-in-first-out register set called
a queue,
o Reads data from memory and I/O devices,
o Writes data to memory and I/O devices,
o It relocates addresses of operands since it gets un-relocated operand addresses from EU. The EU tells
the BIU from where to fetch instructions or where to read data.
It has the following functional parts:
o Instruction Queue: When EU executes instructions, the BIU gets 6-bytes of the next instruction and
stores them in the instruction queue and this process is known as instruction pre fetch. This process
increases the speed of the processor.
o Segment Registers: A segment register contains the addresses of instructions and data in memory
which are used by the processor to access memory locations. It points to the starting address of a
memory segment currently being used.
There are 4 segment registers in 8086 as given below:
o Code Segment Register (CS): Code segment of the memory holds instruction codes of a
program.
o Data Segment Register (DS): The data, variables and constants given in the program are held
in the data segment of the memory.
o Stack Segment Register (SS): Stack segment holds addresses and data of subroutines. It also
holds the contents of registers and memory locations given in PUSH instruction.
o Extra Segment Register (ES): Extra segment holds the destination addresses of some data of
certain string instructions.
o Instruction Pointer (IP): The instruction pointer in the 8086 microprocessor acts as a program
counter. It indicates to the address of the next instruction to be executed.
Execution Unit (EU)
o The EU receives opcode of an instruction from the queue, decodes it and then executes it. While
Execution, unit decodes or executes an instruction, then the BIU fetches instruction codes from the
memory and stores them in the queue.
o The BIU and EU operate in parallel independently. This makes processing faster.
o General purpose registers, stack pointer, base pointer and index registers, ALU, flag registers (FLAGS),
instruction decoder and timing and control unit constitute execution unit (EU). Let's discuss them:
o General Purpose Registers: There are four 16-bit general purpose registers: AX (Accumulator
Register), BX (Base Register), CX (Counter) and DX. Each of these 16-bit registers are further
subdivided into 8-bit registers as shown below:
16-bit registers 8-bit high-order registers 8-bit low-order registers
AX AH AL
BX BH BL
CX CH CL
DX DH DL
o Index Register: The following four registers are in the group of pointer and index registers:
o Stack Pointer (SP)
o Base Pointer (BP)
o Source Index (SI)
o Destination Index (DI)
o ALU: It handles all arithmetic and logical operations. Such as addition, subtraction, multiplication,
division, AND, OR, NOT operations.
o Flag Register: It is a 16?bit register which exactly behaves like a flip-flop, means it changes states
according to the result stored in the accumulator. It has 9 flags and they are divided into 2 groups i.e.
conditional and control flags.
o Conditional Flags: This flag represents the result of the last arithmetic or logical instruction
executed. Conditional flags are:
o Carry Flag
o Auxiliary Flag
o Parity Flag
o Zero Flag
o Sign Flag
o Overflow Flag
o Control Flags: It controls the operations of the execution unit. Control flags are:
o Trap Flag
o Interrupt Flag
o Direction Flag
Interrupts
Interrupt is a process of creating a temporary halt during program execution and allows peripheral devices
to access the microprocessor.
Microprocessor responds to these interrupts with an interrupt service routine (ISR), which is a short
program or subroutine to instruct the microprocessor on how to handle the interrupt.
There are different types of interrupt in 8086:
Hardware Interrupts
Hardware interrupts are that type of interrupt which are caused by any peripheral device by sending a signal
through a specified pin to the microprocessor.
The Intel 8086 has two hardware interrupt pins:
o NMI (Non-Maskbale Interrupt)

o INTR (Interrupt Request) Maskable Interrupt.
NMI: NMI is a single Non-Maskable Interrupt having higher priority than the maskable interrupt.
o It cannot be disabled (masked) by user using software.

o It is used by the processor to handle emergency conditions.
For example: It can be used to save program and data in case of power failure. An external electronic
circuitry is used to detect power failure, and to send an interrupt signal to 8086 through NMI line.
INTR: The INTR is a maskable interrupt. It can be enabled/disabled using interrupt flag (IF). After receiving
INTR from external device, the 8086 acknowledges through INTA signal.
It executes two consecutive interrupt acknowledge bus cycles.
Software Interrupt
A microprocessor can also be interrupted by internal abnormal conditions such as overflow; division by zero;
etc. A programmer can also interrupt microprocessor by inserting INT instruction at the desired point in the
program while debugging a program. Such an interrupt is called a software interrupt.
The interrupt caused by an internal abnormal conditions also came under the heading of software interrupt.
Example of software interrupts are:
o TYPE 0 (division by zero)

o TYPE 1 (single step execution for debugging a program)
o TYPE 2 represents NMI (power failure condition)
o TYPE 3 (break point interrupt)
o TYPE 4 (overflow interrupt)
Interrupt pointer table for 8086
Fig: Interrupt pointer table for 8086
The 8086 can handle up to 256, hardware and software interrupts.
1KB memory acts as a table to contain interrupt vectors (or interrupt pointers), and it is called interrupt
vector table or interrupt pointer table. The 256 interrupt pointers have been numbered from 0 to 255 (FF
hex). The number assigned to an interrupt pointer is known as type of that interrupt. For example, Type 0,
Type 1, Type 2,...........Type 255 interrupt.
Addressing modes of 8086
The way for which an operand is specified for an instruction in the accumulator, in a general purpose register
or in memory location, is called addressing mode.
The 8086 microprocessors have 8 addressing modes. Two addressing modes have been provided for
instructions which operate on register or immediate data.
These two addressing modes are:
Register Addressing: In register addressing, the operand is placed in one of the 16-bit or 8-bit general
purpose registers.
Example
o MOV AX, CX
o ADD AL, BL
o ADD CX, DX
Immediate Addressing: In immediate addressing, the operand is specified in the instruction itself.
Example
o MOV AL, 35H

o MOV BX, 0301H
o MOV [0401], 3598H
o ADD AX, 4836H
The remaining 6 addressing modes specify the location of an operand which is placed in a memory.
These 6 addressing modes are:
Direct Addressing: In direct addressing mode, the operand?s offset is given in the instruction as an 8-bit or
16-bit displacement element.
Example
o ADD AL, [0301]
The instruction adds the content of the offset address 0301 to AL. the operand is placed at the given offset
(0301) within the data segment DS.
Register Indirect Addressing: The operand's offset is placed in any one of the registers BX, BP, SI or DI as
specified in the instruction.
Example
o MOV AX, [BX]
It moves the contents of memory locations addressed by the register BX to the register AX.
Based Addressing: The operand's offset is the sum of an 8-bit or 16-bit displacement and the contents of
the base register BX or BP. BX is used as base register for data segment, and the BP is used as a base register
for stack segment.
Effective address (Offset) = [BX + 8-bit or 16-bit displacement].
Example
o MOV AL, [BX+05]; an example of 8-bit displacement.

o MOV AL, [BX + 1346H]; example of 16-bit displacement.
Indexed Addressing: The offset of an operand is the sum of the content of an index register SI or DI and an
8-bit or 16-bit displacement.
Offset (Effective Address) = [SI or DI + 8-bit or 16-bit displacement]
Example
o MOV AX, [SI + 05]; 8-bit displacement.

o MOV AX, [SI + 1528H]; 16-bit displacement.
Based Indexed Addressing: The offset of operand is the sum of the content of a base register BX or BP and
an index register SI or DI.
Effective Address (Offset) = [BX or BP] + [SI or DI]
Here, BX is used for a base register for data segment, and BP is used as a base register for stack segment.
Example
o ADD AX, [BX + SI]

o MOV CX, [BX + SI]
Based Indexed with Displacement: In this mode of addressing, the operand's offset is given by:
Effective Address (Offset) = [BX or BP] + [SI or DI] + 8-bit or 16-bit displacement
Example
o MOV AX, [BX + SI + 05]; 8-bit displacement

o MOV AX, [BX + SI + 1235H]; 16-bit displacement
Unit 4 : ASSEMBLY LANGUAGE
Simple Programs
Let's see the simple example of printing 1 to 10 numbers using respective languages.
Program in C
1. #include<stdio.h>
2. int main()
3. {
4. int i=1;
5. do
6. {
7. printf("%d ",i);
8. i++;
9. }while(i<=10);
10. return 0;
11. }
In this program, the value of i is 1. The "do-while" loop is used in this program to print the numbers from 1
to 10 using printf() function.
Program in C++
1. #include<iostream>
2. using namespace std;
3. int main()
4. {
5. int i=1;
6. do
7. {
8. std::cout <<i<<" ";
9. i++;
10. }while(i<=10);
11. return 0;
12. }
In this program, i contains the value 1. The do while loop is used to print the numbers from 1 to 10 using
cout object.
Program in C#
1. using System;
2. namespace Rextester
3. {
4. public class Program
5. {
6. public static void Main(string[] args)
7. {
8. int i=1;
9. do{
10. Console.Write(i);
11. Console.Write(" ");
12. i++;
13. }while(i<=10);
14. } }}
In this example, i contains the value 1. The do-while loop is used in this program to print the numbers from
1 to 10 using Console.Write().
Program in Java
1. public class HelloWorld{
2. public static void main(String []args){
3. int i=1;
4. do
5. {
6. System.out.print(i);
7. System.out.print(" ");
8. i++;
9. }while(i<=10);
10.
11. }
12. }
In this example, i contains the value 1. The do-while loop is used in this program to print the numbers from
1 to 10 using System.out.print().
Program in JavaScript
1. <script>
2. var i=1;
3. do
4. {
5. document.write(i);
6. document.write(" ");
7. i++;
8. }while(i<=10)
9. </script>
10. </p>
In this program, variable i contains the value 1. The do while loop is used in this program to print 1 to 10
numbers using document.write() funtion.
Program in Perl
1. $i=1;
2. do
3. {
4. printf("$i");
5. printf(" ");
6. $i=$i+1;
7. }while($i<=10);
In this program, $i contains the value 1 and printf() function is used to print the numbers from 1 to 10.
Program in PHP
1. <?php //php 7.0.8
2. $i=1;
3. do{
4. echo $i;
5. echo " ";
6. $i=$i+1;
7. }while($i<=10);
8. ?>
In this program, $i contains the value 1 and an echo statement is used to print the values of i.
Program in Ruby
1. $i=1;
2. loop do
3. print $i;
4. $i=$i+1;
5. break if($i>10)
6. end
In this program, ruby contains "do if" block. This loop opposes the "if-condition" i.e the i>10. Therefore, the
loop is executed till i=10. When, i becomes 11, control terminates the loop.
Program in Swift
1. var i=1
2. repeat{
3. print ("\(i)")
4. i=i+1;
5. }while(i<=10)
In this program, variable i contains the value 1.The "repeat -while" loop is executed till i=10. When i becomes
11, it leads to the termination of a loop.
Output:
1 2 3 4 5 6 7 8 9 10
Assembly Language
Assembly language is introduced for providing mnemonics or symbols for the machine level code
instructions. Assembly language program is consisting of mnemonics that is translated into machine code. A
program that is used for this conversion is known as assembler.
Assembly language is also called as low-level language because it directly works with the internal structure
of CPU. For programming in assembly language, a programmer must have the knowledge of all the registers
in a CPU.
Different programming languages like C, C++, Java and various other languages are called as high-level
languages because they are not dealing with the internal details of CPU.
Assembling and Running of 8051 Program
Let's see the steps for creating, assembling and running an assembly language program are as follows:
o Editor Program : At first, we use an editor for type in a program. Editors like MS-DOS program that
comes with all Microsoft operating systems can be used for creating or edit a program. The editor
produces an ASCII file. The ?asm? extension for a source file is used by an assembler during next step.
o Assembler Program: The "asm" source file contain the code created in Step 1. It is transferred to an
8051 assembler. The assembler is used for converting the assembly language instructions into
machine code instructions and it produced the .obj file (object file) and .lst file (list file). It is also
called as source file because some assembler requires that this file must have "src" extension.
o Linker Program: The linker program is used for generating one or more object files and produces an
absolute object file with an extension "abs".
o OH Program: The OH program fetches the "abs" file and fed it to a program called "OH". OH is called
as object to hex converter it creates a file with an extension "hex" that is ready for burn in to the
ROM.
Labels in assembly Language
All labels used in assembly language follow the certain rules as given below:
o Each label name should be unique. The name used as label in assembly language programming
consist of alphabetic letters in both lowercase and uppercase, numbers from 0 to 9, and special
characters such as at the rate (@), question mark (?), underscore(_), and dollar ($) etc.
o Reserved words are not allowed to be used as a label in the program. For example, MOV and ADD
words are reserved words.
o The first character must be an alphabetical character, it cannot be a number.
Branch Instruction in Computer Organization
A branch is an instruction in a computer program that can cause a computer to begin executing a different
instruction sequence and thus deviate from its default behaviour of executing instructions in order. Branch
may also refer to the act of switching execution to a different instruction sequence as a result of executing
a branch instruction. Branch instructions are used to implement control flow in program loops and
conditionals (i.e., executing a particular sequence of instructions only if certain conditions are satisfied).
A branch instruction can be either an unconditional branch, which always results in branching or
a conditional branch, which may or may not cause branching depending on some condition. Also, depending
on how it specifies the address of the new instruction sequence (the target address).
A branch instruction is generally classified as direct, indirect or relative. It means the instruction contains
the target address, specifies where the target address is to be found (e.g., a register or memory location), or
specifies the difference between the current and target addresses. A branch instruction computes the target
address in one of four ways:
o A target address is the sum of a constant and the address of the branch instruction itself.
o The target address is the absolute address given as an operand to the instruction.
o The target address is the address found in the Link Register.
o The target address is the address found in Count Register.
The target address can be computed sufficiently ahead of the branch to pre-fetch instructions along the
target path using the first two methods.
Using the third and fourth methods, pre-fetching instructions along the branch path is also possible provided
the Link Register or Count Register is loaded sufficiently ahead of the branch instruction.
Types of Brach Instructions
There are three types of branching instructions in computer organization:
1. Jump Instructions
The jump instruction transfers the program sequence to the memory address given in the operand based on
the specified flag. Jump instructions are further divided into two parts, Unconditional Jump Instructions and
Conditional Jump Instructions.
o Unconditional Jump Instructions:Transfers the program sequence to the described memory address.
o Conditional Jump Instructions: Transfers the program sequences to the described memory address
only if the condition is satisfied.
2. Call Instructions
The call instruction transfers the program sequence to the memory address given in the operand. Before
transferring, the address of the next instruction after CALL is pushed onto the stack. Call instructions are also
two types: Unconditional Call Instructions and Conditional Call Instructions.
o Unconditional Call Instructions:It transfers the program sequence to the memory address given in
the operand.
o Conditional Call Instructions:Only if the condition is satisfied, the instructions execute.
3. Return Instructions
The return instruction transfers the program sequence from the subroutine to the calling program. Return
instructions are two types: Unconditional Jump Instructions and Conditional Jump Instructions.
o Unconditional Return Instruction:The program sequence is transferred unconditionally from the

subroutine to the calling program.
o Conditional Return Instruction: The program sequence is transferred unconditionally from the
subroutine to the calling program only if the condition is satisfied.
Implementation of Branch Instruction
Mechanically, a branch instruction can change the program counter of a CPU. The program counter stores
the memory address of the next instruction to be executed. Therefore, a branch can cause the CPU to begin
fetching its instructions from a different sequence of memory cells. Machine level branch instructions are
sometimes called jump instructions.
1. Machine level jump instructions typically have unconditional and conditional forms where the latter
may be takenor not taken depending on some condition. Usually, there are distinct forms for one-
way jump, called jump and subroutine invocations are known as a call, which automatically saves the
originating address as a return address on the stack, allowing a single subroutine to be invoked from
multiple locations in code.
o When a branch is taken, the CPU's program counter is set to the argumentof the jump
instruction. So, the next instruction becomes the instruction at that address in memory.
Therefore, the flow of control changes.
o When a branch is not taken, the CPU's program counter is unchanged. Therefore, the next
instruction executed is the instruction after the branch instruction. Therefore, the flow of
control is unchanged.
2. The term branch can refer to programs in high-level languages and written in machine codeor
assembly language.
o In high-level programming languages, branches usually take the form of conditional
statementsof various forms that encapsulate the instruction sequence that will be executed
if the conditions are satisfied.
o Unconditional branch instructions such as GOTOare used to unconditionally "jump" to (begin
execution of) a different instruction sequence.
3. In CPUs with flag registers, an earlier instruction sets a condition in the flag register. The earlier
instruction may be arithmetic or logic It is often close to the branch, though not necessarily the
instruction immediatelybefore the branch.
o The stored condition is then used in a branch such as a jump if overflow-flag set.
o This temporary information is often stored in a flag register but may also be located
elsewhere.
o A flag register design is simple in slower, simple computers. A flag register can place a
bottleneck on speed in fast computers because instructions that could operate in parallel
need to set the flag bits in a particular sequence.
4. There are also machines or particular instructions where the condition may be checked by the jump
instruction itself, such as branch <label> if register X negative. In simple computer designs,
comparison branches execute more arithmetic and use more power than flag register branches.
o Computer design comparison branches can run faster than flag register branches because
comparison branches can access the registers with more parallelism, using the same CPU
mechanisms as a calculation.
5. Some early and simple CPU architectures, still found in microcontrollers, may not implement a
conditional jump but rather a conditional "skip the next instruction" operation. A conditional jump
or call is thus implemented as a conditional skip of an unconditional jump or call instruction.
Handling of Branch Instructions
Branch instructions can handle in several ways to reduce their negative impact on the rate of execution of
instructions.
1. Branch delay slot
The processor fetches the next instructions before it determines whether the current instruction is a branch
instruction. When execution of current instruction is completed, and a branch is to be made, the processor
must discard remaining instructions and fetch the new branched instruction at the branch target. The
location following a branch instruction is called a branch delay slot. Depending on the time to execute a
branch instruction, there may be more than one branch delay slot.
A technique called delayed branching can minimize the penalty incurred as a result of conditional branch
instructions. The instructions in the delay slots are always fetched. Therefore, we would like to arrange for
them to be fully executed whether the branch is taken or not taken. The objective is to be able to place
useful instructions in these slots. If no useful instructions can be placed in the delay slots, these slots must
be filled with NOP instructions.
2. Branch prediction
Branch prediction took statistics and used the result to optimize code. A programmer would compile a test
version of a program and run it with test data.
o The test code counted how the branches were taken.

o The compiler then used the statistics from the test code to optimize the branches of the released
code. The optimization would arrange that the fastest branch direction (taken or not) would always
be the most frequently taken control flow path.
o To permit this, CPUs must be designed with predictable branch timing. Some CPUs have instruction
sets designed with "branch hints" so that a compiler can tell a CPU how each branch is to be taken.
The problem with software branch prediction is that it requires a complex software development process.
3. Branch-free code
Some logic can be written without branches or with fewer branches. It is often possible to use bitwise
operations, conditional moves or other predication instead of branches. Branch-free code is a must for
cryptography due to timing attacks.
4. Hardware branch predictors
To run any software, hardware branch predictors moved the statistics into the electronics. Branch predictors
are parts of a processor that guess the outcome of a conditional branch. Then the processor's logic gambles
on the guess by beginning to execute the expected instruction flow.
An example of a simple hardware branch prediction scheme is to assume that all backward branches (to a
smaller program counter) are taken (because they are part of a loop), and all forward branches (to a larger
program counter) are not taken (because they leave a loop).
Better branch predictors are developed and validated statistically by running them in simulation on various
test programs. Good predictors usually count the outcomes of previous executions of a branch.
Sorting Algorithms
Sorting is the process of arranging the elements of an array so that they can be placed either in ascending or
descending order. For example, consider an array A = {A1, A2, A3, A4, ?? An }, the array is called to be in
ascending order if element of A are arranged like A1 > A2 > A3 > A4 > A5 > ? > An .
Consider an array;
int A[10] = { 5, 4, 10, 2, 30, 45, 34, 14, 18, 9 )
The Array sorted in ascending order will be given as;
A[] = { 2, 4, 5, 9, 10, 14, 18, 30, 34, 45 }
There are many techniques by using which, sorting can be performed. In this section of the tutorial, we will
discuss each method in detail.
Sorting Algorithms
Sorting algorithms are described in the following table along with the description.
SN Sorting Description
Algorithms
1 Bubble Sort It is the simplest sort method which performs sorting by repeatedly moving the
largest element to the highest index of the array. It comprises of comparing each
element to its adjacent element and replace them accordingly.
2 Bucket Sort Bucket sort is also known as bin sort. It works by distributing the element into the
array also called buckets. In this sorting algorithms, Buckets are sorted individually
by using different sorting algorithm.
3 Comb Sort Comb Sort is the advanced form of Bubble Sort. Bubble Sort compares all the
adjacent values while comb sort removes all the turtle values or small values near
the end of the list.
4 Counting Sort It is a sorting technique based on the keys i.e. objects are collected according to
keys which are small integers. Counting sort calculates the number of occurrence
of objects and stores its key values. New array is formed by adding previous key
elements and assigning to objects.
5 Heap Sort In the heap sort, Min heap or max heap is maintained from the array elements
deending upon the choice and the elements are sorted by deleting the root
element of the heap.
6 Insertion Sort As the name suggests, insertion sort inserts each element of the array to its proper
place. It is a very simple sort method which is used to arrange the deck of cards
while playing bridge.
7 Merge Sort Merge sort follows divide and conquer approach in which, the list is first divided
into the sets of equal elements and then each half of the list is sorted by using
merge sort. The sorted list is combined again to form an elementary sorted array.
8 Quick Sort Quick sort is the most optimized sort algorithms which performs sorting in O(n log
n) comparisons. Like Merge sort, quick sort also work by using divide and conquer
approach.
9 Radix Sort In Radix sort, the sorting is done as we do sort the names according to their
alphabetical order. It is the lenear sorting algorithm used for Inegers.
10 Selection Sort Selection sort finds the smallest element in the array and place it on the first place
on the list, then it finds the second smallest element in the array and place it on
the second place. This process continues until all the elements are moved to their
correct ordering. It carries running time O(n2) which is worst than insertion sort.
11 Shell Sort Shell sort is the generalization of insertion sort which overcomes the drawbacks of
insertion sort by comparing elements separated by a gap of several positions.
Evaluation of Expressions
In our previous sections, we understood various concepts in query processing. We learned about the query
processing steps, selection operations, and also several types of algorithms used for performing the join
operation with their cost estimations.
We are already aware of computing and representing the individual relational operations for the given user
query or expression. Here, we will get to know how to compute and evaluate an expression with multiple
operations.
For evaluating an expression that carries multiple operations in it, we can perform the computation of each
operation one by one. However, in the query processing system, we use two methods for evaluating an
expression carrying multiple operations. These methods are:
1. Materialization
2. Pipelining
Let's take a brief discussion of these methods.
Materialization
In this method, the given expression evaluates one relational operation at a time. Also, each operation is
evaluated in an appropriate sequence or order. After evaluating all the operations, the outputs are
materialized in a temporary relation for their subsequent uses. It leads the materialization method to a
disadvantage. The disadvantage is that it needs to construct those temporary relations for materializing the
results of the evaluated operations, respectively. These temporary relations are written on the disks unless
they are small in size.
Pipelining
Pipelining is an alternate method or approach to the materialization method. In pipelining, it enables us to

evaluate each relational operation of the expression simultaneously in a pipeline. In this approach, after
evaluating one operation, its output is passed on to the next operation, and the chain continues till all the
relational operations are evaluated thoroughly. Thus, there is no requirement of storing a temporary relation
in pipelining. Such an advantage of pipelining makes it a better approach as compared to the approach used
in the materialization method. Even the costs of both approaches can have subsequent differences in-
between. But, both approaches perform the best role in different cases. Thus, both ways are feasible at their
place.
We have described and discussed the materialization as well as pipelining method deeply in our next sections
one by one.
Assembler Directives of the 8086 Microprocessor

(a) The DB directive
(b) The DW directive
(c) The DD directive
(d) The STRUCT (or STRUC) and ENDS directives (counted as one)
(e)The EQU Directive
(f)The COMMENT directive
(g)ASSUME
(h) EXTERN
(i) GLOBAL
(j) SEGMENT
(k)OFFSET
(l) PROC
(m)GROUP
(n) INCLUDE
Data declaration directives:

1. DB – The DB directive is used to declare a BYTE -2-BYTE variable – A BYTE is made up of 8 bits.
Declaration examples:
Byte1 DB 10h
Byte2 DB 255 ; 0FFh, the max. possible for a BYTE
CRLF DB 0Dh, 0Ah, 24h ;Carriage Return, terminator BYTE
2. DW – The DW directive is used to declare a WORD type variable – A WORD occupies 16 bits or (2
BYTE).
Word DW 1234h
Word2 DW 65535; 0FFFFh, (the max. possible for a WORD)

3. DD – The DD directive is used to declare a DWORD – A DWORD double word is made up of 32 bits =2
Word’s or 4 BYTE.
Dword1 DW 12345678h
Dword2 DW 4294967295 ;0FFFFFFFFh.
4. STRUCT and ENDS – The directives to define a structure template for grouping data items.
(1) The STRUCT directive tells the assembler that a user defined uninitialized data structure follows. The
uninitialized data structure consists of a combination of the three supported data types. DB, DW, and DD.
The labels serve as zero-based offsets into the structure. The first element’s offset for any structure is 0. A
structure element is referenced with the base “+” operator before the element’s name.
A Structure ends by using the ENDS directive meaning END of Structure.
Syntax:
STRUCT
Structure_element_name element_data_type?
...
...
...
ENDS
(OR)
STRUC
Structure_element_name element_data_type?
...
...
...
ENDS
DECLARATION:
STRUCT
Byte1 DB?
Byte2 DB?
Word1 DW?
Word2 DW?
Dword1DW?
Dword2 DW?
ENDS
Use OF STRUCT:
The STRUCT directive enables us to change the order of items in the structure when, we reform a file
header and shuffle the data. Shuffle the data items in the file header and reformat the sequence of data
declaration in the STRUCT and off you go. No change in the code we write that processes the file header is
necessary unless you inserted an extra data element.
(5) The EQU Directive

The EQU directive is used to give name to some value or symbol. Each time the assembler finds the given
names in the program, it will replace the name with the value or a symbol. The value can be in the range 0
through 65535 and it can be another Equate declared anywhere above or below.
The following operators can also be used to declare an Equate:

THIS BYTE
THIS WORD
THIS DWORD
A variable – declared with a DB, DW, or DD directive – has an address and has space reserved at that
address for it in the .COM file. But an Equate does not have an address or space reserved for it in the .COM
file.
Example:
A – Byte EQU THIS BYTE
DB 10
A_ word EQU THIS WORD
DW 1000
A_ dword EQU THIS DWORD
DD 4294967295
Buffer Size EQU 1024
Buffer DB 1024 DUP (0)
Buffed_ ptr EQU $ ; actually points to the next byte after the; 1024th byte in buffer.
(6) Extern:
It is used to tell the assembler that the name or label following the directive are I some other assembly
module. For example: if you call a procedure which is in program module assembled at a different time
from that which contains the CALL instructions ,you must tell the assembler that the procedure is external
the assembler will put information in the object code file so that the linker can connect the two module
together.
Example:
PROCEDURE -HERE SEGMENT
EXTERN SMART-DIVIDE: FAR ; found in the segment; PROCEDURES-HERE
PROCEDURES-HERE ENDS
(7) GLOBAL:
The GLOBAL directive can be used in place of PUBLIC directive .for a name defined in the current assembly
module; the GLOBAL directive is used to make the symbol available to the other modules. Example:
GLOBAL DIVISOR:
WORD tells the assembler that DIVISOR is a variable of type of word which is in another assembly module
or EXTERN.
(8) SEGMENT:
It is used to indicate the start of a logical segment. It is the name given to the the segment. Example: the
code segment is used to indicate to the assembler the start of logical segment.
(9) PROC: (PROCEDURE)

It is used to identify the start of a procedure. It follows a name we give the procedure.
After the procedure the term NEAR and FAR is used to specify the procedure Example: SMART-DIVIDE
PROC FAR identifies the start of procedure named SMART-DIVIDE and tells the assembler that the
procedure is far.
(10) NAME:
It is used to give a specific name to each assembly module when program consists of several modules.
Example: PC-BOARD used to name an assembly module which contains the instructions for controlling a
printed circuit board.
(11) INCLUDE:
It is used to tell the assembler to insert a block of source code from the named file into the current source
module. This shortens the source module. An alternative is use of editor block command to cop the file
into the current source module.
(12) OFFSET:
It is an operator which tells the assembler to determine the offset or displacement of a named data item
from the start of the segment which contains it. It is used to load the offset of a variable into a register so
that variable can be accessed with one of the addressed modes. Example: when the assembler read MOV
BX.OFFSET PRICES, it will determine the offset of the prices.
(13) GROUP:
It can be used to tell the assembler to group the logical segments named after the directive into one logical
group. This allows the contents of all he segments to be accessed from the same group. Example: SMALL-
SYSTEM GROUP CODE, DATA, STACK-SEG.
Difference between Macro and Procedure
A microprocessor is a computer system processor that accomplishes the functions of a CPU on a single
integrated circuit. It manages the output devices, processes instructions stored in its memory, and shows
the results. These processors are made up of both combinational and sequential digital circuitry.
Furthermore, Assembly language is a programming language that aids in the programming of
microprocessors. Both Macro and Procedure are two ideas that are utilized in microprocessor programming.
The primary distinction between these processes is that the Macro is utilized for a small number of
commands. In contrast, the Procedure is utilized for a large number of instructions.
In this article, you will learn about the difference between Macro and Procedure. But before discussing the
differences, you must know about Macro and Procedure.
What is Macro?
Macro is a sequence of instructions that may be utilized anywhere in the software by utilizing its name. It is
primarily used for modular programming. As a result, the same set of instructions may be utilized several
times with the help of a macro. The macro's identifier is substituted with the actual defined instructions
during compilation. Therefore no calling and returning occur.
Syntax:
1. %macro macro_name number_of_params

2. <macro body>
3. %endmacro
Explanation:
The macro_name is used to identify the macro, while the number_of_params is utilized to represent the
number of parameters. In addition, the macro can be invoked using the macro name and the appropriate
parameters. As a result, if the same set of directives must be executed numerous times, the programmer
may write those directives in a macro and utilize it in his program.
What is the Procedure?
Procedures are similar to macros, but these are utilized for large sets of instructions, whereas macros are
beneficial for tiny sets of instructions. It includes sets of instructions that accomplish a specified goal. It has
three major components: the procedure name, which identifies the process. The procedure body contains a
sequence of instructions, and the RET statement, which signifies the return statement. Procedures use the
call-return approach to achieve complete modularity.
Syntax:
1. procedure_name :
2. procedure body
3. ?.......................
4. RET
To call a procedure function, you can use this:
1. CALL procedure_name
Finally, the control transfers to the calling procedure via the RET instruction after the procedure has been
completed.
Key Differences between Macro and Procedure
Here, you will learn about the key differences between Macro and Procedure. Some of the main differences
between the Macro and Procedure are as follows:
1. A macro definition defines a macro as a series of instructions that facilitate modular programming.
On the other hand, a procedure is a sequence of instructions that a programmer can repeatedly
invoke and that carry out a particular task.
2. When a macro is called, a new machine code is created. In contrast, only one instance of the machine
code is generated during the procedure.
3. A macro also removes the overhead time involved in calling the procedure and starting the program
again. In contrast, calling a process and returning to the calling procedure from the calling procedure
require greater overhead time.
4. The parameters in the macro are given as part of a sentence that calls the macro. In contrast,
parameters are supplied in registers and memory locations on the stack in a procedure.
5. CALL and RET instructions are not required for the macro. On the other hand, a procedure
necessitates CALL and RETS commands.
6. A macro is utilized for a small number of instructions, usually less than ten. In contrast, a procedure
is utilized for a large number of instructions, usually more than ten.
7. A macro necessitates extra memory. On the other hand, a procedure necessitates less memory.
8. The execution speed of a macro is faster. In contrast, the execution speed of a procedure is slower
than a macro.
Head-to-head comparison between Macro and Procedure
Here, you will learn the head-to-head comparisons between Macro and Procedure. The main differences
between Macro and Procedure are as follows:
Features Macro Procedure
Definition It is a series of rules or programmable It is a sequence of instructions that a

patterns that decrypts a specified input programmer can repeatedly call to
sequence into a predefined output sequence. execute a specified purpose.
Memory It needs large memory. It needs less memory.

Requirement
Machine Code When a macro is called, a new machine code Only one instance of the machine code
is created. is generated during the procedure.
Sets of It is utilized for a small number of instructions, It is utilized for a large number of
Instructions usually less than ten. instructions, usually more than ten.
CALL and RET It doesn't need CALL and RET instructions. It needs CALL and RET instructions.
Overhead Time It removes the overhead time involved in Calling a process and returning to the
calling the procedure and starting the calling procedure from the calling
program again. procedure require greater overhead
time.
Execution The execution speed of a macro is faster. The execution speed of a procedure is
Speed slower than a macro.
Passing A parameter is passed as part of the The parameters are transmitted

Parameters statement that calls the macro in a macro. through registers and stack memory
addresses.
Assembler Assembly directive MACRO is utilized to Assembler directive PROC is utilized to

Directives define macros, while the assembler directive specify the procedure, and ENDP is
ENDM is utilized to signify that the body has utilized to signify that the body has
finished. finished.
Conclusion
In summary, assembly language is a popular programming language that is utilized for microprocessor
programming, and Macro and Procedure are two Assembly concepts. A macro is utilized for a limited number
of instructions, usually less than ten. In contrast, a procedure is utilized for a large number of instructions,
usually more than ten.
Unit 5 : Memory and Digital Interface
Memory and I/O Interfacing
Several memory chips and I/O devices are connected to a microprocessor.
The following figure shows a schematic diagram to interface memory chips and I/O devices to a
microprocessor.
Memory Interfacing
When we are executing any instruction, the address of memory location or an I/O device is sent out by the
microprocessor. The corresponding memory chip or I/O device is selected by a decoding circuit.
Memory requires some signals to read from and write to registers and microprocessor transmits some
signals for reading or writing data.
The interfacing process includes matching the memory requirements with the microprocessor signals.
Therefore, the interfacing circuit should be designed in such a way that it matches the memory signal
requirements with the microprocessor's signals.
I/O interfacing
As we know, keyboard and displays are used as communication channel with outside world. Therefore, it is
necessary that we interface keyboard and displays with the microprocessor. This is called I/O interfacing. For
this type of interfacing, we use latches and buffers for interfacing the keyboards and displays with the
microprocessor.
But the main drawback of this interfacing is that the microprocessor can perform only one function.
8279 Programmable Keyboard
The Intel 8279 is a programmable keyboard interfacing device. Data input and display are the integral part
of microprocessor kits and microprocessor-based systems.
8279 has been designed for the purpose of 8-bit Intel microprocessors.
8279 has two sections namely keyboard section and display section.
The function of the keyboard section is to interface the keyboard which is used as input device for the
microprocessor. It can also interface toggle or thumb switches.
The purpose of the display section is to drive alphanumeric displays or indicator lights. It is directly
connected to the microprocessor bus.
The microprocessor is relieved from the burden of scanning the keyboard or refreshing the display.
Some important Features are:
o Simultaneous keyboard display operations

o Scanned sensor mode
o Scanned keyboard mode
o 8-character keyboard FIFO
o Strobed input entry mode
o 2-key lock out or N-key roll over with contact debounce
o Single 16-charcter display
o Dual 8 or 16 numerical display
o Interrupt output on key entry
o Programmable scan timing and mode programmable from CPU
8257 DMA Controller
The data transfer from fast I/O devices to the memory or from the memory to I/O devices through the
accumulator is a time consuming process. For this situation, the Direct Memory Access (DMA) technique is
preferred. In DMA data transfer scheme, data is directly transferred from an I/O device to RAM or from RAM
to an I/O device.
Using a DMA controller, the device requests the CPU to hold its address, data and control bus, so the device
is free to transfer data directly to/from the memory. The DMA data transfer is initiated only after receiving
HLDA signal from the CPU.
How DMA operations are performed?
Following are the operations performed by a DMA:
o Initially, the device has to send DMA request (DRQ) to DMA controller for sending the data between
the device and the memory.
o The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU for the HLDA.
o When CPU gets the HLDA signal then, it leaves the control over the bus and acknowledges the HOLD
request through HLDA signal.
o Now the CPU is in the HOLD state and the DMA controller has to manage the operations over the
buses between the CPU, memory and I/O devices.
Intel 8257
o The Intel 8257 is a programmable DMA controller.

o It is a 4-channel programmable Direct Memory Access (DMA) controller.
o It is a 40 pin I.C. package and requires +5V supply for its operation.
o It can perform three operations, namely read, write, and verify.
o Each channel incorporates two 16-bit registers, namely DMA address register and byte count register.
o Each channel can transfer data up to 64kb and can be programmed independently.
o It operates in 2 -modes: Master mode and Slave mode.
8257 Architecture
The following diagram is the architecture of Intel 8257:

8257 Pin Description
DRQ0 - DRQ3: These are DMA request lines. An I/O device sends the DMA request on one of these lines. On
the line, a HIGH status generates a DMA request.
DACK0 - DACK3 : These are DMA acknowledge lines. The Intel 8257 sends an acknowledge signal through one
of these lines informing an I/O device that it has been selected for DMA data transfer. On the line, a LOW
acknowledges the I/O device.
A0 - A7: These are address lines. A0 - A3 are bidirectional lines. These lines carry 4 LSBs of 16-bit memory
address generated by the 8257 in the master mode. In the slave mode, these lines are all the input lines. The
inputs select one from the registers to be read or programmed. A 4 - A7 lines gives tristated outputs in the
master mode which carry 4 through 7 of the 16-bit memory address generated by the Intel 8257.
D0 - D7: These are data lines. These are bidirectional three state lines. While programming the controller the
CPU sends data for the DMA address register, the byte count register and the mode set register through
these data lines.
AEN: Address latch enable.
ADSTB: A HIGH on this line latches the 8MSBs of the address, which are sent on D-bus, into Intel 8212
connected for this purpose.
CS: It is chip select.

(I/OR): I/O read. It is a bidirectional line. In output mode it is used to access data from the I/O device during
the DMA write cycle.
(I/OW): I/O write. It is a bidirectional line. In output mode it allows the transfer of data to the I/O device
during the DMA read cycle. Data is transferred from the memory.
MEMR: Memory read
MEMW: Memory write
TC: Byte count (Terminal count).
MARK: Modulo 128 Mark.
CLK: Clock
HRQ: Hold request
HLDA: Hold acknowledge
INTERFACING MEMORY AND I/O DEVICES WITH 8085
The programs and data that are executed by the microprocessor have to be stored in ROM/EPROM and RAM,
which are basically semiconductor memory chips. The programs and data that are stored in ROM/EPROM
are not erased even when power supply to the chip is removed. Hence, they are called non-volatile memory.
They can be used to store permanent programs.
In a RAM, stored programs and data are erased when the power supply to the chip is removed. Hence, RAM
is called volatile memory. RAM can be used to store programs and data that include, programs written during
software development for a microprocessor based system, program written when one is learning assembly
language programming and data enter while testing these programs.
Input and output devices, which are interfaced with 8085, are essential in any microprocessor based system.
They can be interfaced using two schemes: I/O mapped I/O and memory-mapped I/O. In the I/O mapped I/O
scheme, the I/O devices are treated differently from memory. In the memory-mapped I/O scheme, each I/O
device is assumed to be a memory location.
INTERFACING MEMORY CHIPS WITH 8085
8085 has 16 address lines (A0 - A15), hence a maximum of 64 KB (= 216 bytes) of memory locations can be
interfaced with it. The memory address space of the 8085 takes values from 0000H to FFFFH.
Ex: Interface a 6264 IC (8K x 8 RAM) with the 8085 using NAND gate decoder such that the starting address
assigned to the chip is 4000H.
Specification of IC 6264:
· 8K x 8 RAM
· 8 KB = 213 bytes
· 13 address lines
The ending address of the chip is 5FFFH (since 4000H + 1FFFH = 5FFFH). When the address 4000H to 5FFFH
are written in binary form, the values in the lines A15, A14, A13 are 0, 1 and 0 respectively. The NAND gate
is designed such that when the lines A15 and A13 carry 0 and A14 carries 1, the output of the NAND gate is
0. The NAND gate output is in turn connected to the ^(CE1) pin of the RAM chip. A NAND output of 0 selects
the RAM chip for read or write operation, since CE2 is already 1 because of its connection to +5V. Fig. 18
shows the interfacing of IC 6264 with the 8085.
Ex: Interface two 6116 ICs with the 8085 using 74LS138 decoder such that the starting addresses assigned
to them are 8000H and 9000H, respectively.
Specification of IC 6116:
· 2 K x 8 RAM
· 2 KB = 211 bytes
· 11 address lines
6116 has 11 address lines and since 2 KB, therefore ending addresses of 6116 chip 1 is and chip 2 are 87FFH
and 97FFH, respectively. Table 10 shows the address range of the two chips.
Table 10 Address range for IC 6116

Interfacing:
· Fig. 19 shows the interfacing.
· A0 – A10 lines of 8085 are connected to 11 address lines of the RAM chips.
· Three address lines of 8085 having specific value for a particular RAM are connected to the three
select inputs (C, B and A) of 74LS138 decoder.
Peripheral Devices
To communicate with the outside world microcomputers use peripherals (I/O devices). Commonly used
peripherals are: A/D converter, D/A converter, CRT, printers, Hard disks, floppy disks, magnetic tapes etc.
Peripherals are connected to the microcomputer through electronic circuits known as interfacing circuits.
Programmable Peripheral interface (PPI)
A programmable peripheral interface is a multiport device. The ports may be programmed in a variety of
ways as required by the programmer. The device is very useful for interfacing peripheral devices. The term
PIA, Peripheral Interface Adapter is also used by some manufacturer.
Intel 8255
The Intel 8255 is a programmable peripheral interface (PPI). It has two versions, namely the Intel
8255A and Intel 8255A-5. General descriptions for both are same. There are some differences in their
electrical characteristics. Hereafter, they will be referred to as 8255. Its main functions are to interface
peripheral devices to the microcomputer.
It has three 8-bit ports, namely Port A, Port B and Port C. The port C has been further divided into two 4-bit
ports, port C upper and Port C lower. Thus a total of 4-ports are available, two 8-bit ports and two 4-bit ports.
Each port can be programmed either as an input port or an output port.
Operating Modes of 8255
The Intel 8255 has the following three modes of operation which are selected by software:
Mode 0 - Simple Input/output: The 8255 has two 8-bit ports (Port A and Port B) and two 4-bit ports (Port
Cupper and Port Clower). In Mode 0 operation, a port can be operated as a simple input or output port. Each of
the 4 ports of 8255 can be programmed to be either an input or output port.
Mode 1-Strobed Input/output: Mode 1 is strobed input/output mode of operation. The Port A and Port B
both are designed to operate in this mode of operation. When Port A and Port B are programmed in Mode
1, six pins of Port C are used for their control.
Mode 2 -Bidirectional Port: Mode 2 is strobed bidirectional mode of operation. In this mode Port A can be
programmed to operate as a bidirectional port. The mode 2 operation is only for Port A. When Port A is
programmed in Mode 2, the port B can be used either Mode 1 or Mode 0.
Architecture of Intel 8255
Intel 8255A pin description
It is a 40 pin I.C. package. It operates on a single 5 Vd.c. supply. Its important characteristics are as follows:
Ambient temperature 0 to 700C, Voltage on any pin: 0.5 V to 7 V. Power dissipation 1 Watt V IL = Input low
voltage = Minimum 0.5 V, Maximum 0.8 V. VIH = Input high voltage = Minimum 2 V, Maximum Vcc. VOL =
Output low voltage = 0.45 V VOH = Output High Voltage = 2.4 V IDR = Darlington drive connect = Minimum 1
mA, Maximum 4 mA of any 8 pins of the port.
The pins of various ports are as follows:
PA0 - PA7 8 Pins of port A PB0 - PB7 8 pins of port B PC0 - PC3 4 pins of port Clower PC4 - PC7 4 pins of Port Cupper
The important control signals are:
CS (Chip Select): It is a chip select signal. The LOW status of this signal enables communication between the
CPU and 8255.
RD (READ): When RD goes LOW the 8255 sends out data or status information to the CPU on the data bus.
In other words it allows the CPU to read data from the input port of 8255.
WR (Write): When WR goes LOW the CPU writes data or control word into 8255. The CPU writes data into
the output port of 8255 and the control word into the control word register.
RESET: RESET is an active high signal. It clears the control register and sets all ports in the input mode.
A0 and A1: The selection of input port and control word register is done using A0 and A1 in conjunction with
RD and WR. A0 and A1 are normally connected to the least significant bits of the address bus. If two 8255
units are used the addresses of ports are as follows:
For the First unit of 8255, i.e. 8255.1:

Port/Control word register Port/Control word register Address
Port A 00
Port B 01
Port C 02
Control word register 03
For the 2nd unit of 8255, i.e. 8255.2:
Port/Control word register Port/Control word register Address
Port A 08
Port B 09
Port C 0A
Control word register 0B
8253 Programmable Interval Timer
A programmable counter/interval timer is used in real time application for timing and counting function
such as BCD/binary counting, generation of accurate time delay, generation of square wave of desired
frequency, rate generation, hardware/software triggered strobe signal, one shot signal of desired width etc.
Popular programmable interval timer chips are Intel 8253 and 8254. Both are pin to pin compatible and
operate in the following six modes:
Mode 0: Interrupt on terminal count
Mode 1: Programmable one-shot
Mode 2: Rate generator
Mode 3: Square wave generator
Mode 4: Software triggered mode
Mode 5: Hardware triggered mode

The 8254 is compatible to 8086, 8088, 8085 and most other microprocessors. The 8253 is compatible to
8085 microprocessor. The 8254 is superset of the 8253.
Architecture of Intel 8253/54
Intel 8253
The 8253 is 24-pin IC and operates at 5 Vd.c.. It contains three independent 16-bit counters. The programmer
can program 8253 to operate in any one of the 6 operating modes. It operates under software control.
The description of its important pins is as follows:

RD (Read): When this pin is LOW the CPU reads data.
¯WR: (Write): When this is low, the CPU outputs data in the form of mode information or loading of
counters.
A0, A1: These pins are connected to the address bus. These are used to select one of three counters. These
are also used to address the control word registers for mode selection.
CS: Chip Select.
D0 - D7: Bidirectional data bus.
CLK0, CLK1 and CLK2 are clock for Counter 0, Counter 1 and Counter 2 respectively.
GATE0, GATE1 and GATE2 are gate terminals of Counter 0, Counter 1 and Counter 2 respectively.
OUT0, OUT1 and OUT2 are output terminals of Counter 0, Counter 1 and Counter 2 respectively.
The 8253 contains a data buffer, read/write logic and control word register as described below:
Data Bus Buffer: This buffer is within 8253. It is a 3-state, bidirectional, 8-bit buffer. It is used to interface
8253 to the system data bus through D0 - D7 lines.
Read/Write logic: The 8253 contains a read/write logic which accepts input from the system bus and then
generates control signals for the operation of 8253. The following table shows the status of pins associated
with read/write logic for various controls:
CS A1 A0 RD WR Result
0 0 0 0 1 Read Counter No. 0
0 1 1 1 0 Write Mode word
0 1 1 0 1 No-operation 3 state
0 X X 1 1 No-operation 3 state
0 X X X X Disable 3 -state
Counter Word Register: When the pins A0, A1 are 11, the control word register is selected. The control word
format is shown below:
D7 D6 D5 D4 D3 D2 D1 D0
SC1 SC0 RL1 RL0 M2 M1 M0 BCD
The bits D7 and D6 of the control word are to select one of the 3 counters. D5 and D4 are for loading/reading
the count. D3, D2 and D1 are for the selection of operating mode of the selected counter. These are six modes
of operation for each counter of 8253. The six modes of operation are: MODE 0, MODE 1, MODE 2, MODE
3, MODE 4 and MODE 5. The bit D0 is for the selection of binary or BCD counting.
8253/54 Operational Modes
8253/54 can be operated in 6 different modes. These modes are:
MODE 0 : Interrupt on Terminal Count
o Mode 0 is used for the generation of accurate time delay under software control.
o One of the counters of 8253 is initialized and loaded with suitable count for the desired time delay.
o When counting is finished the counter interrupts the CPU. On interruption the microprocessor
performs the required task which is to be performed after the desired time delay.
o For MODE 0 operation GATE is kept high. While counting is going on the counter output OUT remains
LOW. When the terminal count is reached i.e. count reaches 0, the output becomes HIGH until the
count is reloaded or new count is loaded.
o When the count is reloaded or OUT becomes LOW and the counter starts its counting operation
again.
MODE 1 : Programmable One-Shot
o In MODE 1 the counter acts as a retriggerable and programmable one-shot.

o The LOW to HIGH transition of the signal applied to GATE acts as a trigger signal.
o In this mode of operation OUT becomes initially HIGH after the mode is set. After mode set operation
the counter is loaded by a count value of N. The counter decrements count, and the output (OUT)
goes LOW for N clock cycles for every LOW to HIGH transition of the GATE input.
MODE 2 : RATE Generator
o In MODE 2 the counter acts as a simple divide by N counter.

o When this mode is set the output of the counter becomes initially HIGH.
o After mode set operation the counter is loaded by a count of value N.
o For MODE 2 operation GATE is kept HIGH.
o In this mode the output remains HIGH for (N-1) clock pulses and then goes LOW for one clock pulse.
MODE 3 : Square Wave Generation
o In MODE 3 the counter acts as a square wave generator. After mode set operation the counter is
loaded by a count of value N.
o For MODE 3 operation GATE is kept HIGH.
o For even values of N the output remains HIGH for N/2 clock pulses abd then goes LOW for next N/2
clock pulses.
MODE 4 : Software Triggered Strobe
o In MODE 4 operation the output of the counter becomes initially HIGH after the mode is set.
o GATE is kept HIGH for this mode of operation. The counter begins counting immediately after the
count is loaded into the count register.
o When the counter reaches terminal count (i.e. counter content = 0) the output goes LOW for one
clock period, then it returns to HIGH.
o The output signal may be used as strobe.
o This mode of operation is referred to as a software triggered strobe because the generation of the
strobe signal is triggered by loading the count into the count register.
MODE 5 : Hardware Triggered Strobe
o In this mode of operation GATE input acts as a trigger.

o After the mode is set, the output becomes initially HIGH.
o A count value of N is loaded into the counter.
o Following a LOW to HIGH transition of the GATE input the counter starts decrementing the count.
o The counting begins at the first negative edge of the clock after the rising edge of the GATE input.
o On terminal count the output goes LOW for one clock period, and then it goes HIGH again.
o As the LOW to HIGH transition of the GATE input causes triggering, this mode is referred to
as hardware triggered strobe.
Cache Memory
The data or contents of the main memory that are used frequently by CPU are stored in the cache memory
so that the processor can easily access that data in a shorter time. Whenever the CPU needs to access
memory, it first checks the cache memory. If the data is not found in cache memory, then the CPU moves
into the main memory.
Cache memory is placed between the CPU and the main memory. The block diagram for a cache memory
can be represented as:
The cache is the fastest component in the memory hierarchy and approaches the speed of CPU components.
Cache memory is organised as distinct set of blocks where each set contains a small fixed number of blocks.
As shown in the above sets are represented by the rows. The example contains N sets and each set contains
four blocks. Whenever an access is made to cache, the cache controller does not search the entire cache in
order to look for a match. Rather, the controller maps the address to a particular set of the cache and
therefore searches only the set for a match.
If a required block is not found in that set, the block is not present in the cache and cache controller does
not search it further. This kind of cache organisation is called set associative because the cache is divided
into distinct sets of blocks. As each set contains four blocks the cache is said to be four way set associative.
The basic operation of a cache memory is as follows:
o When the CPU needs to access memory, the cache is examined. If the word is found in the cache, it
is read from the fast memory.
o If the word addressed by the CPU is not found in the cache, the main memory is accessed to read the
word.
o A block of words one just accessed is then transferred from main memory to cache memory. The
block size may vary from one word (the one just accessed) to about 16 words adjacent to the one
just accessed.
o The performance of the cache memory is frequently measured in terms of a quantity called hit ratio.
o When the CPU refers to memory and finds the word in cache, it is said to produce a hit.
o If the word is not found in the cache, it is in main memory and it counts as a miss.
o The ratio of the number of hits divided by the total CPU references to memory (hits plus misses) is
the hit ratio.
Levels of memory:
Level 1
It is a type of memory in which data is stored and accepted that are immediately stored in CPU. Most
commonly used register is accumulator, Program counter, address register etc.
Level 2
It is the fastest memory which has faster access time where data is temporarily stored for faster access.
Level 3
It is memory on which computer works currently. It is small in size and once power is off data no longer stays
in this memory.
Level 4
It is external memory which is not as fast as main memory but data stays permanently in this memory.
Cache Mapping:
There are three different types of mapping used for the purpose of cache memory which are as follows:
o Direct mapping,
o Associative mapping
o Set-Associative mapping
Direct Mapping -
In direct mapping, the cache consists of normal high-speed random-access memory. Each location in the
cache holds the data, at a specific address in the cache. This address is given by the lower significant bits of
the main memory address. This enables the block to be selected directly from the lower significant bit of the
memory address. The remaining higher significant bits of the address are stored in the cache with the data
to complete the identification of the cached data.
As shown in the above figure, the address from processor is divided into two field a tag and an index.
The tag consists of the higher significant bits of the address and these bits are stored with the data in cache.
The index consists of the lower significant b of the address. Whenever the memory is referenced, the
following sequence of events occurs
1. The index is first used to access a word in the cache.

2. The tag stored in the accessed word is read.
3. This tag is then compared with the tag in the address.
4. If two tags are same this indicates cache hit and required data is read from the cache word.
5. If the two tags are not same, this indicates a cache miss. Then the reference is made to the main
memory to find it.
For a memory read operation, the word is then transferred into the cache. It is possible to pass the
information to the cache and the process simultaneously.
In direct mapped cache, there can also be a line consisting of more than one word as shown in the following
figure
In such a case, the main memory address consists of a tag, an index and a word within a line. All the words
within a line in the cache have the same stored tag
The index part in the address is used to access the cache and the stored tag is compared with required tag
address.
For a read operation, if the tags are same, the word within the block is selected for transfer to the processor.
If tags are not same, the block containing the required word is first transferred to the cache. In direct
mapping, the corresponding blocks with the same index in the main memory will map into the same block
in the cache, and hence only blocks with different indices can be in the cache at the same time. It is important
that all words in the cache must have different indices. The tags may be the same or different.
Set Associative Mapping -
In set associative mapping a cache is divided into a set of blocks. The number of blocks in a set is known as
associativity or set size. Each block in each set has a stored tag. This tag together with index completely
identify the block.
Thus, set associative mapping allows a limited number of blocks, with the same index and different tags.
An example of four way set associative cache having four blocks in each set is shown in the following figure
In this type of cache, the following steps are used to access the data from a cache:
1. The index of the address from the processor is used to access the set.
2. Then the comparators are used to compare all tags of the selected set with the incoming tag.
3. If a match is found, the corresponding location is accessed.
4. If no match is found, an access is made to the main memory.
The tag address bits are always chosen to be the most significant bits of the full address, the block address
bits are the next significant bits and the word/byte address bits are the least significant bits. The number of
comparators required in the set associative cache is given by the number of blocks in a set. The set can be
selected quickly and all the blocks of the set can be read out simultaneously with the tags before waiting for
the tag comparisons to be made. After a tag has been identified, the corresponding block can be selected.
Fully associative mapping
In fully associative type of cache memory, each location in cache stores both memory address as well as
data.
Whenever a data is requested, the incoming memory address a simultaneously compared with all stored
addresses using the internal logic the associative memory.
If a match is found, the corresponding is read out. Otherwise, the main memory is accessed if address is not
found in cache.
This method is known as fully associative mapping approach because cached data is related to the main
memory by storing both memory address and data in the cache. In all organisations, data can be more than
one word as shown in the following figure.
A line constitutes four words, each word being 4 bytes. In such case, the least significant part of the address
selects the particular byte, the next part selects the word, and the remaining bits form the address. These
address bits are compared to the address in the cache. The whole line can be transferred to and from the
cache in one transaction if there are sufficient data paths between the main memory and the cache. With
only one data word path, the words of the line have to be transferred in separate transactions.
The main advantage of fully associative mapped cache is that it provides greatest flexibility of holding
combinations of blocks in the cache and conflict for a given cache.
It suffers from certain disadvantages:
1. It is expensive method because of the high cost of associative memory.

2. It requires a replacement algorithm in order to select a block to be removed whenever cache miss
occurs.
3. Such an algorithm must be implemented in hardware to maintain a high speed of operation.
The fully associative mechanism is usually employed by microprocessors with small internal cache.
Virtual Memory
Virtual Memory is a storage scheme that provides user an illusion of having a very big main memory. This is
done by treating a part of secondary memory as the main memory.
In this scheme, User can load the bigger size processes than the available main memory by having the illusion
that the memory is available to load the process.
Instead of loading one big process in the main memory, the Operating System loads the different parts of
more than one process in the main memory.
By doing this, the degree of multiprogramming will be increased and therefore, the CPU utilization will also
be increased.
How Virtual Memory Works?
In modern word, virtual memory has become quite common these days. In this scheme, whenever some
pages needs to be loaded in the main memory for the execution and the memory is not available for those
many pages, then in that case, instead of stopping the pages from entering in the main memory, the OS
search for the RAM area that are least used in the recent times or that are not referenced and copy that into
the secondary memory to make the space for the new pages in the main memory.
Since all this procedure happens automatically, therefore it makes the computer feel like it is having the
unlimited RAM.
Demand Paging
Demand Paging is a popular method of virtual memory management. In demand paging, the pages of a
process which are least used, get stored in the secondary memory.
A page is copied to the main memory when its demand is made or page fault occurs. There are various page
replacement algorithms which are used to determine the pages which will be replaced. We will discuss each
one of them later in detail.
Snapshot of a virtual memory management system
Let us assume 2 processes, P1 and P2, contains 4 pages each. Each page size is 1 KB. The main memory
contains 8 frame of 1 KB each. The OS resides in the first two partitions. In the third partition, 1 st page of P1
is stored and the other frames are also shown as filled with the different pages of processes in the main
memory.
The page tables of both the pages are 1 KB size each and therefore they can be fit in one frame each. The
page tables of both the processes contain various information that is also shown in the image.
The CPU contains a register which contains the base address of page table that is 5 in the case of P1 and 7 in
the case of P2. This page table base address will be added to the page number of the Logical address when
it comes to accessing the actual corresponding entry.
Advantages of Virtual Memory
1. The degree of Multiprogramming will be increased.

2. User can run large application with less real RAM.
3. There is no need to buy more memory RAMs.
Disadvantages of Virtual Memory
1. The system becomes slower since swapping takes time.

2. It takes more time in switching between applications.
3. The user will have the lesser hard disk space for its use.
Difference Between Cache Memory and Virtual Memory
Computer Memory is just like a human brain used to store data and instructions either temporarily or
permanently. It is a physical device capable of storing information temporarily like RAM (Random Access
Memory), or permanently, like ROM (Read Only Memory). The main memory refers to physical memory, and
it is known as RAM. In computer memory, we can edit or update only the data that is in the main memory.
We can say that when we want to access the secondary storage media or any file that must be loaded into
the main memory from the secondary device.
Cache Memory
Cache Memory is a faster memory used by the central processing unit (CPU). It is a memory that helps to
reduce the access time for files or data that is recently used by the main memory. It is smaller in size, high-
speed memory, and located near a processor core that stores the copies of the information or instruction
frequently used by the main memory locations.
Furthermore, it behaves like a buffer between the CPU and the main memory to hold those data or programs
most frequently called by the CPU. For example, whenever we execute a program by the processor, it fetches
data from the main memory and fetched data to be copied to the cache memory. When the program's copy
is already available to the cache memory, it directly calls the processor to execute it; otherwise, the
program/files are fetched from memory. Hence, it reduces the access time of the data from the main
memory.
Advantages of Cache Memory
1. The access time of files or instruction in the cache memory is less than the main memory.
2. It stores frequently used data by the main memory.
3. It is the faster computer memory as compared to the main memory.
4. Store the program in a cache memory that is executed within a short time.
Disadvantages of Cache Memory
1. It has limited space to store the data.

2. It is very costly as it is a fast memory to access the data.
Virtual Memory
Virtual Memory is used in the computer memory to increase the storage capacity of the main memory. It is
a logical storage unit of a computer that creates an illusion to execute a large program that may not be
completely placed in the main memory. Furthermore, it allows the user to load or store the data program or
files larger than the size of the main memory.
Advantages of Virtual Memory
1. Virtual Memory allows the users to run more than one application at once.
2. It enhances the degree of multiprogramming in the virtual memory.
3. Virtual Memory is a logical unit of computer memory that increases the main memory capacity by
storing or executing a large size program than the main memory.
4. It does not require any fixed limit on the degree of multiprogramming.
5. It increases the CPU utilization in the virtual memory.
6. It is required whenever the system does not have much space to store any big programs or files.
Disadvantages of Virtual Memory
1. Virtual Memory can slow the process of application in the system.

2. It may take more time to switch between the applications.
3. It reduces the stability of the system.
4. It allows the user to lesser hard disk space for its use in the system.
Difference Between Cache Memory and Virtual Memory
S. Parameter Cache Memory Virtual Memory

N. Difference
1. Definition Cache Memory is the high speed of Virtual Memory is a logical unit of computer
computer memory that reduces memory that increases the capacity of main
the access time of files or memory by storing or executing programs of
documents from the main larger size than the main memory in the
memory. computer system.
2. Memory Unit Cache Memory is defined as a Virtual Memory is not defined as a memory
memory unit in a computer unit.
system.
3. Size Its size is very small as compared Its size is very large as compared to the Cache
to Virtual Memory. Memory.
4. Speed It is a high-speed memory as It is not a high-speed memory as compared to

compared to Virtual Memory. the Cache Memory.
5. Operation Generally, it stores frequently The virtual memory keeps those data or
used data in the cache memory to programs that may not completely be placed in
reduce the access time of files. the main memory.
6. Management Cache Memory is controlled by the Whereas the virtual memory is control by the
hardware of a system. Operating System (OS).
7. Mapping It does not require a mapping It requires a mapping structure to map the
structure to access the files in virtual address with a physical address.
Cache Memory.

Computer System Organization

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Unit 1 :STRUCTURES OF COMPUTER AND MICRO OPERATION

Functional Units of Digital System

Arithmetic & logical unit

A Von Neumann-based computer:

o Central Processing Unit

Central Processing Unit

Arithmetic and Logic Unit (ALU)

Control Bus Control Bus carries signals/commands from the CPU.

Two major types of memories are used in computer systems:

1. RAM (Random Access Memory)

Bus and Memory Transfers

A bus system can also be constructed using three-state

The graphical symbol of a three-state buffer gate can be represented as:

Basic Operational Concepts

Data Representation in Computer Organization

The data can be represented in the following ways:

The number can be represented in the following way:

The text can be represented in the following ways:

Representing Bits and Bytes

The bits and bytes can be represented in the following ways:

Bits and Bytes

Types of Operands in Computer Organization

o Whether the number is signed or unsigned,

1. American Standard Code for Information Interchange (ASCII)

o 32 control codes (mainly to do with printing)

For example, the word "Computer" would be represented as:

1000011 1101111 1101101 1110000 1110101 1110100 1100101 1110010

There are two advantages to the bit-oriented view:

Error Detection and Correction Code

Error detection code

Features of Error detection codes

These are the following features of error detection codes:

Error correction code

The hamming code technique is used for error correction.

o The memory address register is designated by MAR.

The basic Arithmetic Micro-operations are classified in the following categories:

Some additional Arithmetic Micro-operations are classified as:

1. Add with carry

Symbolic Representation Description

R3 ← R1 + R2 The contents of R1 plus R2 are transferred to R3.

R3 ← R1 - R2 The contents of R1 minus R2 are transferred to R3.

R2 ← R2' Complement the contents of R2 (1's complement)

R2 ← R2' + 1 2's complement the contents of R2 (negate)

R3 ← R1 + R2' + 1 R1 plus the 2's complement of R2 (subtraction)

R1 ← R1 + 1 Increment the contents of R1 by one

R1 ← R1 - 1 Decrement the contents of R1 by one

P: R1←R1[Math Processing Error]⊕R2

For example, in the statement

P+Q: R1←R2+R3,R 4←R5V R6

There are three types of shift micro-operations are as follows −

Symbolic Designation Description

R ←R1 shl R Shift-left register R

R ←R1 shr R Shift-right register R

R ←R1 cil R Circular shift-left register R

R ←R1 cir R Circular shift-right register R

R ←R1 ashl R Arithmetic shift-left R

R ←R1 ashr R Arithmetic shift-right R

Arithmetic Shift Right

Bit Rn-1 in the leftmost position holds the sign bit.

Rn-2 is the most significant bit of the number and

Rn-1 remains the equal,

Rn-2 receives the bit from

S3 S2 S1 S0 Cin Operation Function

0 0 0 1 1 F=A+B+1 Add with carry