University of Basrah

College of Engineering
Department of Electrical Engineering

Digital Electronics
CS308

Third Year Class

Lecturer
Assist. Prof. Dr. Abdul-Basset A. Al-Hussein

1
Simple Programmable Logic Devices (SPLDs)

➢ Two major PLDs types are available: PAL and GAL, PAL are stands for programmable
array logic and GAL stands for generic array logic. Generally a PAL is one-time
programmable (OTP), and a GAL is a type of PAL that is reprogrammable.
➢ The basic structure of both PALs and GALs is a programmable AND array and a fixed
OR array, which is a basic sum-of-products (SOP) architecture

The PAL: A simple PAL structure is shown in Fig.1-1, for two inputs variables and one
output. Each programmable link which is a fuse and called a cell.
For example, the sum-of-products expression below can be represented in Fig.1-2.

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Fig.1.1 Basic AND/OR structure of a PAL Fig.1.2 PAL implementation of a SOP expression

Assist. Prof. Dr. Abdul-Basset A. Al-Hussein

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 The GAL is essentially a PAL that can be reprogrammed. The basic difference is that a GAL
uses a reprogrammable process technology, such as EEPROM instead of fuses, as shown in
Fig.1-3.

Fig.1.3 simplified GAL array.

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Simplified Notation for PAL/GAL Diagrams

Most PAL and GAL diagrams that you may see on a data sheet use simplified notation as shown in Fig.1-4.

Note that the input variables to a PAL or GAL

are usually buffered to prevent loading by a
large number of AND gate inputs to which
they are connected.

Fig.1.4 simplified notation of PAL/GAL.

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Example 1-1: Show how a PAL is programmed for the following 3-variable logic function:

The solution is shown in Fig.1-5.

Fig.1.5 Example1-1 solution.

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PAL/GAL General Block Diagram

A block diagram of a PAL or GAL is shown in Fig.1-6. The basic difference is that a GAL has a reprogrammable
array and the PAL is OTP.

Fig.1.6 General block diagram of a

PAL or GAL.

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Macrocells
A macrocell generally consists of one OR gate and some associated output logic. A macrocell can be configured for
combinational logic, registered logic, or a combination of both. Figure 1-7 shows the basic types of PAL/GAL
macrocells for combinational logic.

Fig.1-7 Combinational logic basic

types of macrocells.

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Complex Programmable Logic Devices (CPLDs)

A CPLD consists of multiple SPLD arrays with programmable interconnections. Figure 1-8 shows a generic CPLD.

Note that the way CPLDs are internally

organized varies with the manufacturer.

Fig.1-8 Basic block diagram of a

generic CPLD.

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➢ We will refer to each SPLD array in a CPLD as a LAB (logic array block).
➢ The programmable interconnections are generally called the PIA (programmable interconnect array).
➢ Several manufacturers, for example, Altera, Xilink, Lattice, and Atmel produce CPLDs.
➢ Figure 1-9 shows a general block diagram of a typical CPLD. Four LABs are shown, but there can be up to
sixteen, depending on the particular device in a series.
➢ Each of the four LABs consists of 16 macrocells, and multiple LABs are linked together via the PIA which is
programmable global bus structure to which the general-purpose inputs, the I/Os, and the macrocells are
connected.

The Macrocell
➢ Figure 1-10 shows the simplified diagram of a typical macrocell.
➢ As shown from Fig.1-10, five AND gates feed products terms from the PIA into the product term selection
matrix. The product term from the bottom AND gate can be fed back inverted into the programmable array
as a shared expander for use by other macrocells. The parallel expander inputs allow borrowing of unused
products terms from other macrocells to expand an SOP expression. The product term selection matrix is
an array of programmable connections that is used to connect selected outputs from the AND array and from
the expander inputs to the OR gate.

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Fig.1-9 Block diagram of a typical CPLD.

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 Fig.1-10 Simplified diagram of a macrocell in a typical CPLD.

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Shared Expanders
A complemented product term that can be used to increase the number of product terms in a SOP expression is
available from each macrocell in a LAB. Figure 1-11 shows how a shared expander term from another macrocell
can be used to create additional product terms.

Fig.1-11 Example of how a shared expander can be used in a macrocell to increase the number of product term.

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 Fig.1-12 Simplified indication of using a shared
expander term from another macrocell to increase
an SOP expression. The red Xs and lines represent
the connections produced in the hardware by the
software compiler running programmed design.

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Parallel Expanders
➢ Another way to increase the number of product terms for a macrocell is by using parallel expanders in which
additional product terms are ORed with the terms generated by a macrocell instead of being combined in the
AND array, as in the shared expander.
➢ A given macrocell can borrow unused terms from neighboring macrocells. See example in Fig.1-13.

Fig.1-13 Basic concept of the parallel expander.

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 Fig.1-14 shows a macrocell 2 uses three product
terms from macrocell 1 to produce a eight-term
SOP expression.

Fig.1-14 Simplified indication of using a parallel expander

terms from another macrocell to increase an SOP
expression. The red Xs and lines represent the connections
produced in the hardware by the software compiler running
programmed design.
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LUT CPLD Architecture

Figure 1-15 shows the architecture that contains logic array blocks (LABs), each with multiple logic elements (LEs).
An LE is the basic logic design unit and is analogous to the macrocell.
Look-up tables (LUTs) are used instead of AND/OR arrays. An LUT is basically a type of memory that can be
programmed to produce SOP functions.

Fig.1-15 Simplified block

diagram of an LUT CPLD.

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 Fig.1-16 Two types of logic
function generation in CPLDs.

Fig.1-17 (a) LUT CPLDs have

row/column interconnections (b)
Classic CPLDs have channel-type
interconnections.

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Macrocell Modes
• Figure 1-18 shows the multiplexer common symbol.
• Figure 1-19 shows a complete macrocell including the flip-flop (register).
• The XOR gate provides for complementing the SOP function from OR gate to produce a function in POS form.
• MUX 1 provides for selection of either the XOR output or an input from the I/O.
• MUX 2 can be programmed to select either the global clock or a clock signal based on a product term.
• MUX 3 can be programmed to select either a HIGH (Vcc) or a product term enable for the flip-flop.
• MUX 4 can select the global clear or a product-term clear.
• MUX 5 is used to bypass the flip-flop and connect the combinational logic output to the I/O or to connect the
registered output to the I/O.
• The flip-flop can be programmed as a D, T, or J-K flip-flop.

Figure 1-18 Multiplexer symbol.

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 Figure 1-19 A CPLD macrocell.
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The Combinational Mode

Figure 1-20 shows a macrocell configured for generation of an SOP logic function. It is clear that only one
MUX is used and the register (flip-flop) is bypassed. The logic elements in the data path are shown in red.

Figure 1-20 Generation of an SOP logic function, combinational mode data path (red color).
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The registered Mode
Figure 1-21 shows a macrocell when is programmed for the registered mode with the SOP combinational logic
Output providing the data input to the register and clocked by the global clock, the elements in the data path are
Shown in red color.

Figure 1-21 A macrocell

configured for generation
of a registered logic
function. Red indicates
data path.

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Field-Programmable Gate Arrays (FPGAs)

• Basically, the FPGA differs in architecture, dose not use PAL/GAL types arrays, and has much greater densities
than CPLDs.
• The three basic elements in an FPGA are the configurable logic block (CLB), the interconnections, and the I/O
blocks as shown in Fig. 1-22.
• FPGAs are reprogrammable and use SRAM or antifuse process technology for the programmable links.
• Densities can range from hundreds of logic modules to hundreds of thousands of logic modules in packages with
up to over 1000 pins.
• DC supply voltages are typically 1.8 V to 5 V, depending on the specific device.

Configurable Logic Blocks

• Figure 1-23 shows the CLB within the global row/column programmable interconnects that are used to connect
logic blocks.
• Each CLB also called as logic array block LAB is made up of multiple smaller logic modules and local
programmable interconnections.

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Figure 1-22 Basic structure
of an FPGA.

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Figure 1-23 Basic structure of CLB.

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Logic Modules

• A logic module in an FPGA logic block can be configured for combinational logic, registered logic, or a
combination of both.
• A flip-flop is part of the associated logic and is used for registered logic.
• Figure 1-24 shows a block diagram of a typical LUT-based logic module.
• An LUT is a type of memory that is programmable and used to generate SOP combinational logic functions.
• The LUT does the same job as the PAL does.

Figure 1-24 Basic block diagram of a logic module in an FPGA.

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The organization of an LUT consists of number of memory cells equal to , where n is the number of input
Variables

Example 1-2: Show a basic 3-variable LUT programmed to produce the following SOP functions:

Figure 1-25 Example 1-2 solution.

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Operating Modes of a Logic Module

A logic module (LM) can be programmed for the following modes of operation:
▪ Normal mode
▪ Extended LUT mode
▪ Arithmetic mode
▪ Shared arithmetic mode
The normal mode is used primarily for generating combinational logic functions. Figure 1-26 shows some
examples of four LUT configurations in a logic module in the normal mode.
Figure 1-27 shows an expansion to a 7-variable function of the extended LUT mode.

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Fig. 1-26 Examples of possible LUT configurations in a logic module (LM) in the normal mode.
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 Fig. 1-27 Expansion of a LM to produce a 7-variable SOP function in the extended LUT mode.
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Example 1-3: A logic module is configured in the extended LUT mode, as shown in Fig. 1-28. for the specific LUT
outputs shown determine the final SOP output.
Solution: The SOP output expression is as follows:

Fig. 1-38 Example 1-3 solution.

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FPGA Cores
❑ FPGAs consists of hard-core and soft-core.
❑ A hard-core is a portion of logic in an FPGA that is put in by the manufacturer to provide a specific function
that cannot be reprogrammed. i.e., if a customer needs a small microprocessor as part of system design, it can
be programmed into the FPGA by the customer or it can be provided as hard-core by the manufacturer.
❑ A soft-core is a portion of logic embedded in an FPGA that has some programmable features.
❑ Hard cores are generally available for functions that are commonly used in digital systems, such as a
microprocessor, standard input/output interfaces, and digital signal processors. More than one hard-core
function can be programmed in an FBGA, see Fig. 1-39.

Fig. 1-39 Basic idea of

a hard-core function
embedded in an FPGA.
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Programmable Logic Software

Figure 1-40 shows the design flow diagram for programming a SPLD, CPLD, or FPGA.

Fig. 1-40 General design

flow diagram for
programming a SPLD,
CPLD, or FPGA.
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VHDL Language:
For simplicity, Fig.1-41 shows the predefined VHDL descriptions of a 2-input AND gate and a 2-input OR gate.

Fig. 1-41 Predefined programs for a 2-input AND gate and a 2-input OR gate.
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VHDL code Examples:

Example 1-3:

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 Electrical Engineering Department/ University of Basrah 37

(b) After the minimization, the simplified expression is given as:

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Example 1-4: Write a VHDL code for a 4-input multiplexer.

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Example 1-5: Write a VHDL code for a 4-bit magnitude comparator.

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Example 1-6: Write a VHDL code for a decimal to BCD encoder.

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