Serial Communication (Cuuduongthancong - Com)

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Chuyên đề II
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Vi điều khiển và ứng dụng
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Serial Communication
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CuuDuongThanCong.com https://fb.com/tailieudientucntt
Truyền thông nối tiếp
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 2 the Universal Asynchronous Receiver and
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Transmitters (UARTs)
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 2 the SPI synchronous serial interfaces
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 2 the I 2 C synchronous serial interfaces
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Synchronous serial
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Asynchronous Serial
Interfaces
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Some comparisons
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More
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Synchronous Communication
Using the SPI Modules
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SPI applications
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 Interfacing with memory devices
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 Serial EEPROMs - e.g., 25xx256
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 Interfacing with codecs
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 Control Ports or PCM Data
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 Interfacing with communication chips
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Bluetooth
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 Boot Loader
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Giải thích các bit điều khiển
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Bít điều khiển
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SPI overview
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 Serial transmission and reception of 8-bit or 16-bit
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data
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 Full-duplex, synchronous communication
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 Compatible with Motorola’s SPI and SIOP
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interfaces
 3-wire interface
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 Supports 4 different clock formats and serial
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clock speeds up to 10 Mbps

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 Buffered Transmission and Reception
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SPI - Master / Slave
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 SPI module can be configured as Master or Slave
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 In any SPI data transfer, there is a single Master
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and a single Slave
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 Selected by MSTEN bit, SPIxCON<5>
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 Master generates serial clock pulse (on SCK pin)
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 SCK frequency determined by Primary
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 Prescaler bits (PPRE) and Secondary Prescaler
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(SPRE) bits in SPIxCON register

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Fsck = Fcy / (PPRE * SPRE)
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SPI - Serial Clock Formats
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 4 clock formats - set by CKP and CKE bits
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in the SPIxCON register
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 SCK is low when module is idle, SDO changes on
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clock going high (CKP=0, CKE=0)
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 SCK is low when module is idle, SDO changes on
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clock going low (CKP=0, CKE=1)
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 SCK is high when module is idle, SDO changes on
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clock going low (CKP=1, CKE=0)

 SCK is high when module is idle, SDO changes on
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clock going high (CKP=1, CKE=1)
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Ví dụ
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SPI - Transmission
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 Module is enabled by setting SPIEN bit in the SPIxSTAT register
 Transmission begins when data is written into the Master’s Transmit
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Buffer
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 SCK pulses are generated by the Master only when SPIxSR
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contains data
 Transmission can be disabled by setting the DISSDO bit in the
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SPIxCON register
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 SPIxBUF is buffered ng
 You can write SPIxBUF while data is being shifted out through
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SPIxSR
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 SPITBF bit in the SPIxSTAT register indicates that the Transmit

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Buffer is full
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 Wait until SPITBF = 0 to write data

 Transmission of the new data starts as soon as SPIxSR is idle
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SPI - Reception
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 Reception occurs concurrently with the transmission
 When all bits of data have been shifted in through SPIxSR,
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SPIxSR contents are transferred to Receive Buffer
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 SPI interrupt (indicated by SPIIF bit and enabled by SPIIE bit)
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is generated so that buffer can be read
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 SPIxBUF subject to Receive Overflow
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 SPIRBF bit in the SPIxSTAT register = 1 indicates that the
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Receive Buffer is full
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 SPIxBUF must be read before new data is completely shifted in
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When receive overflow occurs...

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 New data not transferred to Receive Buffer

 SPIROV bit in SPIxSTAT is set
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Configuration
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SPI - Data Sizes
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 8-bit and 16-bit data communication
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 SPI operation is identical for both data sizes,
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except number of bits transmitted
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 For 8-bit data, Master generates 8 SCK pulses
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 For 16-bit data, Master generates 16 SCK pulses
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 16-bit operation is selected by setting the
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MODE16 bit in the SPIxCON register
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SPI - Framed SPI
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 SPI supports Frame Synchronization
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 Enabled by setting FRMEN bit in the SPIxCON
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register
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 SCK pulses are continuous in this mode
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SPI - Framed SPI
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 Frame Master generates Frame Sync pulses
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 Frame Master or Slave mode is selected by clearing
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or setting the SPIFSD bit in the SPIxCON register
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 Shifting of data starts only after a Frame Sync
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pulse is generated on the SS pin
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 4 possible Framed SPI modes ng
 􀁏 SPI Master, Frame Master
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 􀁏 SPI Master, Frame Slave

 􀁏 SPI Slave, Frame Master
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 􀁏 SPI Slave, Frame Slave
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SPI - chức năng phụ
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 Slave Select (SS) pin functionality
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 In this mode, the Slave functions only as
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 long as the SS pin is driven low
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 Enabled by setting SSEN bit in the SPIxCON
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register
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 Slave Wake-up from SLEEP ng
 Since SCK pulses are provided by the Master, SPI
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Slave can function in SLEEP

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 Slave Reception wakes up the device from

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SLEEP
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Ví dụ ghép nối với Serial EEROM
25L256
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// 1. init the SPI peripheral
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#define SPI_CONF 0 x 8120 // SPI on, 8-bit master, CKE=1,CKP=0
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TCSEE = 0; // make SSEE pin output
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CSEE = 1; // de-select the EEPROM
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SPI2CON = SPI_CONF; // select mode and enable
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// send one byte of data and receive one back at the same time
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int writeSPI2( int i)
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{
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SPI2BUF = i; // write to buffer for TX

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while( !SPI2STATbits.SPIRBF); // wait for transfer complete

return SPI2BUF; // read the received value
}//writeSPI2
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Đọc Serial ROM
// 25LC256 Serial EEPROM commands
#define SEE_WRSR 1 // write status register
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#define SEE_WRITE 2 // write command
#define SEE_READ 3 // read command
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#define SEE_WDI 4 // write disable
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#define SEE_STAT 5 // read status register
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#define SEE_WEN 6 // write enable
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Ví dụ chương trình đầy đủ
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Writing/read Data to the
EEPROM
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// send a Write command
CSEE = 0; // select the Serial EEPROM
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writeSPI2( SEE_WRITE); // send command, ignore data
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writeSPI2( ADDR_MSB); // send MSB of memory address
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writeSPI2( ADDR_LSB); // send LSB of memory address
writeSPI2( data); // send the actual data
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// send more data here to perform a page write
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CSEE = 1; // start actual EEPROM write cycle
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// send a Write command
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CSEE = 0; // select the Serial EEPROM
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writeSPI2( SEE_READ); // send command, ignore data

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writeSPI2( ADDR_MSB); // send MSB of memory address

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writeSPI2( ADDR_LSB); // send LSB of memory address

data=writeSPI2( 0); // send dummy, read data
// read more data here sequentially incrementing the address
CSEE = 1; // terminate the read sequence
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Read 32bit values
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Write 32bit values
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DAC ví dụ MCP4921
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Ví dụ phần mềm DAC
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Serial Communications using
the dsPIC30F UART Module
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 Serial transmission and reception
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 􀁏 8-bit or 9-bit data
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 􀁏 Full-duplex, asynchronous communication
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 􀁏 Support for communication protocols such
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 as RS-232, RS-422, RS-485 and LIN
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 􀁏 4-deep Transmit and Receive buffers
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 􀁏 Transmit and Receive interrupts

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 􀁏 Error detection
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 􀁏 Support for receiver addressing
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Cấu
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truyền
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thống
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Phần cứng
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Các thanh ghi
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Giải thích thanh ghi
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Thanh ghi (tiếp)
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UART - Baud Rate Generator
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 Dedicated 16-bit Baud Rate Generator
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 􀁏 Baud Rate controlled by UxBRG register
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 (x = 1 or 2)
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 􀁏 Baud Rate = Fcy / ( 16 * (UxBRG + 1) )
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 where Fcy = Instruction Cycle Frequency
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 􀁏 Both transmitting and receiving devices
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 must use same Baud Rate

 􀁏 Bits are transmitted and/or received at
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 the rate defined by the Baud Rate
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Ví dụ
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 If FCY=8MHz, and the desired baud rate is 9600,
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 UxBRG=(8•106/(16•9600))-1=51.083.
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 UxBRG=51.
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 The new baud rate for UxBRG=51 is 9615.384,
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i.e. the deviation is 0.16%
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Ví dụ (tiếp)
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UART - Transmission
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 The first bit transmitted is a START bit
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 􀁏 Low level on UxTX pin for 1 bit time
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 􀁏 START bit followed by data and parity
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 bits
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 􀁏 Data format (8 or 9 bits) and parity type
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 (even, odd or no parity) are configured
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 by PDSEL control bits in UxMODE

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 register
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 􀁏 No parity for 9-bit data
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UART - Transmission
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 Last bit transmitted is a STOP bit
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 􀁏 High level on UxTX pin for 1 or 2 bit
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 times
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 􀁏 Number of STOP bits are configured by
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 STSEL control bit in UxMODE register
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 􀁏 During a transmission, TRMT status
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bit in the UxSTA register is clear

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UART - Transmit Buffers
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 4-deep Transmit FIFO Buffer
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 􀁏 The characters in the buffer are shifted
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 out of the buffer through UxTSR
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 􀁏 All 8 (or 9) data bits, are buffered
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 􀁏 Only the first character in the buffer is
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 memory-mapped and thus useraccessible
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 􀁏 The UTXBF status bit in the UxSTA

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 register indicates if the buffer is full

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UART - Transmit Interrupts
 Transmit Interrupt indicated by UxTXIF bit and
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enabled by UxTXIE bit
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 􀁏 When UTXISEL bit in the UxSTA register = 1
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 􀁏 Interrupt occurs when buffer becomes empty
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 􀁏 Used for transmitting a block of 4 characters
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 􀁏 When UTXISEL bit = 0 ng
 􀁏 Interrupt occurs whenever a character is
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 transferred to UxTSR
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 􀁏 Used for transmitting a single character

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In this mode, an interrupt is generated as soon as

the UTXEN bit is set
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UART - Reception
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 4-deep Receive FIFO Buffer
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 􀁏 All 8 (or 9) data bits, as well as Error
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 flags, are buffered
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 􀁏 Only the first character in the buffer is
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 memory-mapped (UxRXREG)
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 􀁏 The error flags in the UxSTA register
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 reflect the error states of the first

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 character in the buffer

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 􀁏 URXDA status bit in the UxSTA register

 indicates if the buffer contains new data
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UART - Receive Interrupts
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 Receive Interrupt indicated by UxRXIF bit and
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enabled by UxRXIE bit
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 When URXISEL bits in the UxSTA register = 11
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 􀁏 Interrupt occurs when buffer becomes full
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 􀁏 Used for receiving a block of 4 characters
 􀁏 When URXISEL bits = 10
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 􀁏 Interrupt when buffer has 3 characters
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 􀁏 Used for receiving a block of 3 characters

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 􀁏 When URXISEL bits = 01 or 00

 􀁏 Interrupt whenever a character is received
 􀁏 Used for receiving a single character
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UART - Error Detection
 Parity Error
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 􀁏 When received parity does not match the parity
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calculated by module from received data
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 􀁏 Indicated by PERR bit in the UxSTA register set
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 Framing Error
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 􀁏 When a STOP bit is expected on UxRX pin but
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a low logic level is detected
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 􀁏 Indicated by FERR bit in the UxSTA register set
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 Receive Overrun Error

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 􀁏 When the Receive Buffer is full and a 5th

character is received
 􀁏 Indicated by OERR bit in the UxSTA register set
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UART - Address Detection
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 When the UART is operating in 9-bit mode
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(PDSEL = 11), and the ADDEN bit in the UxSTA
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register is set
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 􀁏 The module will wait for an Address word, i.e., a
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9-bit word with the 9th bit set
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 At this stage, the URXISEL bits in the UxSTA
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register must be set to 00 or 01
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 On receiving the Address word, the user inspects
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the lower byte to verify an address match

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 If an address match occurred, the user should clear

the ADDEN bit, after which the module will wait for
Data words (9-bit words with MSB clear)
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UART - Features for LIN Support
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 Transmission of Break Characters
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 􀁏 A Break character can be transmitted by
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setting the UTXBRK bit in the UxSTA register for
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at least 13 bit times
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 Autobaud Detection
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 The UxRX pin is internally routed to an Input
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Capture pin (U1RX to IC1, U2RX to IC2)
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 Used for capturing both edges of START bit

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for determining baud rate

 Enabled by setting the ABAUD bit in the
UxMODE register
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UART - Additional Features
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 Alternate I/O
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 Some devices have an alternate pair of TX/RX pins
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 Enabled by setting ALTIO bit in UxMODE register
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 Loopback Mode
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 UxTX pin internally connected to UxRX pin
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 Enabled by setting LPBACK bit in UxMODE
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Register
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 Wake-up from SLEEP

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 Device can be woken up from SLEEP by START bit

 Enabled by setting WAKE bit in UxMODE register
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Ví dụ
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om

clock speeds up to 10 Mbps

 Buffered Transmission and Reception

(SPRE) bits in SPIxCON register

Fsck = Fcy / (PPRE * SPRE)

clock going low (CKP=1, CKE=0)

clock going high (CKP=1, CKE=1)

 SPITBF bit in the SPIxSTAT register indicates that the Transmit

 Wait until SPITBF = 0 to write data

When receive overflow occurs...

 New data not transferred to Receive Buffer

 􀁏 SPI Master, Frame Slave

 􀁏 SPI Slave, Frame Slave

Slave can function in SLEEP

 Slave Reception wakes up the device from

SPI2BUF = i; // write to buffer for TX

while( !SPI2STATbits.SPIRBF); // wait for transfer complete

writeSPI2( SEE_READ); // send command, ignore data

writeSPI2( ADDR_MSB); // send MSB of memory address

writeSPI2( ADDR_LSB); // send LSB of memory address

 􀁏 Transmit and Receive interrupts

 􀁏 Support for receiver addressing

 must use same Baud Rate

 the rate defined by the Baud Rate

 by PDSEL control bits in UxMODE

 􀁏 No parity for 9-bit data

bit in the UxSTA register is clear

 􀁏 The UTXBF status bit in the UxSTA

 register indicates if the buffer is full

 􀁏 Used for transmitting a single character

In this mode, an interrupt is generated as soon as

 reflect the error states of the first

 character in the buffer

 􀁏 URXDA status bit in the UxSTA register

 􀁏 Used for receiving a block of 3 characters

 􀁏 When URXISEL bits = 01 or 00

 Receive Overrun Error

 􀁏 When the Receive Buffer is full and a 5th

the lower byte to verify an address match

 If an address match occurred, the user should clear

 Used for capturing both edges of START bit

for determining baud rate

 Wake-up from SLEEP

 Device can be woken up from SLEEP by START bit

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