Project Proposal on

16-bit RISC Multi Cycle CPU

DIGITAL SYSTEM DESIGN WITH FPGA

Submitted by
BASATI SIVAKRISHNA (22976)

KATTA JOHN AKHIL (23021)

10 MARCH,2024
Course Instructor: Prof. Debayan Das

Indian Institute of Science, Bangalore

 1. INTRODUCTION AND MOTIVATION:

In computer design, people are always looking for ways to make computers faster, simpler,
and more efficient. One big step in this direction is using what's called Reduced Instruction Set
Computing, or RISC. RISC focuses on doing tasks with fewer and simpler instructions.

Here's why we want to create a 16-bit RISC multi-cycle CPU:

Efficiency: By using RISC, we can make the processor run instructions faster and use less
energy.

Space and Power: In small devices like IoT gadgets, saving space and power is crucial. A 16-
bit CPU takes up less room and uses less power, which is great for these devices.

Easy to Use: With RISC, we can make instructions simple and easy to understand. This helps
programmers write software and build tools for the processor more easily.

Learning Tool: Building a 16-bit RISC CPU is a fantastic way to learn about how computers
work. It lets students and hobbyists get hands-on experience with designing and building a
processor.

Small Devices: Many gadgets and devices today need small, energy-efficient processors. A
16-bit RISC CPU fits well for these kinds of gadgets.

Customization: Making our own processor lets us tailor it to specific tasks. This means we
can make it work well for certain jobs, like controlling machines or handling data.

Fig1. Expected architecture for the designing Processor

 2. BACKGROUND STUDY:

Designing a 16-bit multi-cycle RISC (Reduced Instruction Set Computing)

processor involves several steps, including background research to understand the requirements,
architecture choices, instruction set design, pipeline stages, control unit design, and more. Here's a
comprehensive background study for designing a 16-bit multi-cycle RISC processor:

1. Understanding RISC Architecture:

● Research the principles of RISC architecture, which emphasizes simplicity and efficiency
by using a small set of simple instructions.
● Study key characteristics such as load-store architecture, fixed-length instruction
format, and single-cycle execution.
2. Processor Components:
● Study the basic components of a processor, including the arithmetic logic unit (ALU),
registers, control unit, memory, and data paths.
● Understand the role of each component and their interactions within the processor.
3. Instruction Set Architecture (ISA):
● Research existing 16-bit RISC ISAs like ARM Thumb, MIPS-16, or PIC.
● Analyze instruction types (e.g., arithmetic, logical, control transfer), addressing modes,
and encoding schemes.
● Determine the subset of instructions to be supported and their corresponding opcodes.
4. Pipeline Design:
● Study different pipeline stages such as instruction fetch, decode, execute, memory
access, and write back.
● Explore pipeline hazards (structural, data, and control hazards) and techniques to
mitigate them (e.g., forwarding, branch prediction).
● Decide the number of pipeline stages suitable for the target application and performance
requirements.
5. Multi-cycle Execution:
● Understand the concept of multi-cycle instruction execution where instructions take
multiple clock cycles to complete.
● Design the control unit to orchestrate the multi-cycle execution of instructions.

DIFFERENCE BETWEEN SINGLE AND MULTI-CYCLE PROCESSOR:

2. INNOVATIVE FEATURES AND DESIGN GOALS:

• Branch Instructions will be included in the designing ISA to enable looping and Program
counter control.
• The designing Verilog modules will be adaptable to add new assembly instructions of RISC
ISA.
• Basic Arithmetic and Logical operations like Addition, subtraction, Multiplication, Shifting,
AND, OR, EX-OR, NAND etc. will be available in CPU Core.
• The designed CPU will be running in multi cycle mode, so it would be easier for the user to
extend it for the Pipelined version to increase the throughput.
• To demonstrate the working of this Module, one should convert his Assembly code into Binary
and hard code into the instruction memory accordingly.
• The end goal would be to fetch the code from the instruction memory, decode and execute. And
show the results on Seven Segment Display of the FPGA board (Xilinx Artix-7 XC7A35T-
ICPG236C).

EXPECTED FSM FOR THE DESIGN:

STATE_RESET

S
0
INITILIAZE

S
1
FETCH

S
2
DECODE HALT

HALT_INST
S S1
3 4

S S S
4 5 7

PC_UPDATE S
6
4.TIMELINE:

TASK DESCRIPTION NO. OF DAYS DATE

Wish specifications Defining the basic 2 09/03/2024 - 11/03/2024

requirements and supporting
functionalities.

ISA Architecture Defining assembly 3 12/03/2024 - 14/03/2024

Instructions required for the
above requirements.

Individual Module Design Designing Individual modules 10 15/03/2024 - 25/03/2024

of the architecture including
data path and controller
design (Registers, ALU,
Instruction Decoder, PC,
Memory interface etc.)

Integration Connecting all the individual 5 26/03/2024 - 30/03/2024

modules designed and
synchronizing the data flow
over the modules.

Testing and Simulation Implementation of test bench 4 31/03/2024 - 3/03/2024

and correcting the edge cases.

Performance Optimization Revisiting the design to 3 04/04/2024 - 06/04/2024

optimize power consumption,
area, and maximum
frequency of operation.

Demonstration and 2 07/04/2024 - 10/04/2024

Documentation
-

5. REFERENCES:
1. RISC architecture

2. Design of a 16-Bit microprocessor using multi cycle data path

3. Design and Implementation of a RISC V Processor on FPGA

4. Design and application of RISC processor