Recent singlecycle problems

Question 2 b c (Retake Spring 2016): Modifying MIPS Singlecycle Datapath and Control

In this question, you are asked to modify the MIPS single-cycle datapath and control, in order to
add instructions to the architecture of the MIPS processor. The following 3 parts are independent
of each other, you should answer each as if it is a separate question.

b) In this part, you will add to MIPS the new instruction stack_add. This I-type instruction
allows MIPS to begin to behave like a stack machine, in which arithmetic instructions are
performed on the top 2 values in stack. The behavior should be that TOS and TOS-1 are
popped off, their sum computed, and the result pushed back onto top of stack, all in one clock
cycle. Hint: remember how MIPS implements the stack.

Assembly code: stack_add

Machine code: | 011000 | 11101 | 11101 | 0000000000000000

The datapath given below must be modified, in order to add the stack_add instruction. Make
any necessary changes, but be sure to only make changes that are necessary, adding the
minimum amount of new hardware. It will be necessary to modify the Data Memory.
Expanding existing MUXes is preferable to adding new MUXes. Be sure to indicate any
changes to control signals that arise from your datapath modifications. [Hint: first write the
RTL expressions, then use those to guide your datapath changes.]

stack_add: IM[PC]
DM[RF[29]+ 4]  DM[RF[29]] + DM[RF[29] + 4 ]
RF[29] RF[29] + 4
PC  PC + 4
The Data Memory must have two read ports, A0/RD0 and A1/RD1. The A0 read address is
ALUResult, and the A1 read address is supplied by a new 32-bit adder, that adds ALUResult +
4. The RD0 and RD1 outputs go to an new 32-bit adder. The output of that adder will be
DM[RF[29]] + DM[RF[29] + 4 ]. This bus is brought to one input of a new 2-to-1 MUX, whose
other data input is WriteData. The MUX output goes to WD on the Data Memory. A new control
signal Stack+ goes to the MUX as select, and also to a new input of the Data Memory WA, which
controls which address (A0 or A1) will be the write address for WD.

c) (9 points) In this part you will add the instructions sll, sllv, srl, srlv, sra and srav to the MIPS
instruction set. These R-type shift instructions require an enhanced ALU which can do shifting.
But they also require some modifications to the datapath, which are shown in the diagram below:
 Implementing these in the processor will also require changes to the control tables. The control
tables for the unmodified single-cycle MIPS processor are given below. It is your job to add
these 6 R-type shift instructions to the processor.

Make the necessary changes and additions to the main and ALU control tables (below),
including any new control signals, so that the processor can have sll, sllv, srl, srlv, sla and slav
functioning correctly with the datapath given above.

The RTL expressions for sllv, srlv, and srav are like other R-type operations:
RF[rd]  RF[rt] op RF[rs] (where op is <<, >> and >>>)

But for sll, srl and sra, the RTL is different, requiring shamtExt(shamt):
RF[rd]  RF[rt] op shamtExt(shamt) (where op is again <<, >> and >>>)

So 3 new ALU operations are required (shift left logical, shift right logical, and shift right
arithmetical). And a way to distinguish sll, srl and sra from the other R-type operations is
needed—this means detecting their function codes in the ALU decoder, and sending a signal
back to the main decoder. In this way, the ShiftExt signal can be different for sll/srl/sra

Sha Reg
Instruc- Reg Alu Mem Mem ALU Ju Shift
mtSh Op5:0 Wri Branch
tion Dst Src Write toReg Op1:0 mp Ext
ift te
0 R-type 000000 1 1 0 0 0 0 10 0 0
except
 sll, srl,
sra
0 lw 100011 1 0 1 0 0 1 00 0 0
0 sw 101011 0 X 1 0 1 X 00 0 0
0 beq 000100 0 X 0 1 0 X 01 0 0
0 j 000010 0 X X X 0 X XX 1 0
1 sll,srl, 000000 1 1 0 0 0 0 10 0 1
sra

Since only the ALU control unit “sees” the funct bits, it must detect the sll, srl, and sra
instructions by their function codes, and send a signal (ShamtShift) to the main control decoder.
The main decoder needs this new input, so that it can distinguish sll/srl/sra from the other R-type
instructions (including sllv, srlv, and srav). In the case of sll, srl, or sra, the ShiftExt control
signal to the MUX goes high, for selecting ShamtExt(shamt) as the SrcA input to the ALU.
Otherwise, it is low, which means that RF[rs] is selected on the sllv, srlv and srav shifts, as well
as for all the other R-types and for the other instructions, as it should be. Since only 3 new ALU
operations are added (<<, >>, and >>>) 3 bits of ALUControl is still enough, since the total is
now 8 operations.

Shamt
ALUOp Funct ALUControl
Shift

00 x 010 (add) 0

01 x 110 (sub) 0

10 100000 (add) 010 (add) 0

10 100010 (sub) 110 (sub) 0

10 100100 (and) 000 (and) 0

10 100101 ( or ) 001 (or) 0

10 101010 (slt ) 111 (set less than) 0

10 000000 (sll) 011 (shift left logical) 1

10 000100 (sllv) 011 (shift left logical) 0

10 000010 (srl) 100 (shift right logical) 1

10 000110 (srlv) 100 (shift right logical) 0

 10 000011 (sra) 101 (shift right arith.) 1

10 000111 (srav) 101 (shift right arith.) 0

Question 1 b c (Final Spring 2016): Modifying MIPS Singlecycle Datapath and Control

In this question, you are asked to modify the MIPS single-cycle datapath and control, in order to
add instructions to the architecture of the MIPS processor. The following 3 parts are independent
of each other, you should answer each as if it is a separate question.

b) In this part, you will add the new instruction jmemplo. This I-type instruction ( jump memory
plus offset) jumps to the instruction whose address is the sum of the address stored in
memory (found using the standard I-type memory addressing scheme) plus the offset which
is stored in the other register.

Assembly code: jmemplo $t0, 24($s1)

Machine code: | 011000 | 10001 | 01000 | 0000000000011000

The datapath given below must be modified, in order to add the jmemplo instruction. Make
any necessary changes, but be sure to only make changes that are necessary, adding the
minimum amount of new hardware. Expanding existing MUXes is preferable to adding new
MUXes. Be sure to indicate any changes to control signals that arise from your datapath
modifications. [Hint: first write the RTL expressions, then use those to guide your datapath
changes.]
jmemplo: IM[PC]
PC  DM[RF[rs] + SignExt(immed)] + RF[rt]
 There must be a new 32-bit adder, with inputs RF[rt] (labeled WriteData) and DM[RF[rs]
+SignExt(immed)] (labeled ReadData). Its output should go to the Jump MUX, extended to be
3-to-1. The Jump control signal must be 2-bits.

c) In this part you will add the instructions sll, srl, and sra to the MIPS instruction set. These R-
type instructions use the 5-bit shamt field. [Hint: they require an enhanced ALU which can do
shifting.]

Implementing these in the processor may require changes to the datapath, and will require
changes to the control tables. The control tables for the unmodified single-cycle MIPS processor
are given below. It is your job to add these 3 R-type instructions to the processor.

i) Does the datapath need to be modified in any way? If so, explain what changes are needed. If
not, explain why not.

These 3 R-type shifts do the following RTLs: RF[rd]  RF[rt] << shamt (or >> or >>>) .
To add these to the datapath will require bringing shamt into the ALU as a 32-bit input on the
upper (or A) input. This will therefore require that the 5-bit shamt field (Instr[10:6]) be extended
in a Shamt Extender, and the 32-bit output value be brought to a new 2-to-1 MUX, located on the
A input of ALU. A new control signal Shift is need to select the MUX.
Thus: SrcA = (Shift)? ShamtExt(shamt) : RF[rs]

ii) Make the necessary changes and additions to the main and ALU control tables (below),
including any new control signals, so that the processor can have sll, srl and sla functioning
correctly with the datapath you described in part i).

Reg
Shamt Instru Reg Alu Branc Mem Mem ALU Jum
Op5:0 Writ Shift
Shift c-tion Dst Src h Write toReg Op1:0 p
e
0 R-type 00000 1 1 0 0 0 0 10 0 0
0
0 lw 10001 1 0 1 0 0 1 00 0 0
1
0 sw 10101 0 X 1 0 1 X 00 0 0
1
0 beq 00010 0 X 0 1 0 X 01 0 0
 0
0 j 00001 0 X X X 0 X XX 1 0
0
1 sll,srl, 00000 1 1 0 0 0 0 10 0 1
sra 0

Since only ALU control “sees” the funct bits, it must detect the sll, srl and sra instructions and
send a signal (ShamtShift) to the main control decoder, so that it can output the Shift control
signal to the new 2-to-1 MUX for selecting ShamtExt(shamt) as the SrcA input to the ALU.

Shamt
ALUOp Funct ALUControl
Shift
00 x 010 (add) 0
01 x 110 (sub) 0
10 100000 (add) 010 (add) 0
10 100010 (sub) 110 (sub) 0
10 100100 (and) 000 (and) 0
10 100101 ( or ) 001 (or) 0
10 101010 (slt ) 111 (set less than) 0
10 000000 (sll) 011 (shift left logical) 1
10 000010 (srl) 100 (shift right logical) 1
10 000011 (sra) 101 (shift right arith.) 1

Question 4 b c (MT #1 Spring 2016): Modifying MIPS Singlecycle Datapath and Control

In this question, you are asked to modify the MIPS single-cycle datapath and control, in order to
add instructions to the architecture of the MIPS processor. The following 3 parts are independent
of each other, you should answer each as if it is a separate question.

a) In an attempt to provide 3-way branching, it is proposed to add an R-type branch that tests 2
different pairs of registers: bgt_skip. If the value in rs is greater that the value in rt, the
branch is taken to the location stored on top-of-stack. If not, but if the value in rs is greater
than the value in rd, the next instruction is skipped. The intended usage is as follows:

bgt_skip $r1, $r2, $r3 # if $r1> $r2, branch to Target1 (found on stack)
j Target3
Target2: …….. # if $r1 > $r3, branch to here

If bgt_skip were to be implemented in MIPS, what would be the RTL expressions for this
new instruction?
 bgt_skip: IM[PC]
if (RF[rs] > RF[rt])
PC  DM[RF[29]]
else if (RF[rs] > RF[rd])
PC  PC + 8
else PC  PC + 4

b) The new instruction you will add in this part is lwwau. This I-type instruction (load word
with address update) augments the normal load word instruction with a powerful feature: it
automatically updates the address register by 4, so that the next word to be loaded is pointed
to.
Assembly code: lwwau $t0, 24($s1)
Machine code: | 011000 | 10001 | 01000 | 0000000000011000

The datapath given below must be modified, in order to add the lwwau instruction. Make
any necessary changes, but be sure to only make changes that are necessary, adding the
minimum amount of new hardware. Expanding existing MUXes is preferable to adding new
MUXes. Be sure to indicate any changes to control signals that arise from your datapath
modifications. [Hint: first write the RTL expressions, then use those to guide your datapath
changes.]

The RTL expressions are lwwau: IM[PC]

RF[rt]  DM[RF[rs]+ SignExt(immed)]
RF[rs]  RF[rs] + 4
PC  PC + 4
All the above RTL actions and register transfers except RF[rs]  RF[rs] + 4 are possible
already in the given datapath. And that one could be added by making rs a write address, and
creating RF[rs] + 4 with an extra adder and sending it to the Write Data input. But doing 2
register writes into the Register File at the same time is not currently possible. So we must
modify and enhance the Register File, to add a 2nd write port (Data, Address, and Write Enable).
It will share the single clock input CLK with the existing write port.
c) Normal ALUs offer a wide set of arithmetic, logic and shift operations, so that these can be
included in the instructions set. In this part you will add the instructions sllv, srlv, xor and nor to
the MIPS instruction set.

Implementing these in the processor may require changes to the datapath, and will require
changes to the control tables. The control tables for the unmodified single-cycle MIPS processor
are given below. It is your job to add these 4 R-type instructions to the processor.

i) Does the datapath need to be modified in any way? If so, explain what changes are needed. If
not, explain why not.

Yes, the ALUControl signals, going from Control Unit to ALU, must be 4 bits now. Adding 4 new
ALU R-type instructions to the 5 existing ones (add, sub, and, or, slt) the ALU is already capable
of doing means that 4, not 3, ALUControl signals will be needed to specify which one of the 9
operations is to be performed. The other changes required (adding capability to do sllv, srlv,
xor and nor) are internal to the ALU and don’t affect the datapath.

ii) Make the necessary changes and additions to the main and ALU control tables (below),
including any new control signals, so that the processor can have sllv, srlv xor and nor
functioning correctly with the datapath you described in part i).

Instruc- Reg Reg Alu Branc Mem Mem ALU

Op5:0 Jump
tion Write Dst Src h Write toReg Op1:0
 R-type 000000 1 1 0 0 0 0 10 0
lw 100011 1 0 1 0 0 1 00 0

sw 101011 0 X 1 0 1 X 00 0

beq 000100 0 X 0 1 0 X 01 0

j 000010 0 X X X 0 X XX 1

ALUOp Funct ALUControl

00 x 0010 (add)
01 x 0110 (sub)
10 100000 (add) 0010 (add)
10 100010 (sub) 0110 (sub)
10 100100 (and) 0000 (and)
10 100101 ( or ) 0001 ( or )
10 101010 (slt ) 0111 (set less than)
10 000100 (sllv) 1000 (sllv)
10 000110 (srlv) 1001 (srlv)
10 100110 (xor) 1010 (xor)
10 100111 (nor) 1011 (nor)

Question 1bc (Quiz #3 Sec3 Spring 2016)

Four new instructions are to be added to the “mini-MIPS” instruction set.

mfhi $rd (or mflo) puts the value from the HI (or LO) register into the rd register
mthi $rs (or mtlo) puts the value from the rs register into the HI (or LO) register

The RTL expressions for these instructions are:

mfhi: IM[PC] mflo: IM[PC]

RF[rd]  HI RF[rd]  LO
PC  PC + 4 PC  PC + 4

mthi: IM[PC] mtlo: IM[PC]

HI RF[rs] LO RF[rs]
PC  PC + 4 PC  PC + 4
b) To add the 4 new instructions to the MIPS single-cycle architecture will require changes to the
single-cycle datapath and its control. Beware that mfhi, mflo, mthi and mtlo are R-type, but not
the kind that does the work in the ALU ! Add any necessary connections (and possibly new
HW) to the single-cycle datapath given below to make them possible (Hint: look at your
RTLs!). Draw all your changes directly on the figure. Try to make your datapath changes
without adding any new multiplexors, instead you should extend existing multiplexors whenever
possible.

c) Based on the changes you made in b), show the necessary modifications to the main control
table and ALU control table given below. Make whatever changes are needed in the tables to
implement the 4 new instructions, in light of the datapath changes you made in b). Add new
rows for mfhi, mflo, mthi and mtlo and give the values in the columns, adding any new columns
or modifying existing columns (for new control signals) as necessary. Use “don’t cares” when
appropriate.

Instr MHL Reg Mem Mem LD_HI,

Reg Alu Bran ALU Jum
uctio detected Op5:0 Writ Writ toReg LD_LO
Dst Src ch Op1:0 p
n e e 1:0

R- 000 000000 1 1 0 0 0 00 10 0 0 0
type
 lw XXX 100011 1 0 1 0 0 01 00 0 0 0
sw XXX 101011 0 X 1 0 1 XX 00 0 0 0
beq XXX 000100 0 X 0 1 0 XX 01 0 0 0
j XXX 000010 0 X X X 0 XX XX 1 0 0
mfhi 100 000000 1 1 X 0 0 10 XX 0 0 0
mflo 101 000000 1 1 X 0 0 11 XX 0 0 0
mthi 110 000000 0 X X 0 0 XX XX 0 1 0
mtlo 111 000000 0 X X 0 0 XX XX 0 0 1

ALUOp Funct ALUControl MHLdetected

00 x 010 (add) xxx
01 x 110 (sub) xxx
1x 100000 (add) 010 (add) 000
1x 100010 (sub) 110 (sub) 000
1x 100100 (and) 000 (and) 000
1x 100101 ( or ) 001 (or) 000
1x 101010 (slt ) 111 (set less than) 000
1x 010000 (mfhi) xxx 100
1x 010001 (mthi) xxx 110
1x 010010 (mflo) xxx 101
1x 010011 (mtlo) xxx 111

Question 2bc (Quiz #3 Sec2 Spring 2016)

A new logical immediate instruction, xori, is to be added to the “mini-MIPS” instruction set.
xori $rt, $rs, immediate writes the contents of the xor operation to the destination register. (It is
I-format, with a 16-bit logical immediate as the 2nd source operand). The RTL expressions for
this instruction are:
IM[PC]
RF[rt]  RF[rs] xor ZeroExt(immed)
PC  PC + 4

b) To add the xori instruction to the MIPS single-cycle architecture will require changes to the
single-cycle datapath and its control. Add any necessary connections (and possibly new HW) to
the single-cycle datapath given below to make it possible (Hint: look at your RTLs!). Draw all
your changes directly on the figure. Try to make your datapath changes without adding any new
multiplexors, instead you should extend existing multiplexors whenever possible.
c) Based on the changes you made in b), show the necessary modifications to the main control
table and ALU control table given below. Make whatever changes are needed in the tables to
implement the new instruction, in light of the datapath changes you made in b). Add a new row
for xori, and give the values in the columns, adding any new columns or modifying existing
columns (for new control signals) as necessary. Use “don’t cares” when appropriate.

Reg Mem Mem

Instruc- Reg Alu Bran ALU
Op5:0 Writ Writ toRe Jump
tion Dst Src1:0 ch Op1:0
e e g
R-type 000000 1 1 00 0 0 0 10 0
lw 100011 1 0 01 0 0 1 00 0
sw 101011 0 X 01 0 1 X 00 0
beq 000100 0 X 00 1 0 X 01 0
j 000010 0 X XX X 0 X XX 1
xori 001110 1 0 10 0 0 0 11 0

ALUOp Funct ALUControl

00 x 010 (add)
01 x 110 (sub)
10 100000 (add) 010 (add)
10 100010 (sub) 110 (sub)
10 100100 (and) 000 (and)
10 100101 ( or ) 001 (or)
10 101010 (slt ) 111 (set less than)
11 x 101 (xor)

Question 1bc (Quiz #3 Sec2 Spring 2016)

The jump and link instruction (jalr $rs, $rd) writes the value PC + 4 into the rd register, and
writes the contents of the rs register into the PC (it is R-format, with the rt field being set to
zero). The RTL expressions for this instruction are:
jalr: IM[PC]
PC RF[rs]
RF[rd] PC + 4

b) To add the jalr instruction to the MIPS single-cycle architecture will require changes to
the single-cycle datapath and its control. Add any necessary connections (and possibly new
HW) to the single-cycle datapath given below to make it possible (Hint: look at your
RTLs!). Draw all your changes directly on the figure. Try to make your datapath changes
without adding any new multiplexors, instead you should extend existing multiplexors
whenever possible.
c) Based on the changes you made in b), show the necessary modifications to the main control
table and ALU control table given below. Beware that jalr is an R-type, but not the kind that
does its work on the ALU ! Make whatever changes are needed in the tables to implement the
new instruction, in light of the datapath changes you made in b). Add a new row for jalr, and
give the values in the columns, adding any new columns or modifying existing columns (for new
control signals) as necessary. Use “don’t cares” when appropriate.

Inst Jalr Reg

Reg Alu Branc Mem Mem ALU
ruc Detec Op5:0 Writ Jump1:0
Dst Src h Write toReg1:0 Op1:0
tion ted e
R- 0 000000 1 1 0 0 0 00 10 00
type
lw X 100011 1 0 1 0 0 01 00 00
sw X 101011 0 X 1 0 1 XX 00 00
beq X 000100 0 X 0 1 0 XX 01 00
j X 000010 0 X X X 0 XX XX 01
jalr 1 000000 1 X X X 0 10 XX 10

ALUOp Funct ALUControl JalrDetected

00 x 010 (add) X
01 x 110 (sub) X
1x 100000 (add) 010 (add) 0
1x 100010 (sub) 110 (sub) 0
1x 100100 (and) 000 (and) 0
1x 100101 ( or ) 001 (or) 0
1x 101010 (slt ) 111 (set less than) 0
1x 001001 (jalr) XXX 1

Question 1 (Quiz #2 Sec1 Spring 2016)

In a software system with lots of nested calls, it will be necessary to store the return address for
each call. Rather than store it in the $ra register each time, and then have to push the $ra register
onto the stack repeatedly (Mem  R[$ra]  PC+ 4), an alternative is to store directly from PC
to Memory, using an instruction like:

spc X($rx) where X is an integer value, and $rx is any of the general purpose registers

This “store PC” instruction is I-type (with the rt field being ignored). Its meaning is that the
incremented value of the program counter (PC + 4) is stored into the memory location whose
address is calculated in the usual way. RTL expressions for the spc instruction are given:
 spc: IM[PC]
PC PC + 4
DM[RF[rs] + SignExt(immed)]  PC + 4

To add this instruction to the MIPS single-cycle architecture will require changes to the single-
cycle datapath and its control. Your highest goal is to find a solution that minimizes the impact
on system performance by having the lowest impact on the clock cycle. The second goal should
be to add as little new hardware as possible.

Solution: A new 2-to-1 MUX must be added. Its 2 inputs are PCPlus4 and The RD2 output from
register file (which is RF[rt]. The MUX output is WriteData, and goes to the write port of the
Data Memory. The signal StorePC can be used to select the input to the MUX. If StorePC=1
select PC+4 , otherwise select RF[rt] .

The control table needs a\ new row for the spc instruction, and a new column for the StorePC
signal

Question 1 (Final Fall 2015) Modifying MIPS Singlecycle Datapath and Control

b) The new instruction you will add in this part is jalstack. This I-type instruction (jump and
link stack) is an unconditional change of control. It uses a direct target address, finding the
JTA on the top of stack. It stores the return address on the top of stack.

Examples of usage:
Assembly code: jalstack
Machine code: | 011001 | 11101 | 00000 | 0000000000000000 |

The datapath given below must be modified, in order to add the jalstack instruction. Make any
necessary changes, but be sure to only make changes that are necessary, adding the minimum
amount of new hardware. Expanding existing MUXes is preferable to adding new MUXes. Be
sure to indicate any changes to control signals that arise from your datapath modifications. [Hint:
first write the RTL expressions, then use those to guide your datapath changes.]

The jalstack instruction requires the following RTL operations:

IM[PC]
PC  DM[RF[29]] # JTA is read from stack area of memory
DM[RF[29]]  PC + 4 # store the return address on stack

Since a new value of JTA (coming from the Data Memory) needs to be able to load into the PC,
the datapath must add this new JTA value to the Jump MUX. The Jump MUX becomes a 3-to-1
MUX, and its control signal becomes 2-bit Jump. The memory value DM[…] needs to be chosen
in the MemtoReg MUX and the Result brought to this MUX as the JTA for jalstack. The other
change needed is to allow PC + 4 to be the write data input (WD) to the Data Memory. To
implement this, we must add a new 2-to-1 MUX with a control signal (Jalstack) just before the
WD input, and bring the PCPlus4 bus to this MUX as a data input. (The other data input to the
MUX will be the current WriteData value going to Data Memory, RF[rt] from the RD2 port of
the Register File. With these 2 changes, the datapath will allow the RTLs for jalstack.

c) MIPS offers 2 primary branch operations beq and bne. Your job in this part is to implement
the control for both of these, in the main control table. The MIPS single-cycle datapath is
somewhat different in this problem: there is no AND gate in the datapath, the Zero signal from
the ALU comes directly into the Control Unit, and the Control Unit produces a control signal
named Branch which goes to the Branch MUX, as the 1-bit select input.

The RTL expressions for these 2 branch instructions are given here:

beq: IM[PC]
if (RF[rs] = = RF[rt]) PC  PC + 4 + SignExt(immed16) || 00
else PC  PC + 4

bne: IM[PC]
if (RF[rs] ! = RF[rt]) PC  PC + 4 + SignExt(immed16) || 00
else PC  PC + 4

The main control table for the unmodified single-cycle MIPS processor is given below. It is your
job to add the beq and bne instructions to the control tables, along with any new control signals.
Make the necessary changes and additions to the control table, so that the processor can have beq
and bne functioning correctly with the datapath described above.

Since these new instructions are I-type, the main decoder can decode them, based on their
opcodes. But it needs to use the Zero signal as an additional input, to correctly determine the
value of control output Branch. So Zero (a new input) and Branch (an output which is missing)
must be added to the table, as well as 2 additional beq and bne rows, and all missing values must
be determined. The modified table is shown below, with changes in bold italic.

Mem
Instruc- Reg Reg Alu Mem ALU
Zero Op5:0 to Jump Branch
tion Write Dst Src Write Op1:0
Reg
X R-type 000000 1 1 0 0 0 10 0 0

X lw 100011 1 0 1 0 1 00 0 0

X sw 101011 0 X 1 1 X 00 0 0

X j 000010 0 X X 0 X XX 1 X
0 beq 000100 0 X 0 0 X 01 0 0
1 beq 000100 0 X 0 0 X 01 0 1
0 bne 000101 0 X 0 0 X 01 0 1
1 bne 000101 0 X 0 0 X 01 0 0

Question 1 (Quiz #4 Fall 2015) A new jump instruction jalr is to be added to the “mini-MIPS”
instruction set.

jalr $rs, $rd puts the value PC + 4 into the rd register , and writes the contents of the rs register
into the PC (it is R-format, with the rt field being set to zero. The RTL expressions for this
instruction are:
IM[PC]
PC  RF[rs]
RF[rd]  PC + 4

The datapath changes needed to make these register transfer actions possible are shown in the
diagram below. The given datapath is capable of doing the jalr instruction.
Based on the RTL expressions and datapath, show the necessary modifications to the main
control table and ALU control table given below. Beware that jalr is an R-type, but not the kind
that does its work on the ALU ! Make whatever changes are needed in the tables to implement
the new instruction. Add a new row for jalr, and give the values in the columns, adding any new
columns or modifying existing columns (for new control signals) as necessary. Use “don’t cares”
when appropriate.

Instr Reg Mem Mem

Reg Alu Bran ALU Jump
Jalr uctio Op5:0 Writ Writ toReg
Dst Src ch Op1:0 1:0
n e e 1:0

0 R- 000000 1 1 0 0 0 00 10 00
type
X lw 100011 1 0 1 0 0 01 00 00
X sw 101011 0 X 1 0 1 XX 00 00
X beq 000100 0 X 0 1 0 XX 01 00
X j 000010 0 X X X 0 XX XX 01
1 jalr 00000 1 1 X X 0 10 10 10
 ALUOp Funct ALUControl Jalr
00 x 010 (add) X
01 x 110 (sub) X
1x 100000 (add) 010 (add) 0
1x 100010 (sub) 110 (sub) 0
1x 100100 (and) 000 (and) 0
1x 100101 ( or ) 001 (or) 0
1x 101010 (slt ) 111 (set less than) 0
1x 001001 (jalr) xxx 1
Changes to the tables are indicated in bold italic font

Question 4 (MT #1 Fall 2015): Modifying MIPS Singlecycle Datapath and Control

In this question, you are asked to modify the MIPS single-cycle datapath and control, in order to
add instructions to the architecture of the MIPS processor. The following 3 questions are
independent of each other, you should answer each as if it is a separate question.

b) The new instructions you will add in this part are jm and bm. These I-type instructions (jump
memory and branch memory) are both unconditional changes of control flow. Both access
memory in the usual way, in order to get the address value. jm uses a direct target address
(its JTA is like jr in that respect). bm uses a PC-relative calculation to get its BTA (similar to
the other branches). Examples of usage:
Assembly code: jm 24($s1)
Machine code: | 011000 | 10001 | 00000 | 0000000000011000

Assembly code: bm 36($gp)

Machine code: | 011001 | 11100 | 00000 | 0000000000100100

The datapath given below must be modified, in order to add the jm and bm instructions. Make
any necessary changes, but be sure to only make changes that are necessary, adding the
minimum amount of new hardware. Expanding existing MUXes is preferable to adding new
MUXes. Be sure to indicate any changes to control signals that arise from your datapath
modifications. [Hint: first write the RTL expressions, then use those to guide your datapath
changes.]

The jm instruction requires the following RTL operations:

IM[PC]
PC  DM[RF[rs] + SignExt(immed16)] # JTA is read from memory

The bm instruction requires the following RTL operations:

IM[PC]
PC  PC + 4 + DM[RF[rs] + SignExt(immed16)] # BTA is calculated PC-relative,
# using the memory value
Since 2 new values need to be able to load into the PC, the choice of adding them to the Branch
MUX or the Jump MUX needs to be made. Since both jm and bm are unconditional, it is simpler
to add their JTA and BTA values to the Jump MUX. The Jump MUX becomes a 4-to-1 MUX,
and its control signal becomes 2-bit Jump. The memory value DM[…] needs to be brought to
this MUX as the JTA for jm, and it needs to be brought to a 32-bit adder, where it is combined
with PCPlus4, to make the BTA for bm. This adder’s output is also brought to the Jump MUX.
Rather than add a new 32-bit adder just for bm, we will use one already there (for beq) and
allow double use by adding a 2-to-1 MUX with a control signal. [Adding a new 32-bit adder
would be far more costly!]

c) Conditional operations for data movement and data manipulation are sometimes part of the
instruction set. The condition depends on the result of a previous data operation, recorded in a
flip flop. This avoids test-and-branch operations, and their associated control hazards. In this
part, you will add two conditional operations to single-cycle MIPS. addc (add conditional) is an
R-type operation that adds the two source operands and puts the result into the destination
register only if the condition bit (in the flip flop) is set. Otherwise, it does not change the
destination register. Similarly, movc (move conditional) is an R-type operation that performs a
data move from source register to destination register only if the condition bit is set. Otherwise
no data is moved.

The RTL expressions for these 2 new instructions are given here:
addc: IM[PC]
if (Cond) RF[rd]  RF[rs] + RF[rt]
PC  PC + 4
 movc: IM[PC]
if (Cond) RF[rd]  RF[rs]
PC  PC + 4

The necessary changes have been made on the processor datapath below in order to add these
two instructions to MIPS. [Note: while these two instructions don’t set and reset the Cond flip
flop, other instructions will set and reset it, so those control signals are shown also.] Assume that
the function codes for addc and movc are 20 and 21, respectively.

The control tables for the unmodified single-cycle MIPS processor are given below. It is your job
to add the 2 new R-type instructions (addc and movc) to the control tables, along with any new
control signals. Make the necessary changes and additions to the control tables, so that the
processor can have addc and movc functioning correctly with the given datapath.

Since these new instructions are R-type, it will be necessary for the ALU control to decode them,
since it sees and decodes the function codes, and not the main control decoder. Giving notice,
from ALU decoder to main decoder, requires a new 2-bit output (named C_Op, for conditional
operation) from the ALU decoder, and a corresponding input to the main decoder. In addition to
this, the main decoder must also receive the Cond FF value as an input. The modified tables are
shown below, with changes in bold italic.
 Mem Ju
Instruc- Reg Reg Alu Bran Mem ALU
Cond C_ Op5:0 to m
tion Write Dst Src ch Write Op1:0
FF Op Reg1:0 p

X 00 R-type 000000 1 1 0 0 0 00 10 0

X 00 lw 100011 1 0 1 0 0 01 00 0

X 00 sw 101011 0 X 1 0 1 XX 00 0

X 00 beq 000100 0 X 0 1 0 XX 01 0

X 00 j 000010 0 X X X 0 XX XX 1

0 01 addc 000000 0 X X 0 0 XX 10 0

1 01 addc 000000 1 1 0 0 0 00 10 0

0 10 movc 000000 0 X X 0 0 XX 10 0

1 10 movc 000000 1 1 X 0 0 10 10 0

ALUOp Funct ALUControl C_Op

00 x 010 (add) 00
01 x 110 (sub) 00
10 100000 (add) 010 (add) 00
10 100010 (sub) 110 (sub) 00
10 100100 (and) 000 (and) 00
10 100101 ( or ) 001 (or) 00
10 101010 (slt ) 111 (set less than) 00
10 010100 (addc) 010 (add) 01
10 010101 (movc) xxx 10

Question 4 (MT1 Spring 2015): bgezal, ll, sc

You are an engineer for the MIPS Corporation, and you have been asked to modify the MIPS single-cycle
datapath and control, in order to add instructions to the architecture of the MIPS processor. The following
questions are independent of each other, you should answer each as if it is a separate question.
b) The new instruction you will add in this part is bgezal. This I-type instruction (bgezal means branch
and link if greater than or equal to zero) is a conditional call instruction, testing whether the register
value RF[rs] is greater than or equal to zero. It is like jal, but conditional. An example of bgezal:

Assembly code: bgezal $t0, Label

Machine code: | 000001 | 01000 | 10001 | difference to Label |

The datapath given below must be modified, in order to add the bgezal instruction. Make any necessary
changes, but be sure to only make changes that are necessary, adding the minimum amount of new
hardware. Be sure to indicate any changes to control signals that arise from your datapath modifications.

The bgezal instruction requires the following register transfer operations:

IM[PC]
if (RF[rs] >= 0)
RF[31]  PC + 4
PC  PC + 4 + ((SignExt(immed) <<2 ) # Branch Target Address (BTA)
else
PC  PC + 4

Testing whether RF[rs] is greater than or equal to zero amounts to looking at the MSB (the sign bit) of
the register operand after it is fetched from the Register File. If Read_data1[31] = 0, then (RF[rs] >=
0) is true. If Read_data1[31] = 1, then RF[rs] is negative. From the above RTL expressions, the
singlecycle MIPS datapath can already do the fetch (IM[PC]) and the PC  PC + 4 incrementation, and
the PC  BTA for taking the branch. But the datapath needs modification in order to be able to do
R[31]  PC + 4, and in order to be able to decide (in hardware) whether or not to take the branch and
load RF[31], or not. So both PC and register file need conditional loads, which load if the instruction is
bgezal AND the Read_data1[31] bit is 0.
 --the MUX controlled by MemtoReg is extended to be 3-to-1, and MemtoReg becomes a 2-bit control
signal. At the new data input 2, a bus from the PC + 4 adder is connected, so that PC + 4 can be selected
to go to the Write_data part of the write port of the register file.

--the MUX controlled by RegDst is extended to be 3-to-1 and RegDst becomes a 2-bit control signal. At
the new data input 2, the 5-bit constant “31” is hardwired.

--the Control unit needs to decode this I-type instruction (which is possible from the opcode bits), and
create a new control signal Bgezal.

--the gate arrangement that controls the select signal for Branch MUX must be modified, since there is
another condition that must be tested: we must branch if the instruction is bgezal and the sign bit of
RF[rs] = 0 The MUX control expression requires an extra AND gate plus an OR gate to implement:
select(BranchMUX) = (Branch & Zero) + (Bgezal & ~Read_data1[31])

--the write enable signal for the Register File is now conditional, as follows:

WriteEnable(reg file) = RegWrite + (Bgezal & ~Read_data1[31]). The AND condition is already
available from the gates added for the Branch MUX, so only an additional OR gate is also needed.

c) In multi-process and multiprocessor systems, it is necessary for synchronization purposes to prevent

access to a critical memory location between reading it and writing it. A single atomic instruction which
performs read-modify-write is often too slow for high clock rate RISC processors. Instead, two short
instructions that are linked logically are used in MIPS: load linked and store conditional. The store is
only performed if there has been no other write to the memory location since the load—hence, the two
instructions together act as one atomic action. The necessary changes have been made on the processor
datapath below in order to add these two instructions to MIPS.
 Reg
ALUO
Instruction Writ RegDst ALUSrc Branch Jump MemWrite MemtoReg Ll Sc
p
e

R-type 1 1 0 0 0 0 10

lw 1 0 1 0 0 0 00

sw 0 x 1 0 0 1 00

beq 0 x 0 1 0 0 01

j 0 x x x 1 0 xx

ll

sc

The control table above is for the single-cycle MIPS processor whose datapath is given on the previous
page. Note that it is your job to add the 2 new instructions (ll and sc) to the control table. Load linked (ll)
performs the load in the usual way, but also saves a copy of the value loaded in a Test register. Later,
when store conditional (sc) is performed, if the value in memory has not been changed since the ll
instruction (i.e if Test = DM[address]), then the store is performed in the usual way, and the success value
of 1 is written to the RF[rt] register. But if the value in memory has been modified, then the ll-sc action is
not atomic, and the store is not performed. In this case, the failure value of 0 is written to the RF[rt]
register. Make the necessary changes and additions to the control table so that the processor can have ll
and sc functioning correctly with the given datapath.

Solution:
RegW
Instruction RegDst ALUSrc Branch Jump MemWrite ALUOp Mem2Reg Ll Sc
r

R-type 1 1 0 0 0 0 10 00 0 0

lw 1 0 1 0 0 0 00 01 0 0

sw 0 x 1 0 0 1 00 xx 0 0

beq 0 x 0 1 0 0 01 xx 0 0

j 0 x x x 1 0 xx xx 0 0

ll 1 0 1 0 0 0 00 01 1 0
sc 1 0 1 0 0 0 00 10 0 1
Question 1 (MT #2 Spring 2015): syscall, eret

You are an engineer for the MIPS Corporation, and you have been asked to modify the MIPS single-cycle
datapath and control, in order to add instructions to the architecture of the MIPS processor. The following
2 questions are independent of each other, you should answer each as if it is a separate question.

b) The new instructions you will add in this part are syscall and eret.

i) The first one syscall is an R-type instruction. An example of syscall usage is:
Assembly code: syscall
Machine code: | 000000 | 00000 | 00000 | 00000 | 00000 | 001100

As you know, the effect of syscall is to cause an exception (32 is the code for this exception), which
means the exception handler code in the operating system will process the syscall, according to the
values in $v0 and the other parameter registers (if any). [Hint: don’t forget that all exceptions,
whether HW- or SW-caused, change the Cause, EPC and Status registers.]

ii) The second new instruction to be added is eret, which returns to user code from the exception
handler, at the end of exception handler routine. An example of eret usage is:
Assembly code: eret
Machine code: | 010000 | 10000 | 00000 | 00000 | 00000 | 011000

(Note that since it is a coprocessor instruction, it has opcode 0x16, and that the rs
field plus the func field are used in decoding it)

This R-format (but not R-type!!) instruction restores the PC and transfers control to the place in the
user program after (or where, if it will retry) the place the exception was caused.

The datapath given below must be modified, in order to add the syscall and eret instructions. Make
any necessary changes, but be sure to only make changes that are necessary, adding the minimum
amount of new hardware. Be sure to indicate any changes to control signals that
arise from your datapath modifications.

Before making any datapath changes, we must first determine the RTL expressions that are needed for
these 2 new instructions. Here are the RTLs:
syscall eret

IM[PC] IM[PC]
Cause  32 Status[4]  1
Status[1]1 Status[1]  0
EPC  PC PC  EPC
PC  0x80000180

The syscall instruction is R-type, and because it has op=0 and func=12, it must be recognized by either the
Main Control decoder (adding Instr[5:0] as additional inputs), or by the ALU Control, with a signal Syscall
sent back to Main Control as additional input. The actions of syscall are to put 32 in the Cause register, put
PC in the EPC register, put the Exception Address (0x80000180) into the PC and set bits in the Status
register (to force the CPU into kernel mode and disables interrupts). [Note: the “green card” and other
sources give different info about which Status register bits to set.]
The eret instruction is R-format but not R-type, and must be decoded based on op=16, rs=16 and func=24.
There are several ways to do this, one of which is to have an “rs Decoder” which recognizes 16. This signal
and FuncIs24 (decoded in the ALU Control) are sent to the Main Control as additional inputs. The actions
of eret are to put EPC into the PC, and to change bits of the Status register (to enable interrupts and return
to user mode). [Note: the “green card” and other sources give different info about which Status register bits
to change.]

From the above, we can determine the additional hardware which is needed . We must have a Cause
register, a Status register, and an EPC register, each with appropriate inputs, outputs, and control signals
(clk is assumed and thus not shown in the diagram). Also, a NewStatus unit, which takes current Status bits
and control inputs which specify the instruction (Syscall or Eret) and determines the new status bits to be
loaded. The Jump MUX needs to be extended to 4-to-1, with a 2-bit control signal. Other new control signals
are Cause_LD, EPC_LD, Status_LD, (going to the load enable inputs of the Cause, EPC and Status
registers, respectively) and Eret, which along with Syscall, are control inputs to the NewStatus unit.
Question 4 (Final Retake Spring 2015): reverseW_endian

Incompatible data formats between big-endian and little-endian processors can be handled by software
routines to do the conversion. They do byte-order reversal, so that MSB  LSB, 2ndMSB 
2ndLSB, etc. But this is very slow, especially for large data sets. A better way is to handle the conversion
in hardware. The processor architecture can be modified to add special instructions to do fast big-endian
to little-endian conversion, and vice versa. In this problem, you will modify the MIPS single-cycle
datapath and control to do this, and then analyze the performance improvement of this approach.

a. Add a new I-type instruction reverseW_endian to MIPS. This instruction takes a 32-bit value
from a source register, converts the “endian-ness” of the bytes, and puts the modified data word
into the destination register.

i. If reverseW_endian were to be implemented in MIPS, what would be the RTL

expressions for this new instruction?

To avoid complicated RTL expressions, an operator byte_reversal (implemented in a

hardware unit which criss-crosses the bytes), is used in the expression below:
IM[PC]
RF[rt]  byte_reversal (RF[rs])
PC PC + 4

ii. Modify the MIPS datapath given below to add the reverseW_endian instruction. Make
any necessary changes, but be sure to only make changes that are necessary, adding the minimum
amount of new hardware. Be sure to indicate any changes to control signals that arise from your
datapath modification.

--the reverseW_endian instruction requires the addition of a byte_reversal unit, whose

Input comes from R[rs] and whose Output is the 32-bit value resulting from the following
swaps:
Input[31:24]  Output[7:0]
Input[23:16]  Output[15:8]
Input[15:8]  Output[23:16]
Input[7:0]  Output[31:24]

--the MUX controlled by MemtoReg is extended to be 3-to-1, and MemtoReg becomes a

2-bit control signal. At the new data input 2, a bus from the Output of byte_reversal is
connected, so that it can be selected to go to the Write_data part of the write port of the
register file.

--the Control unit needs to decode this I-type instruction (which is possible from the
opcode bits). No new control signal is needed (except the increase from 1-bit to 2-bits in
MemtoReg).
 iii) The control table below is for the single-cycle MIPS processor whose datapath is given
above. It is your job to add the new instruction reverseW_endian to the control table.
Make the necessary changes and additions to the control table so that the processor can
have reverseW_endian functioning correctly with the modified datapath you gave in part
ii.

As mentioned earlier, the only changes needed are to make MemtoReg into a 2-bit
control signal, and to add the new instruction to the table (and therefore include it in
the decoder implementation). The table’s new additions are in italic font.
Instruction Reg Reg ALUSr Branch Jump Mem ALUO Mem Mem
Dst c Write p
 toReg toReg
Write
[LSB] [MSB]

R-type 1 1 0 0 0 0 10 0 0

lw 1 0 1 0 0 0 00 1 0

sw 0 x 1 0 0 1 00 x x

beq 0 x 0 1 0 0 01 x x

j 0 x x x 1 0 xx x x

revW_end 1 0 x 0 0 0 xx 0 1

Question 4 (MT #1 Spring 2014): sll, whereami, whereami_m,

You are an engineer for the MIPS Corporation, and you have been asked to modify the MIPS single-cycle
datapath and control, in order to add instructions to the architecture of the MIPS processor. The following
3 questions are independent of each other, you should answer each as if it is a separate question.

a i) Give the RTL expressions for the MIPS sll instruction (shift left logical)

IM[PC]
RF[rd]  RF[rt] <<shamt
PC  PC + 4

a ii) Modify the Verilog code for the ALU given below, so that it becomes capable of doing sll when the
ALUControl bits are 100.

module alu ( input [31:0] A, input [31:0] B, input [2:0] ALUControl,

output reg[31:0] Result, output Zero);

always @ (A or B or ALUControl)
case(ALUControl)
3'b000: Result <= A & B; // AND
3'b001: Result <= A | B; // OR
3'b010: Result <= A + B; // ADD
3'b110: Result <= A - B; // SUB
3'b111: Result <= (A < B)? 1:0; // SLT
 default: Result <= {32{1'b1}}; //undefined ALU operation
endcase
assign Zero = (Result==0) ? 1 : 0 ;
endmodule

Solution:
module alu ( input [31:0] A, input [31:0] B, input [2:0] ALUControl, input [4:0] shamt,
output reg[31:0] Result, output Zero);

always @ (A or B or ALUControl or shamt)

case(ALUControl)
3'b000: Result <= A & B; // AND
3'b001: Result <= A | B; // OR
3'b010: Result <= A + B; // ADD
3'b100: Result <= B << shamt; // SLL
3'b110: Result <= A - B; // SUB
3'b111: Result <= (A < B)? 1:0; // SLT
default: Result <= {32{1'b1}}; //undefined ALU operation
endcase
assign Zero = (Result==0) ? 1 : 0 ;
endmodule

b) The new instructions you will add in this part are whereamI and whereamI_m. These I-type
instructions load the PC value into a register (whereamI) or into a memory location (whereamI_m), so
that the program can learn what its current PC value is, answering the question “Where am I?”

Example of whereamI:
Assembly code: whereamI $t0
Machine code: | 010101 | 00000 | 01000 | 0000000000000000 |

Example of whereamI_m:
Assembly code: whereamI_m 100 ($s1)
Machine code: | 010110 | 10001 | 00000 | 0000000001100100 |

Note that the opcodes 21 and 22 are used for these new instructions.

The datapath given below must be modified, in order to add the whereamI and whereamI_m instructions.
Make any necessary changes, but be sure to only make changes that are necessary, adding the minimum
amount of new hardware. Be sure to indicate any changes to control signals that arise from your datapath
modifications.

Solution:
whereamI: to make RF[rt]PC possible, PC is brought to a new input to the MemtoReg MUX . The
MUX is now 3-to-1, with a 2-bit control signal.
whereamI_m: to make DM[RF[rs]+ SignExt(immed)]PC possible, PC is brought to a new 2-to-1
MUX, whose other input is the RF[rt] bus from Readdata2 of the Register File. The MUX output
goes to the Writedata input of Data Memory. The new MUX’s select input is a new control signal
from the main control unit (we can call it whereamI_m , since it is only high for this instruction).
c) Reminder: this part is independent of parts a) and b) above. The datapath given below implements the
following instructions: R-type, lw, sw, beq, and j, plus jal, jr and jalr. Your job is to complete the control
table (given on the following page). Be sure to include all control signal values for all instructions. [The
“green card” needs the following corrections and additions: the return address is PC+4, this is stored in
the rd register of the jalr instruction.

The following things must be added to the datapath drawing (by hand) in order to complete the problem, so that it is capable of
implementing jal, jr and jalr 1) an extension of the Jump MUX, to make it 3-to-1. The control signal will become 2-bit, and the
input2 will come from RF[rs] 2) an extension of the MemtoReg MUX, to make it 3-to-1. The control signal will become 2-bit,
and the input2 will come from PC+4 3) an extension of the RegDst MUX, to make it 3-to-1. The control signal will become 2-
bit, and the input2 will be a hardwired ”31” 4) the function field bits (Instruction[5-0] must be brought into the main Control
unit OR signals from the ALU control unit named jr and jalr must be brought into the main Control unit
 Reg Reg ALUSr Mem Mem
Instruction Branch ALUOp Jump
Write Dst c Write toReg

R-type
1 01 0 0 0 00 10 00
(not jr, jalr)

lw 1 00 1 0 0 01 00 00

sw 0 xx 1 0 1 xx 00 00

beq 0 xx 0 1 0 xx 01 00

j 0 xx x x 0 xx xx 01

jal 1 10 x x 0 10 xx 01

jr 0 xx x x 0 xx xx 10

jalr 1 01 x x 0 10 xx 10

The values in italics are the solutions

Question 2 (Final Spring 2014): mfhi, mflo, mthi, mtlo

You are the chief architect for an embedded processor, incorporating a MIPS core. Your system needs to
extend the MIPS instruction set, by adding some new instructions to the architecture, modifying the
MIPS single-cycle datapath and control. The following questions are independent of each other, you
should answer each as if it is a separate question.

b) The new instructions you will add in this part are mfhi, mflo, mthi, and mtlo. These 4 special
instructions are actually defined in the MIPS architecture, but until now your company had not
implemented them. Now you will. They move values between the HI and LO registers and the register
file. Examples of usage might be:

mfhi $s3 , with machine format 0 | 0 | 0 | 19 | 0 | 16

mtlo $gp , having machine format 0 | 28 | 0 | 0 | 0 | 19

Note that these 4 instructions are all R-type operations, already defined in MIPS.
The datapath below must be modified, in order to add the mfhi, mflo, mthi, and mtlo instructions. Make any
necessary changes, but be sure to only make changes that are necessary, adding the minimum amount of new
hardware. Be sure to indicate any changes to control signals that arise from your datapath modifications.

The solution needs 2 additional registers, HI and LO to be added to the datapath. The 32-bit inputs to each
come from the Read data1 port of the Register File. The 32-bit outputs of each go to the MemtoReg MUX, to
additional inputs 2 and 3. LD signals to these registers, named mthi and mtlo respectively, come from the
Control Unit. The MemtoReg MUX becomes 4-to-1, and its control signal is now 2-bits.
c) The datapath given below implements the following instructions: R-type, lw, sw, beq, and j, plus jal, jr
and jalr. Your job is to complete the control table (given on the following page). Be sure to include all
control signal values for all instructions. [The “green card” needs the following corrections and additions:
the return address is PC+4, this is stored in the rd register in the jalr instruction. [Reminder: this part is
independent of parts a) and b) above .]

The following things must be added to the datapath drawing (by hand) in order to complete the problem, so that it is
capable of implementing jal, jr and jalr 1) an extension of the Jump MUX, to make it 3-to-1. The control signal
will become 2-bit, and the input2 will come from RF[rs] 2) an extension of the MemtoReg MUX, to make it 3-to-1.
The control signal will become 2-bit, and the input2 will come from PC+4 3) an extension of the RegDst MUX, to
make it 3-to-1. The control signal will become 2-bit, and the input2 will be a hardwired ”31” 4) the function field
bits (Instruction[5-0] must be brought into the Main Control unit (or else, signals from the ALU control unit named
jr and jalr must be brought into the Main Control unit)
 RegW Reg Mem Mem
Instruction ALUSrc Branch ALUOp Jump
Write Dst Write toReg

R-type (not
1 01 0 0 0 00 10 00
jr, jalr)

lw 1 00 1 0 0 01 00 00

sw 0 xx 1 0 1 xx 00 00

beq 0 xx 0 1 0 xx 01 00

j 0 xx x x 0 xx xx 01

jal 1 10 x x 0 10 xx 01

jr 0 xx x x 0 xx xx 10

jalr 1 01 x x 0 10 xx 10

The solution is the values in bold italics

Question 2 (Final Retake Spring 2014): movep_skip, movenp_skip

b) The new instructions you will add in this part are movp_skip and movnp_skip. These R-type
instructions move a register value into another register and skip the next instruction if the 3 rd register is
positive (movep_skip) or if it is non-positive (movnp_skip). If the condition is not met, then they do
nothing. The RTL expressions for these 2 instructions are:

movp_skip: movnp_skip:
IM[PC] IM[PC]
if (RF[rs] > 0) if (RF[rs] ≤ 0)
RF[rd] RF[rt] RF[rd] RF[rt]
PC PC + 8 PC PC + 8
else PC PC + 4 else PC PC + 4

To add these instructions to the MIPS single-cycle architecture will require changes to the single-cycle
datapath and control. In this part, you will make changes to the datapath only. Using the RTL expressions
given above, you should modify the datapath, adding whatever is needed: busses, datapath elements, and
control signals. Your goal should be to add as little new hardware as possible. Be sure to indicate any
changes to control signals that arise from your datapath modifications. Draw all your changes directly on
the figure on the next page.
Solution: The following hardware changes are needed:

--the Main Control, in order to generate the correct control signals, needs to know if the R-type
instructions are movp_skip or movnp_skip. Therefore signals from ALU Control, indicating when it
decodes movp_skip or movnp_skip, must come to Main Control. Similarly, Main Control needs to know
if RF[rs] > 0 or not.

--PC + 8 must be created with a new adder. The signal must be deliverable to PC, via the Jump MUX, by
adding a new input and making the control signal 2-bits.

--the RF[rs] value from Readdata1 port of Register File must go to a new GTZ ( > 0 ) comparator box,
whose output is GTZ

--the GTZ signal goes to the Main Control, so that it can generate the correct control signals.
c) Next, your job is to add whatever is necessary to the control table given below, in light of the datapath
changes you have made. Be sure to include all control signal values for all instructions.

Reg RegD ALU Mem Mem ALU

Instruction Branch Jump
Write st Src Write toReg Op

R-type, exc.
1 1 0 0 0 0 10 00
movX_skip

lw 1 0 1 0 0 1 00 00

sw 0 x 1 0 1 x 00 00

beq 0 x 0 1 0 x 01 00

j 0 x x x 0 x xx 01

movp_skip GTZ 1 0 0 0 0 11 GTZ ? 10 : 00

movnp_skip !GTX 1 0 0 0 0 11 GTZ ? 00 : 10

Reg RegD ALU Mem Mem ALU

Instruction Branch Jump
Write st Src Write toReg Op

R-type, exc.
1 1 0 0 0 0 10 00
movX_skip

lw 1 0 1 0 0 1 00 00

sw 0 x 1 0 1 x 00 00

beq 0 x 0 1 0 x 01 00

j 0 x x x 0 x xx 01

movp_skip GTZ 1 0 0 0 0 11 GTZ ? 10 : 00

movnp_skip !GTX 1 0 0 0 0 11 GTZ ? 00 : 10

The solution is the values in bold italics

The solution is the values in bold italics
Note: new ALUOp value of 11 causes passB (ALUOut  B input)

Question 4 (Midterm Spring 2013): wai_R, wai_M, R-types, lw, sw, beq, bne, and jal

You are an engineer for the MIPS Corporation, and you have been asked to modify the MIPS single-cycle
datapath and control, in order to add instructions to the ISA of the MIPS processor. In the following,
parts b and c are independent on each other

b) Sometimes programs want to examine the PC contents, so a way is needed to get the PC value into
register (or memory). To meet this need, the wai (where am I?) instructions cause the current value of the
PC to be copied into a register, or into memory.

wai_R is an R-type instruction which causes R[rs]  PC. All fields in the machine instruction are 0
except rs and func.

wai_M is an I-type instruction which causes DM[R[rs]]  PC. All fields in the machine instruction are 0
except op and rs.

To add these instructions to the MIPS single-cycle architecture will require changes to the single-cycle
datapath and control. In this part, you will make changes to the datapath only. Using the RTL expressions
given above, you should modify the datapath, adding whatever is needed: busses, datapath elements, and
control signals. Your goal should be to add as little new hardware as possible. Draw all your changes
directly on the figure.
Solution:
To add wai_R to the datapath requires the PC value to be made available as an input to the Register File.
So a bus is added, to bring it to the MemtoReg MUX, making it a 3-to-1 MUX. The MUX now needs a 2-
bit control. The Instruc[25-21] bits (the rs field) must be connected as a new input to the RegDst MUX,
making it a 3-to-1 MUX. The MUX now needs a 2-bit control. To identify the wai_R instruction, the
function field bits must be decoded. If the Instruc[5-0] bits are brought to the main Control unit, it can
decode the instruction and send 2-bit control signals to the MemtoReg and RegDst MUXes. If the
Instruc[5-0] bits are not brought into the main Control unit for decoding, then the decoding must take
place in the ALU Control unit. A new output Wai_R signal can be sent to the 2 MUXes directly (so they
would have mixed control signals, with one coming from main control and one from ALU control), or it
can be sent as an input to the main control unit, to allow it to generate the 2-bit control signals to the
MUXes correctly.

To add wai_M to the datapath requires the PC value to be made available as an input to the Data
Memory. So a bus and a new MUX is added, to bring it to the Write Data input. The control signal to the
new MUX is Wai_M, which is coming from the main Control unit, based on decoding the opcode. Since
the 16-bit immediate field is 0, R[rs] is the same as R[rs] + SignExt (immed); therefore the memory
address is calculated in the usual way.
c) For the datapath given below, which implements R-types, lw, sw, beq, bne, and jal instructions, give
the complete control table (starting with the partial table given on this and the next page). In completing
the table, be sure to include all control signal values for all instructions. Use X for ‘don’t care’ when the
value doesn’t matter.

[These things must be drawn on the datapath diagram for this part c problem: Connect PC + 4 to MemtoReg MUX, extend it to
3-to-1. Make its control signals 2-bit. Connect “11111” (a hardwired ‘31’) to RegDst MUX, extend it to 3-to-1. Make its control
signals 2-bit. Extra control signals coming from Control Unit are MemtoReg(2 bit), and RegDst ( 2-bit) and Bne (1-bit). Note
that Jump should be renamed Jal, and Branch should be renamed Beq]

Inputs Signal Name R-type lw sw beq bne jal

Op5 0 1 1 0 0 0

Op4 0 0 0 0 0 0

Op3 0 0 1 0 0 0

Op2 0 0 0 1 1 0
 Op1 0 1 1 0 0 1

Op0 0 1 1 0 1 1

Outputs 0 X
ALUSrc 0 1 1 0
0 1
RegWrite 1 1 0 0
0 0
MemRead 0 1 0 0
0 0
MemWrite 0 0 1 0
0 X
ALUOp1 1 0 0 0
1 X
ALUOp0 0 0 0 1
XX 10
RegDst (2) 01 00 XX XX
XX 10
MemtoReg(2) 00 01 XX XX
0 0 0 1 0 X
Beq
0 0 0 0 1 X
Bne
0 0 0 0 0 1
Jal
The solution is the values in bold italics

Question 5 (Makeup Spring 2013): push, pop, swap

You are an engineer for the MIPS Corporation, and you have been asked to modify the MIPS ISA to add
3 new instructions: push, pop, and swap. You will add these 3 instructions to the MIPS processor, by
modifying the single-cycle datapath and control.

a) The push and pop instructions have standard meaning—they access the top-of-stack to add or remove a
1-word data item. Both will be I-type MIPS instructions, with opcodes 22 and 23, respectively. For
example, push causes the 32-bit value stored in the specified register to be copied to the top-of-stack.
After pushing, the stack pointer will point to the new top-of-stack. Examples of these instructions and
their formats are:

push $a0 22 | 29 | 4 | 000 … … 0100

pop $ra 23 | 29 | 31 | 000 … … 0000

The swap instruction will also be I-type—it exchanges the values of two registers in the register file. If
opcode 19 is assigned to this new instruction, then an example of the swap instruction and its format are:

swap $t0, $s0 19 | 8 | 16 | 000 … . . . 0000

List all the Register Transfer Language (RTL) statements that implement the MIPS push, pop and swap
instructions (the general push, pop and swap statements, not the specific example statements above!)
Solution:
push: IM[PC]
DM[R[rs] - 4] R[rt]
R[rs]  R[rs] – 4
PC  PC + 4

pop: IM[PC]
R[rt]  DM[R[rs]]
R[rs]  R[rs] + 4
PC  PC + 4

swap: IM[PC]
R[rt]  R[rs]
R[rs]  R[rt]
PC  PC + 4

b) Now the push, pop and swap instructions need to implemented in hardware.

To add these instructions to the MIPS single-cycle architecture will require changes to the single-cycle
datapath and control. In this part, you will make changes to the datapath only. Using the RTL expressions
that you found in part a), you should modify the datapath, adding whatever is needed: busses, datapath
elements, and control signals. You can modify any element in the datapath, except the ALU. Your goal
should be to add as little new hardware as possible. Draw all your changes directly on the figure given
below.
Both the pop and the swap require two writes to the Register File, so we must add a second Write port:
32-bit data input (Write2 data), 5-bit address input (Write2 register), and new load control signal
(RegWrie2). The R[rs] writes in pop, and in swap will be done using this new port. The R[rs] write in
push could be done with either Write port.

There are 2 main ways to use the new Write port:

1) Allowing all 3 R[rs] writes to be done using the new Write2 port will require no change on the RegDst
MUX or the MemtoReg MUX, but a new 3-to-1 32-bit MUX for the 3 values to write into R[rs]. OR…
2) If we use the existing Write port to bring in R[rs] – 4 (from the ALU, via MemtoReg MUX) then we will
need to make the RegDst MUX into 3-to-1 5-bit MUX, and add a new 2-to1 32-bit MUX for the other 2
values going into R[rs] via Write2 port, and make no changes to the MemtoReg MUX. This is lest
hardware than the first option.

1) If we let the R[rs] writes all be done at the new Write port2, then the datapath will require a 32-bit
adder (to create R[rs] + 4) and a 3-to-1 MUX for the Write2 data input. The MUX chooses between
R[rs] – 4, R[rs] + 4, and R[rt], connected from the ALU, the new adder and the Register File,
respectively. The MUX control is a new 2-bit signal Write2sel. The Write2 register address is connected
to the rs field bits, Inst[25-21].

2) If we let the R[rs]  R[rs] -4 write (from push) be done on the existing Write port, the only change
needed is to bring the rs field bits, Inst[25-21], to the RegDest MUX, making it a 3-to-1 MUX. So we must
expand its control signal to 2-bits.The other two writes to R[rs], in pop and swap, must be written to the
new Write2 port, with data chosen via a 2-to-1 MUX, controlled by the new 1-bit Write2sel control
signal. The register address of this 2nd Write port is always the rs field bits, Inst[25-21]. Of course,
creating the R[rs] + 4 value (for pop) requires a 32-bit adder in the datapath.

Note that R[rs] – 4 in push can be done using the ALU and the subtract instruction, so no additional
hardware is needed for it. Similarly, in the swap instruction, the ALU can simply add (or sub) the R[rs]
value with the sign-extended immediate, which is 0, to create R[rs].

c) The datapath in the previous page, including the changes you made for solving part b), should now be
able to implement R-types, lw, sw, beq, j, push, pop, and swap instructions. Now give the complete
control table (starting with the partial table given below) to make all those instructions possible. In
completing the table, be sure to include all control signal values for all instructions, including any new
control signals you created in part b. Use X for ‘don’t care’ when the value doesn’t matter.

Inputs Control R-type lw sw beq j push pop swap

Signal

Op5 0 1 1 0 0 0 0 0

Op4 0 0 0 0 0 1 1 1

Op3 0 0 1 0 0 0 0 0

Op2 0 0 0 1 0 1 1 0
 Op1 0 1 1 0 1 1 1 1

Op0 0 1 1 0 0 0 1 1

Outputs X 1 1 1
ALUSrc 0 1 1 0

0 0 1 1
RegWrite 1 1 0 0

0 0 1 0
MemRead 0 1 0 0

0 1 0 0
MemWrite 0 0 1 0

X 0 0 0
ALUOp1 1 0 0 0

X 1 0 0
ALUOp0 0 0 0 1

X X 0 0
RegDst 1 0 X X

X X 1 0
MemtoReg 0 1 X X

0 0 0 1 X 0 0 0
Branch

0 0 0 0 1 0 0 0
Jump

0 0 0 0 0 1 1 1
RegWrite2

XX XX XX XX XX 00 01 10
Write2sel
The solution is the values in bold italics
Question 2 (Final Spring 2013): Modifying MIPS datapath & control to add instructions

You are an engineer for the MIPS Corporation, and you have been asked to modify the MIPS
single-cycle datapath and control, in order to add 3 instructions to the ISA of the MIPS
processor. In the following, parts b and c are dependent on each other, so you must solve b)
correctly in order to solve c) correctly.

b) The instructions you will add in this part are jz and jnz. These conditional jump instructions
test a condition bit, and will jump only if the condition is met (see RTLs below). The Z bit is the
stored result of the Zero value of the ALU from the previous instruction. To add these J-type
instructions to the MIPS single-cycle architecture will require changes to the single-cycle
datapath and control. In this part, you will make changes to the datapath only. Using the RTL
expressions given below, you should modify the datapath, adding (or removing) busses, datapath
elements, gates and control signals. Your goal should be to add as little new hardware as
possible. In any case however, the register file must not be changed and additional multiplexors
should not be added (of course, you may expand existing multiplexors as needed). Draw all your
changes directly on the figure.

jz: IM[PC]
if (Z = = 1) PC (PC + 4)[31:28] || instruct[25:0] || 00
else PC PC + 4

jnz: IM[PC]
if (Z ! = 1) PC (PC + 4)[31:28] || instruct[25:0] || 00
else PC PC + 4
Solution:
PC (PC + 4)[31:28] || instruct[25:0] || 00 (jump target address) is already is possible in the
datapath. So is PC PC + 4 + (SignExt(immed16) << 2) (branch target address) and PC  PC + 4.
The beq and j instructions already work in the datapath, we want to add jz and jnz without
changing the functionality of the existing instructions.
Since Z is the stored condition bit from the ALU result of the previous instruction, we must store
it in a flip-flop (i.e a 1-bit register) in case the following instruction is jz or jnz. This flip-flop
(named Z) will always load the Zero value on every instruction (i.e every clock cycle), to be
prepared in case the next instruction is a conditional jump.

The Jump MUX must select PCjump_target_address when j + jz·Z + jnz·Z’ is true. While it is
possible to build this logic function using an OR and 2 AND gates in the datapath, the easiest
way to make the function, with the smallest amount of hardware, is to do it in the Control unit.
The combinational circuits of a control unit are often implemented with structured functions
such as PLA, ROM, etc (since these match well to the control table) and these often have unused
capability, meaning that we can add new functionality for “free”, i.e no additional cost in
hardware. So making Jump= j + jz·Z + jnz·Z’ (done inside the control unit) is the best solution,
with minimum hardware cost.
This solution requires that the Z bit be a new control input to the Control unit.

The other approach, of adding gates to the datapath to form the function j + jz·Z + jnz·Z’
requires two new output signals from the control unit: jz and jnz. These are used by the AND
gates, to form the conditional decision about jumping. The output of the OR gate must become
the new MUX control input to the “jump” MUX. Note that the Jump signal from the Control unit
is used for j, since that is its current meaning.

c) To add the jz and jnz instructions (whose codes shall be 20 and 21) to the MIPS single-cycle
architecture will require changes to the single-cycle datapath and control. In this part, you will
make the changes to the control table only, since the datapath changes have already been made.
Give the complete control table for the datapath of part b) (including of course the modifications
you made), which implements R-types, lw, sw, beq, j, jz and jnz. In completing the table, be sure
to include all control signal values for all instructions. You should use the table given below.

Inputs Signal Name R-type lw sw beq j jz jnz

Op5 0 1 1 0 0 0 0

Op4 0 0 0 0 0 1 1

Op3 0 0 1 0 0 0 0

Op2 0 0 0 1 0 1 1

Op1 0 1 1 0 1 0 0

Op0 0 1 1 0 0 0 1

x 0/1 0/1
Z x x x x

Outputs x x x
RegDst 1 0 x x

0 0 0
RegWrite 1 1 0 0

0 0 0
MemRead 0 1 0 0

0 0 0
MemWrite 0 0 1 0

0 1 1 0 x x x
ALUSrc

x x x
ALUOp1 1 0 0 0
ALUOp0 0 0 0 1 x x x
 0 1 x x x x x
MemtoReg

x 0 0
Branch 0 0 0 1

1 Z Z’
Jump 0 0 0 0
Question 3 (Final Retake Spring 2013): Modifying MIPS datapath to add instructions

You are an engineer for the MIPS Corporation, and you have been asked to modify the MIPS
single-cycle datapath, in order to add 5 instructions to the ISA of the MIPS processor. In the
following, b) and c) are all independent, i.e 2 separate questions.

b) The instruction you will add in this part is jalm (“jump and link memory). This I-format jump
instruction stores the return address in the rt register, and jumps to the address found in memory
(using the other fields of the instruction to calculate the memory address). To add this I-type
instruction to the MIPS single-cycle architecture will require changes to the single-cycle datapath
and control. In this part, you will make the necessary changes to the datapath. Using the RTL
expressions given below, you should modify the datapath, adding (or removing) busses, datapath
elements, gates and control signals. Your goal should be to add as little new hardware as
possible. In any case however, the register file must not be changed and additional multiplexors
should not be added (of course, you may expand existing multiplexors). Draw all your changes
directly on the figure.

jalm: IM[PC]
R[rt]  PC + 4
PC DM[R[rs] + SignExt(immed)]
To add jalm to the datapath means that PC+4 must be connected to the Writedata port of the
Register File, through the MemtoReg MUX which becomes 3-to-1. The additional MUX input (let
it be input 2 or binary 10) means that MemtoReg will need to be a 2-bit control signal now. The
other change is to bring the DataMemory value from its Read data port to the Jump MUX, which
also becomes 3-to-1. This means that Jump will need to be a 2-bit control signal now also. The
additional Jump MUX input can be input 2 or binary 10.

c) The instructions you will add in this part are movz and movn. These conditional move
instructions test the value of a register, and move the data only if the condition is met (see RTLs
below). To add these R-type instructions to the MIPS single-cycle architecture will require
changes to the single-cycle datapath and control. In this part, you will make the necessary
changes to the datapath. Using the RTL expressions given below, you should modify the
datapath, adding (or removing) busses, datapath elements, gates and control signals. Your goal
should be to add as little new hardware as possible. In any case however, the register file must
not be changed and additional multiplexors should not be added (of course, you may expand
existing multiplexors as needed). Draw all your changes directly on the figure on the next page.

movz: IM[PC]
if (R[rt] = = 32’b0) R[rd]  R[rs]
PC PC + 4

movn: IM[PC]
if (R[rt] ! = 32’b0) R[rd]  R[rs]
PC PC + 4

In addition to the external changes that you will draw on the datapath drawing (on the next page),
complete the table below to explain the internal changes needed in 3 units for your design
solution.

There are 4 things that must be done for these 2 instructions to be realized:
 The movz and movn instructions must be recognized, from their func field bit values: the
two ways to do this are:
o bring the Instruction[5-0]bits to main Control, for decoding there
o let ALU Control decode them, giving new outputs Movz and Movn
 The R[rt] value must be compared against 0, to determine equality/inequality: there are
2 ways to do this:
o Use the ALU to pass R[rt] to the output, so the Zero signal does this
o Use an external “=0” comparator
 The R[rs] value must be brought to the MemtoReg MUX, so that it can be written into
the Register File (to R[rd]). The two ways to do this are:
o Use the ALU to pass R[rs] to the output, and hence to the MemtoReg MUX
o Make a new data bus to bring R[rs] as the 3rd input to the MUX
  The Load input of the Register File must be controlled properly, so that it is true when the
instruction is R-type or lw or (movz and R[rt]=0) or (movn and R[rt]≠ 0). This can be done
by either of the following:
o Do the function R-type + lw + movz·RtZ + movn·RtZ’ inside the main Control unit,
and output it as RegWrite
o Add external gates to make Load = RegWrite + movz·RtZ + movn·RtZ’ (since
currently RegWrite = R-type + lw)

Not all 24 combinations are possible, but any correct set will be given full credit. One is shown
below, to give an example.

Unit Internal changes Description of changes

(yes/no)

Control Yes It decodes movz and movn, and uses RtZ to make
RegWrite = R-type + lw + movz·RtZ + movn·RtZ’

ALU control Yes It has a new control signal output combination to

cause ALUresult  R[rt]

ALU Yes It has a new operation for ALUresult  R[rt]

This solution brings R[rs] directly to the MemtoReg MUX as a 3rd input, thus the MemtoReg signal becomes
a 2-bit control, for the 3-to-1 MUX. In this way, the ALU is used for determining if R[rt] is 0 or not (the Zero
output is our new RtZ signal). Since the main Control will implement the function RegWrite = R-type + lw +
movz·RtZ + movn·RtZ’, it needs to have the 6-bit function field, and RtZ as inputs.